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Remove tic80 support This is one way of fixing ubsan bug reports, just delete the code. The assembler support was removed back in 2005 along with other non-BFD assemblers, but somehow the remainder of the port stayed in. bfd/ * coff-tic80.c: Delete file. * cpu-tic80.c: Delete file. * archures.c: Remove tic80 support. * coffcode.h: Likewise. * coffswap.h: Likewise. * targets.c: Likewise. * config.bfd: Likewise. * configure.ac: Likewise. * Makefile.am: Likewise. * Makefile.in: Regenerate. * bfd-in2.h: Regenerate. * configure: Regenerate. * po/SRC-POTFILES.in: Regenerate. binutils/ * testsuite/binutils-all/objcopy.exp: Remove tic80 support. * testsuite/binutils-all/objdump.exp: Likewise. gas/ * doc/as.texi: Remove mention of tic80. include/ * coff/tic80.h: Delete file. * opcode/tic80.h: Delete file. ld/ * emulparams/tic80coff.sh: Delete file. * scripttempl/tic80coff.sc: Delete file. * configure.tgt: Remove tic80 support. * Makefile.am: Likewise. * Makefile.in: Regenerate. * po/BLD-POTFILES.in: Regenerate. opcodes/ * tic80-dis.c: Delete file. * tic80-opc.c: Delete file. * disassemble.c: Remove tic80 support. * disassemble.h: Likewise. * Makefile.am: Likewise. * configure.ac: Likewise. * Makefile.in: Regenerate. * configure: Regenerate. * po/POTFILES.in: Regenerate.
2019-12-17 11:53:55 +08:00
2019-12-17 Alan Modra <amodra@gmail.com>
* tic80-dis.c: Delete file.
* tic80-opc.c: Delete file.
* disassemble.c: Remove tic80 support.
* disassemble.h: Likewise.
* Makefile.am: Likewise.
* configure.ac: Likewise.
* Makefile.in: Regenerate.
* configure: Regenerate.
* po/POTFILES.in: Regenerate.
ubsan: bpf: left shift cannot be represented in type 'DI' (aka 'long') cpu/ * bpf.cpu (f-imm64): Avoid signed overflow. opcodes/ * bpf-ibld.c: Regenerate.
2019-12-17 11:56:39 +08:00
2019-12-17 Alan Modra <amodra@gmail.com>
* bpf-ibld.c: Regenerate.
ubsan: aarch64: left shift of negative value * aarch64-dis.c (sign_extend): Return uint64_t. Rewrite without conditional. (aarch64_ext_imm): Avoid signed overflow.
2019-12-16 14:28:30 +08:00
2019-12-16 Alan Modra <amodra@gmail.com>
* aarch64-dis.c (sign_extend): Return uint64_t. Rewrite without
conditional.
(aarch64_ext_imm): Avoid signed overflow.
ubsan: microblaze: left shift cannot be represented in type 'int' * microblaze-dis.c (read_insn_microblaze): Avoid signed overflow.
2019-12-16 07:29:23 +08:00
2019-12-16 Alan Modra <amodra@gmail.com>
* microblaze-dis.c (read_insn_microblaze): Avoid signed overflow.
ubsan: nios2: left shift cannot be represented in type 'int' * nios2-dis.c (nios2_print_insn_arg): Avoid signed overflow
2019-12-16 07:28:52 +08:00
2019-12-16 Alan Modra <amodra@gmail.com>
* nios2-dis.c (nios2_print_insn_arg): Avoid signed overflow
ubsan: xstormy16: left shift of negative value cpu/ * xstormy16.cpu (f-rel12a): Avoid signed overflow. opcodes/ * xstormy16-ibld.c: Regenerate.
2019-12-16 07:30:07 +08:00
2019-12-16 Alan Modra <amodra@gmail.com>
* xstormy16-ibld.c: Regenerate.
asan: score: global-buffer-overflow I'm flying blind here, not having an s+core s3 insn set reference, but this seems reasonably obvious from what is done by the assembler. s3_do16_rpop does some mixing of imm and reg values to place in the rpop reg field, but I'm not going to try to fix the disassembly there. * score-dis.c (print_insn_score16): Move rpush/rpop imm field value adjustment so that it doesn't affect reg field too.
2019-12-16 07:30:39 +08:00
2019-12-16 Alan Modra <amodra@gmail.com>
* score-dis.c (print_insn_score16): Move rpush/rpop imm field
value adjustment so that it doesn't affect reg field too.
ubsan: crx: left shift cannot be represented in type 'int' The ubsan complaint is fixed by the SBM change, with similar possible complaints fixed by the EXTRACT change. The rest is just cleanup. include/ * opcode/crx.h (inst <match>): Make unsigned int. opcodes/ * crx-dis.c (EXTRACT, SBM): Avoid signed overflow. (get_number_of_operands, getargtype, getbits, getregname), (getcopregname, getprocregname, gettrapstring, getcinvstring), (getregliststring, get_word_at_PC, get_words_at_PC, build_mask), (powerof2, match_opcode, make_instruction, print_arguments), (print_arg): Delete forward declarations, moving static to.. (getregname, getcopregname, getregliststring): ..these definitions. (build_mask): Return unsigned int mask. (match_opcode): Use unsigned int vars.
2019-12-16 07:28:09 +08:00
2019-12-16 Alan Modra <amodra@gmail.com>
* crx-dis.c (EXTRACT, SBM): Avoid signed overflow.
(get_number_of_operands, getargtype, getbits, getregname),
(getcopregname, getprocregname, gettrapstring, getcinvstring),
(getregliststring, get_word_at_PC, get_words_at_PC, build_mask),
(powerof2, match_opcode, make_instruction, print_arguments),
(print_arg): Delete forward declarations, moving static to..
(getregname, getcopregname, getregliststring): ..these definitions.
(build_mask): Return unsigned int mask.
(match_opcode): Use unsigned int vars.
ubsan: bfin: left shift of negative value * bfin-dis.c (fmtconst, fmtconst_val): Avoid signed overflow.
2019-12-16 08:01:34 +08:00
2019-12-16 Alan Modra <amodra@gmail.com>
* bfin-dis.c (fmtconst, fmtconst_val): Avoid signed overflow.
ubsan: nds32: left shift cannot be represented in type 'int' Note that using 1u in N32_BIT makes all of N32_BIT, __MASK, __MF, __GF and __SEXT evaluate as unsigned int (the latter three when when their v arg is int or smaller). This would be a problem if assigning the result to a bfd_vma, long, or other type wider than an int since the __SEXT result would be zero extended to the wider type. Fortunately nds32 target code doesn't use wider types unnecessarily. include/ * opcode/nds32.h (N32_BIT): Define using 1u. (__SEXT): Use __MASK and N32_BIT. (N32_IMMS): Remove duplicate mask. opcodes/ * nds32-dis.c (print_insn16, print_insn32): Remove forward decls. (struct objdump_disasm_info): Delete. (nds32_parse_audio_ext, nds32_parse_opcode): Cast result of N32_IMMS to unsigned before shifting left.
2019-12-16 07:05:30 +08:00
2019-12-16 Alan Modra <amodra@gmail.com>
* nds32-dis.c (print_insn16, print_insn32): Remove forward decls.
(struct objdump_disasm_info): Delete.
(nds32_parse_audio_ext, nds32_parse_opcode): Cast result of
N32_IMMS to unsigned before shifting left.
ubsan: moxie: left shift of negative value Commit 8c9b4171877df didn't remove a glaring left shift of a number that had just been sign extended. * moxie-dis.c (INST2OFFSET): Don't left shift a signed value. (print_insn_moxie): Remove unnecessary cast.
2019-12-16 07:27:22 +08:00
2019-12-16 Alan Modra <amodra@gmail.com>
* moxie-dis.c (INST2OFFSET): Don't left shift a signed value.
(print_insn_moxie): Remove unnecessary cast.
csky: tidy csky_chars_to_number * csky-dis.c (csky_chars_to_number): Remove abort and unnecessary mask.
2019-12-12 14:14:24 +08:00
2019-12-12 Alan Modra <amodra@gmail.com>
* csky-dis.c (csky_chars_to_number): Remove abort and unnecessary
mask.
Remove more shifts for sign/zero extension cpu/ * epiphany.cpu (f-sdisp11): Don't sign extend with shifts. * lm32.cpu (f-branch, f-vall): Likewise. * m32.cpu (f-lab-8-16): Likewise. opcodes/ * arc-dis.c (BITS): Don't truncate high bits with shifts. * nios2-dis.c (nios2_print_insn_arg): Don't sign extend with shifts. * tic54x-dis.c (print_instruction): Likewise. * tilegx-opc.c (parse_insn_tilegx): Likewise. * tilepro-opc.c (parse_insn_tilepro): Likewise. * visium-dis.c (disassem_class0): Likewise. * pdp11-dis.c (sign_extend): Likewise. (SIGN_BITS): Delete. * epiphany-ibld.c: Regenerate. * lm32-ibld.c: Regenerate. * m32c-ibld.c: Regenerate.
2019-12-11 14:15:14 +08:00
2019-12-11 Alan Modra <amodra@gmail.com>
* arc-dis.c (BITS): Don't truncate high bits with shifts.
* nios2-dis.c (nios2_print_insn_arg): Don't sign extend with shifts.
* tic54x-dis.c (print_instruction): Likewise.
* tilegx-opc.c (parse_insn_tilegx): Likewise.
* tilepro-opc.c (parse_insn_tilepro): Likewise.
* visium-dis.c (disassem_class0): Likewise.
* pdp11-dis.c (sign_extend): Likewise.
(SIGN_BITS): Delete.
* epiphany-ibld.c: Regenerate.
* lm32-ibld.c: Regenerate.
* m32c-ibld.c: Regenerate.
Re: ubsan: ns32k: left shift cannot be represented in type * ns32k-dis.c (sign_extend): Correct last patch.
2019-12-11 10:41:07 +08:00
2019-12-11 Alan Modra <amodra@gmail.com>
* ns32k-dis.c (sign_extend): Correct last patch.
ubsan: vax: left shift cannot be represented in type 'int' * vax-dis.c (NEXTLONG): Avoid signed overflow.
2019-12-11 06:27:45 +08:00
2019-12-11 Alan Modra <amodra@gmail.com>
* vax-dis.c (NEXTLONG): Avoid signed overflow.
ubsan: v850: left shift cannot be represented in type 'long' * v850-dis.c (get_operand_value): Use unsigned arithmetic. Don't sign extend using shifts.
2019-12-11 06:23:50 +08:00
2019-12-11 Alan Modra <amodra@gmail.com>
* v850-dis.c (get_operand_value): Use unsigned arithmetic. Don't
sign extend using shifts.
ubsan: tic6x: shift left of int * tic6x-dis.c (tic6x_extract_32): Avoid signed overflow.
2019-12-11 06:22:22 +08:00
2019-12-11 Alan Modra <amodra@gmail.com>
* tic6x-dis.c (tic6x_extract_32): Avoid signed overflow.
ubsan: tic4x: segv and signed shifts * tic4x-dis.c (tic4x_print_register): Formatting. Don't segfault on NULL registertable entry. (tic4x_hash_opcode): Use unsigned arithmetic.
2019-12-11 06:17:35 +08:00
2019-12-11 Alan Modra <amodra@gmail.com>
* tic4x-dis.c (tic4x_print_register): Formatting. Don't segfault
on NULL registertable entry.
(tic4x_hash_opcode): Use unsigned arithmetic.
ubsan: s12z: left shift cannot be represented in type 'int' * s12z-opc.c (z_decode_signed_value): Avoid signed overflow.
2019-12-11 06:07:53 +08:00
2019-12-11 Alan Modra <amodra@gmail.com>
* s12z-opc.c (z_decode_signed_value): Avoid signed overflow.
ubsan: ns32k: left shift cannot be represented in type 'int' * ns32k-dis.c (bit_extract): Use unsigned arithmetic. (bit_extract_simple, sign_extend): Likewise.
2019-12-11 06:04:57 +08:00
2019-12-11 Alan Modra <amodra@gmail.com>
* ns32k-dis.c (bit_extract): Use unsigned arithmetic.
(bit_extract_simple, sign_extend): Likewise.
ubsan: nios2: left shift cannot be represented in type 'int' * nios2-dis.c (nios2_print_insn_arg): Use 1u << 31.
2019-12-11 06:02:18 +08:00
2019-12-11 Alan Modra <amodra@gmail.com>
* nios2-dis.c (nios2_print_insn_arg): Use 1u << 31.
ubsan: moxie: left shift of negative value * moxie-dis.c (INST2OFFSET): Don't sign extend using shifts.
2019-12-11 05:56:58 +08:00
2019-12-11 Alan Modra <amodra@gmail.com>
* moxie-dis.c (INST2OFFSET): Don't sign extend using shifts.
ubsan: m68k: left shift cannot be represented in type 'int' * m68k-dis.c (COERCE32): Cast value first. (NEXTLONG, NEXTULONG): Avoid signed overflow.
2019-12-11 05:53:33 +08:00
2019-12-11 Alan Modra <amodra@gmail.com>
* m68k-dis.c (COERCE32): Cast value first.
(NEXTLONG, NEXTULONG): Avoid signed overflow.
ubsan: h8300: left shift cannot be represented in type 'int' This is *cst = (data[0] << 24) + (data[1] << 16) + (data[2] << 8) + data[3]; data is unsigned char which promotes to int. * h8300-dis.c (extract_immediate): Avoid signed overflow. (bfd_h8_disassemble): Likewise.
2019-12-10 21:23:57 +08:00
2019-12-11 Alan Modra <amodra@gmail.com>
* h8300-dis.c (extract_immediate): Avoid signed overflow.
(bfd_h8_disassemble): Likewise.
ussan: d30v: index out of bounds * d30v-dis.c (print_insn): Make opind unsigned. Don't access past end of operands array.
2019-12-10 21:20:02 +08:00
2019-12-11 Alan Modra <amodra@gmail.com>
* d30v-dis.c (print_insn): Make opind unsigned. Don't access
past end of operands array.
ubsan: csky: left shift cannot be represented in type 'int' In the following buf is an unsigned char array, so elements are promoted to int before arithmetic operations. if (dis_info.info->endian == BFD_ENDIAN_BIG) while (n--) val |= buf[n] << (n*8); else for (i = 0; i < n; i++) val |= buf[i] << (i*8); * csky-dis.c (csky_chars_to_number): Rewrite. Avoid signed overflow when collecting bytes of a number.
2019-12-10 21:07:03 +08:00
2019-12-11 Alan Modra <amodra@gmail.com>
* csky-dis.c (csky_chars_to_number): Rewrite. Avoid signed
overflow when collecting bytes of a number.
ubsan: cris: signed integer overflow This was the following in print_with_operands case 4: number = buffer[2] + buffer[3] * 256 + buffer[4] * 65536 + buffer[5] * 0x1000000; and buffer[5] * 0x1000000 can indeed overflow. So to fix this we need to use unsigned arithmetic where overflow semantics are specified. But number is a long, and the expression is int which will be sign extended to long. If we make the expression unsigned it will be zero extended. So make number an int32_t and rearrange a little for some of the places that need fixing. * cris-dis.c (print_with_operands): Avoid signed integer overflow when collecting bytes of a 32-bit integer.
2019-12-10 20:52:10 +08:00
2019-12-11 Alan Modra <amodra@gmail.com>
* cris-dis.c (print_with_operands): Avoid signed integer
overflow when collecting bytes of a 32-bit integer.
ubsan: cr16: left shift cannot be represented in type 'int' This was: unsigned long mask = SBM (instruction->match_bits); with #define SBM(offs) ((((1 << (32 - offs)) -1) << (offs))) Well, there are a couple of problems. Firstly, the expression uses int values (1 rather than 1u or 1ul) resulting in the ubsan error, and secondly, a zero offs will result in a 32-bit shift which is undefined if ints are only 32 bits. * cr16-dis.c (EXTRACT, SBM): Rewrite. (cr16_match_opcode): Delete duplicate bcond test.
2019-12-10 20:32:37 +08:00
2019-12-11 Alan Modra <amodra@gmail.com>
* cr16-dis.c (EXTRACT, SBM): Rewrite.
(cr16_match_opcode): Delete duplicate bcond test.
ubsan: bfin: shift exponent is too large This was the following in fmtconst_val, x is unsigned int. x = SIGNEXTEND (x, constant_formats[cf].nbits); Problem is, the SIGNEXTEND macro assumed its arg was a long and sign extended by shifting left then shifting right, and didn't cast the arg. So don't do the silly shift thing. It's not guaranteed to work anyway according to the C standard. ">>" might do a logical shift even if its args are signed. * bfin-dis.c (HOST_LONG_WORD_SIZE, XFIELD): Delete. (SIGNBIT): New. (MASKBITS, SIGNEXTEND): Rewrite. (fmtconst): Don't use ? expression now that SIGNEXTEND uses unsigned arithmetic, instead assign result of SIGNEXTEND back to x. (fmtconst_val): Use 1u in shift expression.
2019-12-10 20:02:06 +08:00
2019-12-11 Alan Modra <amodra@gmail.com>
* bfin-dis.c (HOST_LONG_WORD_SIZE, XFIELD): Delete.
(SIGNBIT): New.
(MASKBITS, SIGNEXTEND): Rewrite.
(fmtconst): Don't use ? expression now that SIGNEXTEND uses
unsigned arithmetic, instead assign result of SIGNEXTEND back
to x.
(fmtconst_val): Use 1u in shift expression.
ubsan: arc: shift exponent 32 is too large for 32-bit type 'int' When operand->bits is 32, the following results in UB. value = (insn >> operand->shift) & ((1 << operand->bits) - 1); * arc-dis.c (find_format_from_table): Use ull constant when shifting by up to 32.
2019-12-10 16:39:47 +08:00
2019-12-11 Alan Modra <amodra@gmail.com>
* arc-dis.c (find_format_from_table): Use ull constant when
shifting by up to 32.
aarch64 disassembler infinite loop Assembling this to an object and trying to disassemble results in objdump -d looping forever. .inst 0x45205120 PR 25270 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Return false when field is zero for sve_size_tsz_bhs.
2019-12-10 16:34:37 +08:00
2019-12-11 Alan Modra <amodra@gmail.com>
PR 25270
* aarch64-dis.c (aarch64_decode_variant_using_iclass): Return
false when field is zero for sve_size_tsz_bhs.
ubsan: epiphany: left shift of negative value Two places in epiphany_cgen_extract_operand, "value" is a long. value = ((((value) << (1))) + (pc)); cpu/ * epiphany.cpu (f-simm8, f-simm24): Use multiply rather than shift left to avoid UB on left shift of negative values. opcodes/ * epiphany-ibld.c: Regenerate.
2019-12-10 15:36:09 +08:00
2019-12-11 Alan Modra <amodra@gmail.com>
* epiphany-ibld.c: Regenerate.
PR24960, Memory leak from disassembler PR 24960 include/ * dis-asm.h (disassemble_free_target): Declare. opcodes/ * disassemble.c (disassemble_free_target): New function. binutils/ * objdump.c (disassemble_data): Call disassemble_free_target.
2019-12-09 18:04:49 +08:00
2019-12-10 Alan Modra <amodra@gmail.com>
PR 24960
* disassemble.c (disassemble_free_target): New function.
Use disassemble_info.private_data in place of insn_sets No cgen target uses private_data. This patch removes a disassemble_info field that is only used by cgen, and instead uses private_data. It also removes a macro that is no longer used. include/ * dis-asm.h (struct disassemble_info): Delete insn_sets. (INIT_DISASSEMBLE_INFO_NO_ARCH): Don't define. opcodes/ * cgen-dis.in (print_insn_@arch@): Replace insn_sets with private_data. * disassemble.c (disassemble_init_for_target): Likewise. * bpf-dis.c: Regenerate. * epiphany-dis.c: Regenerate. * fr30-dis.c: Regenerate. * frv-dis.c: Regenerate. * ip2k-dis.c: Regenerate. * iq2000-dis.c: Regenerate. * lm32-dis.c: Regenerate. * m32c-dis.c: Regenerate. * m32r-dis.c: Regenerate. * mep-dis.c: Regenerate. * mt-dis.c: Regenerate. * or1k-dis.c: Regenerate. * xc16x-dis.c: Regenerate. * xstormy16-dis.c: Regenerate.
2019-12-09 20:16:26 +08:00
2019-12-10 Alan Modra <amodra@gmail.com>
* cgen-dis.in (print_insn_@arch@): Replace insn_sets with private_data.
* disassemble.c (disassemble_init_for_target): Likewise.
* bpf-dis.c: Regenerate.
* epiphany-dis.c: Regenerate.
* fr30-dis.c: Regenerate.
* frv-dis.c: Regenerate.
* ip2k-dis.c: Regenerate.
* iq2000-dis.c: Regenerate.
* lm32-dis.c: Regenerate.
* m32c-dis.c: Regenerate.
* m32r-dis.c: Regenerate.
* mep-dis.c: Regenerate.
* mt-dis.c: Regenerate.
* or1k-dis.c: Regenerate.
* xc16x-dis.c: Regenerate.
* xstormy16-dis.c: Regenerate.
Remove backup ppc struct dis_private. ppc-dis.c used a global struct whenever malloc failed to provide the eight bytes of memory necessary for struct dis_private. Which is quite ridiculous. If that malloc failed there is zero chance some other malloc won't fail too. * ppc-dis.c (private): Delete variable. (get_powerpc_dialect): Don't segfault on NULL info->private_data. (powerpc_init_dialect): Don't use global private.
2019-12-09 20:27:15 +08:00
2019-12-10 Alan Modra <amodra@gmail.com>
* ppc-dis.c (private): Delete variable.
(get_powerpc_dialect): Don't segfault on NULL info->private_data.
(powerpc_init_dialect): Don't use global private.
s12z-opc.c formatting fixes Wrap overlong lines, whitespace fixes, and for function definitions start a line with the name of the function. * s12z-opc.c: Formatting.
2019-12-07 13:34:33 +08:00
2019-12-10 Alan Modra <amodra@gmail.com>
* s12z-opc.c: Formatting.
S12Z disassembler memory leak * s12z-opc.c (exg_sex_discrim): Don't leak memory on invalid registers.
2019-12-07 08:55:52 +08:00
2019-12-08 Alan Modra <amodra@gmail.com>
* s12z-opc.c (exg_sex_discrim): Don't leak memory on invalid
registers.
Arm64: simplify Crypto arch extension handling This, at the assembler level, is just a "brace" feature covering both AES and SHA2. Hence there's no need for it to have a separate feature flag, freeing up a bit for future re-use. Along these lines there are also a number of dead definitions/variables in the opcode table file.
2019-12-05 15:44:22 +08:00
2019-12-05 Jan Beulich <jbeulich@suse.com>
* aarch64-tbl.h (aarch64_feature_crypto,
aarch64_feature_crypto_v8_2, CRYPTO, CRYPTO_V8_2, CRYP_INSN,
CRYPTO_V8_2_INSN): Delete.
PR25249, Memory leak in microblaze-dis.c PR 25249 * microblaze-dis.c (NUM_STRBUFS, STRBUF_SIZE): Define. (struct string_buf): New. (strbuf): New function. (get_field): Use strbuf rather than strdup of local temp. (get_field_imm, get_field_imm5, get_field_imm5_mbar): Likewise. (get_field_rfsl, get_field_imm15): Likewise. (get_field_rd, get_field_r1, get_field_r2): Update macros. (get_field_special): Likewise. Don't strcpy spr. Formatting. (print_insn_microblaze): Formatting. Init and pass string_buf to get_field functions.
2019-12-05 12:12:44 +08:00
2019-12-05 Alan Modra <amodra@gmail.com>
PR 25249
* microblaze-dis.c (NUM_STRBUFS, STRBUF_SIZE): Define.
(struct string_buf): New.
(strbuf): New function.
(get_field): Use strbuf rather than strdup of local temp.
(get_field_imm, get_field_imm5, get_field_imm5_mbar): Likewise.
(get_field_rfsl, get_field_imm15): Likewise.
(get_field_rd, get_field_r1, get_field_r2): Update macros.
(get_field_special): Likewise. Don't strcpy spr. Formatting.
(print_insn_microblaze): Formatting. Init and pass string_buf to
get_field functions.
x86-64: accept 64-bit LFS/LGS/LSS forms with suffix or operand size specifier Since we accept these without suffix / operand size specifier, we should also do so with one. (The fact that we unilaterally accept these, other than far branches, rather than limiting them to Intel64 mode, will be taken care of later on.) Also take the opportunity and make sure "lfs <reg>, tbyte ptr <mem>" et al get rejected outside of 64-bit mode. This became broken by dc2be329b950 ("i386: Only check suffix in instruction mnemonic"). Furthermore cover lgdt et al in the Intel syntax handling as well, which continued to work after said commit just by coincidence.
2019-12-04 17:45:17 +08:00
2019-12-04 Jan Beulich <jbeulich@suse.com>
* i386-opc.tbl (lfs, lgs, lss): Drop No_qSuf.
* i386-tbl.h: Re-generate.
x86/Intel: extend MOVDIRI testing Test also memory operands with operand size specifier, which was broken prior to dc2be329b950 ("i386: Only check suffix in instruction mnemonic"), due to the template not permitting any suffixes. Note that this uncovered a disassembler issue, which is being fixed here as well.
2019-12-04 17:41:43 +08:00
2019-12-04 Jan Beulich <jbeulich@suse.com>
* i386-dis.c (mod_table): Use Ev instead of Em for movdiri.
x86: drop some stray/bogus DefaultSize Insns permitting only GPR operands (and hence implicit sizing when there's no suffix) don't ever have their DefaultSize attribute inspected, so it shouldn't be there in the first place. Additionally XBEGIN is like JMP, not CALL, and hence shouldn't be converted to 32-bit operand size in .code16gcc mode. While the same is true for SYSRET, it permitting more than one suffix makes it FLDENV- like, and hence rather than dropping the attribute, for now add it to the exclusion list to avoid it getting an operand size prefix emitted in .code16gcc mode. (This will be dealt with later, perhaps together with FLDENV and friends.)
2019-12-04 17:40:02 +08:00
2019-12-04 Jan Beulich <jbeulich@suse.com>
* i386-opc.tbl (push, pop): Drop DefaultSize from GPR-only
forms.
(xbegin): Drop DefaultSize.
* i386-tbl.h: Re-generate.
Arm: Change CRC from fpu feature to archititectural extension This patch changes the CRC extension to use the core feature bits instead of the coproc/fpu feature bits. CRC is not an fpu feature and it causes issues with the new fpu reset patch (f439988037a589de3798f44e7268301adaec21a9). CRC can be set using the '.arch_extension' directive, which sets bits in the coproc bitfield. When a '.fpu' directive is encountered, the CRC feature bit gets removed and there is no way to set it back using '.fpu'. With this patch, CRC will be marked in the feature core bits, which prevents it from getting removed when setting/changing the fpu options. gas/ChangeLog: * config/tc-arm.c (arm_ext_crc): New. (crc_ext_armv8): Remove. (insns): Rename crc_ext_armv8 to arm_ext_crc. (arm_cpus): Replace CRC_EXT_ARMV8 with ARM_EXT2_CRC. (armv8a_ext_table, armv8r_ext_table, arm_option_extension_value_table): Redefine the crc extension in terms of ARM_EXT2_CRC. * gas/testsuite/gas/arm/crc-ext.s: New. * gas/testsuite/gas/arm/crc-ext.d: New. include/ChangeLog: * opcode/arm.h (ARM_EXT2_CRC): New extension feature to replace CRC_EXT_ARMV8. (CRC_EXT_ARMV8): Remove and mark bit as unused. (ARM_ARCH_V8A_CRC, ARM_ARCH_V8_1A, ARM_ARCH_V8_2A, ARM_ARCH_V8_3A, ARM_ARCH_V8_4A, ARM_ARCH_V8_5A, ARM_ARCH_V8_6A): Redefine using ARM_EXT2_CRC instead of CRC_EXT_ARMV8. opcodes/ChangeLog: * opcodes/arm-dis.c (arm_opcodes, thumb32_opcodes): Change the coproc CRC conditions to use the extension feature set, second word, base on ARM_EXT2_CRC.
2019-11-22 21:44:17 +08:00
2019-11-22 Mihail Ionescu <mihail.ionescu@arm.com>
* opcodes/arm-dis.c (arm_opcodes, thumb32_opcodes):
Change the coproc CRC conditions to use the extension
feature set, second word, base on ARM_EXT2_CRC.
x86: drop redundant SYSCALL/SYSRET templates The Cpu64 forms are no different in their attributes except for the CPU flags; there's no need to key these off of anything other than CpuSYSCALL even for the 64-bit forms. Dropping these improves the diagnostic on SYSRETQ used in 32-bit code from "unsupported instruction `sysret'" to "invalid instruction suffix for `sysret'".
2019-11-14 15:48:22 +08:00
2019-11-14 Jan Beulich <jbeulich@suse.com>
* i386-opc.tbl (syscall, sysret): Drop Cpu64 forms.
* i386-tbl.h: Re-generate.
x86: fold individual Jump* attributes into a single Jump one ..., taking just 3 bits instead of 5. No two of them are used together.
2019-11-14 15:47:44 +08:00
2019-11-14 Jan Beulich <jbeulich@suse.com>
* i386-gen.c (opcode_modifiers): Remove JumpDword, JumpByte,
JumpInterSegment, and JumpAbsolute entries.
* i386-opc.h (JUMP, JUMP_DWORD, JUMP_BYTE, JUMP_INTERSEGMENT,
JUMP_ABSOLUTE): Define.
(struct i386_opcode_modifier): Extend jump field to 3 bits.
Remove jumpdword, jumpbyte, jumpintersegment, and jumpabsolute
fields.
* i386-opc.tbl (JumpByte, JumpDword, JumpAbsolute,
JumpInterSegment): Define.
* i386-tbl.h: Re-generate.
x86: make JumpAbsolute an insn attribute ... instead of an operand one: There's only ever one operand here anyway.
2019-11-14 15:47:03 +08:00
2019-11-14 Jan Beulich <jbeulich@suse.com>
* i386-gen.c (operand_type_init): Remove
OPERAND_TYPE_JUMPABSOLUTE entry.
(opcode_modifiers): Add JumpAbsolute entry.
(operand_types): Remove JumpAbsolute entry.
* i386-opc.h (JumpAbsolute): Move between enums.
(struct i386_opcode_modifier): Add jumpabsolute field.
(union i386_operand_type): Remove jumpabsolute field.
* i386-opc.tbl (call, lcall, jmp, ljmp): Move JumpAbsolute.
* i386-init.h, i386-tbl.h: Re-generate.
x86: make AnySize an insn attribute ... instead of an operand one. Which operand it applies to can be determined from other operand properties, but as it turns out the only place it is actually used at doesn't even need further qualification.
2019-11-14 15:46:19 +08:00
2019-11-14 Jan Beulich <jbeulich@suse.com>
* i386-gen.c (opcode_modifiers): Add AnySize entry.
(operand_types): Remove AnySize entry.
* i386-opc.h (AnySize): Move between enums.
(struct i386_opcode_modifier): Add anysize field.
(OTUnused): Un-comment.
(union i386_operand_type): Remove anysize field.
* i386-opc.tbl (lea, invlpg, clflush, prefetchnta, prefetcht0,
prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote): Move
AnySize.
* i386-tbl.h: Re-generate.
RISC-V: Support the INSN_CLASS.*F.* classes for .insn directive. We have to enable the f extension through -march or ELF attribute if we use the FPR in .insn directive. The behavior is same as the riscv_opcodes. 2019-11-12 Nelson Chu <nelson.chu@sifive.com> opcodes/ * riscv-opc.c (riscv_insn_types): Replace the INSN_CLASS_I with INSN_CLASS_F and the INSN_CLASS_C with INSN_CLASS_F_AND_C if we use the floating point register (FPR). gas/ * testsuite/gas/riscv/insn.d: Add the f extension to -march option. Change-Id: I4f59d04c82673ef84c56ecd2659ad8ce164dd626
2019-11-13 08:13:00 +08:00
2019-11-12 Nelson Chu <nelson.chu@sifive.com>
* riscv-opc.c (riscv_insn_types): Replace the INSN_CLASS_I with
INSN_CLASS_F and the INSN_CLASS_C with INSN_CLASS_F_AND_C if we
use the floating point register (FPR).
[binutils][arm] Update the decoding of MVE VMOV, VMVN This patch updates the decoding of the VMOV and VMVN instructions which depend on cmode. Previously VMOV and VMVN with cmode 1101 were not allowed. The cmode changes also required updating of the MVE conflict checking. Now instructions with opcodes 0xef800d50 and 0xef800e70 correctly get decoded as VMOV and VMVN, respectively. 2019-11-12 Mihail Ionescu <mihail.ionescu@arm.com> * opcodes/arm-dis.c (mve_opcodes): Enable VMOV imm to vec with cmode 1101. (is_mve_encoding_conflict): Update cmode conflict checks for MVE_VMVN_IMM. 2019-11-12 Mihail Ionescu <mihail.ionescu@arm.com> * gas/config/tc-arm.c (do_neon_mvn): Allow mve_ext cmode=0xd. * testsuite/gas/arm/mve-vmov-vmvn-vorr-vbic.s: New test. * testsuite/gas/arm/mve-vmov-vmvn-vorr-vbic.d: Likewise.
2019-11-12 21:55:37 +08:00
2019-11-12 Mihail Ionescu <mihail.ionescu@arm.com>
* opcodes/arm-dis.c (mve_opcodes): Enable VMOV imm to vec with
cmode 1101.
(is_mve_encoding_conflict): Update cmode conflict checks for
MVE_VMVN_IMM.
x86: fold EsSeg into IsString EsSeg (a per-operand bit) is used with IsString (a per-insn attribute) only. Extend the attribute to 2 bits, thus allowing to encode - not a string insn, - string insn with neither operand requiring use of %es:, - string insn with 1st operand requiring use of %es:, - string insn with 2nd operand requiring use of %es:, which covers all possible cases, allowing to drop EsSeg. The (transient) need to comment out the OTUnused #define did uncover an oversight in the earlier OTMax -> OTNum conversion, which is being taken care of here.
2019-11-12 16:09:31 +08:00
2019-11-12 Jan Beulich <jbeulich@suse.com>
* i386-gen.c (operand_type_init): Remove OPERAND_TYPE_ESSEG
entry.
(operand_types): Remove EsSeg entry.
(main): Replace stale use of OTMax.
* i386-opc.h (IS_STRING_ES_OP0, IS_STRING_ES_OP1): Define.
(struct i386_opcode_modifier): Expand isstring field to 2 bits.
(EsSeg): Delete.
(OTUnused): Comment out.
(union i386_operand_type): Remove esseg field.
* i386-opc.tbl (IsStringEsOp0, IsStringEsOp1): Define.
(cmps, scmp, scas, ssca, cmpsd): Add IsStringEsOp0.
(ins, movs, smov, movsd): Add IsStringEsOpOp1.
(stos, ssto): Add IsStringEsOp0/IsStringEsOpOp1.
* i386-init.h, i386-tbl.h: Re-generate.
x86: eliminate ImmExt abuse Drop the remaining instances left in place by commit c3949f432f ("x86: limit ImmExt abuse), now that we have a way to specify specific GPRs. Take the opportunity and also introduce proper 16-bit forms of applicable SVME insns as well as 1-operand forms of CLZERO.
2019-11-12 16:08:32 +08:00
2019-11-12 Jan Beulich <jbeulich@suse.com>
* i386-gen.c (operand_instances): Add RegB entry.
* i386-opc.h (enum operand_instance): Add RegB.
* i386-opc.tbl (RegC, RegD, RegB): Define.
(Acc, ShiftCount, InOutPortReg): Adjust definitions.
(monitor, mwait, invlpga, skinit, vmload, vmrun, vmsave, clzero,
monitorx, mwaitx): Drop ImmExt and convert encodings
accordingly.
* i386-reg.tbl (ecx, rcx): Add Instance=RegC.
(edx, rdx): Add Instance=RegD.
(ebx, rbx): Add Instance=RegB.
* i386-tbl.h: Re-generate.
x86: introduce operand type "instance" Special register "class" instances can't be combined with one another (neither in templates nor in register entries), and hence it is not a good use of resources (memory as well as execution time) to represent them as individual bits of a bit field. Furthermore the generalization becoming possible will allow improvements to the handling of insns accepting only individual registers as their operands.
2019-11-12 16:07:34 +08:00
2019-11-12 Jan Beulich <jbeulich@suse.com>
* i386-gen.c (operand_type_init): Adjust
OPERAND_TYPE_INOUTPORTREG, OPERAND_TYPE_SHIFTCOUNT,
OPERAND_TYPE_FLOATACC, OPERAND_TYPE_ACC8, OPERAND_TYPE_ACC16,
OPERAND_TYPE_ACC32, and OPERAND_TYPE_ACC64 entries.
(operand_instances): New.
(operand_types): Drop InOutPortReg, ShiftCount, and Acc entries.
(output_operand_type): New parameter "instance". Process it.
(process_i386_operand_type): New local variable "instance".
(main): Adjust static assertions.
* i386-opc.h (INSTANCE_WIDTH): Define.
(enum operand_instance): New.
(Acc, InOutPortReg, ShiftCount): Replace by ClassInstance.
(union i386_operand_type): Replace acc, inoutportreg, and
shiftcount by instance.
* i386-opc.tbl (Acc, InOutPortReg, ShiftCount): Define.
* i386-reg.tbl (st, al, cl, ax, dx, eax, rax, xmm0, st(0)):
Add Instance=.
* i386-init.h, i386-tbl.h: Re-generate.
Arm64: SVE2's smaxp/sminp require operands 1 and 3 to be the same register This is just like for their umaxp/uminp and fmaxp/fminp counterparts.
2019-11-11 20:28:35 +08:00
2019-11-11 Jan Beulich <jbeulich@suse.com>
* aarch64-tbl.h (aarch64_opcode_table): Switch SVE2's
smaxp/sminp entries' "tied_operand" field to 2.
Arm64: fix build with old glibc Some old glibc versions have string.h surface "index", which some compilers then warn about if shadowed by a local variable. Re-use an existing variable instead.
2019-11-11 20:27:47 +08:00
2019-11-11 Jan Beulich <jbeulich@suse.com>
* aarch64-opc.c (operand_general_constraint_met_p): Replace
"index" local variable by that of the already existing "num".
i386: Only check suffix in instruction mnemonic We should check suffix in instruction mnemonic when matching instruction. In Intel syntax, normally we check for memory operand size. But the same mnemonic with 2 different encodings can have the same memory operand size and i.suffix is set to LONG_DOUBLE_MNEM_SUFFIX from memory operand size in Intel syntax to distinguish them. When there is no suffix in mnemonic, we check LONG_DOUBLE_MNEM_SUFFIX in i.suffix for mnemonic suffix. gas/ PR gas/25167 * config/tc-i386.c (match_template): Don't check instruction suffix set from operand. * testsuite/gas/i386/code16.d: New file. * testsuite/gas/i386/code16.s: Likewise. * testsuite/gas/i386/i386.exp: Run code16. * testsuite/gas/i386/x86-64-branch-4.l: Updated. opcodes/ PR gas/25167 * i386-opc.tbl: Remove IgnoreSize from cmpsd and movsd. * i386-tbl.h: Regenerated.
2019-11-09 01:31:06 +08:00
2019-11-08 H.J. Lu <hongjiu.lu@intel.com>
PR gas/25167
* i386-opc.tbl: Remove IgnoreSize from cmpsd and movsd.
* i386-tbl.h: Regenerated.
x86: convert RegMask and RegBND from bitfield to enumerator This is to further shrink the operand type representation.
2019-11-08 16:06:24 +08:00
2019-11-08 Jan Beulich <jbeulich@suse.com>
* i386-gen.c (operand_type_init): Add Class= to
OPERAND_TYPE_REGMASK and OPERAND_TYPE_REGBND entries. Move up
OPERAND_TYPE_REGBND entry.
(operand_classes): Add RegMask and RegBND entries.
(operand_types): Drop RegMask and RegBND entry.
* i386-opc.h (enum operand_class): Add RegMask and RegBND.
(RegMask, RegBND): Delete.
(union i386_operand_type): Remove regmask and regbnd fields.
* i386-opc.tbl (RegMask, RegBND): Define.
* i386-reg.tbl: Replace RegMask by Class=RegMask and RegBND by
Class=RegBND.
* i386-init.h, i386-tbl.h: Re-generate.
x86: convert RegSIMD and RegMMX from bitfield to enumerator This is to further shrink the operand type representation.
2019-11-08 16:05:36 +08:00
2019-11-08 Jan Beulich <jbeulich@suse.com>
* i386-gen.c (operand_type_init): Add Class= to
OPERAND_TYPE_REGMMX, OPERAND_TYPE_REGXMM, OPERAND_TYPE_REGYMM, and
OPERAND_TYPE_REGZMM entries.
(operand_classes): Add RegMMX and RegSIMD entries.
(operand_types): Drop RegMMX and RegSIMD entries.
* i386-opc.h (enum operand_class): Add RegMMX and RegSIMD.
(RegMMX, RegSIMD): Delete.
(union i386_operand_type): Remove regmmx and regsimd fields.
* i386-opc.tbl (RegMMX): Define.
(RegXMM, RegYMM, RegZMM): Add Class=.
* i386-reg.tbl: Replace RegMMX by Class=RegMMX and RegSIMD by
Class=RegSIMD.
* i386-init.h, i386-tbl.h: Re-generate.
x86: convert Control/Debug/Test from bitfield to enumerator This is to further shrink the operand type representation.
2019-11-08 16:04:53 +08:00
2019-11-08 Jan Beulich <jbeulich@suse.com>
* i386-gen.c (operand_type_init): Add Class= to
OPERAND_TYPE_CONTROL, OPERAND_TYPE_TEST, and OPERAND_TYPE_DEBUG
entries.
(operand_classes): Add RegCR, RegDR, and RegTR entries.
(operand_types): Drop Control, Debug, and Test entries.
* i386-opc.h (enum operand_class): Add RegCR, RegDR, and RegTR.
(Control, Debug, Test): Delete.
(union i386_operand_type): Remove control, debug, and test
fields.
* i386-opc.tbl (Control, Debug, Test): Define.
* i386-reg.tbl: Replace Control by Class=RegCR, Debug by
Class=RegDR, and Test by Class=RegTR.
* i386-init.h, i386-tbl.h: Re-generate.
x86: convert SReg from bitfield to enumerator This is to further shrink the operand type representation.
2019-11-08 16:04:09 +08:00
2019-11-08 Jan Beulich <jbeulich@suse.com>
* i386-gen.c (operand_type_init): Add Class= to
OPERAND_TYPE_SREG entry.
(operand_classes): Add SReg entry.
(operand_types): Drop SReg entry.
* i386-opc.h (enum operand_class): Add SReg.
(SReg): Delete.
(union i386_operand_type): Remove sreg field.
* i386-opc.tbl (SReg): Define.
* i386-reg.tbl: Replace SReg by Class=SReg.
* i386-init.h, i386-tbl.h: Re-generate.
x86: introduce operand type "class" Many operand types, in particular the various kinds of registers, can't be combined with one another (neither in templates nor in register entries), and hence it is not a good use of resources (memory as well as execution time) to represent them as individual bits of a bit field.
2019-11-08 16:03:23 +08:00
2019-11-08 Jan Beulich <jbeulich@suse.com>
* i386-gen.c (operand_type_init): Add Class=. New
OPERAND_TYPE_ANYIMM entry.
(operand_classes): New.
(operand_types): Drop Reg entry.
(output_operand_type): New parameter "class". Process it.
(process_i386_operand_type): New local variable "class".
(main): Adjust static assertions.
* i386-opc.h (CLASS_WIDTH): Define.
(enum operand_class): New.
(Reg): Replace by Class. Adjust comment.
(union i386_operand_type): Replace reg by class.
* i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatReg): Add
Class=.
* i386-reg.tbl: Replace Reg by Class=Reg.
* i386-init.h: Re-generate.
[gas][aarch64] Add the v8.6 Data Gathering Hint mnemonic [10/X] Hi, This patch is part of a series that adds support for Armv8.6-A to binutils. In this last patch, the new Data Gathering Hint mnemonic is introduced. Committed on behalf of Mihail Ionescu. gas/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> * testsuite/gas/aarch64/dgh.s: New test. * testsuite/gas/aarch64/dgh.d: New test. opcodes/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> * opcodes/aarch64-tbl.h (V8_6_INSN): New macro for v8.6 instructions. (aarch64_opcode_table): Add data gathering hint mnemonic. * opcodes/aarch64-dis-2.c: Account for new instruction. Is it ok for trunk? Regards, Mihail
2019-11-08 01:22:45 +08:00
2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
* opcodes/aarch64-tbl.h (V8_6_INSN): New macro for v8.6 instructions.
(aarch64_opcode_table): Add data gathering hint mnemonic.
* opcodes/aarch64-dis-2.c: Account for new instruction.
[Patch][binutils][arm] Armv8.6-A Matrix Multiply extension [9/10] Hi, This patch is part of a series that adds support for Armv8.6-A (Matrix Multiply and BFloat16 extensions) to binutils. This patch introduces the Matrix Multiply (Int8, F32, F64) extensions to the arm backend. The following Matrix Multiply instructions are added: vummla, vsmmla, vusmmla, vusdot, vsudot[1]. [1]https://developer.arm.com/docs/ddi0597/latest/simd-and-floating-point-instructions-alphabetic-order Committed on behalf of Mihail Ionescu. gas/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> * config/tc-arm.c (arm_ext_i8mm): New feature set. (do_vusdot): New. (do_vsudot): New. (do_vsmmla): New. (do_vummla): New. (insns): Add vsmmla, vummla, vusmmla, vusdot, vsudot mnemonics. (armv86a_ext_table): Add i8mm extension. (arm_extensions): Move bf16 extension to context sensitive table. (armv82a_ext_table, armv84a_ext_table, armv85a_ext_table): Move bf16 extension to context sensitive table. (armv86a_ext_table): Add i8mm extension. * doc/c-arm.texi: Document i8mm extension. * testsuite/gas/arm/i8mm.s: New test. * testsuite/gas/arm/i8mm.d: New test. * testsuite/gas/arm/bfloat17-cmdline-bad-3.d: Update test. include/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> * opcode/arm.h (ARM_EXT2_I8MM): New feature macro. opcodes/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> * arm-dis.c (neon_opcodes): Add i8mm SIMD instructions. Regression tested on arm-none-eabi. Is this ok for trunk? Regards, Mihail
2019-11-08 01:20:08 +08:00
2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
* arm-dis.c (neon_opcodes): Add i8mm SIMD instructions.
[binutils][aarch64] Matrix Multiply extension enablement [8/X] Hi, This patch is part of a series that adds support for Armv8.6-A (Matrix Multiply and BFloat16 extensions) to binutils. This patch introduces the Matrix Multiply (Int8, F32, F64) extensions to the aarch64 backend. The following instructions are added: {s/u}mmla, usmmla, {us/su}dot, fmmla, ld1rob, ld1roh, d1row, ld1rod, uzip{1/2}, trn{1/2}. Committed on behalf of Mihail Ionescu. gas/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> * config/tc-aarch64.c: Add new arch fetures to suppport the mm extension. (parse_operands): Add new operand. * testsuite/gas/aarch64/i8mm.s: New test. * testsuite/gas/aarch64/i8mm.d: New test. * testsuite/gas/aarch64/f32mm.s: New test. * testsuite/gas/aarch64/f32mm.d: New test. * testsuite/gas/aarch64/f64mm.s: New test. * testsuite/gas/aarch64/f64mm.d: New test. * testsuite/gas/aarch64/sve-movprfx-mm.s: New test. * testsuite/gas/aarch64/sve-movprfx-mm.d: New test. include/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> * opcode/aarch64.h (AARCH64_FEATURE_I8MM): New. (AARCH64_FEATURE_F32MM): New. (AARCH64_FEATURE_F64MM): New. (AARCH64_OPND_SVE_ADDR_RI_S4x32): New. (enum aarch64_insn_class): Add new instruction class "aarch64_misc" for instructions that do not require special handling. opcodes/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> * aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve, aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm, aarch64_feature_f64mm): New feature sets. (INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN, F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply instructions. (I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set macros. (QL_MMLA64, OP_SVE_SBB): New qualifiers. (OP_SVE_QQQ): New qualifier. (INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC, F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support the movprfx constraint. (aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32. (aarch64_opcode_table): Define new instructions smmla, ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod uzip{1/2}, trn{1/2}. * aarch64-opc.c (operand_general_constraint_met_p): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32. (aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32. * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode): Account for new instructions. * opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new S4x32 operand. * aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand. Regression tested on arm-none-eabi. Is it ok for trunk? Regards, Mihail
2019-11-08 01:10:01 +08:00
2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
* aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve,
aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm,
aarch64_feature_f64mm): New feature sets.
(INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN,
F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply
instructions.
(I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set
macros.
(QL_MMLA64, OP_SVE_SBB): New qualifiers.
(OP_SVE_QQQ): New qualifier.
(INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC,
F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support
the movprfx constraint.
(aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32.
(aarch64_opcode_table): Define new instructions smmla,
ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod,
uzip{1/2}, trn{1/2}.
* aarch64-opc.c (operand_general_constraint_met_p): Handle
AARCH64_OPND_SVE_ADDR_RI_S4x32.
(aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32.
* aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode):
Account for new instructions.
* opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new
S4x32 operand.
* aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand.
[binutils][arm] BFloat16 enablement [4/X] Hi, This patch is part of a series that adds support for Armv8.6-A (Matrix Multiply and BFloat16 extensions) to binutils. This patch introduces BFloat16 instructions to the arm backend. The following BFloat16 instructions are added: vdot, vfma{l/t}, vmmla, vfmal{t/b}, vcvt, vcvt{t/b}. gas/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com> * config/tc-arm.c (arm_archs): Add armv8.6-a option. (cpu_arch_ver): Add TAG_CPU_ARCH_V8 tag for Armv8.6-a. * doc/c-arm.texi (-march): New armv8.6-a arch. * config/tc-arm.c (arm_ext_bf16): New feature set. (enum neon_el_type): Add NT_bfloat value. (B_MNEM_vfmat, B_MNEM_vfmab): New bfloat16 encoder helpers. (BAD_BF16): New message. (parse_neon_type): Add bf16 type specifier. (enum neon_type_mask): Add N_BF16 type. (type_chk_of_el_type): Account for NT_bfloat. (el_type_of_type_chk): Account for N_BF16. (neon_three_args): Split out from neon_three_same. (neon_three_same): Part split out into neon_three_args. (CVT_FLAVOUR_VAR): Add bf16_f32 cvt flavour. (do_neon_cvt_1): Account for vcvt.bf16.f32. (do_bfloat_vmla): New. (do_mve_vfma): New function to deal with the mnemonic clash between the BF16 vfmat and the MVE vfma in a VPT block with a 't'rue condition. (do_neon_cvttb_1): Account for vcvt{t,b}.bf16.f32. (do_vdot): New (do_vmmla): New (insns): Add vdot and vmmla mnemonics. (arm_extensions): Add "bf16" extension. * doc/c-arm.texi: Document "bf16" extension. * testsuite/gas/arm/attr-march-armv8_6-a.d: New test. * testsuite/gas/arm/bfloat16-bad.d: New test. * testsuite/gas/arm/bfloat16-bad.l: New test. * testsuite/gas/arm/bfloat16-bad.s: New test. * testsuite/gas/arm/bfloat16-cmdline-bad-2.d: New test. * testsuite/gas/arm/bfloat16-cmdline-bad-3.d: New test. * testsuite/gas/arm/bfloat16-cmdline-bad.d: New test. * testsuite/gas/arm/bfloat16-neon.s: New test. * testsuite/gas/arm/bfloat16-non-neon.s: New test. * testsuite/gas/arm/bfloat16-thumb-bad.d: New test. * testsuite/gas/arm/bfloat16-thumb-bad.l: New test. * testsuite/gas/arm/bfloat16-thumb.d: New test. * testsuite/gas/arm/bfloat16-vfp.d: New test. * testsuite/gas/arm/bfloat16.d: New test. * testsuite/gas/arm/bfloat16.s: New test. include/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/arm.h (ARM_EXT2_V8_6A, ARM_AEXT2_V8_6A, ARM_ARCH_V8_6A): New. * opcode/arm.h (ARM_EXT2_BF16): New feature macro. (ARM_AEXT2_V8_6A): Include above macro in definition. opcodes/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com> * arm-dis.c (select_arm_features): Update bfd_march_arm_8 with Armv8.6-A. (coprocessor_opcodes): Add bfloat16 vcvt{t,b}. (neon_opcodes): Add bfloat SIMD instructions. (print_insn_coprocessor): Add new control character %b to print condition code without checking cp_num. (print_insn_neon): Account for BFloat16 instructions that have no special top-byte handling. Regression tested on arm-none-eabi. Is it ok for trunk? Regards, Mihail
2019-11-08 00:56:12 +08:00
2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
* arm-dis.c (select_arm_features): Update bfd_march_arm_8 with
Armv8.6-A.
(coprocessor_opcodes): Add bfloat16 vcvt{t,b}.
(neon_opcodes): Add bfloat SIMD instructions.
(print_insn_coprocessor): Add new control character %b to print
condition code without checking cp_num.
(print_insn_neon): Account for BFloat16 instructions that have no
special top-byte handling.
[Patch][binutils][arm] Create a new generic coprocessor array [3/10] Hi, This patch is part of a series that adds support for Armv8.6-A (Matrix Multiply and BFloat16 extensions) to binutils. Some generic instructions match a large range of encoding space (e.g. stc, mcr, mrc). Currently these instructions are in the coprocessor_opcodes array, which means they are checked before many other instructions when disassembling arm and thumb32 codes. This patch moves the generic instructions into a separate array to be checked later on. This is done in order to avoid instruction conflict between the generic instructions and newer ones -- this has already been seen with MVE, and is also a problem with BFloat16. One way to avoid the conflict could be to swap the search order between coprocessor_opcodes and neon_opcodes. We avoid this since it's a larger change that may introduce extra bugs (that aren't caught by the testsuite). We have decided against searching the generic array after searching the arm specific and thumb32 specific arrays with a similar reasoning about keeping the change small. Regression tested with arm-none-linux-gnueabihf. Committed on behalf of Mihail Ionescu. opcodes/ChangeLog: 2019-10-29 Mihail Ionescu <mihail.ionescu@arm.com> 2019-10-29 Matthew Malcomson <matthew.malcomson@arm.com> * arm-dis.c (print_insn_coprocessor, print_insn_generic_coprocessor): Create wrapper functions around the implementation of the print_insn_coprocessor control codes. (print_insn_coprocessor_1): Original print_insn_coprocessor function that now takes which array to look at as an argument. (print_insn_arm): Use both print_insn_coprocessor and print_insn_generic_coprocessor. (print_insn_thumb32): As above. Is it ok for trunk? Regards, Mihail
2019-11-08 00:53:40 +08:00
2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
* arm-dis.c (print_insn_coprocessor,
print_insn_generic_coprocessor): Create wrapper functions around
the implementation of the print_insn_coprocessor control codes.
(print_insn_coprocessor_1): Original print_insn_coprocessor
function that now takes which array to look at as an argument.
(print_insn_arm): Use both print_insn_coprocessor and
print_insn_generic_coprocessor.
(print_insn_thumb32): As above.
[binutils][aarch64] Bfloat16 enablement [2/X] Hi, This patch is part of a series that adds support for Armv8.6-A (Matrix Multiply and BFloat16 extensions) to binutils. This patch introduces the following BFloat16 instructions to the aarch64 backend: bfdot, bfmmla, bfcvt, bfcvtnt, bfmlal[t/b], bfcvtn2. Committed on behalf of Mihail Ionescu. gas/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com> * config/tc-aarch64.c (vectype_to_qualifier): Special case the S_2H operand qualifier. * doc/c-aarch64.texi: Document bf16 and bf16mmla4 extensions. * testsuite/gas/aarch64/bfloat16.d: New test. * testsuite/gas/aarch64/bfloat16.s: New test. * testsuite/gas/aarch64/illegal-bfloat16.d: New test. * testsuite/gas/aarch64/illegal-bfloat16.l: New test. * testsuite/gas/aarch64/illegal-bfloat16.s: New test. * testsuite/gas/aarch64/sve-bfloat-movprfx.s: New test. * testsuite/gas/aarch64/sve-bfloat-movprfx.d: New test. include/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/aarch64.h (AARCH64_FEATURE_BFLOAT16): New feature macros. (AARCH64_ARCH_V8_6): Include BFloat16 feature macros. (enum aarch64_opnd_qualifier): Introduce new operand qualifier AARCH64_OPND_QLF_S_2H. (enum aarch64_insn_class): Introduce new class "bfloat16". (BFLOAT16_SVE_INSNC): New feature set for bfloat16 instructions to support the movprfx constraint. opcodes/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H in reglane special case. * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode): Account for new instructions. * aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H in reglane special case. * aarch64-opc.c (struct operand_qualifier_data): Add data for new AARCH64_OPND_QLF_S_2H qualifier. * aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2, QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers. (aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve, aarch64_feature_bfloat16_bfmmla4): New feature sets. (BFLOAT_SVE, BFLOAT): New feature set macros. (BFLOAT_SVE_INSN, BFLOAT_BFMMLA4_INSN, BFLOAT_INSN): New macros to define BFloat16 instructions. (aarch64_opcode_table): Define new instructions bfdot, bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t] bfcvtn2, bfcvt. Regression tested on aarch64-elf. Is it ok for trunk? Regards, Mihail
2019-11-08 00:38:59 +08:00
2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H
in reglane special case.
* aarch64-dis-2.c (aarch64_opcode_lookup_1,
aarch64_find_next_opcode): Account for new instructions.
* aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H
in reglane special case.
* aarch64-opc.c (struct operand_qualifier_data): Add data for
new AARCH64_OPND_QLF_S_2H qualifier.
* aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2,
QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers.
(aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve): New feature
sets.
(BFLOAT_SVE, BFLOAT): New feature set macros.
(BFLOAT_SVE_INSN, BFLOAT_INSN): New macros to define BFloat16
instructions.
(aarch64_opcode_table): Define new instructions bfdot,
bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t]
bfcvtn2, bfcvt.
[gas][aarch64] Armv8.6-a option [1/X] Hi, This patch is part of a series that adds support for Armv8.6-A to binutils. This first patch adds the Armv8.6-A flag to binutils. No instructions are behind it at the moment. Commited on behalf of Mihail Ionescu. gas/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com> * config/tc-aarch64.c (armv8.6-a): New arch. * doc/c-aarch64.texi (armv8.6-a): Document new arch. include/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/aarch64.h (AARCH64_FEATURE_V8_6): New. (AARCH64_ARCH_V8_6): New. opcodes/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-tbl.h (ARMV8_6): New macro. Is it ok for trunk? Regards, Mihail
2019-11-08 00:18:51 +08:00
2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-tbl.h (ARMV8_6): New macro.
x86: support further AMD Zen2 instructions Both RDPRU and MCOMMIT have been publicly documented meanwhile: https://www.amd.com/system/files/TechDocs/24594.pdf.
2019-11-07 16:29:14 +08:00
2019-11-07 Jan Beulich <jbeulich@suse.com>
* i386-dis.c (prefix_table): Add mcommit.
(rm_table): Add rdpru.
* i386-gen.c (cpu_flag_init): Adjust CPU_ZNVER2_FLAGS entry. Add
CPU_RDPRU_FLAGS and CPU_MCOMMIT_FLAGS entries.
(cpu_flags): Add CpuRDPRU and CpuMCOMMIT entries.
* i386-opc.h (CpuRDPRU, CpuMCOMMIT): New.
(union i386_cpu_flags): Add cpurdpru and cpumcommit fields.
* i386-opc.tbl (mcommit, rdpru): New.
* i386-init.h, i386-tbl.h: Re-generate.
x86: adjust register names printed for MONITOR/MWAIT As the comments (here: almost, in the opcode table: fully) correctly state - all register operands except MONITOR's address one are fixed at 32 bit size. Don't print 64-bit registers there. Also adjust x86-64-suffix.d's name such that it wouldn't be identical to x86-64-rep-suffix.d's, but instead resemble that of its sibling x86-64-suffix-intel.d.
2019-11-07 16:28:20 +08:00
2019-11-07 Jan Beulich <jbeulich@suse.com>
* i386-dis.c (OP_Mwait): Drop local variable "names", use
"names32" instead.
(OP_Monitor): Drop local variable "op1_names", re-purpose
"names" for it instead, and replace former "names" uses by
"names32" ones.
x86/Intel: drop IgnoreSize from operand-less MOVSD/CMPSD again These were mistakenly added by d241b91073 ("x86/Intel: correct MOVSD and CMPSD handling"). This addresses part of PR/gas 25167.
2019-11-07 16:27:16 +08:00
2019-11-07 Jan Beulich <jbeulich@suse.com>
PR/gas 25167
* opcodes/i386-opc.tbl (movsd, cmpsd): Drop IgnoreSize from
operand-less forms.
* opcodes/i386-tbl.h: Re-generate.
x86: fold OP_Mwaitx() into OP_Mwait() There's no need to have separate functions, the difference can easily be expressed using the function arguments.
2019-11-05 16:19:50 +08:00
2019-11-05 Jan Beulich <jbeulich@suse.com>
* i386-dis.c (OP_Mwaitx): Delete.
(prefix_table): Use OP_Mwait for mwaitx entry.
(OP_Mwait): Also handle mwaitx.
x86: split MONITORX/MWAITX entries Both encodings do not ignore the 66/F3/F2 prefixes, so don't have the disassembler ignore them either.
2019-11-05 16:19:10 +08:00
2019-11-05 Jan Beulich <jbeulich@suse.com>
* i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_2,
PREFIX_0F01_REG_7_MOD_3_RM_3): New.
(prefix_table): Add respective entries.
(rm_table): Link to those entries.
x86: consolidate disassembler enum naming a little The original idea looks to have been for names to be composed in the order that decoding gets done, which helps both reading and modifying the code. Switch (back) to this model for some of the affected non- vector insn enumerators.
2019-11-05 16:18:23 +08:00
2019-11-05 Jan Beulich <jbeulich@suse.com>
* i386-dis.c (REG_0F1C_MOD_0): Rename to ...
(REG_0F1C_P_0_MOD_0): ... this.
(REG_0F1E_MOD_3): Rename to ...
(REG_0F1E_P_1_MOD_3): ... this.
(RM_0F01_REG_5): Rename to ...
(RM_0F01_REG_5_MOD_3): ... this.
(RM_0F01_REG_7): Rename to ...
(RM_0F01_REG_7_MOD_3): ... this.
(RM_0F1E_MOD_3_REG_7): Rename to ...
(RM_0F1E_P_1_MOD_3_REG_7): ... this.
(RM_0FAE_REG_6): Rename to ...
(RM_0FAE_REG_6_MOD_3_P_0): ... this.
(RM_0FAE_REG_7): Rename to ...
(RM_0FAE_REG_7_MOD_3): ... this.
(PREFIX_MOD_0_0F01_REG_5): Rename to ...
(PREFIX_0F01_REG_5_MOD_0): ... this.
(PREFIX_MOD_3_0F01_REG_5_RM_0): Rename to ...
(PREFIX_0F01_REG_5_MOD_3_RM_0): ... this.
(PREFIX_MOD_3_0F01_REG_5_RM_2): Rename to ...
(PREFIX_0F01_REG_5_MOD_3_RM_2): ... this.
(PREFIX_0FAE_REG_0): Rename to ...
(PREFIX_0FAE_REG_0_MOD_3): ... this.
(PREFIX_0FAE_REG_1): Rename to ...
(PREFIX_0FAE_REG_1_MOD_3): ... this.
(PREFIX_0FAE_REG_2): Rename to ...
(PREFIX_0FAE_REG_2_MOD_3): ... this.
(PREFIX_0FAE_REG_3): Rename to ...
(PREFIX_0FAE_REG_3_MOD_3): ... this.
(PREFIX_MOD_0_0FAE_REG_4): Rename to ...
(PREFIX_0FAE_REG_4_MOD_0): ... this.
(PREFIX_MOD_3_0FAE_REG_4): Rename to ...
(PREFIX_0FAE_REG_4_MOD_3): ... this.
(PREFIX_MOD_0_0FAE_REG_5): Rename to ...
(PREFIX_0FAE_REG_5_MOD_0): ... this.
(PREFIX_MOD_3_0FAE_REG_5): Rename to ...
(PREFIX_0FAE_REG_5_MOD_3): ... this.
(PREFIX_MOD_0_0FAE_REG_6): Rename to ...
(PREFIX_0FAE_REG_6_MOD_0): ... this.
(PREFIX_MOD_1_0FAE_REG_6): Rename to ...
(PREFIX_0FAE_REG_6_MOD_3): ... this.
(PREFIX_0FAE_REG_7): Rename to ...
(PREFIX_0FAE_REG_7_MOD_0): ... this.
(PREFIX_MOD_0_0FC3): Rename to ...
(PREFIX_0FC3_MOD_0): ... this.
(PREFIX_MOD_0_0FC7_REG_6): Rename to ...
(PREFIX_0FC7_REG_6_MOD_0): ... this.
(PREFIX_MOD_3_0FC7_REG_6): Rename to ...
(PREFIX_0FC7_REG_6_MOD_3): ... this.
(PREFIX_MOD_3_0FC7_REG_7): Rename to ...
(PREFIX_0FC7_REG_7_MOD_3): ... this.
(reg_table, prefix_table, mod_table, rm_table): Adjust
accordingly.
Fix potential array overruns when disassembling corrupt v850 binaries. * v850-dis.c (get_v850_sreg_name): New function. Returns the name of a v850 system register. Move the v850_sreg_names array into this function. (get_v850_reg_name): Likewise for ordinary register names. (get_v850_vreg_name): Likewise for vector register names. (get_v850_cc_name): Likewise for condition codes. * get_v850_float_cc_name): Likewise for floating point condition codes. (get_v850_cacheop_name): Likewise for cache-ops. (get_v850_prefop_name): Likewise for pref-ops. (disassemble): Use the new accessor functions.
2019-11-04 20:02:20 +08:00
2019-11-04 Nick Clifton <nickc@redhat.com>
* v850-dis.c (get_v850_sreg_name): New function. Returns the name
of a v850 system register. Move the v850_sreg_names array into
this function.
(get_v850_reg_name): Likewise for ordinary register names.
(get_v850_vreg_name): Likewise for vector register names.
(get_v850_cc_name): Likewise for condition codes.
* get_v850_float_cc_name): Likewise for floating point condition
codes.
(get_v850_cacheop_name): Likewise for cache-ops.
(get_v850_prefop_name): Likewise for pref-ops.
(disassemble): Use the new accessor functions.
Modify the ARNM assembler to accept the omission of the immediate argument for the writeback form of the LDRAA and LDRAB mnemonics This is a shorthand for the immediate argument being 0, as described here: https://developer.arm.com/docs/ddi0596/latest/base-instructions-alphabetic-order/ldraa-ldrab-load-register-with-pointer-authentication This is because the instructions still have a use with an immediate argument of 0, unlike loads without the PAC functionality. Currently, the mnemonics are LDRAA Xt, [Xn, #<simm10>]! LDRAB Xt, [Xn, #<simm10>]! After this patch they become LDRAA Xt, [Xn {, #<simm10>}]! LDRAB Xt, [Xn {, #<simm10>}]! gas * config/tc-aarch64.c (parse_address_main): Accept the omission of the immediate argument for ldraa and ldrab as a shorthand for the immediate being 0. * testsuite/gas/aarch64/ldraa-ldrab-no-offset.d: New test. * testsuite/gas/aarch64/ldraa-ldrab-no-offset.s: New test. * testsuite/gas/aarch64/illegal-ldraa.s: Modified to accept the writeback form with no offset. * testsuite/gas/aarch64/illegal-ldraa.s: Removed missing offset error. opcodes * aarch64-opc.c (print_immediate_offset_address): Don't print the immediate for the writeback form of ldraa/ldrab if it is 0. * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10. * aarch64-opc-2.c: Regenerated.
2019-10-30 21:23:35 +08:00
2019-10-30 Delia Burduv <delia.burduv@arm.com>
* aarch64-opc.c (print_immediate_offset_address): Don't print the
immediate for the writeback form of ldraa/ldrab if it is 0.
* aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
* aarch64-opc-2.c: Regenerated.
x86: re-do "shorthand" handling Now that the opcode table gets preprocessed, undo parts of commit dc821c5f9a ("x86: replace Reg8, Reg16, Reg32, and Reg64"): Have the preprocessor handle the expansion there, while making the expansions explicit in i386-gen and the register table.
2019-10-30 16:07:40 +08:00
2019-10-30 Jan Beulich <jbeulich@suse.com>
* i386-gen.c (operand_type_shorthands): Delete.
(operand_type_init): Expand previous shorthands.
(set_bitfield_from_shorthand): Rename back to ...
(set_bitfield_from_cpu_flag_init): ... this. Drop processing
of operand_type_init[].
(set_bitfield): Adjust call to the above function.
* i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
RegXMM, RegYMM, RegZMM): Define.
* i386-reg.tbl: Expand prior shorthands.
x86: slightly rearrange struct insn_template This avoids holes between the individual fields, (potentially) shrinking the overall template table size by 4 bytes per entry.
2019-10-30 16:06:42 +08:00
2019-10-30 Jan Beulich <jbeulich@suse.com>
* i386-gen.c (output_i386_opcode): Change order of fields
emitted to output.
* i386-opc.h (struct insn_template): Move operands field.
Convert extension_opcode field to unsigned short.
* i386-tbl.h: Re-generate.
x86: drop stray W The flag is used to indicate opcodes which can be switched between byte and word/dword/qword forms (in a "canonical" way). Obviously it's quite odd then to see it on insns not allowing for byte operands in the first place. As a result the opcode bytes need to be adjusted accordingly, which includes comparisons done in optimize_encoding(). To make re-introduction of such issues less likely have i386-gen diagnose it (in a generally non-fatal way for now).
2019-10-30 16:05:46 +08:00
2019-10-30 Jan Beulich <jbeulich@suse.com>
* i386-gen.c (process_i386_opcode_modifier): Report bogus uses
of W.
* i386-opc.h (W): Extend comment.
* i386-opc.tbl (mov, movabs, movq): Drop W and adjust opcodes of
general purpose variants not allowing for byte operands.
* i386-tbl.h: Re-generate.
Fix array overrun when disassembling corrupt TIC30 binaries. * tic30-dis.c (print_branch): Correct size of operand array.
2019-10-29 23:35:30 +08:00
2019-10-29 Nick Clifton <nickc@redhat.com>
* tic30-dis.c (print_branch): Correct size of operand array.
Fix a potential illegal array access in the D30V disassembler. * d30v-dis.c (print_insn): Check that operand index is valid before attempting to access the operands array.
2019-10-29 18:25:09 +08:00
2019-10-29 Nick Clifton <nickc@redhat.com>
* d30v-dis.c (print_insn): Check that operand index is valid
before attempting to access the operands array.
Prevent a left shift by a negative value when disassembling IA64 binaries. * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when locating the bit to be tested.
2019-10-29 18:01:27 +08:00
2019-10-29 Nick Clifton <nickc@redhat.com>
* ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
locating the bit to be tested.
Fix array overruns in the S12Z disassembler. * s12z-dis.c (opr_emit_disassembly): Check for illegal register values. (shift_size_table): Use a fixed size defined as S12Z_N_SIZES. (print_insn_s12z): Check for illegal size values.
2019-10-29 17:17:39 +08:00
2019-10-29 Nick Clifton <nickc@redhat.com>
* s12z-dis.c (opr_emit_disassembly): Check for illegal register
values.
(shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
(print_insn_s12z): Check for illegal size values.
Fix potentially illegal shift and assign operation in CSKY disassembler. * csky-dis.c (csky_chars_to_number): Check for a negative count. Use an unsigned integer to construct the return value.
2019-10-29 00:45:55 +08:00
2019-10-28 Nick Clifton <nickc@redhat.com>
* csky-dis.c (csky_chars_to_number): Check for a negative
count. Use an unsigned integer to construct the return value.
Fix buffer overrun in TIC30 disassembler. * tic30-dis.c (OPERAND_BUFFER_LEN): Define. Use as length of operand buffer. Set value to 15 not 13. (get_register_operand): Use OPERAND_BUFFER_LEN. (get_indirect_operand): Likewise. (print_two_operand): Likewise. (print_three_operand): Likewise. (print_oar_insn): Likewise.
2019-10-29 00:15:34 +08:00
2019-10-28 Nick Clifton <nickc@redhat.com>
* tic30-dis.c (OPERAND_BUFFER_LEN): Define. Use as length of
operand buffer. Set value to 15 not 13.
(get_register_operand): Use OPERAND_BUFFER_LEN.
(get_indirect_operand): Likewise.
(print_two_operand): Likewise.
(print_three_operand): Likewise.
(print_oar_insn): Likewise.
Stop potential illegal memory access in the NS32K disassembler. * ns32k-dis.c (bit_extract): Add sanitiy check of parameters. (bit_extract_simple): Likewise. (bit_copy): Likewise. (pirnt_insn_ns32k): Ensure that uninitialised elements in the index_offset array are not accessed.
2019-10-28 23:44:23 +08:00
2019-10-28 Nick Clifton <nickc@redhat.com>
* ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
(bit_extract_simple): Likewise.
(bit_copy): Likewise.
(pirnt_insn_ns32k): Ensure that uninitialised elements in the
index_offset array are not accessed.
Prevent an illegal memory access in the xgate disassembler. * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA operand.
2019-10-28 23:06:32 +08:00
2019-10-28 Nick Clifton <nickc@redhat.com>
* xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
operand.
Fix potential undefined behaviour in the RX disassembler. * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct access to opcodes.op array element.
2019-10-25 23:10:04 +08:00
2019-10-25 Nick Clifton <nickc@redhat.com>
* rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
access to opcodes.op array element.
Fix typo in RX disassembler error messages. * rx-dis.c (get_register_name): Fix spelling typo in error message. (get_condition_name, get_flag_name, get_double_register_name) (get_double_register_high_name, get_double_register_low_name) (get_double_control_register_name, get_double_condition_name) (get_opsize_name, get_size_name): Likewise.
2019-10-23 17:17:21 +08:00
2019-10-23 Nick Clifton <nickc@redhat.com>
* rx-dis.c (get_register_name): Fix spelling typo in error
message.
(get_condition_name, get_flag_name, get_double_register_name)
(get_double_register_high_name, get_double_register_low_name)
(get_double_control_register_name, get_double_condition_name)
(get_opsize_name, get_size_name): Likewise.
Prevent more potential illegal memory accesses in the RX disassembler. * rx-dis.c (get_size_name): New function. Provides safe access to name array. (get_opsize_name): Likewise. (print_insn_rx): Use the accessor functions.
2019-10-22 19:01:45 +08:00
2019-10-22 Nick Clifton <nickc@redhat.com>
* rx-dis.c (get_size_name): New function. Provides safe
access to name array.
(get_opsize_name): Likewise.
(print_insn_rx): Use the accessor functions.
Fix potential illegal memory access when disassembling corrupt RX binaries. opcodes * rx-dis.c (get_register_name): New function. Provides safe access to name array. (get_condition_name, get_flag_name, get_double_register_name) (get_double_register_high_name, get_double_register_low_name) (get_double_control_register_name, get_double_condition_name): Likewise. (print_insn_rx): Use the accessor functions.
2019-10-16 19:56:58 +08:00
2019-10-16 Nick Clifton <nickc@redhat.com>
* rx-dis.c (get_register_name): New function. Provides safe
access to name array.
(get_condition_name, get_flag_name, get_double_register_name)
(get_double_register_high_name, get_double_register_low_name)
(get_double_control_register_name, get_double_condition_name):
Likewise.
(print_insn_rx): Use the accessor functions.
Fix the disassembly of the LDS and STS instructions of the AVR architecture. PR 25041 opcodes * avr-dis.c (avr_operand): Fix construction of address for lds/sts instructions. gas * testsuite/gas/avr/pr25041.s: New test. * testsuite/gas/avr/pr25041.d: New test driver.
2019-10-09 20:48:06 +08:00
2019-10-09 Nick Clifton <nickc@redhat.com>
PR 25041
* avr-dis.c (avr_operand): Fix construction of address for lds/sts
instructions.
x86/Intel: correct MOVSD and CMPSD handling First and foremost the EsSeg attribute was misplaced for CMPSD. Then both it and MOVSD were lacking Dword on both of their operands. Finally string insns with multiple operands and requiring use of ES: had the wrong operand number reported in the diagnostic.
2019-10-07 14:38:01 +08:00
2019-10-07 Jan Beulich <jbeulich@suse.com>
* opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
(cmpsd): Likewise. Move EsSeg to other operand.
* opcodes/i386-tbl.h: Re-generate.
m68k bfd.h tidy bfd/ * bfd-in.h: Move m68k function declaration.. * cpu-m68k.h: ..to here, new file.. * elf32-m68k.h: ..and here, new file. * elf32-m68k.c: Include cpu-m68k.h and elf32-m68k.h. * bfd-in2.h: Regenerate. ld/ * emultempl/m68kelf.em: Include elf32-m68k.h. opcodes/ * m68k-dis.c: Include cpu-m68k.h
2019-09-23 08:41:29 +08:00
2019-09-23 Alan Modra <amodra@gmail.com>
* m68k-dis.c: Include cpu-m68k.h
mips bfd.h tidy bfd/ * bfd-in.h: Move mips function declaration to.. * elfxx-mips.h: ..here. * bfd-in2.h: Regenerate. opcodes/ * mips-dis.c: Include elfxx-mips.h. Move "elf-bfd.h" and "elf/mips.h" earlier.
2019-09-23 08:30:21 +08:00
2019-09-23 Alan Modra <amodra@gmail.com>
* mips-dis.c: Include elfxx-mips.h. Move "elf-bfd.h" and
"elf/mips.h" earlier.
x86-64: fix handling of PUSH/POP of segment register Commit 21df382b91 ("x86: fold SReg{2,3}") went too far: Folding 64-bit PUSH/POP templates into non-64-bit ones isn't correct, due to the different operand widths, and hence suffixes permitted. Restore the separate templates. Add tests of PUSH/POP with q suffix and %fs/%gs operands to the testsuite. While doing so also add PUSHF/POPF ones _without_ suffix.
2019-09-20 16:18:15 +08:00
2018-09-20 Jan Beulich <jbeulich@suse.com>
PR gas/25012
* i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
with SReg operand.
* i386-tbl.h: Re-generate.
bfd_section_* macros This large patch removes the unnecessary bfd parameter from various bfd section macros and functions. The bfd is hardly ever used and if needed for the bfd_set_section_* or bfd_rename_section functions can be found via section->owner except for the com, und, abs, and ind std_section special sections. Those sections shouldn't be modified anyway. The patch also removes various bfd_get_section_<field> macros, replacing their use with bfd_section_<field>, and adds bfd_set_section_lma. I've also fixed a minor bug in gas where compressed section renaming was done directly rather than calling bfd_rename_section. This would have broken bfd_get_section_by_name and similar functions, but that hardly mattered at such a late stage in gas processing. bfd/ * bfd-in.h (bfd_get_section_name, bfd_get_section_vma), (bfd_get_section_lma, bfd_get_section_alignment), (bfd_get_section_size, bfd_get_section_flags), (bfd_get_section_userdata): Delete. (bfd_section_name, bfd_section_size, bfd_section_vma), (bfd_section_lma, bfd_section_alignment): Lose bfd parameter. (bfd_section_flags, bfd_section_userdata): New. (bfd_is_com_section): Rename parameter. * section.c (bfd_set_section_userdata, bfd_set_section_vma), (bfd_set_section_alignment, bfd_set_section_flags, bfd_rename_section), (bfd_set_section_size): Delete bfd parameter, rename section parameter. (bfd_set_section_lma): New. * bfd-in2.h: Regenerate. * mach-o.c (bfd_mach_o_init_section_from_mach_o): Delete bfd param, update callers. * aoutx.h, * bfd.c, * coff-alpha.c, * coff-arm.c, * coff-mips.c, * coff64-rs6000.c, * coffcode.h, * coffgen.c, * cofflink.c, * compress.c, * ecoff.c, * elf-eh-frame.c, * elf-hppa.h, * elf-ifunc.c, * elf-m10200.c, * elf-m10300.c, * elf-properties.c, * elf-s390-common.c, * elf-vxworks.c, * elf.c, * elf32-arc.c, * elf32-arm.c, * elf32-avr.c, * elf32-bfin.c, * elf32-cr16.c, * elf32-cr16c.c, * elf32-cris.c, * elf32-crx.c, * elf32-csky.c, * elf32-d10v.c, * elf32-epiphany.c, * elf32-fr30.c, * elf32-frv.c, * elf32-ft32.c, * elf32-h8300.c, * elf32-hppa.c, * elf32-i386.c, * elf32-ip2k.c, * elf32-iq2000.c, * elf32-lm32.c, * elf32-m32c.c, * elf32-m32r.c, * elf32-m68hc1x.c, * elf32-m68k.c, * elf32-mcore.c, * elf32-mep.c, * elf32-metag.c, * elf32-microblaze.c, * elf32-moxie.c, * elf32-msp430.c, * elf32-mt.c, * elf32-nds32.c, * elf32-nios2.c, * elf32-or1k.c, * elf32-ppc.c, * elf32-pru.c, * elf32-rl78.c, * elf32-rx.c, * elf32-s390.c, * elf32-score.c, * elf32-score7.c, * elf32-sh.c, * elf32-spu.c, * elf32-tic6x.c, * elf32-tilepro.c, * elf32-v850.c, * elf32-vax.c, * elf32-visium.c, * elf32-xstormy16.c, * elf32-xtensa.c, * elf64-alpha.c, * elf64-bpf.c, * elf64-hppa.c, * elf64-ia64-vms.c, * elf64-mmix.c, * elf64-ppc.c, * elf64-s390.c, * elf64-sparc.c, * elf64-x86-64.c, * elflink.c, * elfnn-aarch64.c, * elfnn-ia64.c, * elfnn-riscv.c, * elfxx-aarch64.c, * elfxx-mips.c, * elfxx-sparc.c, * elfxx-tilegx.c, * elfxx-x86.c, * i386msdos.c, * linker.c, * mach-o.c, * mmo.c, * opncls.c, * pdp11.c, * pei-x86_64.c, * peicode.h, * reloc.c, * section.c, * syms.c, * vms-alpha.c, * xcofflink.c: Update throughout for bfd section macro and function changes. binutils/ * addr2line.c, * bucomm.c, * coffgrok.c, * dlltool.c, * nm.c, * objcopy.c, * objdump.c, * od-elf32_avr.c, * od-macho.c, * od-xcoff.c, * prdbg.c, * rdcoff.c, * rddbg.c, * rescoff.c, * resres.c, * size.c, * srconv.c, * strings.c, * windmc.c: Update throughout for bfd section macro and function changes. gas/ * as.c, * as.h, * dw2gencfi.c, * dwarf2dbg.c, * ecoff.c, * read.c, * stabs.c, * subsegs.c, * subsegs.h, * write.c, * config/obj-coff-seh.c, * config/obj-coff.c, * config/obj-ecoff.c, * config/obj-elf.c, * config/obj-macho.c, * config/obj-som.c, * config/tc-aarch64.c, * config/tc-alpha.c, * config/tc-arc.c, * config/tc-arm.c, * config/tc-avr.c, * config/tc-bfin.c, * config/tc-bpf.c, * config/tc-d10v.c, * config/tc-d30v.c, * config/tc-epiphany.c, * config/tc-fr30.c, * config/tc-frv.c, * config/tc-h8300.c, * config/tc-hppa.c, * config/tc-i386.c, * config/tc-ia64.c, * config/tc-ip2k.c, * config/tc-iq2000.c, * config/tc-lm32.c, * config/tc-m32c.c, * config/tc-m32r.c, * config/tc-m68hc11.c, * config/tc-mep.c, * config/tc-microblaze.c, * config/tc-mips.c, * config/tc-mmix.c, * config/tc-mn10200.c, * config/tc-mn10300.c, * config/tc-msp430.c, * config/tc-mt.c, * config/tc-nds32.c, * config/tc-or1k.c, * config/tc-ppc.c, * config/tc-pru.c, * config/tc-rl78.c, * config/tc-rx.c, * config/tc-s12z.c, * config/tc-s390.c, * config/tc-score.c, * config/tc-score7.c, * config/tc-sh.c, * config/tc-sparc.c, * config/tc-spu.c, * config/tc-tic4x.c, * config/tc-tic54x.c, * config/tc-tic6x.c, * config/tc-tilegx.c, * config/tc-tilepro.c, * config/tc-v850.c, * config/tc-visium.c, * config/tc-wasm32.c, * config/tc-xc16x.c, * config/tc-xgate.c, * config/tc-xstormy16.c, * config/tc-xtensa.c, * config/tc-z8k.c: Update throughout for bfd section macro and function changes. * write.c (compress_debug): Use bfd_rename_section. gdb/ * aarch64-linux-tdep.c, * arm-tdep.c, * auto-load.c, * coff-pe-read.c, * coffread.c, * corelow.c, * dbxread.c, * dicos-tdep.c, * dwarf2-frame.c, * dwarf2read.c, * elfread.c, * exec.c, * fbsd-tdep.c, * gcore.c, * gdb_bfd.c, * gdb_bfd.h, * hppa-tdep.c, * i386-cygwin-tdep.c, * i386-fbsd-tdep.c, * i386-linux-tdep.c, * jit.c, * linux-tdep.c, * machoread.c, * maint.c, * mdebugread.c, * minidebug.c, * mips-linux-tdep.c, * mips-sde-tdep.c, * mips-tdep.c, * mipsread.c, * nto-tdep.c, * objfiles.c, * objfiles.h, * osabi.c, * ppc-linux-tdep.c, * ppc64-tdep.c, * record-btrace.c, * record-full.c, * remote.c, * rs6000-aix-tdep.c, * rs6000-tdep.c, * s390-linux-tdep.c, * s390-tdep.c, * solib-aix.c, * solib-dsbt.c, * solib-frv.c, * solib-spu.c, * solib-svr4.c, * solib-target.c, * spu-linux-nat.c, * spu-tdep.c, * symfile-mem.c, * symfile.c, * symmisc.c, * symtab.c, * target.c, * windows-nat.c, * xcoffread.c, * cli/cli-dump.c, * compile/compile-object-load.c, * mi/mi-interp.c: Update throughout for bfd section macro and function changes. * gcore (gcore_create_callback): Use bfd_set_section_lma. * spu-tdep.c (spu_overlay_new_objfile): Likewise. gprof/ * corefile.c, * symtab.c: Update throughout for bfd section macro and function changes. ld/ * ldcref.c, * ldctor.c, * ldelf.c, * ldlang.c, * pe-dll.c, * emultempl/aarch64elf.em, * emultempl/aix.em, * emultempl/armcoff.em, * emultempl/armelf.em, * emultempl/cr16elf.em, * emultempl/cskyelf.em, * emultempl/m68hc1xelf.em, * emultempl/m68kelf.em, * emultempl/mipself.em, * emultempl/mmix-elfnmmo.em, * emultempl/mmo.em, * emultempl/msp430.em, * emultempl/nios2elf.em, * emultempl/pe.em, * emultempl/pep.em, * emultempl/ppc64elf.em, * emultempl/xtensaelf.em: Update throughout for bfd section macro and function changes. libctf/ * ctf-open-bfd.c: Update throughout for bfd section macro changes. opcodes/ * arc-ext.c: Update throughout for bfd section macro changes. sim/ * common/sim-load.c, * common/sim-utils.c, * cris/sim-if.c, * erc32/func.c, * lm32/sim-if.c, * m32c/load.c, * m32c/trace.c, * m68hc11/interp.c, * ppc/hw_htab.c, * ppc/hw_init.c, * rl78/load.c, * rl78/trace.c, * rx/gdb-if.c, * rx/load.c, * rx/trace.c: Update throughout for bfd section macro changes.
2019-09-16 18:55:17 +08:00
2019-09-18 Alan Modra <amodra@gmail.com>
* arc-ext.c: Update throughout for bfd section macro changes.
Re-generate many configure and Makefile.in files I get some spurious changes when running autoconf/automake for various projects in the tree. This is likely because they were generated using distro-patched tools last time. I ran `autoreconf -f` in the various automake projects of the binutils-gdb tree, and this is the result. The tools I am using have been compiled from source, from the upstream release. bfd/ChangeLog: * Makefile.in: Re-generate. * configure: Re-generate. * doc/Makefile.in: Re-generate. binutils/ChangeLog: * Makefile.in: Re-generate. * configure: Re-generate. * doc/Makefile.in: Re-generate. gas/ChangeLog: * Makefile.in: Re-generate. * configure: Re-generate. * doc/Makefile.in: Re-generate. gold/ChangeLog: * testsuite/Makefile.in: Re-generate. gprof/ChangeLog: * Makefile.in: Re-generate. * configure: Re-generate. ld/ChangeLog: * Makefile.in: Re-generate. * configure: Re-generate. opcodes/ChangeLog: * Makefile.in: Re-generate. * configure: Re-generate.
2019-09-18 21:07:44 +08:00
2019-09-18 Simon Marchi <simon.marchi@polymtl.ca>
* Makefile.in: Re-generate.
* configure: Re-generate.
RISC-V: Gate opcode tables by enum rather than string. Generalize opcode arch dependencies so that we can support the overlapping B extension Zb* subsets. 2019-09-17 Maxim Blinov <maxim.blinov@embecosm.com> gas/ * config/tc-riscv.c (riscv_multi_subset_supports): Handle insn_class enum rather than subset char string. (riscv_ip): Update call to riscv_multi_subset_supports. include/ * opcode/riscv.h (riscv_insn_class): New enum. * opcode/riscv.h (struct riscv_opcode): Change subset field to insn_class field. opcodes/ * riscv-opc.c (riscv_opcodes): Change subset field to insn_class field for all instructions. (riscv_insn_types): Likewise.
2019-09-18 08:59:08 +08:00
2019-09-17 Maxim Blinov <maxim.blinov@embecosm.com>
* riscv-opc.c (riscv_opcodes): Change subset field
to insn_class field for all instructions.
(riscv_insn_types): Likewise.
Update version to 2.33.50 and regenerate configure scripts.
2019-09-16 18:01:00 +08:00
2019-09-16 Phil Blundell <pb@pbcl.net>
* configure: Regenerated.
Use the correct alias for the M68K tdiv instruction. PR 24982 * m68k-opc.c: Correct aliases for tdivsl and tdivul.
2019-09-11 00:17:01 +08:00
2019-09-10 Miod Vallat <miod@online.fr>
PR 24982
* m68k-opc.c: Correct aliases for tdivsl and tdivul.
Add markers for 2.33 branch to NEWS and ChangeLog files.
2019-09-09 17:27:03 +08:00
2019-09-09 Phil Blundell <pb@pbcl.net>
binutils 2.33 branch created.
Fix buffer underrun bug in the TI C30 disassembler. PR 24961 * tic30-dis.c (get_indirect_operand): Check for bufcnt being greater than zero before indexing via (bufcnt -1).
2019-09-03 22:37:12 +08:00
2019-09-03 Nick Clifton <nickc@redhat.com>
PR 24961
* tic30-dis.c (get_indirect_operand): Check for bufcnt being
greater than zero before indexing via (bufcnt -1).
Fix a potential buffer overrun in the MMIX disassembler when processing a corrupt input file. PR 24958 * mmix-dis.c (MAX_REG_NAME_LEN): Define. (MAX_SPEC_REG_NAME_LEN): Define. (struct mmix_dis_info): Use defined constants for array lengths. (get_reg_name): New function. (get_sprec_reg_name): New function. (print_insn_mmix): Use new functions.
2019-09-03 16:53:25 +08:00
2019-09-03 Nick Clifton <nickc@redhat.com>
PR 24958
* mmix-dis.c (MAX_REG_NAME_LEN): Define.
(MAX_SPEC_REG_NAME_LEN): Define.
(struct mmix_dis_info): Use defined constants for array lengths.
(get_reg_name): New function.
(get_sprec_reg_name): New function.
(print_insn_mmix): Use new functions.
Add support for the MVE VMOV instruction to the ARM assembler. This instruction copies the value of one vector register to another vector register. The patch also modifies the decoding of VORR instruction which is effecting decoding of VMOV instruction. gas * config/tc-arm.c (parse_neon_mov): Add check to accept vector register to both the arguments in VMOV instruction. * testsuite/gas/arm/mve-vmov-1.d: Modify. * testsuite/gas/arm/mve-vmov-1.s: Likewise. * testsuite/gas/arm/mve-vorr.d: Likewise. opcodes * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC. (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC. (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
2019-08-27 19:08:21 +08:00
2019-08-27 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
* arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
(is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
(print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
[AArch64][gas] Update MTE system register encodings The MTE specification adjusted the encoding of the TFSRE0_EL1, TFSR_EL1, TFSR_EL2, TFSR_EL3, TFSR_EL12 system registers. This patch brings binutils up to date. The references for the encodings are at: https://developer.arm.com/docs/ddi0595/latest/aarch64-system-registers/tfsre0_el1 (also contains TFSR_EL12 description) https://developer.arm.com/docs/ddi0595/latest/aarch64-system-registers/tfsr_el1 https://developer.arm.com/docs/ddi0595/latest/aarch64-system-registers/tfsr_el2 https://developer.arm.com/docs/ddi0595/latest/aarch64-system-registers/tfsr_el3 Tested check-gas for aarch64-none-elf. opcodes/ * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1, tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12. (aarch64_sys_reg_supported_p): Update checks for the above. gas/ * testsuite/gas/aarch64/sysreg-4.d: Update expected disassembly for tfsre0_el1, tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12 system registers.
2019-08-22 17:20:01 +08:00
2019-08-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
(aarch64_sys_reg_supported_p): Update checks for the above.
Modify the ARM encoding and decoding of SQRSHRL and UQRSHLL MVE instructions. This is a change to the first published specifications [1][a] but since there is no hardware out there that uses the old instructions we do not want to support the old variant. This changes are done based on the latest published specifications [1][b]. [1] https://developer.arm.com/architectures/cpu-architecture/m-profile/docs/ddi0553/latest/armv81-m-architecture-reference-manual [a] version bf [b] version bh gas * config/tc-arm.c (enum operand_parse_code): Add the entry OP_I48_I64. (po_imm1_or_imm2_or_fail): Marco to check the immediate is either of 48 or 64. (parse_operands): Add case OP_I48_I64. (do_mve_scalar_shift1): Add function to encode the MVE shift instructions with 4 arguments. * testsuite/gas/arm/mve-shift-bad.l: Modify. * testsuite/gas/arm/mve-shift-bad.s: Likewise. * testsuite/gas/arm/mve-shift.d: Likewise. * testsuite/gas/arm/mve-shift.s: Likewise. opcodes * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for cases MVE_SQRSHRL and MVE_UQRSHLL. (print_insn_mve): Add case for specifier 'k' to check specific bit of the instruction.
2019-08-13 00:17:18 +08:00
2019-08-12 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
* arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
cases MVE_SQRSHRL and MVE_UQRSHLL.
(print_insn_mve): Add case for specifier 'k' to check
specific bit of the instruction.
Prevent objdump from aborting when asked to disassemble an unknown type of ARC binary file. PR 24854 * arc-dis.c (arc_insn_length): Return 0 rather than aborting when encountering an unknown machine type. (print_insn_arc): Handle arc_insn_length returning 0. In error cases return -1 rather than calling abort.
2019-08-08 00:22:29 +08:00
2019-08-07 Phillipe Antoine <p.antoine@catenacyber.fr>
PR 24854
* arc-dis.c (arc_insn_length): Return 0 rather than aborting when
encountering an unknown machine type.
(print_insn_arc): Handle arc_insn_length returning 0. In error
cases return -1 rather than calling abort.
x86: drop stray FloatMF The flag is supposed to be used in templates which allow for both a "short" and a "long" format memory operand. Drop it from templates not matching this pattern. In the control/status word cases it was (ab)used in place of the intended IgnoreSize.
2019-08-07 16:46:52 +08:00
2019-08-07 Jan Beulich <jbeulich@suse.com>
* i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
(fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
IgnoreSize.
* i386-tbl.h: Re-generate.
Removes support in the ARM assembler for the unsigned variants of the VQ(R)DMLAH and VQ(R)DMLASH MVE instructions. Previously GAS would accept .u32, .u16 and .u8 suffixes to the VQ(R)DMLAH and VQ(R)DMLASH instructions, however the Armv8.1-M Mainline specification states that these functions only have signed variations (.s32, .s16 and .s8 suffixes). This is documented here: https://static.docs.arm.com/ddi0553/bh/DDI0553B_h_armv8m_arm.pdf?_ga=2.143079093.1892401233.1563295591-999473562.1560847439#page=1183 gas * config/tc-arm.c (do_mve_vqdmlah): Use N_S_32 macro. (do_neon_qrdmlah): Use N_S_32 macro. * testsuite/gas/arm/mve-vqdmlah-bad.d: New test. * testsuite/gas/arm/mve-vqdmlah-bad.l: New test. * testsuite/gas/arm/mve-vqdmlah-bad.s: New test. * testsuite/gas/arm/mve-vqdmlah.d: Remove unsigned instruction tests. * testsuite/gas/arm/mve-vqdmlah.s: Remove unsigned instruction tests. * testsuite/gas/arm/mve-vqdmlash-bad.d: New test. * testsuite/gas/arm/mve-vqdmlash-bad.l: New test. * testsuite/gas/arm/mve-vqdmlash-bad.s: New test. * testsuite/gas/arm/mve-vqdmlash.d: Remove unsigned instruction tests. * testsuite/gas/arm/mve-vqdmlash.s: Remove unsigned instruction tests. opcodes * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH instructions.
2019-08-05 19:43:38 +08:00
2019-08-05 Barnaby Wilks <barnaby.wilks@arm.com>
* arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
instructions.
RISC-V: Fix minor issues with FP csr instructions. Mel Chen <mel.chen@sifive.com> gas/ * testsuite/gas/riscv/alias-csr.s: Add testcase for CSR-access alias instructions. * testsuite/gas/riscv/no-aliases-csr.d: Run testcase alias-csr.s with -Mno-aliases. * testsuite/gas/riscv/alias-csr.d: Run testcase alias-csr.s. * testsuite/gas/riscv/priv-reg.d: Update. opcodes/ * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm, fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions. * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr, fscsr.
2019-07-31 05:42:16 +08:00
2019-07-30 Mel Chen <mel.chen@sifive.com>
* riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
* riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
fscsr.
[ARC] Update disassembler opcode selection New instruction are added, and some of them are overlapping. Update disassembler to correctly recognize them. Introduce nps400 option. opcodes/ xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com> * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes, and MPY class instructions. (parse_option): Add nps400 option. (print_arc_disassembler_options): Add nps400 info. gas/ xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com> * testsuite/gas/arc/nps400-6.d: Update test.
2019-07-24 21:52:23 +08:00
2019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
* arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
and MPY class instructions.
(parse_option): Add nps400 option.
(print_arc_disassembler_options): Add nps400 info.
[ARC] Update ARC opcode table Update ARC opcode table by cleaning up invalid instructions, and fixing wrong encodings. opcodes/ xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com> * arc-ext-tbl.h (bspeek): Remove it, added to main table. (bspop): Likewise. (modapp): Likewise. * arc-opc.c (RAD_CHK): Add. * arc-tbl.h: Regenerate. include/ xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com> * include/opcode/arc.h (FASTMATH): Add. (SWITCH): Likewise.
2019-07-24 21:46:01 +08:00
2019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
* arc-ext-tbl.h (bspeek): Remove it, added to main table.
(bspop): Likewise.
(modapp): Likewise.
* arc-opc.c (RAD_CHK): Add.
* arc-tbl.h: Regenerate.
[AArch64] Add support for GMID_EL1 register for +memtag We're missing support for the GMID_EL1 system register from the Memory Tagging Extension in binutils. This is specified at: https://developer.arm.com/docs/ddi0595/latest/aarch64-system-registers/gmid_el1 This simple patch adds the support for this read-only register. Tested make check on gas.
2019-07-23 22:54:54 +08:00
2019-07-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
(aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
Add Changelog entry missing from previous delta. 2019-07-22 Barnaby Wilks <barnaby.wilks@arm.com> * arm-dis.c (is_mve_unpredictable): Stop marking some MVE instructions as UNPREDICTABLE.
2019-07-23 16:47:06 +08:00
2019-07-22 Barnaby Wilks <barnaby.wilks@arm.com>
* arm-dis.c (is_mve_unpredictable): Stop marking some MVE
instructions as UNPREDICTABLE.
cpu,opcodes,gas: use %r0 and %r6 instead of %a and %ctf in eBPF disassembler This patch changes the eBPF CPU description to prefer the register names %r0 and %r6 instead of %a and %ctx when disassembling. This matches better with the current practice, vs. cBPF. It also updates the GAS tests in order to reflect this change. Tested in a x86_64 host. cpu/ChangeLog: 2019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com> * bpf.cpu (h-gpr): when disassembling, use %r0 and %r6 instead of %a and %ctx. opcodes/ChangeLog: 2019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com> * bpf-desc.c: Regenerated. gas/ChangeLog: 2019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com> * testsuite/gas/bpf/alu.d: Use %r6 instead of %ctx. * testsuite/gas/bpf/lddw-be.d: Likewise. * testsuite/gas/bpf/lddw.d: Likewise. * testsuite/gas/bpf/alu-be.d: Likewise. * testsuite/gas/bpf/alu32.d: Likewise.
2019-07-19 21:35:43 +08:00
2019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com>
* bpf-desc.c: Regenerated.
x86: drop stale Mem enumerator This was supposed to also be removed by c48dadc9a8 ('x86: drop "mem" operand type attribute'). It's odd enough that this hasn't caused build issues, considering the careful use of OTunused (apparently to avoid "missing initializer" warnings). To avoid such happening again introduce compile time consistency checks.
2019-07-17 15:15:49 +08:00
2019-07-17 Jan Beulich <jbeulich@suse.com>
* i386-gen.c (static_assert): Define.
(main): Use it.
* i386-opc.h (Opcode_Modifier_Max): Rename to ...
(Opcode_Modifier_Num): ... this.
(Mem): Delete.
x86: make RegMem an opcode modifier ... instead of an operand type bit: It's an insn property, not an operand one. There's just one actual change to be made to the templates: Most are now required to have the (unswapped) destination go into ModR/M.rm, so VMOVD template needs its opcode adjusted accordingly and its operands swapped. {,V}MOVS{S,D}, otoh, are left alone in this regard, as otherwise generated code would differ from what we've been producing so far (which I don't think is wanted). Take the opportunity and add a missing IgnoreSize to pextrb (leading to an error in 16-bit mode), and take the liberty to once again drop stray IgnoreSize attributes from lines changed and neighboring related ones.
2019-07-16 15:31:36 +08:00
2019-07-16 Jan Beulich <jbeulich@suse.com>
* i386-gen.c (operand_types): Move RegMem ...
(opcode_modifiers): ... here.
* i386-opc.h (RegMem): Move to opcode modifer enum.
(union i386_operand_type): Move regmem field ...
(struct i386_opcode_modifier): ... here.
* i386-opc.tbl (RegMem): Define.
(mov, movq): Move RegMem on segment, control, debug, and test
register flavors.
(pextrb): Move RegMem on register only flavors. Add IgnoreSize
to non-SSE2AVX flavor.
(extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
Move RegMem on register only flavors. Drop IgnoreSize from
legacy encoding flavors.
(movss, movsd, vmovss, vmovsd): Drop RegMem from register only
flavors.
(vpinsrb, vpinsrw): Drop IgnoreSize where still present on
register only flavors.
(vmovd): Move RegMem and drop IgnoreSize on register only
flavor. Change opcode and operand order to store form.
* opcodes/i386-init.h, i386-tbl.h: Re-generate.
x86: fold SReg{2,3} They're the only exception to there generally being no mix of register kinds possible in an insn operand template, and there being two bits per operand for their representation is also quite wasteful, considering the low number of uses. Fold both bits and deal with the little bit of fallout. Also take the liberty and drop dead code trying to set REX_B: No segment register has RegRex set on it. Additionally I was quite surprised that PUSH/POP with the permitted segment registers is not covered by the test cases. Add the missing pieces.
2019-07-16 15:30:29 +08:00
2019-07-16 Jan Beulich <jbeulich@suse.com>
* i386-gen.c (operand_type_init, operand_types): Replace SReg
entries.
* i386-opc.h (SReg2, SReg3): Replace by ...
(SReg): ... this.
(union i386_operand_type): Replace sreg fields.
* i386-opc.tbl (mov, ): Use SReg.
(push, pop): Likewies. Drop i386 and x86-64 specific segment
register flavors.
* i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
* opcodes/i386-init.h, i386-tbl.h: Re-generate.
cpu,opcodes,gas: fix explicit arguments to eBPF ldabs instructions This patch fixes the eBPF CPU description in order to reflect the right explicit arguments passed to the ldabs{b,h,w,dw} instructions, updates the corresponding GAS tests, and updates the BPF section of the GAS manual. cpu/ChangeLog: 2019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com> * bpf.cpu (dlabs): New pmacro. (dlind): Likewise. opcodes/ChangeLog: 2019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com> * bpf-desc.c: Regenerate. * bpf-opc.c: Likewise. * bpf-opc.h: Likewise. gas/ChangeLog: 2019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com> * testsuite/gas/bpf/mem.s: ldabs instructions do not take a `src' register as an argument. * testsuite/gas/bpf/mem.d: Updated accordingly. * testsuite/gas/bpf/mem-be.d: Likewise. * doc/c-bpf.texi (BPF Opcodes): Update to reflect the correct explicit arguments to ldabs and ldind instructions.
2019-07-15 22:00:28 +08:00
2019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com>
* bpf-desc.c: Regenerate.
* bpf-opc.c: Likewise.
* bpf-opc.h: Likewise.
cpu,opcodes,gas: fix arguments to ldabs and ldind eBPF instructions The eBPF non-generic load instructions ldind{b,h,w,dw} and ldabs{b,h,w,dw} do not take an explicit destination register as an argument. Instead, they put the loaded value in %r0, implicitly. This patch fixes the CPU BPF description to not expect a 'dst' argument in these arguments, regenerates the corresponding files in opcodes, and updates the impacted GAS tests. Tested in a x86-64 host. cpu/ChangeLog: 2019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com> * bpf.cpu (dlsi): ldabs and ldind instructions do not take an explicit 'dst' argument. opcodes/ChangeLog: 2019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com> * bpf-desc.c: Regenerate. * bpf-opc.c: Likewise. gas/ChangeLog: 2019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com> * testsuite/gas/bpf/mem.s: Do not use explicit arguments for ldabs and ldind instructions. * testsuite/gas/bpf/mem.d: Updated accordingly. * testsuite/gas/bpf/mem-be.d: Likewise.
2019-07-14 20:45:31 +08:00
2019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com>
* bpf-desc.c: Regenerate.
* bpf-opc.c: Likewise.
arm-dis.c (print_insn_coprocessor): Rename index to index_operand. Older gcc warns, arguably incorrectly, about name collisions between global functions and function-local variable names. Consesus has been to rename local variables whenever this is spotted, hence committed as obvious. Note the pre-existing variable named idx; "index_operand" seemed logical given the context. * arm-dis.c (print_insn_coprocessor): Rename index to index_operand.
2019-07-11 00:38:19 +08:00
2019-07-10 Hans-Peter Nilsson <hp@bitrange.com>
* arm-dis.c (print_insn_coprocessor): Rename index to
index_operand.
Kito's 5-part patch set to improve .insn support. From Kito Cheng <kito.cheng@sifive.com> gas/ChangeLog * doc/c-riscv.texi (Instruction Formats): Add r4 type. * testsuite/gas/riscv/insn.d: Add testcase for r4 type. * testsuite/gas/riscv/insn.s: Ditto. * doc/c-riscv.texi (Instruction Formats): Add b and j type. * testsuite/gas/riscv/insn.d: Add test case for b and j type. * testsuite/gas/riscv/insn.s: Ditto. * testsuite/gas/riscv/insn.s: Correct instruction type for load and store. * testsuite/gas/riscv/insn.d: Using regular expression to match address. * doc/c-riscv.texi (Instruction Formats): Fix encoding table for SB type and fix typo. opcode/ChangeLog * riscv-opc.c (riscv_insn_types): Add r4 type. * riscv-opc.c (riscv_insn_types): Add b and j type. * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect format for sb type and correct s type.
2019-07-05 15:19:11 +08:00
2019-07-05 Kito Cheng <kito.cheng@sifive.com>
* riscv-opc.c (riscv_insn_types): Add r4 type.
* riscv-opc.c (riscv_insn_types): Add b and j type.
* opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
format for sb type and correct s type.
[AArch64] Allow MOVPRFX to be used with FMOV The entry for the FMOV alias of FCPY was missing C_SCAN_MOVPRFX. (The entry for FCPY itself was OK.) This was the only /m-predicated instruction I could see that was missing the flag. 2019-07-02 Richard Sandiford <richard.sandiford@arm.com> opcodes/ * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the SVE FMOV alias of FCPY. gas/ * testsuite/gas/aarch64/sve-movprfx_27.s, * testsuite/gas/aarch64/sve-movprfx_27.d: New test.
2019-07-02 17:52:16 +08:00
2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
* aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
SVE FMOV alias of FCPY.
[AArch64] Add missing C_MAX_ELEM flags for SVE conversions SVE FCVTZS, FCVTZU, SCVTF and UCVTF need the same treatment as FCVT: the register size used in a predicated MOVPRFX must be the wider of the destination and source sizes. Since I was adding a (supposedly) complete set of tests for converts, it seemed more consistent to add a complete set of tests for shifts as well, even though there's no bug to fix there. 2019-07-02 Richard Sandiford <richard.sandiford@arm.com> opcodes/ * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries. gas/ * testsuite/gas/aarch64/sve-movprfx_26.s: Also test FCVTZS, FCVTZU, SCVTF, UCVTF, LSR and ASR. * testsuite/gas/aarch64/sve-movprfx_26.d: Update accordingly. * testsuite/gas/aarch64/sve-movprfx_26.l: Likewise.
2019-07-02 17:51:09 +08:00
2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
* aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
[AArch64] Fix bogus MOVPRFX warning for GPR form of CPY One of the MOVPRFX tests has: output register of preceding `movprfx' used as input at operand 3 -- `cpy z1.d,p1/m,x1' But X1 and Z1 are not the same register, so the instruction is actually OK. 2019-07-02 Richard Sandiford <richard.sandiford@arm.com> opcodes/ * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the registers in an instruction prefixed by MOVPRFX. gas/ * testsuite/gas/aarch64/sve-movprfx_25.s: Allow CPY Z1.D.P1/M,X1 to be prefixed by MOVPRFX. * testsuite/gas/aarch64/sve-movprfx_25.d: Update accordingly. * testsuite/gas/aarch64/sve-movprfx_25.l: Likewise.
2019-07-02 17:51:05 +08:00
2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
* aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
registers in an instruction prefixed by MOVPRFX.
[gas][aarch64][SVE2] Fix pmull{t,b} requirement on SVE2-AES I had mistakenly given all variants of the new SVE2 instructions pmull{t,b} a dependency on the feature +sve2-aes. Only the variant specifying .Q -> .D sizes should have that restriction. This patch fixes that mistake and updates the testsuite to have extra tests (matching the given set of tests per line in aarch64-tbl.h that the rest of the SVE2 tests follow). We also add a line in the documentation of the command line to clarify how to enable `pmull{t,b}` of this larger size. This is needed because all other instructions gated under the `sve2-aes` architecture extension are marked in the instruction documentation by an `HaveSVE2AES` check while pmull{t,b} is gated under the `HaveSVE2PMULL128` check. Regtested targeting aarch64-linux. gas/ChangeLog: 2019-07-01 Matthew Malcomson <matthew.malcomson@arm.com> * testsuite/gas/aarch64/illegal-sve2-aes.d: Update tests. * testsuite/gas/aarch64/illegal-sve2.l: Update tests. * doc/c-aarch64.texi: Add special note of pmull{t,b} instructions under the sve2-aes architecture extension. * testsuite/gas/aarch64/illegal-sve2.s: Add small size pmull{t,b} instructions. * testsuite/gas/aarch64/sve2.d: Add small size pmull{t,b} disassembly. * testsuite/gas/aarch64/sve2.s: Add small size pmull{t,b} instructions. include/ChangeLog: 2019-07-01 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/aarch64.h (enum aarch64_insn_class): sve_size_013 renamed to sve_size_13. opcodes/ChangeLog: 2019-07-01 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new sve_size_13 icode to account for variant behaviour of pmull{t,b}. * aarch64-dis-2.c: Regenerate. * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new sve_size_13 icode to account for variant behaviour of pmull{t,b}. * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier. (OP_SVE_VVV_Q_D): Add new qualifier. (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier. (struct aarch64_opcode): Split pmull{t,b} into those requiring AES and those not.
2019-07-01 22:17:22 +08:00
2019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
sve_size_13 icode to account for variant behaviour of
pmull{t,b}.
* aarch64-dis-2.c: Regenerate.
* aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
sve_size_13 icode to account for variant behaviour of
pmull{t,b}.
* aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
(OP_SVE_VVV_Q_D): Add new qualifier.
(OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
(struct aarch64_opcode): Split pmull{t,b} into those requiring
AES and those not.
x86: drop Vec_Imm4 It is pretty wasteful to have a per-operand flag which is used in exactly 4 cases. It can be relatively easily replaced, and by doing so I've actually found some dead code to remove at the same time (there's no case of ImmExt set at the same time as Vec_Imm4).
2019-07-01 14:38:50 +08:00
2019-07-01 Jan Beulich <jbeulich@suse.com>
* opcodes/i386-gen.c (operand_type_init): Remove
OPERAND_TYPE_VEC_IMM4 entry.
(operand_types): Remove Vec_Imm4.
* opcodes/i386-opc.h (Vec_Imm4): Delete.
(union i386_operand_type): Remove vec_imm4.
* i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
* opcodes/i386-init.h, i386-tbl.h: Re-generate.
x86: limit ImmExt abuse In quite a few cases ImmExt gets used when there's not really any immediate, but rather a degenerate ModR/M byte. ENCL{S,U} show how this case is supposed to be dealt with. Eliminate most abuses, leaving in place (for now) only ones where process_immext() is involved.
2019-07-01 14:37:40 +08:00
2019-07-01 Jan Beulich <jbeulich@suse.com>
* i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
monitorx, mwaitx): Drop ImmExt from operand-less forms.
* i386-tbl.h: Re-generate.
x86: optimize AND/OR with twice the same register It seems to be not uncommon for people to use AND or OR in this form for just setting the status flags. TEST, which doesn't write to any register other than EFLAGS, ought to be preferred. Make the change only for -O2 and above though, at least for now.
2019-07-01 14:35:08 +08:00
2019-07-01 Jan Beulich <jbeulich@suse.com>
* i386-opc.tbl (and, or): Add Optimize to forms allowing two
register operands.
* i386-tbl.h: Re-generate.
x86-64: optimize certain commutative VEX-encoded insns When they're in the 0F opcode space, swapping their source operands may allow switching from 3-byte to 2-byte VEX prefix encoding. Note that NaN behavior precludes us doing so for many packed and scalar floating point insns; such an optimization would need to be done by the compiler instead in this case, when it knows that NaN-s have undefined behavior anyway. While for explicitly specified AVX/AVX2 insns the optimization (for now at least) gets done only for -O2 and -Os, it is utilized by default in SSE2AVX mode, as there we're re-writing the programmer's specified insns anyway. Rather than introducing a new attribute flag, the change re-uses one which so far was meaningful only for EVEX-encoded insns.
2019-07-01 14:33:56 +08:00
2019-07-01 Jan Beulich <jbeulich@suse.com>
* i386-opc.tbl (C): New.
(paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
flavors.
* i386-tbl.h: Re-generate.
x86: optimize EVEX packed integer logical instructions As long as there's no write mask as well as no broadcast, and as long as the scaled Disp8 wouldn't result in a shorter EVEX encoding, encode VPAND{D,Q}, VPANDN{D,Q}, VPOR{D,Q}, and VPXOR{D,Q} acting on only the lower 16 XMM/YMM registers using their VEX equivalents with -O1. Also take the opportunity and avoid looping twice over all operands when dealing with memory-with-displacement ones.
2019-07-01 14:31:14 +08:00
2019-07-01 Jan Beulich <jbeulich@suse.com>
* i386-opc.tbl (and, or): Add Optimize to forms allowing two
register operands.
* i386-tbl.h: Re-generate.
x86: add missing pseudo ops for VPCLMULQDQ ISA extension While the ISA extensions doc suggests them to be made available just like the SDM does for the PCLMULQDQ ISA extension, these weren't added when supposrt for the new extension was introduced. Also make sure the 64-bit non-AVX512 test actually tests VEX encodings, not EVEX ones.
2019-07-01 14:28:58 +08:00
2019-07-01 Jan Beulich <jbeulich@suse.com>
* i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
* i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
* i386-tbl.h: Re-generate.
x86: drop bogus Disp8MemShift attributes In commit dc821c5f9a ("x86: replace Reg8, Reg16, Reg32, and Reg64") I apparently blindly copied the original register/memory templates into separate ones, in particular without removing the Disp8MemShift which are applicable to templates with memory operands only.
2019-07-01 14:27:38 +08:00
2019-07-01 Jan Beulich <jbeulich@suse.com>
* i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
Disp8MemShift from register only templates.
* i386-tbl.h: Re-generate.
x86: remove ModRM.mod decoding layer from AVX512F VMOVS{S,D} Just like their AVX counterparts they can utilize XMVexScalar / EXdVexScalarS / EXqVexScalarS taking care of dropping the middle operand for their memory forms.
2019-07-01 14:23:41 +08:00
2019-07-01 Jan Beulich <jbeulich@suse.com>
* i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
EVEX_W_0F11_P_3_M_1): Delete.
(EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
EVEX_W_0F11_P_3): New.
* i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
MOD_EVEX_0F11_PREFIX_3 table entries.
* i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
PREFIX_EVEX_0F11 table entries.
* i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
EVEX_W_0F11_P_3_M_{0,1} table entries.
x86: drop a few dead macros
2019-07-01 14:22:37 +08:00
2019-07-01 Jan Beulich <jbeulich@suse.com>
* i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
Delete.
i386: Check vector length for scatter/gather prefetch instructions Since not all vector lengths are supported by scatter/gather prefetch instructions, decode them only with supported vector lengths. gas/ PR binutils/24719 * testsuite/gas/i386/disassem.s: Add test for vgatherpf0dps with invalid vector length. * testsuite/gas/i386/x86-64-disassem.s: Likewise. * testsuite/gas/i386/disassem.d: Updated. * testsuite/gas/i386/x86-64-disassem.d: Likewise. opcodes/ PR binutils/24719 * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2, EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2, EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0, EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0, EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0, EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and EVEX_LEN_0F38C7_R_6_P_2_W_1. * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and PREFIX_EVEX_0F38C6_REG_6 entries. * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and EVEX_W_0F38C7_R_6_P_2 entries. * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2, EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2, EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0, EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0, EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0, EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
2019-06-28 04:39:19 +08:00
2019-06-27 H.J. Lu <hongjiu.lu@intel.com>
PR binutils/24719
* i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
EVEX_LEN_0F38C7_R_6_P_2_W_1.
* i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
PREFIX_EVEX_0F38C6_REG_6 entries.
* i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
EVEX_W_0F38C7_R_6_P_2 entries.
* i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
x86: fold AVX scalar to/from int conversion insns There's no point doing a separate decode of the VEX.L bit - both decoded forms are identical.
2019-06-27 14:50:28 +08:00
2019-06-27 Jan Beulich <jbeulich@suse.com>
* i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
VEX_LEN_0F2D_P_3): Delete.
(vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
(prefix_table): ... here.
x86: allow VEX et al encodings in 16-bit (protected) mode These encodings aren't valid in real and VM86 modes, but they are very well usable in 16-bit protected mode. A few adjustments in the disassembler tables are needed where Ev or Gv were wrongly used. Additionally an adjustment is needed to avoid printing "addr32" when that's already recognizable by the use of %eiz. Furthermore the Iq operand template was wrong for XOP:0Ah encoding insns: They're having a uniform 32-bit immediate. Drop Iq and introduce Id instead. Clone a few existing test cases to exercise assembler and disassembler.
2019-06-27 14:49:40 +08:00
2019-06-27 Jan Beulich <jbeulich@suse.com>
* i386-dis.c (Iq): Delete.
(Id): New.
(reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
TBM insns.
(vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
(OP_E_memory): Also honor needindex when deciding whether an
address size prefix needs printing.
(OP_I): Remove handling of q_mode. Add handling of d_mode.
RISC-V: Make objdump disassembly work right for binary files. Without the ELF header to set info->endian, it ends up as BFD_UNKNOWN_ENDIAN which gets printed as big-endian. But RISC-V instructions are always little endian, so we can set endian_code correctly, and then set display_endian from that. This is similar to how the aarch64 support works, but without the support for constant pools, as we don't have that on RISC-V. opcodes/ PR binutils/24739 * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code. Set info->display_endian to info->endian_code.
2019-06-27 08:17:09 +08:00
2019-06-26 Jim Wilson <jimw@sifive.com>
PR binutils/24739
* riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
Set info->display_endian to info->endian_code.
x86: correct / adjust debug printing For quite some time we've been using combinations of bits for specifying various registers in operands and templates. I think it was Alan who had indicated that likely the debug printing would need adjustment as a result. Here we go. Accumulator handling for GPRs gets changed to match that for FPU regs. For this to work, OPERAND_TYPE_ACC{32,64} get repurposed, with their original uses replaced by direct checks of the two bits of interest, which is cheaper than operand_type_equal() invocations. For SIMD registers nothing similar appears to be needed, as respective operands get stripped from the (copy of the) template before pt() is reached. The type change on pi() is to silence a compiler diagnostic. Arguably its other parameter could also be const-qualified.
2019-06-25 15:41:33 +08:00
2019-06-25 Jan Beulich <jbeulich@suse.com>
* i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
OPERAND_TYPE_ACC64 entries.
* i386-init.h: Re-generate.
x86: drop dqa_mode I assume this mode was needed when EVEX.W handling wasn't really correct yet for other than 64-bit mode. It's clearly not needed anymore. Its elimination also allows dropping the EVEX.W split of VCVT{,U}SI2SS. (For the record, the dropped mode would have been wrong if used in any table entry not already guaranteeing EVEX.W=1.)
2019-06-25 15:28:33 +08:00
2019-06-25 Jan Beulich <jbeulich@suse.com>
* i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
Delete.
(intel_operand_size, OP_E_register, OP_E_memory): Drop handling
of dqa_mode.
* i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
entries here.
* i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
x86: simplify OP_I64() The only meaningful difference from OP_I() is the handling of the VEX.W=1 case in 64-bit mode for bytemode being v_mode. Funnel everything else into OP_I(), and drop no longer needed local variables.
2019-06-25 15:27:05 +08:00
2019-06-25 Jan Beulich <jbeulich@suse.com>
* i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
variables.
x86: fix (dis)assembly of certain SSE2 insns in 16-bit mode MOVNTI was wrongly assembled with a 66h prefix. Add IgnoreSize to address this. It and the scalar to/from integer conversion insns also were also wrongly using Ev / Gv, leading to 16-bit register names being printed when 32-bit ones were meant. Clone the 32-bit SSE2 test to cover both assembler and disassembler.
2019-06-25 15:25:26 +08:00
2019-06-25 Jan Beulich <jbeulich@suse.com>
* i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
movnti.
RISC-V: Make objdump disassembly work right for binary files. Without the ELF header to set info->endian, it ends up as BFD_UNKNOWN_ENDIAN which gets printed as big-endian. But RISC-V instructions are always little endian, so we can set endian_code correctly, and then set display_endian from that. This is similar to how the aarch64 support works, but without the support for constant pools, as we don't have that on RISC-V. opcodes/ PR binutils/24739 * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code. Set info->display_endian to info->endian_code.
2019-06-27 08:17:09 +08:00
* i386-opc.tbl (movnti): Add IgnoreSize.
x86: fix (dis)assembly of certain SSE2 insns in 16-bit mode MOVNTI was wrongly assembled with a 66h prefix. Add IgnoreSize to address this. It and the scalar to/from integer conversion insns also were also wrongly using Ev / Gv, leading to 16-bit register names being printed when 32-bit ones were meant. Clone the 32-bit SSE2 test to cover both assembler and disassembler.
2019-06-25 15:25:26 +08:00
* i386-tbl.h: Re-generate.
x86-64: also optimize ANDQ with immediate fitting in 7 bits The same reasoning applies here as did/does for immediates fitting in 31 bits.
2019-06-25 15:23:48 +08:00
2019-06-25 Jan Beulich <jbeulich@suse.com>
* i386-opc.tbl (and): Mark Imm8S form for optimization.
* i386-tbl.h: Re-generate.
i386: Break i386-dis-evex.h into small files Break i386-dis-evex.h into small files such that each file is included just once. * i386-dis-evex.h: Break into ... * i386-dis-evex-len.h: New file. * i386-dis-evex-mod.h: Likewise. * i386-dis-evex-prefix.h: Likewise. * i386-dis-evex-reg.h: Likewise. * i386-dis-evex-w.h: Likewise. * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h, i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and i386-dis-evex-mod.h.
2019-06-22 04:18:41 +08:00
2019-06-21 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis-evex.h: Break into ...
* i386-dis-evex-len.h: New file.
* i386-dis-evex-mod.h: Likewise.
* i386-dis-evex-prefix.h: Likewise.
* i386-dis-evex-reg.h: Likewise.
* i386-dis-evex-w.h: Likewise.
* i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
i386-dis-evex-mod.h.
i386: Check vector length for EVEX broadcast instructions Since not all vector lengths are supported by EVEX broadcast instructions, decode them only with supported vector lengths. gas/ PR binutils/24700 * testsuite/gas/i386/disassem.s: Add test for vbroadcasti32x8 with invalid vector length. * testsuite/gas/i386/x86-64-disassem.s: Likewise. * testsuite/gas/i386/disassem.d: Updated. * testsuite/gas/i386/x86-64-disassem.d: Likewise. opcodes/ PR binutils/24700 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and EVEX_W_0F385B_P_2. (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0, EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0, EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0, EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0, EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and EVEX_LEN_0F385B_P_2_W_1. * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum. (EVEX_LEN_0F3819_P_2_W_1): Likewise. (EVEX_LEN_0F381A_P_2_W_0): Likewise. (EVEX_LEN_0F381A_P_2_W_1): Likewise. (EVEX_LEN_0F381B_P_2_W_0): Likewise. (EVEX_LEN_0F381B_P_2_W_1): Likewise. (EVEX_LEN_0F385A_P_2_W_0): Likewise. (EVEX_LEN_0F385A_P_2_W_1): Likewise. (EVEX_LEN_0F385B_P_2_W_0): Likewise. (EVEX_LEN_0F385B_P_2_W_1): Likewise.
2019-06-20 01:01:27 +08:00
2019-06-19 H.J. Lu <hongjiu.lu@intel.com>
PR binutils/24700
* i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
EVEX_W_0F385B_P_2.
(evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
EVEX_LEN_0F385B_P_2_W_1.
* i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
(EVEX_LEN_0F3819_P_2_W_1): Likewise.
(EVEX_LEN_0F381A_P_2_W_0): Likewise.
(EVEX_LEN_0F381A_P_2_W_1): Likewise.
(EVEX_LEN_0F381B_P_2_W_0): Likewise.
(EVEX_LEN_0F381B_P_2_W_1): Likewise.
(EVEX_LEN_0F385A_P_2_W_0): Likewise.
(EVEX_LEN_0F385A_P_2_W_1): Likewise.
(EVEX_LEN_0F385B_P_2_W_0): Likewise.
(EVEX_LEN_0F385B_P_2_W_1): Likewise.
i386: Check vector length for vshufXXX/vinsertXXX/vextractXXX Since not all vector lengths are supported by vshufXXX, vinsertXXX and vextractXXX, decode them only with supported vector lengths. gas/ PR binutils/24691 * testsuite/gas/i386/disassem.s: Add test for vshuff32x4 with invalid vector length. * testsuite/gas/i386/x86-64-disassem.s: Likewise. * testsuite/gas/i386/disassem.d: Updated. * testsuite/gas/i386/x86-64-disassem.d: Likewise. opcodes/ PR binutils/24691 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2. (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0, EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0, EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0, EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0, EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0, EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and EVEX_LEN_0F3A43_P_2_W_1. * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum. (EVEX_LEN_0F3A23_P_2_W_1): Likewise. (EVEX_LEN_0F3A38_P_2_W_0): Likewise. (EVEX_LEN_0F3A38_P_2_W_1): Likewise. (EVEX_LEN_0F3A39_P_2_W_0): Likewise. (EVEX_LEN_0F3A39_P_2_W_1): Likewise. (EVEX_LEN_0F3A3A_P_2_W_0): Likewise. (EVEX_LEN_0F3A3A_P_2_W_1): Likewise. (EVEX_LEN_0F3A3B_P_2_W_0): Likewise. (EVEX_LEN_0F3A3B_P_2_W_1): Likewise. (EVEX_LEN_0F3A43_P_2_W_0): Likewise. (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
2019-06-18 01:20:04 +08:00
2019-06-17 H.J. Lu <hongjiu.lu@intel.com>
PR binutils/24691
* i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
(evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
EVEX_LEN_0F3A43_P_2_W_1.
* i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
(EVEX_LEN_0F3A23_P_2_W_1): Likewise.
(EVEX_LEN_0F3A38_P_2_W_0): Likewise.
(EVEX_LEN_0F3A38_P_2_W_1): Likewise.
(EVEX_LEN_0F3A39_P_2_W_0): Likewise.
(EVEX_LEN_0F3A39_P_2_W_1): Likewise.
(EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
(EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
(EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
(EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
(EVEX_LEN_0F3A43_P_2_W_0): Likewise.
(EVEX_LEN_0F3A43_P_2_W_1): Likewise.
Updated French translation for the opcodes subdirectory. * po/fr.po; Updated French translation.
2019-06-14 18:43:53 +08:00
2019-06-14 Nick Clifton <nickc@redhat.com>
* po/fr.po; Updated French translation.
opcodes/or1k: Regenerate opcodes This picks up changes for: - new orfpx64a32 spec additions - new unordered instructions - symbol and documentation updates opcodes/ChangeLog: * or1k-asm.c: Regenerated. * or1k-desc.c: Regenerated. * or1k-desc.h: Regenerated. * or1k-dis.c: Regenerated. * or1k-ibld.c: Regenerated. * or1k-opc.c: Regenerated. * or1k-opc.h: Regenerated. * or1k-opinst.c: Regenerated.
2019-06-13 05:16:19 +08:00
2019-06-13 Stafford Horne <shorne@gmail.com>
* or1k-asm.c: Regenerated.
* or1k-desc.c: Regenerated.
* or1k-desc.h: Regenerated.
* or1k-dis.c: Regenerated.
* or1k-ibld.c: Regenerated.
* or1k-opc.c: Regenerated.
* or1k-opc.h: Regenerated.
* or1k-opinst.c: Regenerated.
Add missing ChangeLog entries
2019-06-13 04:51:01 +08:00
2019-06-12 Peter Bergner <bergner@linux.ibm.com>
* ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
i386: Check vector length for EVEX vextractfXX and vinsertfXX Since not all vector lengths are supported by EVEX vextractfXX and vinsertfXX, decode them only with supported vector lengths. gas/ PR binutils/24633 * testsuite/gas/i386/disassem.s: Add tests for invalid vector lengths for EVEX vextractfXX and vinsertfXX. * testsuite/gas/i386/x86-64-disassem.s: Likewise. * testsuite/gas/i386/disassem.d: Updated. * testsuite/gas/i386/x86-64-disassem.d: Likewise. opcodes/ PR binutils/24633 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2. (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0, EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0, EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0, EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0, EVEX_LEN_0F3A1B_P_2_W_1. * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum. (EVEX_LEN_0F3A18_P_2_W_1): Likewise. (EVEX_LEN_0F3A19_P_2_W_0): Likewise. (EVEX_LEN_0F3A19_P_2_W_1): Likewise. (EVEX_LEN_0F3A1A_P_2_W_0): Likewise. (EVEX_LEN_0F3A1A_P_2_W_1): Likewise. (EVEX_LEN_0F3A1B_P_2_W_0): Likewise. (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
2019-06-06 01:27:08 +08:00
2019-06-05 H.J. Lu <hongjiu.lu@intel.com>
PR binutils/24633
* i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
(evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
EVEX_LEN_0F3A1B_P_2_W_1.
* i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
(EVEX_LEN_0F3A18_P_2_W_1): Likewise.
(EVEX_LEN_0F3A19_P_2_W_0): Likewise.
(EVEX_LEN_0F3A19_P_2_W_1): Likewise.
(EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
(EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
(EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
(EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
i386: Check for reserved VEX.vvvv and EVEX.vvvv If VEX.vvvv and EVEX.vvvv are reserved, they must be all 1s, which are all 0s in inverted form. Add check for unused VEX.vvvv and EVEX.vvvv when disassembling VEX and EVEX instructions. gas/ PR binutils/24626 * testsuite/gas/i386/disassem.s: Add tests for reserved VEX.vvvv and EVEX.vvvv. * testsuite/gas/i386/x86-64-disassem.s: Likewise. * testsuite/gas/i386/disassem.d: Updated. * testsuite/gas/i386/x86-64-disassem.d: Likewise. opcodes/ PR binutils/24626 * i386-dis.c (print_insn): Check for unused VEX.vvvv and EVEX.vvvv when disassembling VEX and EVEX instructions. (OP_VEX): Set vex.register_specifier to 0 after readding vex.register_specifier. (OP_Vex_2src_1): Likewise. (OP_Vex_2src_2): Likewise. (OP_LWP_E): Likewise. (OP_EX_Vex): Don't check vex.register_specifier. (OP_XMM_Vex): Likewise.
2019-06-05 03:45:20 +08:00
2019-06-04 H.J. Lu <hongjiu.lu@intel.com>
PR binutils/24626
* i386-dis.c (print_insn): Check for unused VEX.vvvv and
EVEX.vvvv when disassembling VEX and EVEX instructions.
(OP_VEX): Set vex.register_specifier to 0 after readding
vex.register_specifier.
(OP_Vex_2src_1): Likewise.
(OP_Vex_2src_2): Likewise.
(OP_LWP_E): Likewise.
(OP_EX_Vex): Don't check vex.register_specifier.
(OP_XMM_Vex): Likewise.
Enable Intel AVX512_VP2INTERSECT insn This patch enables support for VP2INTERSECT in binutils. Please refer to https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf for VP2INTERSECT details. Make check-gas is ok. gas/ 2019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com> Lili Cui <lili.cui@intel.com> * config/tc-i386.c (cpu_arch): Add .avx512_vp2intersect. (cpu_noarch): Likewise. * doc/c-i386.texi: Document avx512_vp2intersect. * testsuite/gas/i386/i386.exp: Run vp2intersect tests. * testsuite/gas/i386/vp2intersect-intel.d: New test. * testsuite/gas/i386/vp2intersect.d: Likewise. * testsuite/gas/i386/vp2intersect.s: Likewise. * testsuite/gas/i386/vp2intersect-inval-bcast.l: Likewise. * testsuite/gas/i386/vp2intersect-inval-bcast.s: Likewise. * testsuite/gas/i386/x86-64-vp2intersect-intel.d: Likewise. * testsuite/gas/i386/x86-64-vp2intersect.d: Likewise. * testsuite/gas/i386/x86-64-vp2intersect.s: Likewise. * testsuite/gas/i386/x86-64-vp2intersect-inval-bcast.l: Likewise. * testsuite/gas/i386/x86-64-vp2intersect-inval-bcast.s: Likewise. opcodes/ 2019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com> Lili Cui <lili.cui@intel.com> * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3. * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT instructions. * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS, CPU_ANY_AVX512_VP2INTERSECT_FLAGS. (cpu_flags): Add CpuAVX512_VP2INTERSECT. * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT. (i386_cpu_flags): Add cpuavx512_vp2intersect. * i386-opc.tbl: Add AVX512_VP2INTERSECT insns. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
2019-06-04 23:58:21 +08:00
2019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
Lili Cui <lili.cui@intel.com>
* i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
* i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
instructions.
* i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
(cpu_flags): Add CpuAVX512_VP2INTERSECT.
* i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
(i386_cpu_flags): Add cpuavx512_vp2intersect.
* i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
Add support for Intel ENQCMD[S] instructions This patch enables support for ENQCMD[S] in binutils. Please refer to https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf for ENQCMD[S] details. Make check-gas is ok. gas/ChangeLog: 2019-06-04 Xuepeng Guo <xuepeng.guo@intel.com> Lili Cui <lili.cui@intel.com> * doc/c-i386.texi: Document enqcmd. * testsuite/gas/i386/enqcmd-intel.d: New file. * testsuite/gas/i386/enqcmd-inval.l: Likewise. * testsuite/gas/i386/enqcmd-inval.s: Likewise. * testsuite/gas/i386/enqcmd.d: Likewise. * testsuite/gas/i386/enqcmd.s: Likewise. * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise. * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise. * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise. * testsuite/gas/i386/x86-64-enqcmd.d: Likewise. * testsuite/gas/i386/x86-64-enqcmd.s: Likewise. * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval, enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval, and x86-64-enqcmd. opcodes/ChangeLog: 2019-06-04 Xuepeng Guo <xuepeng.guo@intel.com> Lili Cui <lili.cui@intel.com> * i386-dis.c (enum): Add MOD_0F38F8_PREFIX_1 and MOD_0F38F8_PREFIX_3. (prefix_table): New instructions (see prefix above). (mod_table): New instructions (see prefix above). * i386-gen.c (cpu_flag_init): Add entries for enqcmd. (cpu_flags): Add a bitfield for enqmcd. * i386-init.h: Regenerated. * i386-opc.h (enum): Add CpuENQCMD. (i386_cpu_flags): Add a bitfield for cpuenqcmd. * i386-opc.tbl: Add enqcmd and enqcmds instructions. * i386-init.h: Regenerated. * i386-tbl.h: Regenerated.
2019-06-04 23:50:10 +08:00
2019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
Lili Cui <lili.cui@intel.com>
* doc/c-i386.texi: Document enqcmd.
* testsuite/gas/i386/enqcmd-intel.d: New file.
* testsuite/gas/i386/enqcmd-inval.l: Likewise.
* testsuite/gas/i386/enqcmd-inval.s: Likewise.
* testsuite/gas/i386/enqcmd.d: Likewise.
* testsuite/gas/i386/enqcmd.s: Likewise.
* testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
* testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
* testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
* testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
* testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
* testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
and x86-64-enqcmd.
Remove an unnecessary set of parentheses in the arm-dis.c source file. * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
2019-06-04 21:25:08 +08:00
2019-06-04 Alan Hayward <alan.hayward@arm.com>
* arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
Don't waste space in prefix_opcd_indices * ppc-dis.c (prefix_opcd_indices): Correct size.
2019-06-03 10:16:04 +08:00
2019-06-03 Alan Modra <amodra@gmail.com>
* ppc-dis.c (prefix_opcd_indices): Correct size.
x86: Add CheckRegSize to AVX512_BF16 instructions with Disp8ShiftVL For AVX512 instructions with Disp8ShiftVL and Broadcast, we may need to add CheckRegSize to check if broadcast matches the destination register size. gas/ PR gas/24625 * testsuite/gas/i386/inval-avx512f.s: Add tests for AVX512_BF16 instructions with invalid broadcast. * testsuite/gas/i386/x86-64-inval-avx512f.s: Likewise. * testsuite/gas/i386/inval-avx512f.l: Updated. * testsuite/gas/i386/x86-64-inval-avx512f.l: Likewise. opcodes/ PR gas/24625 * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with Disp8ShiftVL. * i386-tbl.h: Regenerated.
2019-05-29 01:05:28 +08:00
2019-05-28 H.J. Lu <hongjiu.lu@intel.com>
PR gas/24625
* i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
Disp8ShiftVL.
* i386-tbl.h: Regenerated.
Regen POTFILES for bpf bfd/ * po/SRC-POTFILES.in: Regenerate. gas/ * po/POTFILES.in: Regenerate. ld/ * po/BLD-POTFILES.in: Regenerate. opcodes/ * po/POTFILES.in: Regenerate.
2019-05-24 21:39:56 +08:00
2019-05-24 Alan Modra <amodra@gmail.com>
* po/POTFILES.in: Regenerate.
PowerPC D-form prefixed loads and stores opcodes/ * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34), (insert_pcrel, extract_pcrel, extract_pcrel0): New functions. (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment. (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0, XTOP>): Define and add entries. (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define. (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw, pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd, plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq. gas/ * config/tc-ppc.c (ppc_insert_operand): Only sign extend fields that are 32-bits or smaller. * messages.c (as_internal_value_out_of_range): Do not truncate variables and use BFD_VMA_FMT to print them. * testsuite/gas/ppc/prefix-pcrel.s, * testsuite/gas/ppc/prefix-pcrel.d: New test. * testsuite/gas/ppc/ppc.exp: Run it.
2018-07-28 11:21:43 +08:00
2019-05-24 Peter Bergner <bergner@linux.ibm.com>
Alan Modra <amodra@gmail.com>
* ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
(insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
(extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
(powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
XTOP>): Define and add entries.
(P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
(prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
PowerPC add initial -mfuture instruction support This patch adds initial 64-bit insn assembler/disassembler support. The only instruction added is "pnop" along with the automatic aligning of prefix instruction so they do not cross 64-byte boundaries. include/ * dis-asm.h (WIDE_OUTPUT): Define. * opcode/ppc.h (prefix_opcodes, prefix_num_opcodes): Declare. (PPC_OPCODE_POWERXX, PPC_GET_PREFIX, PPC_GET_SUFFIX), (PPC_PREFIX_P, PPC_PREFIX_SEG): Define. opcodes/ * ppc-dis.c (ppc_opts): Add "future" entry. (PREFIX_OPCD_SEGS): Define. (prefix_opcd_indices): New array. (disassemble_init_powerpc): Initialize prefix_opcd_indices. (lookup_prefix): New function. (print_insn_powerpc): Handle 64-bit prefix instructions. * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK), (PMRR, POWERXX): Define. (prefix_opcodes): New instruction table. (prefix_num_opcodes): New constant. binutils/ * objdump.c (disassemble_bytes): Set WIDE_OUTPUT in flags. gas/ * config/tc-ppc.c (ppc_setup_opcodes): Handle prefix_opcodes. (struct insn_label_list): New. (insn_labels, free_insn_labels): New variables. (ppc_record_label, ppc_clear_labels, ppc_start_line_hook): New funcs. (ppc_frob_label, ppc_new_dot_label): Move functions earlier in file and call ppc_record_label. (md_assemble): Handle 64-bit prefix instructions. Align labels that are on the same line as a prefix instruction. * config/tc-ppc.h (tc_frob_label, ppc_frob_label): Move to later in the file. (md_start_line_hook): Define. (ppc_start_line_hook): Declare. * testsuite/gas/ppc/prefix-align.d, * testsuite/gas/ppc/prefix-align.s: New test. * testsuite/gas/ppc/ppc.exp: Run new test.
2018-05-16 05:48:14 +08:00
2019-05-24 Peter Bergner <bergner@linux.ibm.com>
Alan Modra <amodra@gmail.com>
* ppc-dis.c (ppc_opts): Add "future" entry.
(PREFIX_OPCD_SEGS): Define.
(prefix_opcd_indices): New array.
(disassemble_init_powerpc): Initialize prefix_opcd_indices.
(lookup_prefix): New function.
(print_insn_powerpc): Handle 64-bit prefix instructions.
* ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
(PMRR, POWERXX): Define.
(prefix_opcodes): New instruction table.
(prefix_num_opcodes): New constant.
opcodes: add support for eBPF This patch adds support for the Linux kernel eBPF architecture to the opcodes. The port is based on CGEN. opcodes/ChangeLog: 2019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com> * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch. * configure: Regenerated. * Makefile.am: Add rules for the files generated from cpu/bpf.cpu and cpu/bpf.opc. (HFILES): Add bpf-desc.h and bpf-opc.h. (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c, bpf-ibld.c and bpf-opc.c. (BPF_DEPS): Define. * Makefile.in: Regenerated. * disassemble.c (ARCH_bpf): Define. (disassembler): Add case for bfd_arch_bpf. (disassemble_init_for_target): Likewise. (enum epbf_isa_attr): Define. * disassemble.h: extern print_insn_bpf. * bpf-asm.c: Generated. * bpf-opc.h: Likewise. * bpf-opc.c: Likewise. * bpf-ibld.c: Likewise. * bpf-dis.c: Likewise. * bpf-desc.h: Likewise. * bpf-desc.c: Likewise.
2019-05-24 01:04:36 +08:00
2019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
* configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
* configure: Regenerated.
* Makefile.am: Add rules for the files generated from cpu/bpf.cpu
and cpu/bpf.opc.
(HFILES): Add bpf-desc.h and bpf-opc.h.
(TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
bpf-ibld.c and bpf-opc.c.
(BPF_DEPS): Define.
* Makefile.in: Regenerated.
* disassemble.c (ARCH_bpf): Define.
(disassembler): Add case for bfd_arch_bpf.
(disassemble_init_for_target): Likewise.
(enum epbf_isa_attr): Define.
* disassemble.h: extern print_insn_bpf.
* bpf-asm.c: Generated.
* bpf-opc.h: Likewise.
* bpf-opc.c: Likewise.
* bpf-ibld.c: Likewise.
* bpf-dis.c: Likewise.
* bpf-desc.h: Likewise.
* bpf-desc.c: Likewise.
[binutils, ARM] <spec_reg> changes for VMRS and VMSR instructions This patch makes changes to the <spec_reg> operand for VMRS and VMSR instructions as per the Armv8.1-M Mainline. New <spec_reg> options to support are: 0b0010: FPSCR_nzcvqc, access to FPSCR condition and saturation flags. 0b1100: VPR, privileged only access to the VPR register. 0b1101: P0, access to VPR.P0 predicate fields 0b1110: FPCXT_NS, enables saving and restoring of Non-secure floating point context. 0b1111: FPCXT_S, enables saving and restoring of Secure floating point context *** gas/ChangeLog *** 2019-05-21 Sudakshina Das <sudi.das@arm.com> * config/tc-arm.c (parse_operands): Update case OP_RVC to parse p0 and P0. (do_vmrs): Add checks for valid operands with respect to cpu and fpu options. (do_vmsr): Likewise. (reg_names): New reg_names for FPSCR_nzcvqc, VPR, FPCXT_NS and FPCXT_S. * testsuite/gas/arm/armv8_1-m-spec-reg.d: New. * testsuite/gas/arm/armv8_1-m-spec-reg.s: New. * testsuite/gas/arm/armv8_1-m-spec-reg-bad1.d: New. * testsuite/gas/arm/armv8_1-m-spec-reg-bad2.d: New. * testsuite/gas/arm/armv8_1-m-spec-reg-bad3.d: New. * testsuite/gas/arm/armv8_1-m-spec-reg-bad1.l: New. * testsuite/gas/arm/armv8_1-m-spec-reg-bad2.l: New. * testsuite/gas/arm/armv8_1-m-spec-reg-bad3.l: New. * testsuite/gas/arm/vfp1xD.d: Updated to allow new valid values. * testsuite/gas/arm/vfp1xD_t2.d: Likewise. *** opcodes/ChangeLog *** 2019-05-21 Sudakshina Das <sudi.das@arm.com> * arm-dis.c (coprocessor_opcodes): New instructions for VMRS and VMSR with the new operands.
2019-05-22 01:20:48 +08:00
2019-05-21 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (coprocessor_opcodes): New instructions for VMRS
and VMSR with the new operands.
[binutils, Arm] Add support for conditional instructions in Armv8.1-M Mainline This patch adds the following instructions which are part of the Armv8.1-M Mainline: CINC CINV CNEG CSINC CSINV CSNEG CSET CSETM CSEL gas/ChangeLog: 2019-05-21 Sudakshina Das <sudi.das@arm.com> * config/tc-arm.c (TOGGLE_BIT): New. (T16_32_TAB): New entries for cinc, cinv, cneg, csinc, csinv, csneg, cset, csetm and csel. (operand_parse_code): New OP_RR_ZR. (parse_operand): Handle case for OP_RR_ZR. (do_t_cond): New. (insns): New instructions for cinc, cinv, cneg, csinc, csinv, csneg, cset, csetm, csel. * testsuite/gas/arm/armv8_1-m-cond-bad.d: New test. * testsuite/gas/arm/armv8_1-m-cond-bad.l: New test. * testsuite/gas/arm/armv8_1-m-cond-bad.s: New test. * testsuite/gas/arm/armv8_1-m-cond.d: New test. * testsuite/gas/arm/armv8_1-m-cond.s: New test. opcodes/ChangeLog: 2019-05-21 Sudakshina Das <sudi.das@arm.com> * arm-dis.c (enum mve_instructions): New enum for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv and cneg. (mve_opcodes): New instructions as above. (is_mve_encoding_conflict): Add cases for csinc, csinv, csneg and csel. (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
2019-05-22 01:15:13 +08:00
2019-05-21 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (enum mve_instructions): New enum
for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
and cneg.
(mve_opcodes): New instructions as above.
(is_mve_encoding_conflict): Add cases for csinc, csinv,
csneg and csel.
(print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
[binutils, Arm] Add support for shift instructions in MVE This patch adds the following instructions which are part of Armv8.1-M MVE: ASRL (imm) ASRL (reg) LSLL (imm) LSLL (reg) LSRL SQRSHRL SRQSHR SQSHLL SQSHL SRSHRL SRSHR UQRSHLL UQRSHL UQSHLL UQSHL URSHLL URSHL *** gas/ChangeLog *** 2019-05-21 Sudakshina Das <sudi.das@arm.com> * config/tc-arm.c (operand_parse_code): New entries for OP_RRnpcsp_I32 (register or integer operands). (do_mve_scalar_shift): New. (insns): New instructions for asrl, lsll, lsrl, sqrshrl, sqrshr, sqshl sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll, uqshl, urshrl and urshr. * testsuite/gas/arm/mve-shift.d: New. * testsuite/gas/arm/mve-shift.s: New. * testsuite/gas/arm/mve-shift-bad.d: New. * testsuite/gas/arm/mve-shift-bad.s: New. * testsuite/gas/arm/mve-shift-bad.l: New. *** opcodes/ChangeLog *** 2019-05-21 Sudakshina Das <sudi.das@arm.com> * arm-dis.c (emun mve_instructions): Updated for new instructions. (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl, sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll, uqshl, urshrl and urshr. (is_mve_okay_in_it): Add new instructions to TRUE list. (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15. (print_insn_mve): Updated to accept new %j, %<bitfield>m and %<bitfield>n patterns.
2019-05-22 01:11:08 +08:00
2019-05-21 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (emun mve_instructions): Updated for new instructions.
(mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
uqshl, urshrl and urshr.
(is_mve_okay_in_it): Add new instructions to TRUE list.
(is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
(print_insn_mve): Updated to accept new %j,
%<bitfield>m and %<bitfield>n patterns.
MIPS/gas: Reject $0 as source register for DAUI instruction The MIPS64R6 TRM requires that the source register for DAUI not be r0. [1] "MIPS Architecture for Programmers Volume II-A: The MIPS64 Instruction Set Manual", Imagination Technologies Ltd., Document Number: MD00087, Revision 6.06, December 15, 2016, Section 3.2 "Alphabetical List of Instructions", pp. 67-68. gas/ * testsuite/gas/mips/r6-branch-constraints.s: Rename to ... * testsuite/gas/mips/r6-reg-constraints.s: this and add test case for DAUI. * testsuite/gas/mips/r6-branch-constraints.l: Rename to ... * testsuite/gas/mips/r6-reg-constraints.l: this and add test for DAUI. * testsuite/gas/mips/mips.exp: Rename test from r6-branch-constraints to r6-reg-constraints. opcodes/ * mips-opc.c (mips_builtin_opcodes): Change source register constraint for DAUI.
2019-05-14 08:19:37 +08:00
2019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
* mips-opc.c (mips_builtin_opcodes): Change source register
constraint for DAUI.
Updated translations for various binutils subdirectories. bfd * po/fr.po: Updated French translation. binutils* po/ca.po: Updated Catalan translation. gprof * po/de.po: Updated German translation. opcodes * po/fr.po: Updated French translation.
2019-05-20 23:18:19 +08:00
2019-05-20 Nick Clifton <nickc@redhat.com>
* po/fr.po: Updated French translation.
[PATCH 56/57][Arm][OBJDUMP] Add support for MVE instructions: vpnot, vpsel, vqabs, vqadd, vqsub, vqneg and vrev opcodes/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> Michael Collison <michael.collison@arm.com> * arm-dis.c (thumb32_opcodes): Add new instructions. (enum mve_instructions): Likewise. (enum mve_undefined): Add new reasons. (is_mve_encoding_conflict): Handle new instructions. (is_mve_undefined): Likewise. (is_mve_unpredictable): Likewise. (print_mve_undefined): Likewise. (print_mve_size): Likewise.
2019-05-16 21:48:34 +08:00
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
Michael Collison <michael.collison@arm.com>
* arm-dis.c (thumb32_opcodes): Add new instructions.
(enum mve_instructions): Likewise.
(enum mve_undefined): Add new reasons.
(is_mve_encoding_conflict): Handle new instructions.
(is_mve_undefined): Likewise.
(is_mve_unpredictable): Likewise.
(print_mve_undefined): Likewise.
(print_mve_size): Likewise.
[PATCH 55/57][Arm][OBJDUMP] Add support for MVE instructions: vmul, vmulh, vrmulh and vneg opcodes/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> Michael Collison <michael.collison@arm.com> * arm-dis.c (thumb32_opcodes): Add new instructions. (enum mve_instructions): Likewise. (is_mve_encoding_conflict): Handle new instructions. (is_mve_undefined): Likewise. (is_mve_unpredictable): Likewise. (print_mve_size): Likewise.
2019-05-16 21:47:12 +08:00
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
Michael Collison <michael.collison@arm.com>
* arm-dis.c (thumb32_opcodes): Add new instructions.
(enum mve_instructions): Likewise.
(is_mve_encoding_conflict): Handle new instructions.
(is_mve_undefined): Likewise.
(is_mve_unpredictable): Likewise.
(print_mve_size): Likewise.
[PATCH 54/57][Arm][OBJDUMP] Add support for MVE instructions: vmax(a), vmax(a)v, vmaxnm(a), vmaxnm(a)v, vmin(a), vmin(a)v, vminnm(a), vminnm(a)v and vmla opcodes/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> Michael Collison <michael.collison@arm.com> * arm-dis.c (thumb32_opcodes): Add new instructions. (enum mve_instructions): Likewise. (is_mve_encoding_conflict): Likewise. (is_mve_unpredictable): Likewise. (print_mve_size): Likewise.
2019-05-16 21:45:17 +08:00
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
Michael Collison <michael.collison@arm.com>
* arm-dis.c (thumb32_opcodes): Add new instructions.
(enum mve_instructions): Likewise.
(is_mve_encoding_conflict): Likewise.
(is_mve_unpredictable): Likewise.
(print_mve_size): Likewise.
[PATCH 53/57][Arm][OBJDUMP] Add support for MVE instructions: vand, vbrsr, vcls, vclz and vctp opcodes/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> Michael Collison <michael.collison@arm.com> * arm-dis.c (thumb32_opcodes): Add new instructions. (enum mve_instructions): Likewise. (is_mve_encoding_conflict): Handle new instructions. (is_mve_undefined): Likewise. (is_mve_unpredictable): Likewise. (print_mve_size): Likewise.
2019-05-16 21:44:19 +08:00
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
Michael Collison <michael.collison@arm.com>
* arm-dis.c (thumb32_opcodes): Add new instructions.
(enum mve_instructions): Likewise.
(is_mve_encoding_conflict): Handle new instructions.
(is_mve_undefined): Likewise.
(is_mve_unpredictable): Likewise.
(print_mve_size): Likewise.
[PATCH 52/57][Arm][OBJDUMP] Add support for MVE instructions: vadc, vabav, vabd, vabs, vadd, vsbc and vsub opcodes/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> Michael Collison <michael.collison@arm.com> * arm-dis.c (thumb32_opcodes): Add new instructions. (enum mve_instructions): Likewise. (is_mve_encoding_conflict): Handle new instructions. (is_mve_undefined): Likewise. (is_mve_unpredictable): Likewise. (print_mve_size): Likewise. (print_insn_mve): Likewise.
2019-05-16 21:42:53 +08:00
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
Michael Collison <michael.collison@arm.com>
* arm-dis.c (thumb32_opcodes): Add new instructions.
(enum mve_instructions): Likewise.
(is_mve_encoding_conflict): Handle new instructions.
(is_mve_undefined): Likewise.
(is_mve_unpredictable): Likewise.
(print_mve_size): Likewise.
(print_insn_mve): Likewise.
[PATCH 51/57][Arm][OBJDUMP] Add support for MVE instructions: lctp, letp, wlstp and dlstp opcodes/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> Michael Collison <michael.collison@arm.com> * arm-dis.c (thumb32_opcodes): Add new instructions. (print_insn_thumb32): Handle new instructions.
2019-05-16 21:41:41 +08:00
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
Michael Collison <michael.collison@arm.com>
* arm-dis.c (thumb32_opcodes): Add new instructions.
(print_insn_thumb32): Handle new instructions.
[PATCH 50/57][Arm][OBJDUMP] Add support for MVE shift instructions opcodes/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> Michael Collison <michael.collison@arm.com> * arm-dis.c (enum mve_instructions): Add new instructions. (enum mve_undefined): Add new reasons. (is_mve_encoding_conflict): Handle new instructions. (is_mve_undefined): Likewise. (is_mve_unpredictable): Likewise. (print_mve_undefined): Likewise. (print_mve_size): Likewise. (print_mve_shift_n): Likewise. (print_insn_mve): Likewise.
2019-05-16 21:39:12 +08:00
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
Michael Collison <michael.collison@arm.com>
* arm-dis.c (enum mve_instructions): Add new instructions.
(enum mve_undefined): Add new reasons.
(is_mve_encoding_conflict): Handle new instructions.
(is_mve_undefined): Likewise.
(is_mve_unpredictable): Likewise.
(print_mve_undefined): Likewise.
(print_mve_size): Likewise.
(print_mve_shift_n): Likewise.
(print_insn_mve): Likewise.
[PATCH 49/57][Arm][OBJDUMP] Add support for MVE complex number instructions opcodes/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> Michael Collison <michael.collison@arm.com> * arm-dis.c (enum mve_instructions): Add new instructions. (is_mve_encoding_conflict): Handle new instructions. (is_mve_unpredictable): Likewise. (print_mve_rotate): Likewise. (print_mve_size): Likewise. (print_insn_mve): Likewise.
2019-05-16 21:34:44 +08:00
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
Michael Collison <michael.collison@arm.com>
* arm-dis.c (enum mve_instructions): Add new instructions.
(is_mve_encoding_conflict): Handle new instructions.
(is_mve_unpredictable): Likewise.
(print_mve_rotate): Likewise.
(print_mve_size): Likewise.
(print_insn_mve): Likewise.
[PATCH 48/57][Arm][OBJDUMP] Add support for MVE instructions: vddup, vdwdup, vidup and viwdup opcodes/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> Michael Collison <michael.collison@arm.com> * arm-dis.c (enum mve_instructions): Add new instructions. (is_mve_encoding_conflict): Handle new instructions. (is_mve_unpredictable): Likewise. (print_mve_size): Likewise. (print_insn_mve): Likewise.
2019-05-16 21:33:36 +08:00
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
Michael Collison <michael.collison@arm.com>
* arm-dis.c (enum mve_instructions): Add new instructions.
(is_mve_encoding_conflict): Handle new instructions.
(is_mve_unpredictable): Likewise.
(print_mve_size): Likewise.
(print_insn_mve): Likewise.
[PATCH 47/57][Arm][OBJDUMP] Add support for MVE instructions: vaddv, vmlaldav, vmladav, vmlas, vrmlsldavh, vmlsldav, vmlsdav, vrmlaldavh, vqdmlah, vqrdmlash, vqrdmlash, vqdmlsdh, vqrdmlsdh, vqdmulh and vqrdmulh opcodes/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> Michael Collison <michael.collison@arm.com> * arm-dis.c (enum mve_instructions): Add new instructions. (enum mve_undefined): Add new reasons. (is_mve_encoding_conflict): Handle new instructions. (is_mve_undefined): Likewise. (is_mve_unpredictable): Likewise. (print_mve_undefined): Likewise. (print_mve_size): Likewise. (print_insn_mve): Likewise.
2019-05-16 21:32:01 +08:00
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
Michael Collison <michael.collison@arm.com>
* arm-dis.c (enum mve_instructions): Add new instructions.
(enum mve_undefined): Add new reasons.
(is_mve_encoding_conflict): Handle new instructions.
(is_mve_undefined): Likewise.
(is_mve_unpredictable): Likewise.
(print_mve_undefined): Likewise.
(print_mve_size): Likewise.
(print_insn_mve): Likewise.
[PATCH 46/57][Arm][OBJDUMP] Add support for MVE instructions: vmovl, vmull, vqdmull, vqmovn, vqmovun and vmovn opcodes/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> Michael Collison <michael.collison@arm.com> * arm-dis.c (enum mve_instructions): Add new instructions. (is_mve_encoding_conflict): Handle new instructions. (is_mve_undefined): Likewise. (is_mve_unpredictable): Likewise. (print_mve_size): Likewise. (print_insn_mve): Likewise.
2019-05-16 21:30:38 +08:00
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
Michael Collison <michael.collison@arm.com>
* arm-dis.c (enum mve_instructions): Add new instructions.
(is_mve_encoding_conflict): Handle new instructions.
(is_mve_undefined): Likewise.
(is_mve_unpredictable): Likewise.
(print_mve_size): Likewise.
(print_insn_mve): Likewise.
[PATCH 45/57][Arm][OBJDUMP] Add support for MVE instructions: vmov, vmvn, vorr, vorn, vmovx and vbic opcodes/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> Michael Collison <michael.collison@arm.com> * arm-dis.c (enum mve_instructions): Add new instructions. (enum mve_unpredictable): Add new reasons. (enum mve_undefined): Likewise. (is_mve_okay_in_it): Handle new isntructions. (is_mve_encoding_conflict): Likewise. (is_mve_undefined): Likewise. (is_mve_unpredictable): Likewise. (print_mve_vmov_index): Likewise. (print_simd_imm8): Likewise. (print_mve_undefined): Likewise. (print_mve_unpredictable): Likewise. (print_mve_size): Likewise. (print_insn_mve): Likewise.
2019-05-16 21:29:36 +08:00
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
Michael Collison <michael.collison@arm.com>
* arm-dis.c (enum mve_instructions): Add new instructions.
(enum mve_unpredictable): Add new reasons.
(enum mve_undefined): Likewise.
(is_mve_okay_in_it): Handle new isntructions.
(is_mve_encoding_conflict): Likewise.
(is_mve_undefined): Likewise.
(is_mve_unpredictable): Likewise.
(print_mve_vmov_index): Likewise.
(print_simd_imm8): Likewise.
(print_mve_undefined): Likewise.
(print_mve_unpredictable): Likewise.
(print_mve_size): Likewise.
(print_insn_mve): Likewise.
[PATCH 44/57][Arm][OBJDUMP] Add support for MVE instructions: vcvt and vrint opcodes/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> Michael Collison <michael.collison@arm.com> * arm-dis.c (enum mve_instructions): Add new instructions. (enum mve_unpredictable): Add new reasons. (enum mve_undefined): Likewise. (is_mve_encoding_conflict): Handle new instructions. (is_mve_undefined): Likewise. (is_mve_unpredictable): Likewise. (print_mve_undefined): Likewise. (print_mve_unpredictable): Likewise. (print_mve_rounding_mode): Likewise. (print_mve_vcvt_size): Likewise. (print_mve_size): Likewise. (print_insn_mve): Likewise.
2019-05-16 21:08:17 +08:00
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
Michael Collison <michael.collison@arm.com>
* arm-dis.c (enum mve_instructions): Add new instructions.
(enum mve_unpredictable): Add new reasons.
(enum mve_undefined): Likewise.
(is_mve_encoding_conflict): Handle new instructions.
(is_mve_undefined): Likewise.
(is_mve_unpredictable): Likewise.
(print_mve_undefined): Likewise.
(print_mve_unpredictable): Likewise.
(print_mve_rounding_mode): Likewise.
(print_mve_vcvt_size): Likewise.
(print_mve_size): Likewise.
(print_insn_mve): Likewise.
[PATCH 43/57][Arm][OBJDUMP] Add support for MVE instructions: scatter stores and gather loads opcodes/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> Michael Collison <michael.collison@arm.com> * arm-dis.c (enum mve_instructions): Add new instructions. (enum mve_unpredictable): Add new reasons. (enum mve_undefined): Likewise. (is_mve_undefined): Handle new instructions. (is_mve_unpredictable): Likewise. (print_mve_undefined): Likewise. (print_mve_unpredictable): Likewise. (print_mve_size): Likewise. (print_insn_mve): Likewise.
2019-05-16 21:06:46 +08:00
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
Michael Collison <michael.collison@arm.com>
* arm-dis.c (enum mve_instructions): Add new instructions.
(enum mve_unpredictable): Add new reasons.
(enum mve_undefined): Likewise.
(is_mve_undefined): Handle new instructions.
(is_mve_unpredictable): Likewise.
(print_mve_undefined): Likewise.
(print_mve_unpredictable): Likewise.
(print_mve_size): Likewise.
(print_insn_mve): Likewise.
[PATCH 42/57][Arm][OBJDUMP] Add support for MVE instructions: vldr[bhw] and vstr[bhw] opcodes/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> Michael Collison <michael.collison@arm.com> * arm-dis.c (enum mve_instructions): Add new instructions. (enum mve_undefined): Add new reasons. (insns): Add new instructions. (is_mve_encoding_conflict): (print_mve_vld_str_addr): New print function. (is_mve_undefined): Handle new instructions. (is_mve_unpredictable): Likewise. (print_mve_undefined): Likewise. (print_mve_size): Likewise. (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions. (print_insn_mve): Handle new operands.
2019-05-16 21:05:38 +08:00
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
Michael Collison <michael.collison@arm.com>
* arm-dis.c (enum mve_instructions): Add new instructions.
(enum mve_undefined): Add new reasons.
(insns): Add new instructions.
(is_mve_encoding_conflict):
(print_mve_vld_str_addr): New print function.
(is_mve_undefined): Handle new instructions.
(is_mve_unpredictable): Likewise.
(print_mve_undefined): Likewise.
(print_mve_size): Likewise.
(print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
(print_insn_mve): Handle new operands.
[PATCH 41/57][Arm][OBJDUMP] Add support for MVE instructions: vld[24] and vst[24] opcodes/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> Michael Collison <michael.collison@arm.com> * arm-dis.c (enum mve_instructions): Add new instructions. (enum mve_unpredictable): Add new reasons. (is_mve_encoding_conflict): Handle new instructions. (is_mve_unpredictable): Likewise. (mve_opcodes): Add new instructions. (print_mve_unpredictable): Handle new reasons. (print_mve_register_blocks): New print function. (print_mve_size): Handle new instructions. (print_insn_mve): Likewise.
2019-05-16 21:04:35 +08:00
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
Michael Collison <michael.collison@arm.com>
* arm-dis.c (enum mve_instructions): Add new instructions.
(enum mve_unpredictable): Add new reasons.
(is_mve_encoding_conflict): Handle new instructions.
(is_mve_unpredictable): Likewise.
(mve_opcodes): Add new instructions.
(print_mve_unpredictable): Handle new reasons.
(print_mve_register_blocks): New print function.
(print_mve_size): Handle new instructions.
(print_insn_mve): Likewise.
[PATCH 40/57][Arm][OBJDUMP] Add support for MVE instructions: vdup, veor, vfma, vfms, vhadd, vhsub and vrhadd opcodes/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> Michael Collison <michael.collison@arm.com> * arm-dis.c (enum mve_instructions): Add new instructions. (enum mve_unpredictable): Add new reasons. (enum mve_undefined): Likewise. (is_mve_encoding_conflict): Handle new instructions. (is_mve_undefined): Likewise. (is_mve_unpredictable): Likewise. (coprocessor_opcodes): Move NEON VDUP from here... (neon_opcodes): ... to here. (mve_opcodes): Add new instructions. (print_mve_undefined): Handle new reasons. (print_mve_unpredictable): Likewise. (print_mve_size): Handle new instructions. (print_insn_neon): Handle vdup. (print_insn_mve): Handle new operands.
2019-05-16 21:02:05 +08:00
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
Michael Collison <michael.collison@arm.com>
* arm-dis.c (enum mve_instructions): Add new instructions.
(enum mve_unpredictable): Add new reasons.
(enum mve_undefined): Likewise.
(is_mve_encoding_conflict): Handle new instructions.
(is_mve_undefined): Likewise.
(is_mve_unpredictable): Likewise.
(coprocessor_opcodes): Move NEON VDUP from here...
(neon_opcodes): ... to here.
(mve_opcodes): Add new instructions.
(print_mve_undefined): Handle new reasons.
(print_mve_unpredictable): Likewise.
(print_mve_size): Handle new instructions.
(print_insn_neon): Handle vdup.
(print_insn_mve): Handle new operands.
[PATCH 39/57][Arm][OBJDUMP] Add support for MVE instructions: vpt, vpst and vcmp opcodes/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> Michael Collison <michael.collison@arm.com> * arm-dis.c (enum mve_instructions): Add new instructions. (enum mve_unpredictable): Add new values. (mve_opcodes): Add new instructions. (vec_condnames): New array with vector conditions. (mve_predicatenames): New array with predicate suffixes. (mve_vec_sizename): New array with vector sizes. (enum vpt_pred_state): New enum with vector predication states. (struct vpt_block): New struct type for vpt blocks. (vpt_block_state): Global struct to keep track of state. (mve_extract_pred_mask): New helper function. (num_instructions_vpt_block): Likewise. (mark_outside_vpt_block): Likewise. (mark_inside_vpt_block): Likewise. (invert_next_predicate_state): Likewise. (update_next_predicate_state): Likewise. (update_vpt_block_state): Likewise. (is_vpt_instruction): Likewise. (is_mve_encoding_conflict): Add entries for new instructions. (is_mve_unpredictable): Likewise. (print_mve_unpredictable): Handle new cases. (print_instruction_predicate): Likewise. (print_mve_size): New function. (print_vec_condition): New function. (print_insn_mve): Handle vpt blocks and new print operands.
2019-05-16 20:57:57 +08:00
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
Michael Collison <michael.collison@arm.com>
* arm-dis.c (enum mve_instructions): Add new instructions.
(enum mve_unpredictable): Add new values.
(mve_opcodes): Add new instructions.
(vec_condnames): New array with vector conditions.
(mve_predicatenames): New array with predicate suffixes.
(mve_vec_sizename): New array with vector sizes.
(enum vpt_pred_state): New enum with vector predication states.
(struct vpt_block): New struct type for vpt blocks.
(vpt_block_state): Global struct to keep track of state.
(mve_extract_pred_mask): New helper function.
(num_instructions_vpt_block): Likewise.
(mark_outside_vpt_block): Likewise.
(mark_inside_vpt_block): Likewise.
(invert_next_predicate_state): Likewise.
(update_next_predicate_state): Likewise.
(update_vpt_block_state): Likewise.
(is_vpt_instruction): Likewise.
(is_mve_encoding_conflict): Add entries for new instructions.
(is_mve_unpredictable): Likewise.
(print_mve_unpredictable): Handle new cases.
(print_instruction_predicate): Likewise.
(print_mve_size): New function.
(print_vec_condition): New function.
(print_insn_mve): Handle vpt blocks and new print operands.
[PATCH 38/57][Arm][OBJDUMP] Disable the use of MVE reserved coproc numbers in coprocessor instructions opcodes/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors 8, 14 and 15 for Armv8.1-M Mainline.
2019-05-16 20:55:20 +08:00
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
8, 14 and 15 for Armv8.1-M Mainline.
[PATCH 37/57][Arm][OBJDUMP] Add framework for MVE instructions opcodes/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> Michael Collison <michael.collison@arm.com> * arm-dis.c (enum mve_instructions): New enum. (enum mve_unpredictable): Likewise. (enum mve_undefined): Likewise. (struct mopcode32): New struct. (is_mve_okay_in_it): New function. (is_mve_architecture): Likewise. (arm_decode_field): Likewise. (arm_decode_field_multiple): Likewise. (is_mve_encoding_conflict): Likewise. (is_mve_undefined): Likewise. (is_mve_unpredictable): Likewise. (print_mve_undefined): Likewise. (print_mve_unpredictable): Likewise. (print_insn_coprocessor_1): Use arm_decode_field_multiple. (print_insn_mve): New function. (print_insn_thumb32): Handle MVE architecture. (select_arm_features): Force thumb for Armv8.1-m Mainline.
2019-05-16 20:54:24 +08:00
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
Michael Collison <michael.collison@arm.com>
* arm-dis.c (enum mve_instructions): New enum.
(enum mve_unpredictable): Likewise.
(enum mve_undefined): Likewise.
(struct mopcode32): New struct.
(is_mve_okay_in_it): New function.
(is_mve_architecture): Likewise.
(arm_decode_field): Likewise.
(arm_decode_field_multiple): Likewise.
(is_mve_encoding_conflict): Likewise.
(is_mve_undefined): Likewise.
(is_mve_unpredictable): Likewise.
(print_mve_undefined): Likewise.
(print_mve_unpredictable): Likewise.
(print_insn_coprocessor_1): Use arm_decode_field_multiple.
(print_insn_mve): New function.
(print_insn_thumb32): Handle MVE architecture.
(select_arm_features): Force thumb for Armv8.1-m Mainline.
A series of fixes to addres problems detected by compiling the assembler with address sanitization enabled. PR 24538 gas * macro.c (get_any_string): Increase size of buffer used to hold decimal value of expression result. * dw2gencfi.c (get_debugseg_name): Handle an empty name. * dwarf2dbg.c (get_filenum): Catch integer wraparound when extending allocate file array. (dwarf2_directive_filename): Add extra checks of the computed file number. * config/tc-arm.c (arm_tc_equal_in_insn): Insert copy of name into warning hash table. (s_arm_eabi_attribute): Check for obj_elf_vendor_attribute returning -1. * config/tc-i386.c (i386_output_nops): Catch an attempt to generate nops of negative lengths. * as.h (MAX_LITTLENUMS): Move definition to here from... * config/atof-ieee.c: ...here. * config/tc-aarch64.c: ...here. * config/tc-arc.c: ...here. * config/tc-arm.c: ...here. * config/tc-epiphany.c: ...here. * config/tc-i386.c: ...here. * config/tc-ia64.c: ...here. (And correct the value). * config/tc-m32c.c: ...here. * config/tc-m32r.c: ...here. * config/tc-metag.c: ...here. * config/tc-microblaze.c: ...here. * config/tc-nds32.c: ...here. * config/tc-or1k.c: ...here. * config/tc-score.c: ...here. * config/tc-score7.c: ...here. * config/tc-tic4x.c: ...here. * config/tc-tilegx.c: ...here. * config/tc-tilepro.c: ...here. * config/tc-visium.c: ...here. * config/tc-sh.c (md_assemble): Add check for an instruction with no opcodes. * config/tc-mips.c (mips_lookup_insn): Add check for very short instruction name. * config/tc-tic54x.c: Use unsigned chars to access is_end_of_line array. (tic54x_start_line_hook): Check for an empty line. (next_line_shows_parallel): Do not walk off the end of the string. (tic54x_macro_start): Check for too much macro nesting. (tic54x_start_label): Add label_start parameter. Use this parameter to check the first character of the label. * config/tc-tic54x.h (TC_START_LABEL_WITHOUT_COLON): Pass line_start variable to tic54x_start_label. PR 24538 opcodes * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the end of the table prematurely.
2019-05-10 23:57:31 +08:00
2019-05-10 Nick Clifton <nickc@redhat.com>
PR 24538
* ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
end of the table prematurely.
Add macro expansions for ADD, SUB, DADD and DSUB for MIPS r6 Release 6 of the MIPS architecture does not have an ADDI instruction. ADD/SUB instructions with immediate operands can be expanded to load and immediate value and then perform the operation. gas/ * config/tc-mips.c (macro) <M_ADD_I, M_SUB_I, M_DADD_I, M_DSUB_I>: Add expansions for MIPS r6. * testsuite/gas/mips/add.s: Enable tests for R6. * testsuite/gas/mips/daddi.s: Annotate to test DADD for R6. * testsuite/gas/mips/mipsr6@add.d: Likewise. * gas/testsuite/gas/mips/mipsr6@dadd.d: New test. * gas/testsuite/gas/mips/mips.exp: Run the new test. opcodes/ * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB macros for R6.
2019-05-07 00:29:20 +08:00
2019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
* mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
macros for R6.
PowerPC objdump -Mraw * ppc-dis.c (print_insn_powerpc) Don't skip optional operands when -Mraw is in effect.
2019-05-11 08:12:00 +08:00
2019-05-11 Alan Modra <amodra@gmail.com>
* ppc-dis.c (print_insn_powerpc) Don't skip optional operands
when -Mraw is in effect.
[binutils][aarch64] Add SVE2 instructions. This patch adds all the SVE2 instructions and their associated qualifier sets. Ok for trunk? opcodes/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-dis-2.c: Regenerate. * aarch64-tbl.h (OP_SVE_BBU): New variant set. (OP_SVE_BBB): New variant set. (OP_SVE_DDDD): New variant set. (OP_SVE_HHH): New variant set. (OP_SVE_HHHU): New variant set. (OP_SVE_SSS): New variant set. (OP_SVE_SSSU): New variant set. (OP_SVE_SHH): New variant set. (OP_SVE_SBBU): New variant set. (OP_SVE_DSS): New variant set. (OP_SVE_DHHU): New variant set. (OP_SVE_VMV_HSD_BHS): New variant set. (OP_SVE_VVU_HSD_BHS): New variant set. (OP_SVE_VVVU_SD_BH): New variant set. (OP_SVE_VVVU_BHSD): New variant set. (OP_SVE_VVV_QHD_DBS): New variant set. (OP_SVE_VVV_HSD_BHS): New variant set. (OP_SVE_VVV_HSD_BHS2): New variant set. (OP_SVE_VVV_BHS_HSD): New variant set. (OP_SVE_VV_BHS_HSD): New variant set. (OP_SVE_VVV_SD): New variant set. (OP_SVE_VVU_BHS_HSD): New variant set. (OP_SVE_VZVV_SD): New variant set. (OP_SVE_VZVV_BH): New variant set. (OP_SVE_VZV_SD): New variant set. (aarch64_opcode_table): Add sve2 instructions.
2019-05-09 17:29:28 +08:00
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-dis-2.c: Regenerate.
* aarch64-tbl.h (OP_SVE_BBU): New variant set.
(OP_SVE_BBB): New variant set.
(OP_SVE_DDDD): New variant set.
(OP_SVE_HHH): New variant set.
(OP_SVE_HHHU): New variant set.
(OP_SVE_SSS): New variant set.
(OP_SVE_SSSU): New variant set.
(OP_SVE_SHH): New variant set.
(OP_SVE_SBBU): New variant set.
(OP_SVE_DSS): New variant set.
(OP_SVE_DHHU): New variant set.
(OP_SVE_VMV_HSD_BHS): New variant set.
(OP_SVE_VVU_HSD_BHS): New variant set.
(OP_SVE_VVVU_SD_BH): New variant set.
(OP_SVE_VVVU_BHSD): New variant set.
(OP_SVE_VVV_QHD_DBS): New variant set.
(OP_SVE_VVV_HSD_BHS): New variant set.
(OP_SVE_VVV_HSD_BHS2): New variant set.
(OP_SVE_VVV_BHS_HSD): New variant set.
(OP_SVE_VV_BHS_HSD): New variant set.
(OP_SVE_VVV_SD): New variant set.
(OP_SVE_VVU_BHS_HSD): New variant set.
(OP_SVE_VZVV_SD): New variant set.
(OP_SVE_VZVV_BH): New variant set.
(OP_SVE_VZV_SD): New variant set.
(aarch64_opcode_table): Add sve2 instructions.
[binutils][aarch64] New SVE_SHLIMM_UNPRED_22 operand. New operand describes a shift-left immediate encoded in bits 22:20-19:18-16 where UInt(bits) - esize == shift. This operand is useful for instructions like sshllb. gas/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * config/tc-aarch64.c (parse_operands): Handle new SVE_SHLIMM_UNPRED_22 operand. include/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/aarch64.h (enum aarch64_opnd): New SVE_SHLIMM_UNPRED_22 operand. opcodes/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated. * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking for SVE_SHLIMM_UNPRED_22. (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22. * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22 operand.
2019-05-09 17:29:27 +08:00
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
* aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
for SVE_SHLIMM_UNPRED_22.
(aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
* aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
operand.
[binutils][aarch64] New sve_size_tsz_bhs iclass. Add sve_size_tsz_bhs iclass needed for sqxtnb and similar instructions. This iclass encodes one of three variants by the most significant bit set in a 3-bit value where only one bit may be set. include/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_tsz_bhs iclass. opcodes/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle sve_size_tsz_bhs iclass encode. * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle sve_size_tsz_bhs iclass decode.
2019-05-09 17:29:26 +08:00
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
sve_size_tsz_bhs iclass encode.
* aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
sve_size_tsz_bhs iclass decode.
[binutils][aarch64] New SVE_Zm4_11_INDEX operand. This includes defining a new single bit field SVE_i2h at position 20. SVE_Zm4_11_INDEX handles indexed Zn registers where the index is encoded in bits 20:11 and the register is chosed from range z0-z15 in bits 19-16. gas/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * config/tc-aarch64.c (parse_operands): Handle new SVE_Zm4_11_INDEX operand. include/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/aarch64.h (enum aarch64_opnd): New SVE_Zm4_11_INDEX operand. opcodes/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated. * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking for SVE_Zm4_11_INDEX. (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX. (fields): Handle SVE_i2h field. * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field. * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
2019-05-09 17:29:24 +08:00
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
* aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
for SVE_Zm4_11_INDEX.
(aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
(fields): Handle SVE_i2h field.
* aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
* aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
[binutils][aarch64] New sve_shift_tsz_bhsd iclass. This new iclass encodes the variant by which is the most significant bit used of bits 23-22:20-19, where those bits are usually part of a given constant operand. include/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/aarch64.h (enum aarch64_insn_class): Add sve_shift_tsz_bhsd iclass. opcodes/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle sve_shift_tsz_bhsd iclass encode. * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle sve_shift_tsz_bhsd iclass decode.
2019-05-09 17:29:23 +08:00
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
sve_shift_tsz_bhsd iclass encode.
* aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
sve_shift_tsz_bhsd iclass decode.
[binutils][aarch64] New SVE_SHRIMM_UNPRED_22 operand. Include a new iclass to extract the variant from the most significant 3 bits of this operand. Instructions such as rshrnb include a constant shift amount as an operand, where the most significant three bits of this operand determine what size elements the instruction is operating on. The new SVE_SHRIMM_UNPRED_22 operand denotes this constant encoded in bits 22:20-19:18-16 while the new sve_shift_tsz_hsd iclass denotes that the SVE qualifier is encoded in bits 22:20-19. gas/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * config/tc-aarch64.c (parse_operands): Handle new SVE_SHRIMM_UNPRED_22 operand. include/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/aarch64.h (enum aarch64_opnd): New SVE_SHRIMM_UNPRED_22 operand. (enum aarch64_insn_class): Add sve_shift_tsz_hsd iclass. opcodes/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated. * aarch64-asm.c (aarch64_ins_sve_shrimm): (aarch64_encode_variant_using_iclass): Handle sve_shift_tsz_hsd iclass encode. * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle sve_shift_tsz_hsd iclass decode. * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking for SVE_SHRIMM_UNPRED_22. (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22. * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22 operand.
2019-05-09 17:29:22 +08:00
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
* aarch64-asm.c (aarch64_ins_sve_shrimm):
(aarch64_encode_variant_using_iclass): Handle
sve_shift_tsz_hsd iclass encode.
* aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
sve_shift_tsz_hsd iclass decode.
* aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
for SVE_SHRIMM_UNPRED_22.
(aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
* aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
operand.
[binutils][aarch64] New sve_size_013 iclass. Add sve_size_013 instruction class This new iclass handles instructions such as pmullb whose size specifier can only be encoded as 0, 1, or 3. include/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_013 iclass. opcodes/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle sve_size_013 iclass encode. * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle sve_size_013 iclass decode.
2019-05-09 17:29:21 +08:00
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
sve_size_013 iclass encode.
* aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
sve_size_013 iclass decode.
[binutils][aarch64] New sve_size_bh iclass. Add new iclass sve_size_bh to handle instructions that have two variants encoded with the SVE_sz field. This iclass behaves the same as the sve_size_sd iclass, but it has a nicer name for those instructions that choose between variants using the "B" and "H" size qualifiers. include/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_bh iclass. opcodes/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle sve_size_bh iclass encode. * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle sve_size_bh iclass decode.
2019-05-09 17:29:20 +08:00
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
sve_size_bh iclass encode.
* aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
sve_size_bh iclass decode.
[binutils][aarch64] New sve_size_sd2 iclass. Define new sve_size_sd2 iclass to distinguish between the two variants of ldnt1sb and ldnt1sh. include/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_sd2 iclass. opcodes/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle sve_size_sd2 iclass encode. * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle sve_size_sd2 iclass decode. * aarch64-opc.c (fields): Handle SVE_sz2 field. * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
2019-05-09 17:29:19 +08:00
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
sve_size_sd2 iclass encode.
* aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
sve_size_sd2 iclass decode.
* aarch64-opc.c (fields): Handle SVE_sz2 field.
* aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
[binutils][aarch64] New SVE_ADDR_ZX operand. Add AARCH64_OPND_SVE_ADDR_ZX operand that allows a vector of addresses in a Zn register, offset by an Xm register. This is used with scatter/gather SVE2 instructions. gas/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * config/tc-aarch64.c (REG_ZR): Macro specifying zero register. (parse_address_main): Account for new addressing mode [Zn.S, Xm]. (parse_operands): Handle new SVE_ADDR_ZX operand. include/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/aarch64.h (enum aarch64_opnd): New SVE_ADDR_ZX operand. opcodes/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated. * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking for SVE_ADDR_ZX. (aarch64_print_operand): Add printing for SVE_ADDR_ZX. * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
2019-05-09 17:29:18 +08:00
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
* aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
for SVE_ADDR_ZX.
(aarch64_print_operand): Add printing for SVE_ADDR_ZX.
* aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
[binutils][aarch64] New SVE_Zm3_11_INDEX operand. Introduce new operand SVE_Zm3_11_INDEX that indicates a register between z0-z7 stored in bits 18-16 and an index stored in bits 20-19:11. gas/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * config/tc-aarch64.c (parse_operands): Handle new SVE_Zm3_11_INDEX operand. include/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/aarch64.h (enum aarch64_opnd): New SVE_Zm3_11_INDEX operand. opcodes/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated. * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking for SVE_Zm3_11_INDEX. (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX. (fields): Handle SVE_i3l and SVE_i3h2 fields. * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2 fields. * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
2019-05-09 17:29:17 +08:00
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
* aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
for SVE_Zm3_11_INDEX.
(aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
(fields): Handle SVE_i3l and SVE_i3h2 fields.
* aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
fields.
* aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
[binutils][aarch64] New iclass sve_size_hsd2. Add "sve_size_hsd2" iclass decode that uses the new FLD_SVE_size field value to determine the variant of an instruction. include/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_hsd2 iclass. opcodes/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle sve_size_hsd2 iclass encode. * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle sve_size_hsd2 iclass decode. * aarch64-opc.c (fields): Handle SVE_size field. * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
2019-05-09 17:29:16 +08:00
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
sve_size_hsd2 iclass encode.
* aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
sve_size_hsd2 iclass decode.
* aarch64-opc.c (fields): Handle SVE_size field.
* aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
[binutils][aarch64] Introduce SVE_IMM_ROT3 operand. New operand AARCH64_OPND_SVE_IMM_ROT3 handles a single bit rotate operand encoded at bit position 10. gas/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * config/tc-aarch64.c (parse_operands): Handle new SVE_IMM_ROT3 operand. include/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/aarch64.h (enum aarch64_opnd): New SVE_IMM_ROT3 operand. opcodes/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated. * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking for SVE_IMM_ROT3. (aarch64_print_operand): Add printing for SVE_IMM_ROT3. (fields): Handle SVE_rot3 field. * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field. * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
2019-05-09 17:29:15 +08:00
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
* aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
for SVE_IMM_ROT3.
(aarch64_print_operand): Add printing for SVE_IMM_ROT3.
(fields): Handle SVE_rot3 field.
* aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
* aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
[binutils][aarch64] Allow movprfx for SVE2 instructions. SVE2 introduces a number of new instructions that work with the movprfx instruction. This commit ensures that SVE2 instructions are accounted for. opcodes/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-opc.c (verify_constraints): Check for movprfx for sve2 instructions.
2019-05-09 17:29:13 +08:00
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-opc.c (verify_constraints): Check for movprfx for sve2
instructions.
[binutils][aarch64] SVE2 feature extension flags. Include all feature flag macros. The "sve2" extension that enables the core sve2 instructions. This also enables the sve extension, since sve is a requirement of sve2. Extra optional sve2 features are the bitperm, sm4, aes, and sha3 extensions. These are all given extra feature flags, "bitperm", "sve2-sm4", "sve2-aes", and "sve2-sha3" respectively. The sm4, aes, and sha3 extensions are explicitly marked as sve2 extensions to distinguish them from the corresponding NEON extensions. Rather than continue extending the current feature flag numbers, I used some bits that have been skipped. gas/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * config/tc-aarch64.c: Add command line architecture feature flags "sve2", "sve2-sm4", "sve2-aes", "sve2-sha3", "bitperm". * doc/c-aarch64.texi: Document new architecture feature flags. include/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/aarch64.h (AARCH64_FEATURE_SVE2 AARCH64_FEATURE_SVE2_AES, AARCH64_FEATURE_SVE2_BITPERM, AARCH64_FEATURE_SVE2_SM4, AARCH64_FEATURE_SVE2_SHA3): New feature macros. opcodes/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-tbl.h (aarch64_feature_sve2, aarch64_feature_sve2aes, aarch64_feature_sve2sha3, aarch64_feature_sve2sm4, aarch64_feature_sve2bitperm): New feature sets. (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros for feature set addresses. (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN, SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
2019-05-09 17:29:12 +08:00
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-tbl.h
(aarch64_feature_sve2, aarch64_feature_sve2aes,
aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
aarch64_feature_sve2bitperm): New feature sets.
(SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
for feature set addresses.
(SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
Add load-link, store-conditional paired EVA instructions Add paired load-link and store-conditional instructions to the EVA ASE for MIPS32R6[1]. These instructions are optional within the EVA ASE. Their presence is indicated by the XNP bit in the Config5 register. [1] "MIPS Architecture for Programmers Volume II-A: The MIPS32 Instruction Set Manual", Imagination Technologies Ltd., Document Number: MD00086, Revision 6.06, December 15, 2016, Section 3.2 "Alphabetical List of Instructions", pp. 230-231, pp. 357-360. gas/ * config/tc-mips.c (mips_set_ase): Handle ASE_EVA_R6. (macro) <M_LLWPE_AB, M_SCWPE_AB>: New cases. (mips_after_parse_args): Translate EVA to EVA_R6. * testsuite/gas/mips/ase-errors-1.s: Add new instructions. * testsuite/gas/mips/eva.s: Likewise. * testsuite/gas/mips/ase-errors-1.l: Check errors for new instructions. * testsuite/gas/mips/mipsr6@eva.d: Check new test cases. include/ * opcode/mips.h (ASE_EVA_R6): New macro. (M_LLWPE_AB, M_SCWPE_AB): New enum values. opcodes/ * mips-dis.c (mips_calculate_combination_ases): Add ISA argument and set ASE_EVA_R6 appropriately. (set_default_mips_dis_options): Pass ISA to above. (parse_mips_dis_option): Likewise. * mips-opc.c (EVAR6): New macro. (mips_builtin_opcodes): Add llwpe, scwpe. Derived from patch authored by Andrew Bennett <andrew.bennett@imgtec.com>
2019-04-29 09:21:00 +08:00
2019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
Faraz Shahbazker <fshahbazker@wavecomp.com>
* mips-dis.c (mips_calculate_combination_ases): Add ISA
argument and set ASE_EVA_R6 appropriately.
(set_default_mips_dis_options): Pass ISA to above.
(parse_mips_dis_option): Likewise.
* mips-opc.c (EVAR6): New macro.
(mips_builtin_opcodes): Add llwpe, scwpe.
[BINUTILS, AArch64] Enable Transactional Memory Extension This patch enables the new Transactional Memory Extension added recently as part of Arm's new architecture technologies. We introduce a new optional extension "tme" to enable this. The following instructions are part of the extension: * tstart <Xt> * ttest <Xt> * tcommit * tcancel #<imm> The ISA for the above can be found here: https://developer.arm.com/docs/ddi0602/latest/base-instructions-alphabetic-order *** gas/ChangeLog *** 2019-05-01 Sudakshina Das <sudi.das@arm.com> * config/tc-aarch64.c (parse_operands): Add case for AARCH64_OPND_TME_UIMM16. (aarch64_features): Add "tme". * doc/c-aarch64.texi: Document the same. * testsuite/gas/aarch64/tme-invalid.d: New test. * testsuite/gas/aarch64/tme-invalid.l: New test. * testsuite/gas/aarch64/tme-invalid.s: New test. * testsuite/gas/aarch64/tme.d: New test. * testsuite/gas/aarch64/tme.s: New test. *** include/ChangeLog *** 2019-05-01 Sudakshina Das <sudi.das@arm.com> * opcode/aarch64.h (AARCH64_FEATURE_TME): New. (enum aarch64_opnd): Add AARCH64_OPND_TME_UIMM16. *** opcodes/ChangeLog *** 2019-05-01 Sudakshina Das <sudi.das@arm.com> * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated. * aarch64-opc.c (operand_general_constraint_met_p): Add case for AARCH64_OPND_TME_UIMM16. (aarch64_print_operand): Likewise. * aarch64-tbl.h (QL_IMM_NIL): New. (TME): New. (_TME_INSN): New. (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
2019-05-02 00:14:01 +08:00
2019-05-01 Sudakshina Das <sudi.das@arm.com>
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
* aarch64-opc.c (operand_general_constraint_met_p): Add case for
AARCH64_OPND_TME_UIMM16.
(aarch64_print_operand): Likewise.
* aarch64-tbl.h (QL_IMM_NIL): New.
(TME): New.
(_TME_INSN): New.
(struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
S12Z: Opcodes: Fix crash when trying to decode a truncated operation. opcodes/ * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails. gas/ * testsuite/gas/s12z/truncated.d: New file. * testsuite/gas/s12z/truncated.s: New file. * testsuite/gas/s12z/s12z.exp: Add new test.
2019-04-29 22:05:54 +08:00
2019-04-29 John Darrington <john@darrington.wattle.id.au>
* s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
[MIPS] Add load-link, store-conditional paired instructions Add several baseline MIPS32R6[1] and MIPS64R6[2] instructions that were omitted from the initial spec. These instructions are optional in implementations but not associated with any ASE or pseudo-ASE. Their presence is indicated by the XNP bit in the Config5 register. [1] "MIPS Architecture for Programmers Volume II-A: The MIPS32 Instruction Set Manual", Imagination Technologies Ltd., Document Number: MD00086, Revision 6.06, December 15, 2016, Section 3.2 "Alphabetical List of Instructions", pp. 228-229, pp. 354-357. [2] "MIPS Architecture for Programmers Volume II-A: The MIPS64 Instruction Set Manual", Imagination Technologies Ltd., Document Number: MD00087, Revision 6.06, December 15, 2016, Section 3.2 "Alphabetical List of Instructions", pp. 289-290 and pp. 458-460. gas/ * config/tc-mips.c (macro) <M_LLWP_AB, M_LLDP_AB, M_SCWP_AB, M_SCDP_AB>: New cases and expansions for paired instructions. * testsuite/gas/mips/llpscp-32.s: New test source. * testsuite/gas/mips/llpscp-64.s: Likewise. * testsuite/gas/mips/llpscp-32.d: New test. * testsuite/gas/mips/llpscp-64.d: Likewise. * testsuite/gas/mips/mips.exp: Run the new tests. * testsuite/gas/mips/r6.s: Add new instructions to test source. * testsuite/gas/mips/r6-64.s: Likewise. * testsuite/gas/mips/r6-64-n32.d: Check new instructions. * testsuite/gas/mips/r6-64-n64.d: Likewise. * testsuite/gas/mips/r6-n32.d: Likewise. * testsuite/gas/mips/r6-n64.d: Likwwise. * testsuite/gas/mips/r6.d: Likewise. include/ * opcode/mips.h (M_LLWP_AB, M_LLDP_AB): New enum values. (M_SCWP_AB, M_SCDP_AB): Likewise. opcodes/ * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
2019-04-23 06:12:09 +08:00
2019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
Faraz Shahbazker <fshahbazker@wavecomp.com>
* mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
S12Z: s12z-opc.h: Add extern "C" bracketing opcodes/ * s12z-opc.h: Add extern "C" bracketing to help users who wish to use this interface in c++ code.
2019-04-15 15:25:23 +08:00
2019-04-24 John Darrington <john@darrington.wattle.id.au>
* s12z-opc.h: Add extern "C" bracketing to help
users who wish to use this interface in c++ code.
S12Z: Opcodes: Handle bit map operations with non-canonical operands. opcodes/ * s12z-opc.c (bm_decode): Handle the RESERVERD0 case. gas/ * testsuite/gas/s12z/bit-manip-invalid.d: Extend the test. * testsuite/gas/s12z/bit-manip-invalid.s: Extend the test.
2019-04-24 15:41:23 +08:00
2019-04-24 John Darrington <john@darrington.wattle.id.au>
* s12z-opc.c (bm_decode): Handle bit map operations with the
"reserved0" mode.
[binutils, ARM, 16/16] Add support to VLDR and VSTR of system registers GNU as' Arm backend assumes each mnemonic has a single entry in the instruction table but VLDR (system register) and VSTR (system register) are different instructions than VLDR and VSTR. It is thus necessary to add some form of demultiplexing in the parser. It starts by creating a new operand type OP_VLDR which indicate that the operand is either the existing OP_RVSD operand or a system register. The function parse_operands () then tries these two cases in order, calling the new parse_sys_vldr_vstr for the second case. Since the encoding function is specified in the instruction table entry, it also need to have some sort of demultiplexing. This is done in do_vldr_vstr which either calls the existing do_neon_ldr_str () or calls the new do_t_vldr_vstr_sysreg (). A new internal relocation is needed as well since the offset has a shorter range than in other Thumb coprocessor instructions. Disassembly also requires special care since VSTR (system register) reuse the STC encoding with the coprocessor number 15. Armv8.1-M Mainline ARM manual states that coprocessor 8, 14 and 15 are reserved for floating-point and MVE instructions a feature bit check is added if the coprocessor number is one of this value and we are trying to match a coprocessor instruction (eg. STC) to forbid the match. ChangeLog entries are as follows: *** bfd/ChangeLog *** 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> * reloc.c (BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM): New internal relocation. * bfd-in2.h: Regenerate. * libbfd.h: Likewise. *** gas/ChangeLog *** 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> * config/tc-arm.c (parse_sys_vldr_vstr): New function. (OP_VLDR): New enum operand_parse_code enumerator. (parse_operands): Add logic for OP_VLDR. (do_t_vldr_vstr_sysreg): New function. (do_vldr_vstr): Likewise. (insns): Guard VLDR and VSTR by arm_ext_v4t for Thumb mode. (md_apply_fix): Add bound check for VLDR and VSTR co-processor offset. Add masking logic for BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM relocation. * testsuite/gas/arm/archv8m_1m-cmse-main-bad.s: Add examples of bad uses of VLDR and VSTR. * testsuite/gas/arm/archv8m_1m-cmse-main-bad.l: Add error messages for above bad uses. * testsuite/gas/arm/archv8m_1m-cmse-main.s: Add examples of VLDR and VSTR valid uses. * testsuite/gas/arm/archv8m_1m-cmse-main.d: Add disassembly for the above examples. *** opcodes/ChangeLog *** 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> * arm-dis.c (coprocessor_opcodes): Document new %J and %K format specifier. Add entries for VLDR and VSTR of system registers. (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in coprocessor instructions on Armv8.1-M Mainline targets. Add handling of %J and %K format specifier.
2019-04-15 19:23:24 +08:00
2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
* arm-dis.c (coprocessor_opcodes): Document new %J and %K format
specifier. Add entries for VLDR and VSTR of system registers.
(print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
coprocessor instructions on Armv8.1-M Mainline targets. Add handling
of %J and %K format specifier.
[binutils, ARM, 15/16] Add support for VSCCLRM Like for CLRM, this patch aims to share as much logic with the similar looking VLDM/VSTM. This is achieved by adding 2 new enumerator values in enum reg_list_els for the single-precision and double-precision variants of VSCCLRM and extending parse_vfp_reg_list () to deal with these types. These behave like the existing REGLIST_VFP_S and REGLIST_VFP_D types with extra logic to expect VPR as the last element in the register list. The function is algo augmented with a new partial_match parameter to indicate if any register other than VPR had already been parsed in the register list so as to not try parsing the second variant if that's the case and return the right error message. The rest of the patch is the usual encoding function, new disassembler table entries and format specifier and parsing, encoding and disassembling tests. It is worth mentioning that the new entry in the disassembler table was added in the coprocessor-related table despite VSCCLRM always being available even in FPU-less configurations. The main reason for this is that VSCCLRM also match VLDMIA entry and must thus be tried first but coprocessor entries are tried before T32 entries. It also makes sense because it is in the same encoding space as coprocessor and VFP instructions and is thus the natural place for someone to look for this instruction. Note: Both variants of VSCCLRM support D16-D31 registers but Armv8.1-M Mainline overall does not. I have thus decided not to implement support for these registers in order to keep the code simpler. It can always be added later if needed. ChangeLog entries are as follows: *** gas/ChangeLog *** 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> * config/tc-arm.c (arm_typed_reg_parse): Fix typo in comment. (enum reg_list_els): New REGLIST_VFP_S_VPR and REGLIST_VFP_D_VPR enumerators. (parse_vfp_reg_list): Add new partial_match parameter. Set *partial_match to TRUE if at least one element in the register list has matched. Add support for REGLIST_VFP_S_VPR and REGLIST_VFP_D_VPR register lists which expect VPR as last element in the list. (s_arm_unwind_save_vfp_armv6): Adapt call to parse_vfp_reg_list to new prototype. (s_arm_unwind_save_vfp): Likewise. (enum operand_parse_code): New OP_VRSDVLST enumerator. (parse_operands): Adapt call to parse_vfp_reg_list to new prototype. Handle new OP_VRSDVLST case. (do_t_vscclrm): New function. (insns): New entry for VSCCLRM instruction. * testsuite/gas/arm/archv8m_1m-cmse-main-bad.s: Add invalid VSCCLRM instructions. * testsuite/gas/arm/archv8m_1m-cmse-main-bad.l: Add error expectations for above instructions. * testsuite/gas/arm/archv8m_1m-cmse-main.s: Add tests for VSCCLRM instruction. * testsuite/gas/arm/archv8m_1m-cmse-main.d: Add expected disassembly for above instructions. *** opcodes/ChangeLog *** 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> * arm-dis.c (coprocessor_opcodes): Document new %C format control code. Add new entries for VSCCLRM instruction. (print_insn_coprocessor): Handle new %C format control code.
2019-04-15 19:18:16 +08:00
2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
* arm-dis.c (coprocessor_opcodes): Document new %C format control code.
Add new entries for VSCCLRM instruction.
(print_insn_coprocessor): Handle new %C format control code.
[opcodes, ARM, 14/16] Add mode availability to coprocessor table entries The coprocessor_opcodes table is used both to share commonalities in coprocessor-related instructions and to avoid duplication between Arm and Thumb mode. However, some instructions do have differences between Arm and Thumb. For instance, vldmia allows PC as base register in Arm mode but not in Thumb mode. In that very case the distinction becomes necessary because the encoding with PC as base register is used in Thumb mode to denote a VSCCLRM. It is thus necessary to distinguish what is Arm or Thumb only from what is shared. This patch adds an extra field to the coprocessor_opcodes table entries to indicate what mode is a given instruction available in. The print_insn_coprocessor then uses that field to determine if an entry that matched the mark and value checked should be allowed to match or not given the current mode. ChangeLog entry is as follows: *** opcodes/ChangeLog *** 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> * arm-dis.c (enum isa): New enum. (struct sopcode32): New structure. (coprocessor_opcodes): change type of entries to struct sopcode32 and set isa field of all current entries to ANY. (print_insn_coprocessor): Change type of insn to struct sopcode32. Only match an entry if its isa field allows the current mode.
2019-04-15 19:14:38 +08:00
2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
* arm-dis.c (enum isa): New enum.
(struct sopcode32): New structure.
(coprocessor_opcodes): change type of entries to struct sopcode32 and
set isa field of all current entries to ANY.
(print_insn_coprocessor): Change type of insn to struct sopcode32.
Only match an entry if its isa field allows the current mode.
[binutils, ARM, 13/16] Add support for CLRM Given the similarity between LDM/STM and CLRM register lists, most of the changes in this patch aim at sharing code between those two sets of instruction. Sharing is achieved both in parsing and encoding of those instructions. In terms of parsing, parse_reg_list () is extended to take a type that describe what type of instruction is being parsed. The reg_list_els used for parse_vfp_reg_list () is reused for the type and that function is added an assert for the new REGLIST_CLRM and REGLIST_RN enumerators. parse_reg_list () is then taught to accept APSR and reject SP and PC when parsing for a CLRM instruction. At last, caller of parse_reg_list () is updated accordingly and logic is added for the new OP_CLRMLST operand. Encoding-wise, encode_thumb2_ldmstm () is reused to encode the variable bits of CLRM and is thus renamed encode_thumb2_multi (). A new do_io parameter is added to distinguish between LDM/STM and CLRM which guard all the LDM/STM specific code of the function. Finally objdump is told how to disassemble CLRM, again reusing the logic to print the LDM/STM register list (format specifier 'm'). Tests are also added in the form of negative tests to check parsing and encoding/disassembling tests. ChangeLog entries are as follows: *** gas/ChangeLog *** 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> * config/tc-arm.c (enum reg_list_els): Define earlier and add REGLIST_RN and REGLIST_CLRM enumerators. (parse_reg_list): Add etype parameter to distinguish between regular core register list and CLRM register list. Add logic to recognize CLRM register list. (parse_vfp_reg_list): Assert type is not for core register list. (s_arm_unwind_save_core): Update call to parse_reg_list to new prototype. (enum operand_parse_code): Declare OP_CLRMLST enumerator. (parse_operands): Update call to parse_reg_list to new prototype. Add logic for OP_CLRMLST. (encode_thumb2_ldmstm): Rename into ... (encode_thumb2_multi): This. Add do_io parameter. Add logic to encode CLRM and guard LDM/STM only code by do_io. (do_t_ldmstm): Adapt to use encode_thumb2_multi. (do_t_push_pop): Likewise. (do_t_clrm): New function. (insns): Define CLRM. * testsuite/gas/arm/archv8m_1m-cmse-main-bad.d: New file. * testsuite/gas/arm/archv8m_1m-cmse-main-bad.l: Likewise. * testsuite/gas/arm/archv8m_1m-cmse-main-bad.s: Likewise. * testsuite/gas/arm/archv8m_1m-cmse-main.d: Likewise. * testsuite/gas/arm/archv8m_1m-cmse-main.s: Likewise. *** opcodes/ChangeLog *** 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for CLRM. (print_insn_thumb32): Add logic to print %n CLRM register list.
2019-04-15 19:07:20 +08:00
2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
* arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
CLRM.
(print_insn_thumb32): Add logic to print %n CLRM register list.
[binutils, ARM, 12/16] Scalar Low Overhead loop instructions for Armv8.1-M Mainline s patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils. This patch adds support to the Scalar low overhead loop instructions: LE WLS DLS We also add a new assembler resolvable relocation bfd_reloc_code_real enum for the 12-bit branch offset used in these instructions. ChangeLog entries are as follows: *** bfd/ChnageLog *** 2019-04-12 Sudakshina Das <sudi.das@arm.com> * reloc.c (BFD_RELOC_ARM_THUMB_LOOP12): New. * bfd-in2.h: Regenerated. * libbfd.h: Regenerated. *** gas/ChangeLog *** 2019-04-12 Sudakshina Das <sudi.das@arm.com> Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (operand_parse_code): Add OP_LR and OP_oLR for the LR operand and optional LR operand. (parse_operands): Add switch cases for OP_LR and OP_oLR for both type checking and value checking. (encode_thumb32_addr_mode): New entries for DLS, WLS and LE. (v8_1_loop_reloc): New helper function for handling labels for the low overhead loop instructions. (do_t_loloop): New function to encode DLS, WLS and LE. (insns): New entries for WLS, DLS and LE. (md_pcrel_from_section): New switch case for BFD_RELOC_ARM_THUMB_LOOP12. (md_appdy_fix): Likewise. (tc_gen_reloc): Likewise. * testsuite/gas/arm/armv8_1-m-tloop.s: New. * testsuite/gas/arm/armv8_1-m-tloop.d: New. * testsuite/gas/arm/armv8_1-m-tloop-bad.s: New. * testsuite/gas/arm/armv8_1-m-tloop-bad.d: New. * testsuite/gas/arm/armv8_1-m-tloop-bad.l: New. *** opcodes/ChangeLog *** 2019-04-12 Sudakshina Das <sudi.das@arm.com> * arm-dis.c (print_insn_thumb32): Updated to accept new %P and %Q patterns.
2019-04-15 18:58:47 +08:00
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (print_insn_thumb32): Updated to accept new %P
and %Q patterns.
[binutils, ARM, 11/16] New BFCSEL instruction for Armv8.1-M Mainline s patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils. This patch adds the BFCSEL instruction. It also adds a local relocation with a new bfd_reloc_code_real enum. ChangeLog entries are as follows: 2019-04-15 Sudakshina Das <sudi.das@arm.com> * reloc.c (BFD_RELOC_THUMB_PCREL_BFCSEL): New relocation. * bfd-in2.h: Regenerated. * libbfd.h: Likewise. *** gas/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (T16_32_TAB): New entriy for bfcsel. (do_t_v8_1_branch): New switch case for bfcsel. (toU): Define. (insns): New instruction for bfcsel. (md_pcrel_from_section): New switch case for BFD_RELOC_THUMB_PCREL_BFCSEL. (md_appdy_fix): Likewise (tc_gen_reloc): Likewise. * testsuite/gas/arm/armv8_1-m-bfcsel.d: New. * testsuite/gas/arm/armv8_1-m-bfcsel.s: New. *** ld/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * testsuite/ld-arm/bfcsel.s: New. * testsuite/ld-arm/bfcsel.d: New. * testsuite/ld-arm/arm-elf.exp: Add above test. *** opcodes/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * arm-dis.c (thumb32_opcodes): New instruction bfcsel. (print_insn_thumb32): Edit the switch case for %Z.
2019-04-15 18:53:25 +08:00
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (thumb32_opcodes): New instruction bfcsel.
(print_insn_thumb32): Edit the switch case for %Z.
[binutils, ARM, 10/16] BFCSEL infrastructure with new global reloc R_ARM_THM_BF12 This patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils. This adds infrastructure for the BFCSEL instructions which is one of the first instructions in Arm that have more than one relocations in them. This adds a new relocation R_ARM_THM_BF12. The inconsistency between external R_ARM_THM_BF12 and internal BFD_RELOC_ARM_THUMB_BF13 is because internally we count the static bit-0 of the immediate and we don't externally. ChangeLog entries are as follows : ChangeLog entries are as follows : *** bfd/ChnageLog *** 2019-04-04 Sudakshina Das <sudi.das@arm.com> * reloc.c (BFD_RELOC_ARM_THUMB_BF13): New. * bfd-in2.h: Regenerated. * libbfd.h: Regenerated. * elf32-arm.c (elf32_arm_howto_table_1): New entry for R_ARM_THM_BF13. (elf32_arm_reloc_map elf32_arm_reloc_map): Map BFD_RELOC_ARM_THUMB_BF13 and R_ARM_THM_BF12 together. (elf32_arm_final_link_relocate): New switch case for R_ARM_THM_BF13. *** elfcpp/ChangeLog *** 2019-04-04 Sudakshina Das <sudi.das@arm.com> * arm.h (R_ARM_THM_BF12): New relocation code. *** gas/ChangeLog *** 2019-04-04 Sudakshina Das <sudi.das@arm.com> * config/tc-arm.c (md_pcrel_from_section): New switch case for BFD_RELOC_ARM_THUMB_BF13. (md_appdy_fix): Likewise. (tc_gen_reloc): Likewise. *** include/ChangeLog *** 2019-04-04 Sudakshina Das <sudi.das@arm.com> * elf/arm.h (START_RELOC_NUMBERS): New entry for R_ARM_THM_BF12. *** opcodes/ChangeLog *** 2019-04-04 Sudakshina Das <sudi.das@arm.com> * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
2019-04-15 18:46:54 +08:00
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
[binutils, ARM, 9/16] New BFL instruction for Armv8.1-M Mainline This patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils. This patch adds the BFL instruction. *** gas/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (T16_32_TAB): New entrie for bfl. (do_t_v8_1_branch): New switch case for bfl. (insns): New instruction for bfl. * testsuite/gas/arm/armv8_1-m-bfl.d: New. * testsuite/gas/arm/armv8_1-m-bfl.s: New. * testsuite/gas/arm/armv8_1-m-bfl-bad.s: New. * testsuite/gas/arm/armv8_1-m-bfl-bad.d: New. * testsuite/gas/arm/armv8_1-m-bfl-bad.l: New. * testsuite/gas/arm/armv8_1-m-bfl-rel.d: New. * testsuite/gas/arm/armv8_1-m-bfl-rel.s: New. *** ld/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * testsuite/ld-arm/bfl.s: New. * testsuite/ld-arm/bfl.d: New. * testsuite/ld-arm/arm-elf.exp: Add above test. *** opcodes/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * arm-dis.c (thumb32_opcodes): New instruction bfl.
2019-04-15 18:42:10 +08:00
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (thumb32_opcodes): New instruction bfl.
[binutils, ARM, 8/16] BFL infrastructure with new global reloc R_ARM_THM_BF18 This patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils. This adds infrastructure for the BFL instructions which is one of the first instructions in Arm that have more than one relocations in them. This adds a new relocation R_ARM_THM_BF18. The inconsistency between external R_ARM_THM_BF18 and internal BFD_RELOC_ARM_THUMB_BF19 is because internally we count the static bit-0 of the immediate and we don't externally. ChangeLog entries are as follows : *** bfd/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * reloc.c (BFD_RELOC_ARM_THUMB_BF19): New * libbfd.h: Regenerated. * bfd-in2.h: Regenerated. * bfd-elf32-arm.c (elf32_arm_howto_table_1): New entry for R_ARM_THM_BF18. (elf32_arm_reloc_map elf32_arm_reloc_map): Map BFD_RELOC_ARM_THUMB_BF19 and R_ARM_THM_BF18 together. (elf32_arm_final_link_relocate): New switch case for R_ARM_THM_BF19. *** elfcpp/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * arm.h (R_ARM_THM_BF18): New relocation code. *** gas/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * config/tc-arm.c (md_pcrel_from_section): New switch case for BFD_RELOC_ARM_THUMB_BF19. (md_appdy_fix): Likewise. (tc_gen_reloc): Likewise. *** include/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * elf/arm.h (START_RELOC_NUMBERS): New entry for R_ARM_THM_BF18. *** opcodes/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
2019-04-15 18:37:51 +08:00
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
[binutils, ARM, 7/16] New BFX and BFLX instruction for Armv8.1-M Mainline This patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils. This patch adds the BFX and BFLX instructions. ChangeLog entries are as follows : *** gas/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * config/tc-arm.c (T16_32_TAB): New entries for bfx and bflx. (do_t_v8_1_branch): New switch cases for bfx and bflx. (insns): New instruction for bfx and bflx. * testsuite/gas/arm/armv8_1-m-bf-exchange.d: New. * testsuite/gas/arm/armv8_1-m-bf-exchange.s: New. * testsuite/gas/arm/armv8_1-m-bf-exchange-bad.s: New * testsuite/gas/arm/armv8_1-m-bf-exchange-bad.l: New * testsuite/gas/arm/armv8_1-m-bf-exchange-bad.d: New *** opcodes/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an Arm register with r13 and r15 unpredictable. (thumb32_opcodes): New instructions for bfx and bflx.
2019-04-15 18:29:14 +08:00
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
Arm register with r13 and r15 unpredictable.
(thumb32_opcodes): New instructions for bfx and bflx.
[binutils, ARM, 6/16] New BF instruction for Armv8.1-M Mainline This patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils. This patch adds the BF instruction. ChangeLog entries are as follows: *** gas/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (T16_32_TAB): New entries for bf. (do_t_branch_future): New. (insns): New instruction for bf. * testsuite/gas/arm/armv8_1-m-bf.d: New. * testsuite/gas/arm/armv8_1-m-bf.s: New. * testsuite/gas/arm/armv8_1-m-bf-bad.s: New. * testsuite/gas/arm/armv8_1-m-bf-bad.l: New. * testsuite/gas/arm/armv8_1-m-bf-bad.d: New. * testsuite/gas/arm/armv8_1-m-bf-rel.d: New. * testsuite/gas/arm/armv8_1-m-bf-rel.s: New. *** ld/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * testsuite/ld-arm/bf.s: New. * testsuite/ld-arm/bf.d: New. * testsuite/ld-arm/arm-elf.exp: Add above test. *** opcodes/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * arm-dis.c (thumb32_opcodes): New instructions for bf.
2019-04-15 18:25:12 +08:00
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (thumb32_opcodes): New instructions for bf.
[binutils, ARM, 5/16] BF insns infrastructure with new global reloc R_ARM_THM_BF16 This patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils. This adds infrastructure for the BF instructions which is one of the first instructions in Arm that have more than one relocations in them. This is the third infrastructure patch that adds a new relocation R_ARM_THM_BF16. The inconsistency between external R_ARM_THM_BF16 and internal BFD_RELOC_ARM_THUMB_BF17 is because internally we count the static bit-0 of the immediate and we don't externally. ChangeLog entries are as follows : *** bfd/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * reloc.c (BFD_RELOC_ARM_THUMB_BF17): New enum. * bfd-in2.h: Regenerated. * libbfd.h: Regenerated. * bfd-elf32-arm.c (elf32_arm_howto_table_1): New entry for R_ARM_THM_BF16. (elf32_arm_reloc_map elf32_arm_reloc_map): Map BFD_RELOC_ARM_THUMB_BF17 and R_ARM_THM_BF16 together. (get_value_helper): New reloc helper. (elf32_arm_final_link_relocate): New switch case for R_ARM_THM_BF16. *** elfcpp/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * arm.h (R_ARM_THM_BF16): New relocation code. *** gas/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * config/tc-arm.c (md_pcrel_from_section): New switch case for BFD_RELOC_ARM_THUMB_BF17. (md_appdy_fix): Likewise. (tc_gen_reloc): Likewise. *** include/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * elf/arm.h (START_RELOC_NUMBERS): New entry for R_ARM_THM_BF16. *** opcodes/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
2019-04-15 18:18:57 +08:00
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
[binutils, ARM, 3/16] BF insns infrastructure with new bfd_reloc_code_real for fallback branch This patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils. This adds infrastructure for the Branch Future instructions (BF, BFX, BFL, BFLX, BFCSEL). These are the first instructions in ARM that have more than one relocations in them. This is the first infrastructure patch that adds a new bfd_reloc_code_real enum for the fallback branch offset. This is common for all such instructions and needs to be resolvable by the assembler. ChangeLog entries are as follows : *** bfd/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * reloc.c (BFD_RELOC_THUMB_PCREL_BRANCH5): New enum. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. *** gas/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * config/tc-arm.c (md_pcrel_from_section): New switch case for BFD_RELOC_THUMB_PCREL_BRANCH5. (v8_1_branch_value_check): New function to check branch offsets. (md_appdy_fix): New switch case for BFD_RELOC_THUMB_PCREL_BRANCH5. (tc_gen_reloc): Likewise. *** opcodes/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
2019-04-15 18:06:30 +08:00
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
[binutils, ARM, 1/16] Add support for Armv8.1-M Mainline CLI The patch is straightforward, it does the following: - support the new Tag_CPU_arch build attribute value, ie.: + declare the new value + update all the asserts forcing logic to be reviewed for new architectures + create a corresponding bfd_mach_arm_8_1M_MAIN enumerator in bfd and add mapping from Tag_CPU_arch to it + teach readelf about new Tag_CPU_arch value - declare armv8.1-m.main as a supported architecture value - define Armv8.1-M Mainline in terms of feature bits available - tell objdump mapping from bfd_mach_arm_8_1M_MAIN enumerator to feature bits available - update architecture-specific logic in gas and bfd guarded by the asserts mentioned above. - tests for all the above ChangeLog entries are as follows: *** bfd/ChangeLog *** 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> * archures.c (bfd_mach_arm_8_1M_MAIN): Define. * bfd-in2.h: Regenerate. * cpu-arm.c (arch_info_struct): Add entry for Armv8.1-M Mainline. * elf32-arm.c (using_thumb_only): Return true for Armv8.1-M Mainline and update assert. (using_thumb2): Likewise. (using_thumb2_bl): Update assert. (arch_has_arm_nop): Likewise. (bfd_arm_get_mach_from_attributes): Add case for Armv8.1-M Mainline. (tag_cpu_arch_combine): Add logic for Armv8.1-M Mainline merging. *** binutils/ChangeLog *** 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> * readelf.c (arm_attr_tag_CPU_arch): Add entry for Armv8.1-M Mainline. *** gas/ChangeLog *** 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> * config/tc-arm.c (cpu_arch_ver): Add entry for Armv8.1-M Mainline Tag_CPU_arch build attribute value. Reindent. (get_aeabi_cpu_arch_from_fset): Update assert. (aeabi_set_public_attributes): Update assert for Tag_DIV_use logic. * testsuite/gas/arm/attr-march-armv8_1-m.main.d: New test. *** include/ChangeLog *** 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> * elf/arm.h (TAG_CPU_ARCH_V8_1M_MAIN): new macro. (MAX_TAG_CPU_ARCH): Set value to above macro. * opcode/arm.h (ARM_EXT2_V8_1M_MAIN): New macro. (ARM_AEXT_V8_1M_MAIN): Likewise. (ARM_AEXT2_V8_1M_MAIN): Likewise. (ARM_ARCH_V8_1M_MAIN): Likewise. *** ld/ChangeLog *** 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> * testsuite/ld-arm/attr-merge-13.attr: New test. * testsuite/ld-arm/attr-merge-13a.s: New test. * testsuite/ld-arm/attr-merge-13b.s: New test. *** opcodes/ChangeLog *** 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
2019-04-15 17:54:42 +08:00
2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
* arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
S12Z: opcodes: Replace "operator" with "optr". opcodes/ * s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace operator with optr.
2019-04-13 00:39:01 +08:00
2019-04-12 John Darrington <john@darrington.wattle.id.au>
s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
"optr". ("operator" is a reserved word in c++).
[BINUTILS, AArch64, 2/2] Update Store Allocation Tag instructions This patch updates the Store allocation tags instructions in Armv8.5-A Memory Tagging Extension. This is part of the changes that have been introduced recently in the 00bet10 release All of these instructions have an updated register operand (Xt -> <Xt|SP>) - STG <Xt|SP>, [<Xn|SP>, #<simm>] - STG <Xt|SP>, [<Xn|SP>, #<simm>]! - STG <Xt|SP>, [<Xn|SP>], #<simm> - STZG <Xt|SP>, [<Xn|SP>, #<simm>] - STZG <Xt|SP>, [<Xn|SP>, #<simm>]! - STZG <Xt|SP>, [<Xn|SP>], #<simm> - ST2G <Xt|SP>, [<Xn|SP>, #<simm>] - ST2G <Xt|SP>, [<Xn|SP>, #<simm>]! - ST2G <Xt|SP>, [<Xn|SP>], #<simm> - STZ2G <Xt|SP>, [<Xn|SP>, #<simm>] - STZ2G <Xt|SP>, [<Xn|SP>, #<simm>]! - STZ2G <Xt|SP>, [<Xn|SP>], #<simm> In order to accept <Rt|SP> a new operand type Rt_SP is introduced which has the same field as FLD_Rt but follows other semantics of Rn_SP. *** gas/ChangeLog *** 2019-04-11 Sudakshina Das <sudi.das@arm.com> * config/tc-aarch64.c (process_omitted_operand): Add case for AARCH64_OPND_Rt_SP. (parse_operands): Likewise. * testsuite/gas/aarch64/armv8_5-a-memtag.d: Update tests. * testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise. * testsuite/gas/aarch64/illegal-memtag.l: Likewise. * testsuite/gas/aarch64/illegal-memtag.s: Likewise. *** include/ChangeLog *** 2019-04-11 Sudakshina Das <sudi.das@arm.com> * opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_Rt_SP. *** opcodes/ChangeLog *** 2019-04-11 Sudakshina Das <sudi.das@arm.com> * aarch64-opc.c (aarch64_print_operand): Add case for AARCH64_OPND_Rt_SP. (verify_constraints): Likewise. * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier. (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions to accept Rt|SP as first operand. (AARCH64_OPERANDS): Add new Rt_SP. * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated.
2019-04-11 17:19:37 +08:00
2019-04-11 Sudakshina Das <sudi.das@arm.com>
* aarch64-opc.c (aarch64_print_operand): Add case for
AARCH64_OPND_Rt_SP.
(verify_constraints): Likewise.
* aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
(struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
to accept Rt|SP as first operand.
(AARCH64_OPERANDS): Add new Rt_SP.
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
[BINUTILS, AArch64, 1/2] Add new LDGM/STGM instruction This patch adds the new LDGM/STGM instructions of the Armv8.5-A Memory Tagging Extension. This is part of the changes that have been introduced recently in the 00bet10 release The instructions are as follows: LDGM Xt, [<Xn|SP>] STGM Xt, [<Xn|SP>] *** gas/ChangeLog *** 2019-04-11 Sudakshina Das <sudi.das@arm.com> * testsuite/gas/aarch64/armv8_5-a-memtag.d: New tests for ldgm and stgm. * testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise. * testsuite/gas/aarch64/illegal-memtag.l: Likewise. * testsuite/gas/aarch64/illegal-memtag.s: Likewise. *** opcodes/ChangeLog *** 2019-04-11 Sudakshina Das <sudi.das@arm.com> * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Likewise. * aarch64-opc-2.c: Likewise. * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
2019-04-11 17:13:23 +08:00
2019-04-11 Sudakshina Das <sudi.das@arm.com>
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Likewise.
* aarch64-opc-2.c: Likewise.
* aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
[MIPS] Add RDHWR with the SEL field for MIPS R6. In Release 6 of the MIPS architecture [1], instruction RDHWR supports a 3rd operand to serve as the 3-bit select field for the hardware register. [1] "MIPS Architecture for Programmers Volume II-A: The MIPS32 Instruction Set Manual", Imagination Technologies Ltd., Document Number: MD00086, Revision 6.06, December 15, 2016, Section 3.2 "Alphabetical List of Instructions", pp. 332-334 opcodes/ * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel. gas/ * testsuite/gas/mips/mips.exp: Run hwr-names test. * testsuite/gas/mips/hwr-names.s: Add test cases for RDHWR with the SEL field. * testsuite/gas/mips/mipsr6@hwr-names.d: New file.
2019-04-09 17:30:26 +08:00
2019-04-09 Robert Suchanek <robert.suchanek@mips.com>
* mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
x86: Consolidate AVX512 BF16 entries in i386-opc.tbl 1. Use single entry for vcvtne2ps2bf16 and vdpbf16ps with Disp8ShiftVL. 2. Use 5 entries, instead of 8, for vcvtneps2bf16. * i386-opc.tbl: Consolidate AVX512 BF16 entries. * i386-init.h: Regenerated.
2019-04-09 02:06:04 +08:00
2019-04-08 H.J. Lu <hongjiu.lu@intel.com>
* i386-opc.tbl: Consolidate AVX512 BF16 entries.
* i386-init.h: Regenerated.
print_insn_powerpc tidy * ppc-dis.c (print_insn_powerpc): Use a tiny state machine op_separator to control printing of spaces, comma and parens rather than need_comma, need_paren and spaces vars.
2019-04-07 19:17:06 +08:00
2019-04-07 Alan Modra <amodra@gmail.com>
* ppc-dis.c (print_insn_powerpc): Use a tiny state machine
op_separator to control printing of spaces, comma and parens
rather than need_comma, need_paren and spaces vars.
PR24421, Wrong brackets in opcodes/arm-dis.c PR 24421 * arm-dis.c (print_insn_coprocessor): Correct bracket placement. (print_insn_neon, print_insn_arm): Likewise.
2019-04-07 19:12:16 +08:00
2019-04-07 Alan Modra <amodra@gmail.com>
PR 24421
* arm-dis.c (print_insn_coprocessor): Correct bracket placement.
(print_insn_neon, print_insn_arm): Likewise.
x86: Support Intel AVX512 BF16 Add assembler and disassembler support Intel AVX512 BF16: https://software.intel.com/en-us/download/intel-architecture-instruction-set-extensions-programming-reference gas/ 2019-04-05 Xuepeng Guo <xuepeng.guo@intel.com> * config/tc-i386.c (cpu_arch): Add .avx512_bf16. (cpu_noarch): Add noavx512_bf16. * doc/c-i386.texi: Document avx512_bf16. * testsuite/gas/i386/avx512_bf16.d: New file. * testsuite/gas/i386/avx512_bf16.s: Likewise. * testsuite/gas/i386/avx512_bf16_vl-inval.l: Likewise. * testsuite/gas/i386/avx512_bf16_vl-inval.s: Likewise. * testsuite/gas/i386/avx512_bf16_vl.d: Likewise. * testsuite/gas/i386/avx512_bf16_vl.s: Likewise. * testsuite/gas/i386/x86-64-avx512_bf16.d: Likewise. * testsuite/gas/i386/x86-64-avx512_bf16.s: Likewise. * testsuite/gas/i386/x86-64-avx512_bf16_vl-inval.l: Likesie. * testsuite/gas/i386/x86-64-avx512_bf16_vl-inval.s: Likewise. * testsuite/gas/i386/x86-64-avx512_bf16_vl.d: Likewise. * testsuite/gas/i386/x86-64-avx512_bf16_vl.s: Likewise. * testsuite/gas/i386/i386.exp: Add BF16 related tests. opcodes/ 2019-04-05 Xuepeng Guo <xuepeng.guo@intel.com> * i386-dis-evex.h (evex_table): Updated to support BF16 instructions. * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1 and EVEX_W_0F3872_P_3. * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS. (cpu_flags): Add bitfield for CpuAVX512_BF16. * i386-opc.h (enum): Add CpuAVX512_BF16. (i386_cpu_flags): Add bitfield for cpuavx512_bf16. * i386-opc.tbl: Add AVX512 BF16 instructions. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
2019-04-06 02:03:01 +08:00
2019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
* i386-dis-evex.h (evex_table): Updated to support BF16
instructions.
* i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
and EVEX_W_0F3872_P_3.
* i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
(cpu_flags): Add bitfield for CpuAVX512_BF16.
* i386-opc.h (enum): Add CpuAVX512_BF16.
(i386_cpu_flags): Add bitfield for cpuavx512_bf16.
* i386-opc.tbl: Add AVX512 BF16 instructions.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
PowerPC bc extended branch mnemonics and "y" hints This patch fixes a problem with disassembly of branch instructions for processors complying with PowerPC ISA versions prior to version 2.0, ie. those that use "y" bit branch taken hints. Many of the extended bcctr and bclr mnemonics that should have disassembled with a "-" suffix, ie. not taken, did not display the "-" due to the ordering in powerpc_opcodes. I believe it's been that way from the original 85dcf36d72b commit of ppc-opc.c. I've also added a BH field (optional) to a few opcodes. This gives better disassembly in raw mode, showing the branch taken hint in the mnemonic as is done for bc. It would be reasonable to add a BH field to all bcctr, bclr, and bctar extended mnemonics but that runs into a small difficulty: Currently we print all or none of the optional operands. That means for example that "bgectr cr2" would display as "bgectr cr2,0" if a BH field is added to bgectr. * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK. (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics to favour printing of "-" branch hint when using the "y" bit. Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
2019-04-04 15:49:03 +08:00
2019-04-05 Alan Modra <amodra@gmail.com>
* ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
(powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
to favour printing of "-" branch hint when using the "y" bit.
Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
PowerPC disassembler: Don't emit trailing spaces When an instruction has operands, the PowerPC disassembler prints spaces after the opcode so as to line up operands. If the operands are all optional and all default value, then no operands are printed, leaving trailing spaces. This patch fixes that. opcodes/ * ppc-dis.c (print_insn_powerpc): Delay printing spaces after opcode until first operand is output. gas/ * testsuite/gas/ppc/476.d: Remove trailing spaces. * testsuite/gas/ppc/a2.d: Likewise. * testsuite/gas/ppc/booke.d: Likewise. * testsuite/gas/ppc/booke_xcoff.d: Likewise. * testsuite/gas/ppc/e500.d: Likewise. * testsuite/gas/ppc/e500mc.d: Likewise. * testsuite/gas/ppc/e6500.d: Likewise. * testsuite/gas/ppc/htm.d: Likewise. * testsuite/gas/ppc/power6.d: Likewise. * testsuite/gas/ppc/power8.d: Likewise. * testsuite/gas/ppc/power9.d: Likewise. * testsuite/gas/ppc/vle.d: Likewise. ld/ * testsuite/ld-powerpc/tlsexe32.d: Remove trailing spaces. * testsuite/ld-powerpc/tlsopt5.d: Likewise. * testsuite/ld-powerpc/tlsopt5_32.d: Likewise.
2019-04-05 06:50:16 +08:00
2019-04-05 Alan Modra <amodra@gmail.com>
* ppc-dis.c (print_insn_powerpc): Delay printing spaces after
opcode until first operand is output.
Add extended mnemonics for bctar. Fix setting of 'at' branch hints. opcodes/ PR gas/24349 * ppc-opc.c (valid_bo_pre_v2): Add comments. (valid_bo_post_v2): Add support for 'at' branch hints. (insert_bo): Only error on branch on ctr. (get_bo_hint_mask): New function. (insert_boe): Add new 'branch_taken' formal argument. Add support for inserting 'at' branch hints. (extract_boe): Add new 'branch_taken' formal argument. Add support for extracting 'at' branch hints. (insert_bom, extract_bom, insert_bop, extract_bop): New functions. (BOE): Delete operand. (BOM, BOP): New operands. (RM): Update value. (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete. (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-, bcctrl-, bctar-, bctarl->: Replace BOE with BOM. (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+, bcctrl+, bctar+, bctarl+>: Replace BOE with BOP. <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-, bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar, bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar, bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-, bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-, bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+, bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+, bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl, beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-, bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-, buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+, bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar, bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar, bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+, bttarl+>: New extended mnemonics. gas/ PR gas/24349 * testsuite/gas/ppc/power8.s: (bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-, bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar, bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar, bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-, bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-, bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+, bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+, bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl, beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-, bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-, buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+, bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar, bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar, bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+, bttarl+): Add tests of extended mnemonics. * testsuite/gas/ppc/power8.d: Likewise. Update previous bctar tests to expect new extended mnemonics. * testsuite/gas/ppc/a2.s: <bc, bc-, bc+, bcl, bcl-, bcl+>: Update test to not use illegal BO value. Use a more convenient BI value. * testsuite/gas/ppc/a2.d: Update tests for new expect output.
2019-04-04 22:00:29 +08:00
2019-04-04 Peter Bergner <bergner@linux.ibm.com>
PR gas/24349
* ppc-opc.c (valid_bo_pre_v2): Add comments.
(valid_bo_post_v2): Add support for 'at' branch hints.
(insert_bo): Only error on branch on ctr.
(get_bo_hint_mask): New function.
(insert_boe): Add new 'branch_taken' formal argument. Add support
for inserting 'at' branch hints.
(extract_boe): Add new 'branch_taken' formal argument. Add support
for extracting 'at' branch hints.
(insert_bom, extract_bom, insert_bop, extract_bop): New functions.
(BOE): Delete operand.
(BOM, BOP): New operands.
(RM): Update value.
(XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
(powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
(powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
<bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
bttarl+>: New extended mnemonics.
PR24390, Don't decode mtfsb field as a cr field "mtfsb0 4*cr7+lt" doesn't make all that much sense, but unfortunately glibc uses just that instead of "mtfsb0 28" to clear the fpscr xe bit. So for backwards compatibility accept cr field expressions when assembling mtfsb operands, but disassemble to a plain number. PR 24390 include/ * opcode/ppc.h (PPC_OPERAND_CR_REG): Comment. opcodes/ * ppc-opc.c (BTF): Define. (powerpc_opcodes): Use for mtfsb*. * ppc-dis.c (print_insn_powerpc): Print fields with both PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number. gas/ * testsuite/gas/ppc/476.d: Update mtfsb*. * testsuite/gas/ppc/a2.d: Likewise.
2019-03-28 08:06:55 +08:00
2019-03-28 Alan Modra <amodra@gmail.com>
PR 24390
* ppc-opc.c (BTF): Define.
(powerpc_opcodes): Use for mtfsb*.
* ppc-dis.c (print_insn_powerpc): Print fields with both
PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
Arm: Fix Arm disassembler mapping symbol search. Similar to the AArch64 patches the Arm disassembler has the same issues with out of order sections but also a few short comings. For one thing there are multiple code blocks to determine mapping symbols, and they all work slightly different, and neither fully correct. The first thing this patch does is centralise the mapping symbols search into one function mapping_symbol_for_insn. This function is then updated to perform a search in a similar way as AArch64. Their used to be a value has_mapping_symbols which was used to determine the default disassembly for objects that have no mapping symbols. The problem with the approach was that it was determining this value in the same loop that needed it, which is why this field could take on the states -1, 0, 1 where -1 means "don't know". However this means that until you actually find a mapping symbol or reach the end of the disassembly glob, you don't know if you did the right action or not, and if you didn't you can't correct it anymore. This is why the two jump-reloc-veneers-* testcases end up disassembling some insn as data when they shouldn't. Out of order here refers to an object file where sections are not listed in a monotonic increasing VMA order. The ELF ABI for Arm [1] specifies the following for mapping symbols: 1) A text section must always have a corresponding mapping symbol at it's start. 2) Data sections do not require any mapping symbols. 3) The range of a mapping symbol extends from the address it starts on up to the next mapping symbol (exclusive) or section end (inclusive). However there is no defined order between a symbol and it's corresponding mapping symbol in the symbol table. This means that while in general we look up for a corresponding mapping symbol, we have to make at least one check of the symbol below the address being disassembled. When disassembling different PCs within the same section, the search for mapping symbol can be cached somewhat. We know that the mapping symbol corresponding to the current PC is either the previous one used, or one at the same address as the current PC. However this optimization and mapping symbol search must stop as soon as we reach the end or start of the section. Furthermore if we're only disassembling a part of a section, the search is a allowed to search further than the current chunk, but is not allowed to search past it (The mapping symbol if there, must be at the same address, so in practice we usually stop at PC+4). lastly, since only data sections don't require a mapping symbol the default mapping type should be DATA and not INSN as previously defined, however if the binary has had all its symbols stripped than this isn't very useful. To fix this we determine the default based on the section flags. This will allow the disassembler to be more useful on stripped binaries. If there is no section than we assume you to be disassembling INSN. [1] https://developer.arm.com/docs/ihi0044/latest/elf-for-the-arm-architecture-abi-2018q4-documentation#aaelf32-table4-7 binutils/ChangeLog: * testsuite/binutils-all/arm/in-order-all.d: New test. * testsuite/binutils-all/arm/in-order.d: New test. * testsuite/binutils-all/arm/objdump.exp: Support .d tests. * testsuite/binutils-all/arm/out-of-order-all.d: New test. * testsuite/binutils-all/arm/out-of-order.T: New test. * testsuite/binutils-all/arm/out-of-order.d: New test. * testsuite/binutils-all/arm/out-of-order.s: New test. ld/ChangeLog: * testsuite/ld-arm/jump-reloc-veneers-cond-long.d: Update disassembly. * testsuite/ld-arm/jump-reloc-veneers-long.d: Update disassembly. opcodes/ChangeLog: * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols. (mapping_symbol_for_insn): Implement new algorithm. (print_insn): Remove duplicate code.
2019-03-25 20:16:17 +08:00
2019-03-25 Tamar Christina <tamar.christina@arm.com>
* arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
(mapping_symbol_for_insn): Implement new algorithm.
(print_insn): Remove duplicate code.
AArch64: Have -D override mapping symbol as documented. The documentation for -D says that on Arm platforms -D should disassemble data as instructions. "If the target is an ARM architecture this switch also has the effect of forcing the disassembler to decode pieces of data found in code sections as if they were instructions. " This makes it do as it says on the tincan so it's more consistent with aarch32. The usecase here is for baremetal developers who have created their instructions using .word directives instead if .insn. Though for Linux users I do find this behavior somewhat non-optimal. Perhaps there should be a new flag that just disassembles the values following the actual mapping symbol? binutils/ChangeLog: * testsuite/binutils-all/aarch64/in-order-all.d: New test. * testsuite/binutils-all/aarch64/out-of-order-all.d: New test. * testsuite/binutils-all/aarch64/out-of-order.d: opcodes/ChangeLog: * aarch64-dis.c (print_insn_aarch64): Implement override.
2019-03-25 20:14:37 +08:00
2019-03-25 Tamar Christina <tamar.christina@arm.com>
* aarch64-dis.c (print_insn_aarch64):
Implement override.
AArch64: Fix AArch64 disassembler mapping symbol search My previous patch for AArch64 was not enough to catch all the cases where disassembling an out-of-order section could go wrong. It had missed the case DATA sections could be incorrectly disassembled as TEXT. Out of order here refers to an object file where sections are not listed in a monotonic increasing VMA order. The ELF ABI for AArch64 [1] specifies the following for mapping symbols: 1) A text section must always have a corresponding mapping symbol at it's start. 2) Data sections do not require any mapping symbols. 3) The range of a mapping symbol extends from the address it starts on up to the next mapping symbol (exclusive) or section end (inclusive). However there is no defined order between a symbol and it's corresponding mapping symbol in the symbol table. This means that while in general we look up for a corresponding mapping symbol, we have to make at least one check of the symbol below the address being disassembled. When disassembling different PCs within the same section, the search for mapping symbol can be cached somewhat. We know that the mapping symbol corresponding to the current PC is either the previous one used, or one at the same address as the current PC. However this optimization and mapping symbol search must stop as soon as we reach the end or start of the section. Furthermore if we're only disassembling a part of a section, the search is a allowed to search further than the current chunk, but is not allowed to search past it (The mapping symbol if there, must be at the same address, so in practice we usually stop at PC+4). lastly, since only data sections don't require a mapping symbol the default mapping type should be DATA and not INSN as previously defined, however if the binary has had all its symbols stripped than this isn't very useful. To fix this we determine the default based on the section flags. This will allow the disassembler to be more useful on stripped binaries. If there is no section than we assume you to be disassembling INSN. [1] https://developer.arm.com/docs/ihi0056/latest/elf-for-the-arm-64-bit-architecture-aarch64-abi-2018q4#aaelf64-section4-5-4 binutils/ChangeLog: * testsuite/binutils-all/aarch64/in-order.d: New test. * testsuite/binutils-all/aarch64/out-of-order.d: Disassemble data as well. opcodes/ChangeLog: * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search order.
2019-03-25 20:12:03 +08:00
2019-03-25 Tamar Christina <tamar.christina@arm.com>
* aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
order.
AArch64: Fix disassembler bug with out-of-order sections The AArch64 disassembler has an optimization that it uses to reduce the amount it has to search for mapping symbols during disassembly. This optimization assumes that sections are listed in the section header in monotonic increasing VMAs. However this is not a requirement for the ELF specification. Because of this when such "out of order" sections occur the disassembler would pick the wrong mapping symbol to disassemble the section with. This fixes it by explicitly passing along the stop offset for the current disassembly glob and when this changes compared to the previous one we've seen the optimization won't be performed. In effect this restarts the search from a well defined starting point. Usually the symbol's address. The existing stop_vma can't be used for this as it is allowed to be unset and setting this unconditionally would change the semantics of this field. binutils/ChangeLog: * objdump.c (disassemble_bytes): Pass stop_offset. * testsuite/binutils-all/aarch64/out-of-order.T: New test. * testsuite/binutils-all/aarch64/out-of-order.d: New test. * testsuite/binutils-all/aarch64/out-of-order.s: New test. include/ChangeLog: * dis-asm.h (struct disassemble_info): Add stop_offset. opcodes/ChangeLog: * aarch64-dis.c (last_stop_offset): New. (print_insn_aarch64): Use stop_offset.
2019-03-25 20:08:53 +08:00
2019-03-25 Tamar Christina <tamar.christina@arm.com>
* aarch64-dis.c (last_stop_offset): New.
(print_insn_aarch64): Use stop_offset.
ix86: Disable AVX512F when disabling AVX2 Since AVX2 is required for AVX512F, we should disable AVX512F when AVX2 is disabled. gas/ PR gas/24359 * testsuite/gas/i386/i386.exp: Change optimize-6a, optimize-7, x86-64-optimize-7a and x86-64-optimize-8 tests to run_list_test. Remove optimize-6c and x86-64-optimize-7c tests. * testsuite/gas/i386/noavx-3.l: Updated. * testsuite/gas/i386/noavx-4.d: Likewise. * testsuite/gas/i386/noavx-5.d: Likewise. * testsuite/gas/i386/noavx-3.s: Add AVX512F tests. * testsuite/gas/i386/noavx-4.s: Remove AVX512F tests. * testsuite/gas/i386/nosse-5.s: Likewise. * testsuite/gas/i386/optimize-6a.d: Removed. * testsuite/gas/i386/optimize-6c.d: Likewise. * testsuite/gas/i386/optimize-7.d: Likewise. * testsuite/gas/i386/x86-64-optimize-7a.d: Likewise. * testsuite/gas/i386/x86-64-optimize-7c.d: Likewise. * testsuite/gas/i386/x86-64-optimize-8.d: Likewise. * testsuite/gas/i386/optimize-6a.l: New file. * testsuite/gas/i386/optimize-6a.s: Likewise. * testsuite/gas/i386/optimize-7.l: Likewise. * testsuite/gas/i386/x86-64-optimize-7a.l: Likewise. * testsuite/gas/i386/x86-64-optimize-7a.s: Likewise. * testsuite/gas/i386/x86-64-optimize-8.l: Likewise. opcodes/ PR gas/24359 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to CPU_ANY_AVX2_FLAGS. * i386-init.h: Regenerated.
2019-03-19 21:08:15 +08:00
2019-03-19 H.J. Lu <hongjiu.lu@intel.com>
PR gas/24359
* i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
CPU_ANY_AVX2_FLAGS.
* i386-init.h: Regenerated.
x86: Optimize EVEX vector load/store instructions When there is no write mask, we can encode lower 16 128-bit/256-bit EVEX vector register load and store instructions as VEX vector register load and store instructions with -O1. gas/ PR gas/24348 * config/tc-i386.c (optimize_encoding): Encode 128-bit and 256-bit EVEX vector register load/store instructions as VEX vector register load/store instructions for -O1. * doc/c-i386.texi: Update -O1 documentation. * testsuite/gas/i386/i386.exp: Run PR gas/24348 tests. * testsuite/gas/i386/optimize-1.s: Add tests for EVEX vector load/store instructions. * testsuite/gas/i386/optimize-2.s: Likewise. * testsuite/gas/i386/optimize-3.s: Likewise. * testsuite/gas/i386/optimize-5.s: Likewise. * testsuite/gas/i386/x86-64-optimize-2.s: Likewise. * testsuite/gas/i386/x86-64-optimize-3.s: Likewise. * testsuite/gas/i386/x86-64-optimize-4.s: Likewise. * testsuite/gas/i386/x86-64-optimize-5.s: Likewise. * testsuite/gas/i386/x86-64-optimize-6.s: Likewise. * testsuite/gas/i386/optimize-1.d: Updated. * testsuite/gas/i386/optimize-2.d: Likewise. * testsuite/gas/i386/optimize-3.d: Likewise. * testsuite/gas/i386/optimize-4.d: Likewise. * testsuite/gas/i386/optimize-5.d: Likewise. * testsuite/gas/i386/x86-64-optimize-2.d: Likewise. * testsuite/gas/i386/x86-64-optimize-3.d: Likewise. * testsuite/gas/i386/x86-64-optimize-4.d: Likewise. * testsuite/gas/i386/x86-64-optimize-5.d: Likewise. * testsuite/gas/i386/x86-64-optimize-6.d: Likewise. * testsuite/gas/i386/optimize-7.d: New file. * testsuite/gas/i386/optimize-7.s: Likewise. * testsuite/gas/i386/x86-64-optimize-8.d: Likewise. * testsuite/gas/i386/x86-64-optimize-8.s: Likewise. opcodes/ PR gas/24348 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32 and vmovdqu64. * i386-tbl.h: Regenerated.
2019-03-18 08:56:10 +08:00
2019-03-18 H.J. Lu <hongjiu.lu@intel.com>
PR gas/24348
* i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
vmovdqu16, vmovdqu32 and vmovdqu64.
* i386-tbl.h: Regenerated.
Add missing changelogs for previous commits.
2019-03-12 21:23:10 +08:00
2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
* s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
from vstrszb, vstrszh, and vstrszf.
2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
* s390-opc.txt: Add instruction descriptions.
Add missing ChangeLog files for previous patch.
2019-02-09 05:21:52 +08:00
2019-02-08 Jim Wilson <jimw@sifive.com>
* riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
<bne>: Likewise.
Arm: Backport hlt to all architectures. The software trap instruction HLT that was introduced in Armv8-a is used as the semihosting trap instruction in AArch64. In order to allow systems configured to run AArch64 code to also run AArch32 with semihosting it was decided that AArch32 should also use HLT in the case of the "mixed mode" environment. This requires that HLT also be backported to all earlier architectures. The instruction is in the undefined encoding space earlier architectures but must trigger a semihosting trap [3]. The Arm Architectural Reference Manual [1] doesn't explicitly mention this however this is an explicit requirement in the Semihosting-v2 protocol [2]. [1] https://developer.arm.com/docs/ddi0487/latest/arm-architecture-reference-manual-armv8-for-armv8-a-architecture-profile [2] https://developer.arm.com/docs/100863/latest/the-semihosting-interface [3] https://github.com/qemu/qemu/commit/19a6e31c9d2701ef648b70ddcfc3bf64cec8c37e gas/ChangeLog: * config/tc-arm.c (insns): Redefine THUMB_VARIANT and ARM_VARIANT for hlt to armv1. * testsuite/gas/arm/armv8a-automatic-hlt.d: Update TAGs * testsuite/gas/arm/hlt.d: New test. * testsuite/gas/arm/hlt.s: New test. opcodes/ChangeLog: * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
2019-02-08 01:12:23 +08:00
2019-02-07 Tamar Christina <tamar.christina@arm.com>
* arm-dis.c (arm_opcodes): Redefine hlt to armv1.
AArch64: Add verifier for By elem Single and Double sized instructions. The AArch64 instruction set has cut-outs inside instructions encodings for when a given encoding that would normally fall within the encoding space of an instruction is instead undefined. This updates the first few instructions FMLA, FMLA, FMUL and FMULX in the case where sz:L == 11. gas/ChangeLog: PR binutils/23212 * testsuite/gas/aarch64/undefined_by_elem_sz_l.s: New test. * testsuite/gas/aarch64/undefined_by_elem_sz_l.d: New test. opcodes/ChangeLog: PR binutils/23212 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz. * aarch64-opc.c (verify_elem_sd): New. (fields): Add FLD_sz entr. * aarch64-tbl.h (_SIMD_INSN): New. (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and fmulx scalar and vector by element isns.
2019-02-08 00:55:23 +08:00
2019-02-07 Tamar Christina <tamar.christina@arm.com>
PR binutils/23212
* aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
* aarch64-opc.c (verify_elem_sd): New.
(fields): Add FLD_sz entr.
* aarch64-tbl.h (_SIMD_INSN): New.
(aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
fmulx scalar and vector by element isns.
Updated Swedish translation for the opcodes sub-directory
2019-02-07 22:49:38 +08:00
2019-02-07 Nick Clifton <nickc@redhat.com>
* po/sv.po: Updated Swedish translation.
S/390: Implement instruction set extensions opcodes/ChangeLog: 2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com> * s390-mkopc.c (main): Accept arch13 as cpu string. * s390-opc.c: Add new instruction formats and instruction opcode masks. * s390-opc.txt: Add new arch13 instructions. include/ChangeLog: 2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com> * opcode/s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_ARCH13. gas/ChangeLog: 2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com> * config/tc-s390.c (s390_parse_cpu): New entry for arch13. * doc/c-s390.texi: Document arch13 march option. * testsuite/gas/s390/s390.exp: Run the arch13 related tests. * testsuite/gas/s390/zarch-arch13.d: New test. * testsuite/gas/s390/zarch-arch13.s: New test. * testsuite/gas/s390/zarch-z13.d: Expect the renamed mnemonics also for z13.
2019-02-01 00:01:27 +08:00
2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
* s390-mkopc.c (main): Accept arch13 as cpu string.
* s390-opc.c: Add new instruction formats and instruction opcode
masks.
* s390-opc.txt: Add new arch13 instructions.
AArch64: Add missing changelog for Update encodings for stg, st2g, stzg and st2zg
2019-01-25 23:50:01 +08:00
2019-01-25 Sudakshina Das <sudi.das@arm.com>
* aarch64-tbl.h (QL_LDST_AT): Update macro.
(aarch64_opcode): Change encoding for stg, stzg
st2g and st2zg.
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
AArch64: Add new STZGM instruction for Armv8.5-A Memory Tagging Extension. This patch is part of a series of patches to introduce a few changes to the Armv8.5-A Memory Tagging Extension. This patch adds the new STZGM instruction. STGZM Xt, [<Xn|SP>] Committed on behalf of Sudakshina Das. *** gas/ChangeLog *** * testsuite/gas/aarch64/armv8_5-a-memtag.d: New tests for stzgm. * testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise. * testsuite/gas/aarch64/illegal-memtag.l: Likewise. * testsuite/gas/aarch64/illegal-memtag.s: Likewise. *** opcodes/ChangeLog *** * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Likewise. * aarch64-opc-2.c: Likewise. * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
2019-01-25 22:15:45 +08:00
2019-01-25 Sudakshina Das <sudi.das@arm.com>
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Likewise.
* aarch64-opc-2.c: Likewise.
* aarch64-tbl.h (aarch64_opcode): Add new stzgm.
AArch64: Remove ldgv and stgv instructions from Armv8.5-A Memory Tagging Extension. This patch is part of a series of patches to introduce a few changes to the Armv8.5-A Memory Tagging Extension. This patch removes the LDGV and STGV instructions. These instructions needed special infrastructure to support [base]! style for addressing mode. That is also removed now. Committed on behalf of Sudakshina Das. *** gas/ChangeLog *** * config/tc-aarch64.c (parse_address_main): Remove support for [base]! address expression. (parse_operands): Remove support for AARCH64_OPND_ADDR_SIMPLE_2. (warn_unpredictable_ldst): Remove support for ldstgv_indexed. * testsuite/gas/aarch64/armv8_5-a-memtag.d: Remove tests for ldgv and stgv. * testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise. * testsuite/gas/aarch64/illegal-memtag.l: Likewise. * testsuite/gas/aarch64/illegal-memtag.s: Likewise. *** include/ChangeLog *** * opcode/aarch64.h (enum aarch64_opnd): Remove AARCH64_OPND_ADDR_SIMPLE_2. (enum aarch64_insn_class): Remove ldstgv_indexed. *** opcodes/ChangeLog *** * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove. * aarch64-asm.h (ins_addr_simple_2): Likeiwse. * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise. * aarch64-dis.h (ext_addr_simple_2): Likewise. * aarch64-opc.c (operand_general_constraint_met_p): Remove case for ldstgv_indexed. (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2. * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv. (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2. * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated.
2019-01-25 21:57:14 +08:00
2019-01-25 Sudakshina Das <sudi.das@arm.com>
Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
* aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
* aarch64-asm.h (ins_addr_simple_2): Likeiwse.
* aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
* aarch64-dis.h (ext_addr_simple_2): Likewise.
* aarch64-opc.c (operand_general_constraint_met_p): Remove
case for ldstgv_indexed.
(aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
* aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
(AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
Updated translations for some of the binutils subdirectory.
2019-01-23 18:26:54 +08:00
2019-01-23 Nick Clifton <nickc@redhat.com>
* po/pt_BR.po: Updated Brazilian Portuguese translation.
Updated translations for various binutils subdirectories.
2019-01-21 20:59:20 +08:00
2019-01-21 Nick Clifton <nickc@redhat.com>
* po/de.po: Updated German translation.
* po/uk.po: Updated Ukranian translation.
[MIPS] fix typo in mips_arch_choices. opcodes/ * mips-dis.c (mips_arch_choices): Fix typo in gs464, gs464e and gs264e descriptors.
2019-01-20 09:51:30 +08:00
2019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
* mips-dis.c (mips_arch_choices): Fix typo in
gs464, gs464e and gs264e descriptors.
Change version to 2.32.51 and regenerate configure and pot files.
2019-01-20 00:51:42 +08:00
2019-01-19 Nick Clifton <nickc@redhat.com>
* configure: Regenerate.
* po/opcodes.pot: Regenerate.
Add markers for 2.32 branch to NEWS and ChangeLog files.
2019-01-19 23:55:50 +08:00
2018-06-24 Nick Clifton <nickc@redhat.com>
2.32 branch created.
S12Z: Fix disassembly of indexed OPR operands with zero index. gas/ * testsuite/gas/s12z/jsr.s: New case. * testsuite/gas/s12z/jsr.d: New case. opcodes/ * s12z-dis.c (opr_emit_disassembly): Do not omit an index if it is zero.
2018-12-31 15:48:10 +08:00
2019-01-09 John Darrington <john@darrington.wattle.id.au>
S12Z: Don't crash when disassembling invalid instructions. Check for null before dereferencing an operand pointer. Normally this situation should never arise, but could happen if a "partial" instruction is encountered at the end of a file or section. opcodes/ * s12z-dis.c (print_insn_s12z): Do not dereference an operand if it is null.
2019-01-04 16:44:58 +08:00
* s12z-dis.c (print_insn_s12z): Do not dereference an operand
if it is null.
-dis.c (opr_emit_disassembly): Do not omit an index if it is
S12Z: Fix disassembly of indexed OPR operands with zero index. gas/ * testsuite/gas/s12z/jsr.s: New case. * testsuite/gas/s12z/jsr.d: New case. opcodes/ * s12z-dis.c (opr_emit_disassembly): Do not omit an index if it is zero.
2018-12-31 15:48:10 +08:00
zero.
Adjust bfd/warning.m4 egrep patterns Adjust the `bfd/warning.m4` `egrep` patterns to handle preprocessors that do not define `__GNUC__`, leaving the string in the output. bfd/ * warning.m4: Adjust egrep pattern for non-GNU compilers. * configure: Regenerate. binutils/ * configure: Regenerate. gas/ * configure: Regenerate. gold/ * configure: Regenerate. gprof/ * configure: Regenerate. ld/ * configure: Regenerate. opcodes/ * configure: Regenerate.
2019-01-09 11:21:08 +08:00
2019-01-09 Andrew Paprocki <andrew@ishiboo.com>
* configure: Regenerate.
s12z regen * configure: Regenerate. * po/POTFILES.in: Regenerate.
2019-01-07 12:33:43 +08:00
2019-01-07 Alan Modra <amodra@gmail.com>
* configure: Regenerate.
* po/POTFILES.in: Regenerate.
S12Z: opcodes: Separate the decoding of operations from their display. This change adds an abstraction layer between the decoding of machine operations and their disassembled textual representation. This allows the decoding routines to be re-used for other purposes (at the expense) of slightly slower running time. ChangeLog: opcodes/ * s12z-opc.c: New file. * s12z-opc.h: New file. * s12z-dis.c: Removed all code not directly related to display of instructions. Used the interface provided by the new files instead. * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c. * Makefile.in: regenerate. * configure.ac (bfd_s12z_arch): Correct the dependencies. * configure: regenerate.
2019-01-04 01:30:40 +08:00
2019-01-03 John Darrington <john@darrington.wattle.id.au>
* s12z-opc.c: New file.
* s12z-opc.h: New file.
* s12z-dis.c: Removed all code not directly related to display
of instructions. Used the interface provided by the new files
instead.
* Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
s12z regen * configure: Regenerate. * po/POTFILES.in: Regenerate.
2019-01-07 12:33:43 +08:00
* Makefile.in: Regenerate.
S12Z: opcodes: Separate the decoding of operations from their display. This change adds an abstraction layer between the decoding of machine operations and their disassembled textual representation. This allows the decoding routines to be re-used for other purposes (at the expense) of slightly slower running time. ChangeLog: opcodes/ * s12z-opc.c: New file. * s12z-opc.h: New file. * s12z-dis.c: Removed all code not directly related to display of instructions. Used the interface provided by the new files instead. * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c. * Makefile.in: regenerate. * configure.ac (bfd_s12z_arch): Correct the dependencies. * configure: regenerate.
2019-01-04 01:30:40 +08:00
* configure.ac (bfd_s12z_arch): Correct the dependencies.
s12z regen * configure: Regenerate. * po/POTFILES.in: Regenerate.
2019-01-07 12:33:43 +08:00
* configure: Regenerate.
S12Z: opcodes: Separate the decoding of operations from their display. This change adds an abstraction layer between the decoding of machine operations and their disassembled textual representation. This allows the decoding routines to be re-used for other purposes (at the expense) of slightly slower running time. ChangeLog: opcodes/ * s12z-opc.c: New file. * s12z-opc.h: New file. * s12z-dis.c: Removed all code not directly related to display of instructions. Used the interface provided by the new files instead. * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c. * Makefile.in: regenerate. * configure.ac (bfd_s12z_arch): Correct the dependencies. * configure: regenerate.
2019-01-04 01:30:40 +08:00
Update year range in copyright notice of binutils files
2019-01-01 18:31:27 +08:00
2019-01-01 Alan Modra <amodra@gmail.com>
Update year range in copyright notice of all files.
ChangeLog rotation
2019-01-01 18:53:15 +08:00
For older changes see ChangeLog-2018
New 2016 binutils ChangeLog files Note that this does not create bfd/doc/ChangeLog, */testsuite/ChangeLog and include/*/ChangeLog files.
2016-01-01 18:44:31 +08:00
ChangeLog rotation
2019-01-01 18:53:15 +08:00
Copyright (C) 2019 Free Software Foundation, Inc.
New 2016 binutils ChangeLog files Note that this does not create bfd/doc/ChangeLog, */testsuite/ChangeLog and include/*/ChangeLog files.
2016-01-01 18:44:31 +08:00
Copying and distribution of this file, with or without modification,
are permitted in any medium without royalty provided the copyright
notice and this notice are preserved.
Local Variables:
mode: change-log
left-margin: 8
fill-column: 74
version-control: never
End:
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