2019-04-15 18:58:47 +08:00
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2019-04-15 Sudakshina Das <sudi.das@arm.com>
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* arm-dis.c (print_insn_thumb32): Updated to accept new %P
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and %Q patterns.
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2019-04-15 18:53:25 +08:00
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2019-04-15 Sudakshina Das <sudi.das@arm.com>
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* arm-dis.c (thumb32_opcodes): New instruction bfcsel.
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(print_insn_thumb32): Edit the switch case for %Z.
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2019-04-15 18:46:54 +08:00
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2019-04-15 Sudakshina Das <sudi.das@arm.com>
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* arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
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2019-04-15 18:42:10 +08:00
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2019-04-15 Sudakshina Das <sudi.das@arm.com>
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* arm-dis.c (thumb32_opcodes): New instruction bfl.
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2019-04-15 18:37:51 +08:00
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2019-04-15 Sudakshina Das <sudi.das@arm.com>
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* arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
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2019-04-15 18:29:14 +08:00
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2019-04-15 Sudakshina Das <sudi.das@arm.com>
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* arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
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Arm register with r13 and r15 unpredictable.
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(thumb32_opcodes): New instructions for bfx and bflx.
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2019-04-15 18:25:12 +08:00
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2019-04-15 Sudakshina Das <sudi.das@arm.com>
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* arm-dis.c (thumb32_opcodes): New instructions for bf.
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2019-04-15 18:18:57 +08:00
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2019-04-15 Sudakshina Das <sudi.das@arm.com>
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* arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
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2019-04-15 18:06:30 +08:00
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2019-04-15 Sudakshina Das <sudi.das@arm.com>
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* arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
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2019-04-15 17:54:42 +08:00
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2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
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* arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
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2019-04-13 00:39:01 +08:00
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2019-04-12 John Darrington <john@darrington.wattle.id.au>
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s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
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"optr". ("operator" is a reserved word in c++).
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[BINUTILS, AArch64, 2/2] Update Store Allocation Tag instructions
This patch updates the Store allocation tags instructions in
Armv8.5-A Memory Tagging Extension. This is part of the changes
that have been introduced recently in the 00bet10 release
All of these instructions have an updated register operand (Xt -> <Xt|SP>)
- STG <Xt|SP>, [<Xn|SP>, #<simm>]
- STG <Xt|SP>, [<Xn|SP>, #<simm>]!
- STG <Xt|SP>, [<Xn|SP>], #<simm>
- STZG <Xt|SP>, [<Xn|SP>, #<simm>]
- STZG <Xt|SP>, [<Xn|SP>, #<simm>]!
- STZG <Xt|SP>, [<Xn|SP>], #<simm>
- ST2G <Xt|SP>, [<Xn|SP>, #<simm>]
- ST2G <Xt|SP>, [<Xn|SP>, #<simm>]!
- ST2G <Xt|SP>, [<Xn|SP>], #<simm>
- STZ2G <Xt|SP>, [<Xn|SP>, #<simm>]
- STZ2G <Xt|SP>, [<Xn|SP>, #<simm>]!
- STZ2G <Xt|SP>, [<Xn|SP>], #<simm>
In order to accept <Rt|SP> a new operand type Rt_SP is introduced which has
the same field as FLD_Rt but follows other semantics of Rn_SP.
*** gas/ChangeLog ***
2019-04-11 Sudakshina Das <sudi.das@arm.com>
* config/tc-aarch64.c (process_omitted_operand): Add case for
AARCH64_OPND_Rt_SP.
(parse_operands): Likewise.
* testsuite/gas/aarch64/armv8_5-a-memtag.d: Update tests.
* testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise.
* testsuite/gas/aarch64/illegal-memtag.l: Likewise.
* testsuite/gas/aarch64/illegal-memtag.s: Likewise.
*** include/ChangeLog ***
2019-04-11 Sudakshina Das <sudi.das@arm.com>
* opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_Rt_SP.
*** opcodes/ChangeLog ***
2019-04-11 Sudakshina Das <sudi.das@arm.com>
* aarch64-opc.c (aarch64_print_operand): Add case for
AARCH64_OPND_Rt_SP.
(verify_constraints): Likewise.
* aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
(struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
to accept Rt|SP as first operand.
(AARCH64_OPERANDS): Add new Rt_SP.
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
2019-04-11 17:19:37 +08:00
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2019-04-11 Sudakshina Das <sudi.das@arm.com>
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* aarch64-opc.c (aarch64_print_operand): Add case for
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AARCH64_OPND_Rt_SP.
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(verify_constraints): Likewise.
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* aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
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(struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
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to accept Rt|SP as first operand.
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(AARCH64_OPERANDS): Add new Rt_SP.
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* aarch64-asm-2.c: Regenerated.
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* aarch64-dis-2.c: Regenerated.
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* aarch64-opc-2.c: Regenerated.
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2019-04-11 17:13:23 +08:00
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2019-04-11 Sudakshina Das <sudi.das@arm.com>
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* aarch64-asm-2.c: Regenerated.
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* aarch64-dis-2.c: Likewise.
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* aarch64-opc-2.c: Likewise.
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* aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
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2019-04-09 17:30:26 +08:00
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2019-04-09 Robert Suchanek <robert.suchanek@mips.com>
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* mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
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2019-04-09 02:06:04 +08:00
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2019-04-08 H.J. Lu <hongjiu.lu@intel.com>
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* i386-opc.tbl: Consolidate AVX512 BF16 entries.
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* i386-init.h: Regenerated.
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2019-04-07 19:17:06 +08:00
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2019-04-07 Alan Modra <amodra@gmail.com>
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* ppc-dis.c (print_insn_powerpc): Use a tiny state machine
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op_separator to control printing of spaces, comma and parens
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rather than need_comma, need_paren and spaces vars.
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2019-04-07 19:12:16 +08:00
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2019-04-07 Alan Modra <amodra@gmail.com>
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PR 24421
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* arm-dis.c (print_insn_coprocessor): Correct bracket placement.
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(print_insn_neon, print_insn_arm): Likewise.
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2019-04-06 02:03:01 +08:00
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2019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
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* i386-dis-evex.h (evex_table): Updated to support BF16
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instructions.
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* i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
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and EVEX_W_0F3872_P_3.
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* i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
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(cpu_flags): Add bitfield for CpuAVX512_BF16.
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* i386-opc.h (enum): Add CpuAVX512_BF16.
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(i386_cpu_flags): Add bitfield for cpuavx512_bf16.
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* i386-opc.tbl: Add AVX512 BF16 instructions.
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* i386-init.h: Regenerated.
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* i386-tbl.h: Likewise.
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PowerPC bc extended branch mnemonics and "y" hints
This patch fixes a problem with disassembly of branch instructions
for processors complying with PowerPC ISA versions prior to version
2.0, ie. those that use "y" bit branch taken hints. Many of the
extended bcctr and bclr mnemonics that should have disassembled with a
"-" suffix, ie. not taken, did not display the "-" due to the ordering
in powerpc_opcodes. I believe it's been that way from the original
85dcf36d72b commit of ppc-opc.c.
I've also added a BH field (optional) to a few opcodes. This gives
better disassembly in raw mode, showing the branch taken hint in the
mnemonic as is done for bc. It would be reasonable to add a BH
field to all bcctr, bclr, and bctar extended mnemonics but that runs
into a small difficulty: Currently we print all or none of the
optional operands. That means for example that "bgectr cr2" would
display as "bgectr cr2,0" if a BH field is added to bgectr.
* ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
(powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
to favour printing of "-" branch hint when using the "y" bit.
Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
2019-04-04 15:49:03 +08:00
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2019-04-05 Alan Modra <amodra@gmail.com>
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* ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
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(powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
|
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to favour printing of "-" branch hint when using the "y" bit.
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Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
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2019-04-05 06:50:16 +08:00
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2019-04-05 Alan Modra <amodra@gmail.com>
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* ppc-dis.c (print_insn_powerpc): Delay printing spaces after
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opcode until first operand is output.
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Add extended mnemonics for bctar. Fix setting of 'at' branch hints.
opcodes/
PR gas/24349
* ppc-opc.c (valid_bo_pre_v2): Add comments.
(valid_bo_post_v2): Add support for 'at' branch hints.
(insert_bo): Only error on branch on ctr.
(get_bo_hint_mask): New function.
(insert_boe): Add new 'branch_taken' formal argument. Add support
for inserting 'at' branch hints.
(extract_boe): Add new 'branch_taken' formal argument. Add support
for extracting 'at' branch hints.
(insert_bom, extract_bom, insert_bop, extract_bop): New functions.
(BOE): Delete operand.
(BOM, BOP): New operands.
(RM): Update value.
(XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
(powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
(powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
<bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
bttarl+>: New extended mnemonics.
gas/
PR gas/24349
* testsuite/gas/ppc/power8.s: (bdnztar, bdnztarl, bdztar, bdztarl,
btar, btarl, bdnztar-, bdnztarl-, bdnztar+, bdnztarl+, bdztar-,
bdztarl-, bdztar+, bdztarl+, bgetar, bnltar, bgetarl, bnltarl,
bletar, bngtar, bletarl, bngtarl, bnetar, bnetarl, bnstar, bnutar,
bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-, bnltarl-, bletar-,
bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-, bnstar-, bnutar-,
bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+, bnltarl+, bletar+,
bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+, bnstar+, bnutar+,
bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl, beqtar,
beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
bttarl+): Add tests of extended mnemonics.
* testsuite/gas/ppc/power8.d: Likewise. Update previous bctar tests
to expect new extended mnemonics.
* testsuite/gas/ppc/a2.s: <bc, bc-, bc+, bcl, bcl-, bcl+>: Update test
to not use illegal BO value. Use a more convenient BI value.
* testsuite/gas/ppc/a2.d: Update tests for new expect output.
2019-04-04 22:00:29 +08:00
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|
2019-04-04 Peter Bergner <bergner@linux.ibm.com>
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PR gas/24349
|
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* ppc-opc.c (valid_bo_pre_v2): Add comments.
|
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(valid_bo_post_v2): Add support for 'at' branch hints.
|
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(insert_bo): Only error on branch on ctr.
|
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(get_bo_hint_mask): New function.
|
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(insert_boe): Add new 'branch_taken' formal argument. Add support
|
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|
|
for inserting 'at' branch hints.
|
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|
|
(extract_boe): Add new 'branch_taken' formal argument. Add support
|
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|
|
|
for extracting 'at' branch hints.
|
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|
|
(insert_bom, extract_bom, insert_bop, extract_bop): New functions.
|
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(BOE): Delete operand.
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(BOM, BOP): New operands.
|
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(RM): Update value.
|
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(XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
|
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(powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
|
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|
bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
|
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|
(powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
|
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bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
|
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<bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
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bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
|
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bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
|
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bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
|
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bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
|
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bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
|
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bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
|
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bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
|
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|
beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
|
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bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
|
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buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
|
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bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
|
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bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
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bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
|
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bttarl+>: New extended mnemonics.
|
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|
2019-03-28 08:06:55 +08:00
|
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|
2019-03-28 Alan Modra <amodra@gmail.com>
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PR 24390
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* ppc-opc.c (BTF): Define.
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(powerpc_opcodes): Use for mtfsb*.
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* ppc-dis.c (print_insn_powerpc): Print fields with both
|
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|
PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
|
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Arm: Fix Arm disassembler mapping symbol search.
Similar to the AArch64 patches the Arm disassembler has the same issues with
out of order sections but also a few short comings.
For one thing there are multiple code blocks to determine mapping symbols, and
they all work slightly different, and neither fully correct. The first thing
this patch does is centralise the mapping symbols search into one function
mapping_symbol_for_insn. This function is then updated to perform a search in
a similar way as AArch64.
Their used to be a value has_mapping_symbols which was used to determine the
default disassembly for objects that have no mapping symbols. The problem with
the approach was that it was determining this value in the same loop that needed
it, which is why this field could take on the states -1, 0, 1 where -1 means
"don't know". However this means that until you actually find a mapping symbol
or reach the end of the disassembly glob, you don't know if you did the right
action or not, and if you didn't you can't correct it anymore.
This is why the two jump-reloc-veneers-* testcases end up disassembling some
insn as data when they shouldn't.
Out of order here refers to an object file where sections are not listed in a
monotonic increasing VMA order.
The ELF ABI for Arm [1] specifies the following for mapping symbols:
1) A text section must always have a corresponding mapping symbol at it's
start.
2) Data sections do not require any mapping symbols.
3) The range of a mapping symbol extends from the address it starts on up to
the next mapping symbol (exclusive) or section end (inclusive).
However there is no defined order between a symbol and it's corresponding
mapping symbol in the symbol table. This means that while in general we look
up for a corresponding mapping symbol, we have to make at least one check of
the symbol below the address being disassembled.
When disassembling different PCs within the same section, the search for mapping
symbol can be cached somewhat. We know that the mapping symbol corresponding to
the current PC is either the previous one used, or one at the same address as
the current PC.
However this optimization and mapping symbol search must stop as soon as we
reach the end or start of the section. Furthermore if we're only disassembling
a part of a section, the search is a allowed to search further than the current
chunk, but is not allowed to search past it (The mapping symbol if there, must
be at the same address, so in practice we usually stop at PC+4).
lastly, since only data sections don't require a mapping symbol the default
mapping type should be DATA and not INSN as previously defined, however if the
binary has had all its symbols stripped than this isn't very useful. To fix
this we determine the default based on the section flags. This will allow the
disassembler to be more useful on stripped binaries. If there is no section
than we assume you to be disassembling INSN.
[1] https://developer.arm.com/docs/ihi0044/latest/elf-for-the-arm-architecture-abi-2018q4-documentation#aaelf32-table4-7
binutils/ChangeLog:
* testsuite/binutils-all/arm/in-order-all.d: New test.
* testsuite/binutils-all/arm/in-order.d: New test.
* testsuite/binutils-all/arm/objdump.exp: Support .d tests.
* testsuite/binutils-all/arm/out-of-order-all.d: New test.
* testsuite/binutils-all/arm/out-of-order.T: New test.
* testsuite/binutils-all/arm/out-of-order.d: New test.
* testsuite/binutils-all/arm/out-of-order.s: New test.
ld/ChangeLog:
* testsuite/ld-arm/jump-reloc-veneers-cond-long.d: Update disassembly.
* testsuite/ld-arm/jump-reloc-veneers-long.d: Update disassembly.
opcodes/ChangeLog:
* arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
(mapping_symbol_for_insn): Implement new algorithm.
(print_insn): Remove duplicate code.
2019-03-25 20:16:17 +08:00
|
|
|
|
2019-03-25 Tamar Christina <tamar.christina@arm.com>
|
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|
|
|
|
|
|
|
|
|
|
* arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
|
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|
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|
|
(mapping_symbol_for_insn): Implement new algorithm.
|
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|
|
(print_insn): Remove duplicate code.
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|
2019-03-25 20:14:37 +08:00
|
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|
|
2019-03-25 Tamar Christina <tamar.christina@arm.com>
|
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|
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|
|
* aarch64-dis.c (print_insn_aarch64):
|
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|
|
|
Implement override.
|
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|
|
2019-03-25 20:12:03 +08:00
|
|
|
|
2019-03-25 Tamar Christina <tamar.christina@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
|
|
|
|
|
|
order.
|
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|
|
2019-03-25 20:08:53 +08:00
|
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|
|
2019-03-25 Tamar Christina <tamar.christina@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-dis.c (last_stop_offset): New.
|
|
|
|
|
|
(print_insn_aarch64): Use stop_offset.
|
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|
|
2019-03-19 21:08:15 +08:00
|
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|
2019-03-19 H.J. Lu <hongjiu.lu@intel.com>
|
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|
|
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|
|
PR gas/24359
|
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|
|
* i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
|
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|
|
|
|
CPU_ANY_AVX2_FLAGS.
|
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|
|
|
|
* i386-init.h: Regenerated.
|
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|
2019-03-18 08:56:10 +08:00
|
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|
2019-03-18 H.J. Lu <hongjiu.lu@intel.com>
|
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|
|
|
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|
|
|
PR gas/24348
|
|
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|
|
* i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
|
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|
|
|
|
vmovdqu16, vmovdqu32 and vmovdqu64.
|
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|
|
|
* i386-tbl.h: Regenerated.
|
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|
2019-03-12 21:23:10 +08:00
|
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|
|
2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
|
|
|
|
|
|
from vstrszb, vstrszh, and vstrszf.
|
|
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|
2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
|
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|
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|
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|
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|
|
* s390-opc.txt: Add instruction descriptions.
|
|
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|
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|
|
2019-02-09 05:21:52 +08:00
|
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|
|
2019-02-08 Jim Wilson <jimw@sifive.com>
|
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|
|
|
|
|
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|
|
* riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
|
|
|
|
|
|
<bne>: Likewise.
|
|
|
|
|
|
|
2019-02-08 01:12:23 +08:00
|
|
|
|
2019-02-07 Tamar Christina <tamar.christina@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c (arm_opcodes): Redefine hlt to armv1.
|
|
|
|
|
|
|
2019-02-08 00:55:23 +08:00
|
|
|
|
2019-02-07 Tamar Christina <tamar.christina@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR binutils/23212
|
|
|
|
|
|
* aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
|
|
|
|
|
|
* aarch64-opc.c (verify_elem_sd): New.
|
|
|
|
|
|
(fields): Add FLD_sz entr.
|
|
|
|
|
|
* aarch64-tbl.h (_SIMD_INSN): New.
|
|
|
|
|
|
(aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
|
|
|
|
|
|
fmulx scalar and vector by element isns.
|
|
|
|
|
|
|
2019-02-07 22:49:38 +08:00
|
|
|
|
2019-02-07 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* po/sv.po: Updated Swedish translation.
|
|
|
|
|
|
|
2019-02-01 00:01:27 +08:00
|
|
|
|
2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* s390-mkopc.c (main): Accept arch13 as cpu string.
|
|
|
|
|
|
* s390-opc.c: Add new instruction formats and instruction opcode
|
|
|
|
|
|
masks.
|
|
|
|
|
|
* s390-opc.txt: Add new arch13 instructions.
|
|
|
|
|
|
|
2019-01-25 23:50:01 +08:00
|
|
|
|
2019-01-25 Sudakshina Das <sudi.das@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-tbl.h (QL_LDST_AT): Update macro.
|
|
|
|
|
|
(aarch64_opcode): Change encoding for stg, stzg
|
|
|
|
|
|
st2g and st2zg.
|
|
|
|
|
|
* aarch64-asm-2.c: Regenerated.
|
|
|
|
|
|
* aarch64-dis-2.c: Regenerated.
|
|
|
|
|
|
* aarch64-opc-2.c: Regenerated.
|
|
|
|
|
|
|
2019-01-25 22:15:45 +08:00
|
|
|
|
2019-01-25 Sudakshina Das <sudi.das@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-asm-2.c: Regenerated.
|
|
|
|
|
|
* aarch64-dis-2.c: Likewise.
|
|
|
|
|
|
* aarch64-opc-2.c: Likewise.
|
|
|
|
|
|
* aarch64-tbl.h (aarch64_opcode): Add new stzgm.
|
|
|
|
|
|
|
2019-01-25 21:57:14 +08:00
|
|
|
|
2019-01-25 Sudakshina Das <sudi.das@arm.com>
|
|
|
|
|
|
Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
|
|
|
|
|
|
* aarch64-asm.h (ins_addr_simple_2): Likeiwse.
|
|
|
|
|
|
* aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
|
|
|
|
|
|
* aarch64-dis.h (ext_addr_simple_2): Likewise.
|
|
|
|
|
|
* aarch64-opc.c (operand_general_constraint_met_p): Remove
|
|
|
|
|
|
case for ldstgv_indexed.
|
|
|
|
|
|
(aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
|
|
|
|
|
|
* aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
|
|
|
|
|
|
(AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
|
|
|
|
|
|
* aarch64-asm-2.c: Regenerated.
|
|
|
|
|
|
* aarch64-dis-2.c: Regenerated.
|
|
|
|
|
|
* aarch64-opc-2.c: Regenerated.
|
|
|
|
|
|
|
2019-01-23 18:26:54 +08:00
|
|
|
|
2019-01-23 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* po/pt_BR.po: Updated Brazilian Portuguese translation.
|
|
|
|
|
|
|
2019-01-21 20:59:20 +08:00
|
|
|
|
2019-01-21 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* po/de.po: Updated German translation.
|
|
|
|
|
|
* po/uk.po: Updated Ukranian translation.
|
|
|
|
|
|
|
2019-01-20 09:51:30 +08:00
|
|
|
|
2019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
|
|
|
|
|
|
* mips-dis.c (mips_arch_choices): Fix typo in
|
|
|
|
|
|
gs464, gs464e and gs264e descriptors.
|
|
|
|
|
|
|
2019-01-20 00:51:42 +08:00
|
|
|
|
2019-01-19 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* configure: Regenerate.
|
|
|
|
|
|
* po/opcodes.pot: Regenerate.
|
|
|
|
|
|
|
2019-01-19 23:55:50 +08:00
|
|
|
|
2018-06-24 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
2.32 branch created.
|
|
|
|
|
|
|
2018-12-31 15:48:10 +08:00
|
|
|
|
2019-01-09 John Darrington <john@darrington.wattle.id.au>
|
|
|
|
|
|
|
2019-01-04 16:44:58 +08:00
|
|
|
|
* s12z-dis.c (print_insn_s12z): Do not dereference an operand
|
|
|
|
|
|
if it is null.
|
|
|
|
|
|
-dis.c (opr_emit_disassembly): Do not omit an index if it is
|
2018-12-31 15:48:10 +08:00
|
|
|
|
zero.
|
|
|
|
|
|
|
2019-01-09 11:21:08 +08:00
|
|
|
|
2019-01-09 Andrew Paprocki <andrew@ishiboo.com>
|
|
|
|
|
|
|
|
|
|
|
|
* configure: Regenerate.
|
|
|
|
|
|
|
2019-01-07 12:33:43 +08:00
|
|
|
|
2019-01-07 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* configure: Regenerate.
|
|
|
|
|
|
* po/POTFILES.in: Regenerate.
|
|
|
|
|
|
|
2019-01-04 01:30:40 +08:00
|
|
|
|
2019-01-03 John Darrington <john@darrington.wattle.id.au>
|
|
|
|
|
|
|
|
|
|
|
|
* s12z-opc.c: New file.
|
|
|
|
|
|
* s12z-opc.h: New file.
|
|
|
|
|
|
* s12z-dis.c: Removed all code not directly related to display
|
|
|
|
|
|
of instructions. Used the interface provided by the new files
|
|
|
|
|
|
instead.
|
|
|
|
|
|
* Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
|
2019-01-07 12:33:43 +08:00
|
|
|
|
* Makefile.in: Regenerate.
|
2019-01-04 01:30:40 +08:00
|
|
|
|
* configure.ac (bfd_s12z_arch): Correct the dependencies.
|
2019-01-07 12:33:43 +08:00
|
|
|
|
* configure: Regenerate.
|
2019-01-04 01:30:40 +08:00
|
|
|
|
|
2019-01-01 18:31:27 +08:00
|
|
|
|
2019-01-01 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
Update year range in copyright notice of all files.
|
|
|
|
|
|
|
2019-01-01 18:53:15 +08:00
|
|
|
|
For older changes see ChangeLog-2018
|
2016-01-01 18:44:31 +08:00
|
|
|
|
|
2019-01-01 18:53:15 +08:00
|
|
|
|
Copyright (C) 2019 Free Software Foundation, Inc.
|
2016-01-01 18:44:31 +08:00
|
|
|
|
|
|
|
|
|
|
Copying and distribution of this file, with or without modification,
|
|
|
|
|
|
are permitted in any medium without royalty provided the copyright
|
|
|
|
|
|
notice and this notice are preserved.
|
|
|
|
|
|
|
|
|
|
|
|
Local Variables:
|
|
|
|
|
|
mode: change-log
|
|
|
|
|
|
left-margin: 8
|
|
|
|
|
|
fill-column: 74
|
|
|
|
|
|
version-control: never
|
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|
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End:
|
