binutils-gdb/gas/config/tc-i386.h

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/* tc-i386.h -- Header file for tc-i386.c
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Copyright 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
2001, 2002, 2003, 2004, 2005, 2006, 2007
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Free Software Foundation, Inc.
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This file is part of GAS, the GNU Assembler.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
GAS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GAS; see the file COPYING. If not, write to the Free
Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
02110-1301, USA. */
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#ifndef TC_I386
#define TC_I386 1
#include "opcodes/i386-opc.h"
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struct fix;
#define TARGET_BYTES_BIG_ENDIAN 0
#define TARGET_ARCH bfd_arch_i386
#define TARGET_MACH (i386_mach ())
extern unsigned long i386_mach (void);
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#ifdef TE_FreeBSD
#define AOUT_TARGET_FORMAT "a.out-i386-freebsd"
#endif
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#ifdef TE_NetBSD
#define AOUT_TARGET_FORMAT "a.out-i386-netbsd"
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#endif
#ifdef TE_386BSD
#define AOUT_TARGET_FORMAT "a.out-i386-bsd"
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#endif
#ifdef TE_LINUX
#define AOUT_TARGET_FORMAT "a.out-i386-linux"
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#endif
#ifdef TE_Mach
#define AOUT_TARGET_FORMAT "a.out-mach3"
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#endif
#ifdef TE_DYNIX
#define AOUT_TARGET_FORMAT "a.out-i386-dynix"
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#endif
#ifndef AOUT_TARGET_FORMAT
#define AOUT_TARGET_FORMAT "a.out-i386"
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#endif
#ifdef TE_FreeBSD
#define ELF_TARGET_FORMAT "elf32-i386-freebsd"
#define ELF_TARGET_FORMAT64 "elf64-x86-64-freebsd"
2005-05-05 Paul Brook <paul@codesourcery.com> bfd/ * config.bfd: Use bfd_elf32_i386_vxworks_vec for i?86-*-vxworks. * configure.in: Add bfd_elf32_i386_vxworks_vec. i386 targets need elf-vxworks.lo. * configure: Regenerate. * Makefile.am (BFD32_BACKENDS): Add elf-vxworks.lo. (BFD32_BACKENDS_CFILES): Add elf-vxworks.c. (elf32-i386.lo): Depend on elf-vxworks.h. (elf-vxworks.lo): New rule. * Makefile.in: Regenerate. * elf-bfd.h (elf_backend_data): Update type of elf_backend_emit_relocs. (_bfd_elf_link_output_relocs): Update prototype. * elflink.c (_bfd_elf_link_output_relocs): Always use bed->elf_backend_emit_relocs when outputting relocations. * elfxx-target.h (elf_backend_emit_relocs): Default to _bfd_elf_link_output_relocs. * targets.c (bfd_elf32_i386_vxworks_vec): Declare. (_bfd_target_vector): Add bfd_elf32_i386_vxworks_vec. * elf32-i386.c: Add elf32-i386-vxworks target BFD. (elf_i386_plt0_entry): Remove padding. (elf_i386_pic_plt0_entry): Ditto. (PLTRESOLVE_RELOCS_SHLIB, PLTRESOLVE_RELOCS): Define. (PLT_NON_JUMP_SLOT_RELOCS): Define. (elf_i386_link_hash_table): Add srelplt2, hgot, hplt, is_vxworks and plt0_pad_byte fields. (elf_i386_link_hash_table_create): Zero them. (elf_i386_create_dynamic_sections): Create static relocation section. (allocate_dynrelocs): Allocate space for static PLT relocations. (elf_i386_size_dynamic_sections): Save shortcuts to PLT and GOT symbols. Give PLT symbols function type. Don't strip PLT sections if we have exported symbols from them. (elf_i386_finish_dynamic_symbol): Fill in VxWorks PLT static relocation section. Don't mark _GLOBAL_OFFSET_TABLE_ as absolute on VxWorks. (elf_i386_finish_dynamic_sections): Allow different pad bytes. Add relocation for GOT location. Fill in PLT static relocations. (elf_i386_vxworks_link_hash_table_create): New function. (elf_i386_vxworks_link_output_symbol_hook): New function. * elf-vxworks.h: New file. gas/ * config/tc-i386.h (ELF_TARGET_FORMAT): Define for TE_VXWORKS. gas/testsuite/ * gas/i386/i386.exp: Don't run divide test on vxworks. ld/ * Makefile.am: Add eelf_i386_vxworks. * Makefile.in: Regenerate. * configure.tgt: Make i?86-*-vxworks use targ_emul=elf_i386_vxworks. * emulparams/elf_i386_vxworks.sh: New file. * emulparams/vxworks.sh: New file. * scripttempl/elf.sc: Add DATA_END_SYMBOLS and ETEXT_NAME.
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#elif defined (TE_VXWORKS)
#define ELF_TARGET_FORMAT "elf32-i386-vxworks"
#endif
2005-05-05 Paul Brook <paul@codesourcery.com> bfd/ * config.bfd: Use bfd_elf32_i386_vxworks_vec for i?86-*-vxworks. * configure.in: Add bfd_elf32_i386_vxworks_vec. i386 targets need elf-vxworks.lo. * configure: Regenerate. * Makefile.am (BFD32_BACKENDS): Add elf-vxworks.lo. (BFD32_BACKENDS_CFILES): Add elf-vxworks.c. (elf32-i386.lo): Depend on elf-vxworks.h. (elf-vxworks.lo): New rule. * Makefile.in: Regenerate. * elf-bfd.h (elf_backend_data): Update type of elf_backend_emit_relocs. (_bfd_elf_link_output_relocs): Update prototype. * elflink.c (_bfd_elf_link_output_relocs): Always use bed->elf_backend_emit_relocs when outputting relocations. * elfxx-target.h (elf_backend_emit_relocs): Default to _bfd_elf_link_output_relocs. * targets.c (bfd_elf32_i386_vxworks_vec): Declare. (_bfd_target_vector): Add bfd_elf32_i386_vxworks_vec. * elf32-i386.c: Add elf32-i386-vxworks target BFD. (elf_i386_plt0_entry): Remove padding. (elf_i386_pic_plt0_entry): Ditto. (PLTRESOLVE_RELOCS_SHLIB, PLTRESOLVE_RELOCS): Define. (PLT_NON_JUMP_SLOT_RELOCS): Define. (elf_i386_link_hash_table): Add srelplt2, hgot, hplt, is_vxworks and plt0_pad_byte fields. (elf_i386_link_hash_table_create): Zero them. (elf_i386_create_dynamic_sections): Create static relocation section. (allocate_dynrelocs): Allocate space for static PLT relocations. (elf_i386_size_dynamic_sections): Save shortcuts to PLT and GOT symbols. Give PLT symbols function type. Don't strip PLT sections if we have exported symbols from them. (elf_i386_finish_dynamic_symbol): Fill in VxWorks PLT static relocation section. Don't mark _GLOBAL_OFFSET_TABLE_ as absolute on VxWorks. (elf_i386_finish_dynamic_sections): Allow different pad bytes. Add relocation for GOT location. Fill in PLT static relocations. (elf_i386_vxworks_link_hash_table_create): New function. (elf_i386_vxworks_link_output_symbol_hook): New function. * elf-vxworks.h: New file. gas/ * config/tc-i386.h (ELF_TARGET_FORMAT): Define for TE_VXWORKS. gas/testsuite/ * gas/i386/i386.exp: Don't run divide test on vxworks. ld/ * Makefile.am: Add eelf_i386_vxworks. * Makefile.in: Regenerate. * configure.tgt: Make i?86-*-vxworks use targ_emul=elf_i386_vxworks. * emulparams/elf_i386_vxworks.sh: New file. * emulparams/vxworks.sh: New file. * scripttempl/elf.sc: Add DATA_END_SYMBOLS and ETEXT_NAME.
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#ifndef ELF_TARGET_FORMAT
#define ELF_TARGET_FORMAT "elf32-i386"
#endif
#ifndef ELF_TARGET_FORMAT64
#define ELF_TARGET_FORMAT64 "elf64-x86-64"
#endif
* tc-i386.h (i386_target_format): Define even for ELFs. (QWORD_MNEM_SUFFIX): New macro. (CpuK6,CpuAthlon,CpuSledgehammer, Cpu64, CpuNo64, CpuUnknownFlags): New macros (CpuMMX,CpuSSE,Cpu3dnow, CpuUnknown): Renumber. (IgnoreSize, DefaultSize, No_?Suf, FWait, IsString, regKludge, IsPrefix, ImmExt): Renumber. (Size64, No_qSuf, NoRex64, Rex64): New macros. (Reg64, Imm32S, Imm64, Disp32S, Disp64): New macros. (Imm8, Imm8S, Imm16, Imm32, Imm1, BaseIndex, Disp8, Disp16, Disp32, InOutPortReg,ShiftCount, Control, Debug, Test, FloatReg, FloatAcc, SReg2, SReg3, Acc, JumpAbsolute, RegMMX, RegXMM, EsSeg, InvMem): Renumber. (Reg, WordReg): Add Reg64. (Imm): Add Imm32S and Imm64. (EncImm): New. (Disp): Add Disp64 and Disp32S. (AnyMem): Add Disp32S. (RegRex, RegRex64): New macros. (rex_byte): New type. * tc-i386.c (set_16bit_code_flag): Kill. (fits_in_unsigned_long, fits_in_signed_long): New functions. (reloc): New parameter "signed"; support x86_64. (set_code_flag): New. (DEFAULT_ARCH): New macro; default to "i386". (default_arch): New static variable. (struct _i386_insn): New fields Operand_PCrel; rex. (flag_16bit_code): Kill; All tests replaced to "flag_code == CODE_64BIT"; (flag_code): New enum and static variable. (use_rela_relocations): New static variable. (flag_code_names): New static variable. (cpu_arch_flags): Default to CpuUnknownFlags|CpuNo64. (cpu_arch): Add "sledgehammer"; Add CPUAthlon to Athlon and CpuK6 to K6 and Athlon. (i386_align_code): Return plain "nop" for x86_64. (mode_from_disp_size): Support Disp32S. (smallest_imm_type): Support Imm32S and Imm64. (offset_in_range): Support size of 8. (set_cpu_arch): Do not clobber to Cpu64/CpuNo64. (md_pseudo_table): Add "code64"; use set_code_flat. (md_begin): Emit sane error message on hash failure. (tc_i386_fix_adjustable): Support x86_64 relocations. (md_assemble): Support QWORD_MNEM_SUFFIX, REX registers, instructions supported on particular arch just partially, output of 64bit immediates, handling of Imm32S and Disp32S type. (i386_immedaite): Support x86_64 relocations; support 64bit constants. (i386_displacement): Likewise. (i386_index_check): Cleanup; support 64bit addresses. (md_apply_fix3): Support x86_64 relocation and rela. (md_longopts): Add "32" and "64". (md_parse_option): Add OPTION_32 and OPTION_64. (i386_target_format): Call even for ELFs; choose between elf64-x86-64 and elf32-i386. (i386_validate_fix): Refuse GOTOFF in 64bit mode. (tc_gen_reloc): Support rela relocations and x86_64. (intel_e09_1): Support QWORD. * i386.h (i386_optab): Replace "Imm" with "EncImm". (i386_regtab): Add flags field.
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#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
|| defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
extern const char *i386_target_format (void);
#define TARGET_FORMAT i386_target_format ()
#else
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#ifdef OBJ_ELF
#define TARGET_FORMAT ELF_TARGET_FORMAT
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#endif
#ifdef OBJ_AOUT
#define TARGET_FORMAT AOUT_TARGET_FORMAT
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#endif
#endif
#if (defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF))
#define md_end i386_elf_emit_arch_note
extern void i386_elf_emit_arch_note (void);
#endif
#define SUB_SEGMENT_ALIGN(SEG, FRCHAIN) 0
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#define LOCAL_LABELS_FB 1
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extern const char extra_symbol_chars[];
#define tc_symbol_chars extra_symbol_chars
extern const char *i386_comment_chars;
#define tc_comment_chars i386_comment_chars
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/* Prefixes will be emitted in the order defined below.
WAIT_PREFIX must be the first prefix since FWAIT is really is an
instruction, and so must come before any prefixes.
The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
LOCKREP_PREFIX. */
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#define WAIT_PREFIX 0
#define SEG_PREFIX 1
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#define ADDR_PREFIX 2
#define DATA_PREFIX 3
#define LOCKREP_PREFIX 4
* tc-i386.h (i386_target_format): Define even for ELFs. (QWORD_MNEM_SUFFIX): New macro. (CpuK6,CpuAthlon,CpuSledgehammer, Cpu64, CpuNo64, CpuUnknownFlags): New macros (CpuMMX,CpuSSE,Cpu3dnow, CpuUnknown): Renumber. (IgnoreSize, DefaultSize, No_?Suf, FWait, IsString, regKludge, IsPrefix, ImmExt): Renumber. (Size64, No_qSuf, NoRex64, Rex64): New macros. (Reg64, Imm32S, Imm64, Disp32S, Disp64): New macros. (Imm8, Imm8S, Imm16, Imm32, Imm1, BaseIndex, Disp8, Disp16, Disp32, InOutPortReg,ShiftCount, Control, Debug, Test, FloatReg, FloatAcc, SReg2, SReg3, Acc, JumpAbsolute, RegMMX, RegXMM, EsSeg, InvMem): Renumber. (Reg, WordReg): Add Reg64. (Imm): Add Imm32S and Imm64. (EncImm): New. (Disp): Add Disp64 and Disp32S. (AnyMem): Add Disp32S. (RegRex, RegRex64): New macros. (rex_byte): New type. * tc-i386.c (set_16bit_code_flag): Kill. (fits_in_unsigned_long, fits_in_signed_long): New functions. (reloc): New parameter "signed"; support x86_64. (set_code_flag): New. (DEFAULT_ARCH): New macro; default to "i386". (default_arch): New static variable. (struct _i386_insn): New fields Operand_PCrel; rex. (flag_16bit_code): Kill; All tests replaced to "flag_code == CODE_64BIT"; (flag_code): New enum and static variable. (use_rela_relocations): New static variable. (flag_code_names): New static variable. (cpu_arch_flags): Default to CpuUnknownFlags|CpuNo64. (cpu_arch): Add "sledgehammer"; Add CPUAthlon to Athlon and CpuK6 to K6 and Athlon. (i386_align_code): Return plain "nop" for x86_64. (mode_from_disp_size): Support Disp32S. (smallest_imm_type): Support Imm32S and Imm64. (offset_in_range): Support size of 8. (set_cpu_arch): Do not clobber to Cpu64/CpuNo64. (md_pseudo_table): Add "code64"; use set_code_flat. (md_begin): Emit sane error message on hash failure. (tc_i386_fix_adjustable): Support x86_64 relocations. (md_assemble): Support QWORD_MNEM_SUFFIX, REX registers, instructions supported on particular arch just partially, output of 64bit immediates, handling of Imm32S and Disp32S type. (i386_immedaite): Support x86_64 relocations; support 64bit constants. (i386_displacement): Likewise. (i386_index_check): Cleanup; support 64bit addresses. (md_apply_fix3): Support x86_64 relocation and rela. (md_longopts): Add "32" and "64". (md_parse_option): Add OPTION_32 and OPTION_64. (i386_target_format): Call even for ELFs; choose between elf64-x86-64 and elf32-i386. (i386_validate_fix): Refuse GOTOFF in 64bit mode. (tc_gen_reloc): Support rela relocations and x86_64. (intel_e09_1): Support QWORD. * i386.h (i386_optab): Replace "Imm" with "EncImm". (i386_regtab): Add flags field.
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#define REX_PREFIX 5 /* must come last. */
#define MAX_PREFIXES 6 /* max prefixes per opcode */
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/* we define the syntax here (modulo base,index,scale syntax) */
#define REGISTER_PREFIX '%'
#define IMMEDIATE_PREFIX '$'
#define ABSOLUTE_PREFIX '*'
/* these are the instruction mnemonic suffixes. */
#define WORD_MNEM_SUFFIX 'w'
#define BYTE_MNEM_SUFFIX 'b'
#define SHORT_MNEM_SUFFIX 's'
#define LONG_MNEM_SUFFIX 'l'
* tc-i386.h (i386_target_format): Define even for ELFs. (QWORD_MNEM_SUFFIX): New macro. (CpuK6,CpuAthlon,CpuSledgehammer, Cpu64, CpuNo64, CpuUnknownFlags): New macros (CpuMMX,CpuSSE,Cpu3dnow, CpuUnknown): Renumber. (IgnoreSize, DefaultSize, No_?Suf, FWait, IsString, regKludge, IsPrefix, ImmExt): Renumber. (Size64, No_qSuf, NoRex64, Rex64): New macros. (Reg64, Imm32S, Imm64, Disp32S, Disp64): New macros. (Imm8, Imm8S, Imm16, Imm32, Imm1, BaseIndex, Disp8, Disp16, Disp32, InOutPortReg,ShiftCount, Control, Debug, Test, FloatReg, FloatAcc, SReg2, SReg3, Acc, JumpAbsolute, RegMMX, RegXMM, EsSeg, InvMem): Renumber. (Reg, WordReg): Add Reg64. (Imm): Add Imm32S and Imm64. (EncImm): New. (Disp): Add Disp64 and Disp32S. (AnyMem): Add Disp32S. (RegRex, RegRex64): New macros. (rex_byte): New type. * tc-i386.c (set_16bit_code_flag): Kill. (fits_in_unsigned_long, fits_in_signed_long): New functions. (reloc): New parameter "signed"; support x86_64. (set_code_flag): New. (DEFAULT_ARCH): New macro; default to "i386". (default_arch): New static variable. (struct _i386_insn): New fields Operand_PCrel; rex. (flag_16bit_code): Kill; All tests replaced to "flag_code == CODE_64BIT"; (flag_code): New enum and static variable. (use_rela_relocations): New static variable. (flag_code_names): New static variable. (cpu_arch_flags): Default to CpuUnknownFlags|CpuNo64. (cpu_arch): Add "sledgehammer"; Add CPUAthlon to Athlon and CpuK6 to K6 and Athlon. (i386_align_code): Return plain "nop" for x86_64. (mode_from_disp_size): Support Disp32S. (smallest_imm_type): Support Imm32S and Imm64. (offset_in_range): Support size of 8. (set_cpu_arch): Do not clobber to Cpu64/CpuNo64. (md_pseudo_table): Add "code64"; use set_code_flat. (md_begin): Emit sane error message on hash failure. (tc_i386_fix_adjustable): Support x86_64 relocations. (md_assemble): Support QWORD_MNEM_SUFFIX, REX registers, instructions supported on particular arch just partially, output of 64bit immediates, handling of Imm32S and Disp32S type. (i386_immedaite): Support x86_64 relocations; support 64bit constants. (i386_displacement): Likewise. (i386_index_check): Cleanup; support 64bit addresses. (md_apply_fix3): Support x86_64 relocation and rela. (md_longopts): Add "32" and "64". (md_parse_option): Add OPTION_32 and OPTION_64. (i386_target_format): Call even for ELFs; choose between elf64-x86-64 and elf32-i386. (i386_validate_fix): Refuse GOTOFF in 64bit mode. (tc_gen_reloc): Support rela relocations and x86_64. (intel_e09_1): Support QWORD. * i386.h (i386_optab): Replace "Imm" with "EncImm". (i386_regtab): Add flags field.
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#define QWORD_MNEM_SUFFIX 'q'
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/* Intel Syntax */
#define LONG_DOUBLE_MNEM_SUFFIX 'x'
#define END_OF_INSN '\0'
/*
'templates' is for grouping together 'template' structures for opcodes
of the same name. This is only used for storing the insns in the grand
ole hash table of insns.
The templates themselves start at START and range up to (but not including)
END.
*/
typedef struct
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{
const template *start;
const template *end;
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}
templates;
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/* 386 operand encoding bytes: see 386 book for details of this. */
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typedef struct
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{
unsigned int regmem; /* codes register or memory operand */
unsigned int reg; /* codes register operand (or extended opcode) */
unsigned int mode; /* how to interpret regmem & reg */
}
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modrm_byte;
* tc-i386.h (i386_target_format): Define even for ELFs. (QWORD_MNEM_SUFFIX): New macro. (CpuK6,CpuAthlon,CpuSledgehammer, Cpu64, CpuNo64, CpuUnknownFlags): New macros (CpuMMX,CpuSSE,Cpu3dnow, CpuUnknown): Renumber. (IgnoreSize, DefaultSize, No_?Suf, FWait, IsString, regKludge, IsPrefix, ImmExt): Renumber. (Size64, No_qSuf, NoRex64, Rex64): New macros. (Reg64, Imm32S, Imm64, Disp32S, Disp64): New macros. (Imm8, Imm8S, Imm16, Imm32, Imm1, BaseIndex, Disp8, Disp16, Disp32, InOutPortReg,ShiftCount, Control, Debug, Test, FloatReg, FloatAcc, SReg2, SReg3, Acc, JumpAbsolute, RegMMX, RegXMM, EsSeg, InvMem): Renumber. (Reg, WordReg): Add Reg64. (Imm): Add Imm32S and Imm64. (EncImm): New. (Disp): Add Disp64 and Disp32S. (AnyMem): Add Disp32S. (RegRex, RegRex64): New macros. (rex_byte): New type. * tc-i386.c (set_16bit_code_flag): Kill. (fits_in_unsigned_long, fits_in_signed_long): New functions. (reloc): New parameter "signed"; support x86_64. (set_code_flag): New. (DEFAULT_ARCH): New macro; default to "i386". (default_arch): New static variable. (struct _i386_insn): New fields Operand_PCrel; rex. (flag_16bit_code): Kill; All tests replaced to "flag_code == CODE_64BIT"; (flag_code): New enum and static variable. (use_rela_relocations): New static variable. (flag_code_names): New static variable. (cpu_arch_flags): Default to CpuUnknownFlags|CpuNo64. (cpu_arch): Add "sledgehammer"; Add CPUAthlon to Athlon and CpuK6 to K6 and Athlon. (i386_align_code): Return plain "nop" for x86_64. (mode_from_disp_size): Support Disp32S. (smallest_imm_type): Support Imm32S and Imm64. (offset_in_range): Support size of 8. (set_cpu_arch): Do not clobber to Cpu64/CpuNo64. (md_pseudo_table): Add "code64"; use set_code_flat. (md_begin): Emit sane error message on hash failure. (tc_i386_fix_adjustable): Support x86_64 relocations. (md_assemble): Support QWORD_MNEM_SUFFIX, REX registers, instructions supported on particular arch just partially, output of 64bit immediates, handling of Imm32S and Disp32S type. (i386_immedaite): Support x86_64 relocations; support 64bit constants. (i386_displacement): Likewise. (i386_index_check): Cleanup; support 64bit addresses. (md_apply_fix3): Support x86_64 relocation and rela. (md_longopts): Add "32" and "64". (md_parse_option): Add OPTION_32 and OPTION_64. (i386_target_format): Call even for ELFs; choose between elf64-x86-64 and elf32-i386. (i386_validate_fix): Refuse GOTOFF in 64bit mode. (tc_gen_reloc): Support rela relocations and x86_64. (intel_e09_1): Support QWORD. * i386.h (i386_optab): Replace "Imm" with "EncImm". (i386_regtab): Add flags field.
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/* x86-64 extension prefix. */
typedef int rex_byte;
* tc-i386.h (i386_target_format): Define even for ELFs. (QWORD_MNEM_SUFFIX): New macro. (CpuK6,CpuAthlon,CpuSledgehammer, Cpu64, CpuNo64, CpuUnknownFlags): New macros (CpuMMX,CpuSSE,Cpu3dnow, CpuUnknown): Renumber. (IgnoreSize, DefaultSize, No_?Suf, FWait, IsString, regKludge, IsPrefix, ImmExt): Renumber. (Size64, No_qSuf, NoRex64, Rex64): New macros. (Reg64, Imm32S, Imm64, Disp32S, Disp64): New macros. (Imm8, Imm8S, Imm16, Imm32, Imm1, BaseIndex, Disp8, Disp16, Disp32, InOutPortReg,ShiftCount, Control, Debug, Test, FloatReg, FloatAcc, SReg2, SReg3, Acc, JumpAbsolute, RegMMX, RegXMM, EsSeg, InvMem): Renumber. (Reg, WordReg): Add Reg64. (Imm): Add Imm32S and Imm64. (EncImm): New. (Disp): Add Disp64 and Disp32S. (AnyMem): Add Disp32S. (RegRex, RegRex64): New macros. (rex_byte): New type. * tc-i386.c (set_16bit_code_flag): Kill. (fits_in_unsigned_long, fits_in_signed_long): New functions. (reloc): New parameter "signed"; support x86_64. (set_code_flag): New. (DEFAULT_ARCH): New macro; default to "i386". (default_arch): New static variable. (struct _i386_insn): New fields Operand_PCrel; rex. (flag_16bit_code): Kill; All tests replaced to "flag_code == CODE_64BIT"; (flag_code): New enum and static variable. (use_rela_relocations): New static variable. (flag_code_names): New static variable. (cpu_arch_flags): Default to CpuUnknownFlags|CpuNo64. (cpu_arch): Add "sledgehammer"; Add CPUAthlon to Athlon and CpuK6 to K6 and Athlon. (i386_align_code): Return plain "nop" for x86_64. (mode_from_disp_size): Support Disp32S. (smallest_imm_type): Support Imm32S and Imm64. (offset_in_range): Support size of 8. (set_cpu_arch): Do not clobber to Cpu64/CpuNo64. (md_pseudo_table): Add "code64"; use set_code_flat. (md_begin): Emit sane error message on hash failure. (tc_i386_fix_adjustable): Support x86_64 relocations. (md_assemble): Support QWORD_MNEM_SUFFIX, REX registers, instructions supported on particular arch just partially, output of 64bit immediates, handling of Imm32S and Disp32S type. (i386_immedaite): Support x86_64 relocations; support 64bit constants. (i386_displacement): Likewise. (i386_index_check): Cleanup; support 64bit addresses. (md_apply_fix3): Support x86_64 relocation and rela. (md_longopts): Add "32" and "64". (md_parse_option): Add OPTION_32 and OPTION_64. (i386_target_format): Call even for ELFs; choose between elf64-x86-64 and elf32-i386. (i386_validate_fix): Refuse GOTOFF in 64bit mode. (tc_gen_reloc): Support rela relocations and x86_64. (intel_e09_1): Support QWORD. * i386.h (i386_optab): Replace "Imm" with "EncImm". (i386_regtab): Add flags field.
2000-12-20 21:24:13 +08:00
2007-09-15 02:21:09 +08:00
/* The SSE5 instructions have a two bit instruction modifier (OC) that
is stored in two separate bytes in the instruction. Pick apart OC
into the 2 separate bits for instruction. */
#define DREX_OC0(x) (((x) & 1) != 0)
#define DREX_OC1(x) (((x) & 2) != 0)
#define DREX_OC0_MASK (1 << 3) /* set OC0 in byte 4 */
#define DREX_OC1_MASK (1 << 2) /* set OC1 in byte 3 */
/* OC mappings */
#define DREX_XMEM_X1_X2_X2 0 /* 4 op insn, dest = src3, src1 = reg/mem */
#define DREX_X1_XMEM_X2_X2 1 /* 4 op insn, dest = src3, src2 = reg/mem */
#define DREX_X1_XMEM_X2_X1 2 /* 4 op insn, dest = src1, src2 = reg/mem */
#define DREX_X1_X2_XMEM_X1 3 /* 4 op insn, dest = src1, src3 = reg/mem */
#define DREX_XMEM_X1_X2 0 /* 3 op insn, src1 = reg/mem */
#define DREX_X1_XMEM_X2 1 /* 3 op insn, src1 = reg/mem */
/* Information needed to create the DREX byte in SSE5 instructions. */
typedef struct
{
unsigned int reg; /* register */
unsigned int rex; /* REX flags */
unsigned int modrm_reg; /* which arg goes in the modrm.reg field */
unsigned int modrm_regmem; /* which arg goes in the modrm.regmem field */
} drex_byte;
/* 386 opcode byte to code indirect addressing. */
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typedef struct
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{
unsigned base;
unsigned index;
unsigned scale;
}
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sib_byte;
enum processor_type
{
PROCESSOR_UNKNOWN,
gas/ 2007-07-23 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (cpu_arch): Change i386 to PROCESSOR_I386. (f32_15): Removed. (jump_31): New. (f32_patt): Remove f32_15. (f16_patt): Likewise. (i386_align_code): Updated to alt_long_patt for 64bit by default. * config/tc-i386.h (processor_type): Add PROCESSOR_I386. 2007-07-23 Evandro Menezes <evandro.menezes@amd.com> * config/tc-i386.c (i386_align_code): Enable alignment up to MAX_MEM_FOR_RS_ALIGN_CODE bytes. Remove special treatment for K8. * config/tc-i386.h (MAX_MEM_FOR_RS_ALIGN_CODE): Changed to 31. gas/testsuite/ 2007-07-23 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/i386.exp: Run nops16-1, nops-1-i386-i686, nops-1-k8, nops-3-i386, nops-4, nops-4-i386, x86-64-nops-2, x86-64-nops-3, x86-64-nops-4, x86-64-nops-4-core2 and x86-64-nops-4-k8. * gas/i386/nops-1-i386-i686.d: New. * gas/i386/nops-1-k8.d: Likewise. * gas/i386/nops-3-i386.d : Likewise. * gas/i386/nops-3-i686.d: Likewise. * gas/i386/nops-4-i386.d: Likewise. * gas/i386/nops-4.d: Likewise. * gas/i386/nops16-1.d: Likewise. * gas/i386/nops16-1.s: Likewise. * gas/i386/x86-64-nops-1-k8.d: Likewise. * gas/i386/x86-64-nops-2.d: Likewise. * gas/i386/x86-64-nops-3.d: Likewise. * gas/i386/x86-64-nops-4-core2.d: Likewise. * gas/i386/x86-64-nops-4-k8.d: Likewise. * gas/i386/x86-64-nops-4.d: Likewise. * gas/i386/nops-1-i386.d: Updated. * gas/i386/nops-1-i686.d: Likewise. * gas/i386/nops-1.d: Likewise. * gas/i386/nops-2-i386.d: Likewise. * gas/i386/nops-2-merom.d : Likewise. * gas/i386/nops-2.d: Likewise. * gas/i386/nops-3.d: Likewise. * gas/i386/x86-64-nops-1-merom.d: Likewise. * gas/i386/x86-64-nops-1-nocona.d: Likewise. * gas/i386/x86-64-nops-1.d: Likewise. * gas/i386/x86-64-nops-1.s: Removed. 2007-07-23 Evandro Menezes <evandro.menezes@amd.com> H.J. Lu <hongjiu.lu@intel.com> * gas/i386/i386.exp: Don't run x86-64-nops-1-k8. Run nops-3-i686 and nops-4-i686. * gas/i386/nops-3-i686.d: New. * gas/i386/nops-4-i686.d: Likewise. * gas/i386/nops-4.s: Likewise. * gas/i386/x86-64-nops-1-k8.d: Removed.
2007-07-24 04:03:23 +08:00
PROCESSOR_I386,
PROCESSOR_I486,
PROCESSOR_PENTIUM,
PROCESSOR_PENTIUMPRO,
PROCESSOR_PENTIUM4,
PROCESSOR_NOCONA,
PROCESSOR_CORE,
PROCESSOR_CORE2,
PROCESSOR_K6,
PROCESSOR_ATHLON,
PROCESSOR_K8,
PROCESSOR_GENERIC32,
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PROCESSOR_GENERIC64,
PROCESSOR_AMDFAM10
};
/* x86 arch names, types and features */
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typedef struct
{
const char *name; /* arch name */
enum processor_type type; /* arch type */
gas/ 2007-09-08 H.J. Lu <hongjiu.lu@intel.com> * configure.in (AC_CHECK_HEADERS): Add limits.h. * configure: Regenerated. * config.in: Likewise. * config/tc-i386.c: Include "opcodes/i386-init.h". (_i386_insn): Use i386_operand_type for types. (cpu_arch_flags): Updated to new types with bitfield. (cpu_arch_tune_flags): Likewise. (cpu_arch_isa_flags): Likewise. (cpu_arch): Likewise. (i386_align_code): Likewise. (set_code_flag): Likewise. (set_16bit_gcc_code_flag): Likewise. (set_cpu_arch): Likewise. (md_assemble): Likewise. (parse_insn): Likewise. (process_operands): Likewise. (output_branch): Likewise. (output_jump): Likewise. (parse_real_register): Likewise. (mode_from_disp_size): Likewise. (smallest_imm_type): Likewise. (pi): Likewise. (type_names): Likewise. (pt): Likewise. (pte): Likewise. (swap_2_operands): Likewise. (optimize_imm): Likewise. (optimize_disp): Likewise. (match_template): Likewise. (check_string): Likewise. (process_suffix): Likewise. (check_byte_reg): Likewise. (check_long_reg): Likewise. (check_qword_reg): Likewise. (check_word_reg): Likewise. (finalize_imm): Likewise. (build_modrm_byte): Likewise. (output_insn): Likewise. (disp_size): Likewise. (imm_size): Likewise. (output_disp): Likewise. (output_imm): Likewise. (gotrel): Likewise. (i386_immediate): Likewise. (i386_displacement): Likewise. (i386_index_check): Likewise. (i386_operand): Likewise. (parse_real_register): Likewise. (i386_intel_operand): Likewise. (intel_e09): Likewise. (intel_bracket_expr): Likewise. (intel_e11): Likewise. (cpu_arch_flags_not): New. (cpu_flags_check_x64): Likewise. (cpu_flags_all_zero): Likewise. (cpu_flags_not): Likewise. (i386_cpu_flags_biop): Likewise. (cpu_flags_biop): Likewise. (cpu_flags_match); Likewise. (acc32): New. (acc64): Likewise. (control): Likewise. (reg16_inoutportreg): Likewise. (disp16): Likewise. (disp32): Likewise. (disp32s): Likewise. (disp16_32): Likewise. (anydisp): Likewise. (baseindex): Likewise. (regxmm): Likewise. (imm8): Likewise. (imm8s): Likewise. (imm16): Likewise. (imm32): Likewise. (imm32s): Likewise. (imm64): Likewise. (imm16_32): Likewise. (imm16_32s): Likewise. (imm16_32_32s): Likewise. (operand_type): Likewise. (operand_type_check): Likewise. (operand_type_match): Likewise. (operand_type_register_match): Likewise. (update_imm): Likewise. (set_code_flag): Also update cpu_arch_flags_not. (set_16bit_gcc_code_flag): Likewise. (md_begin): Likewise. (parse_insn): Use cpu_flags_check_x64 to check 64bit support. Use cpu_flags_match to match instructions. (i386_target_format): Update cpu_arch_isa_flags and cpu_arch_tune_flags to i386_cpu_flags type with bitfield. (smallest_imm_type): Check cpu_arch_tune to tune for i486. (match_template): Don't initialize overlap0, overlap1, overlap2, overlap3 and operand_types. (process_suffix): Handle crc32 with 64bit register. (MATCH): Removed. (CONSISTENT_REGISTER_MATCH): Likewise. * config/tc-i386.h (arch_entry): Updated to i386_cpu_flags type. opcodes/ 2007-09-08 H.J. Lu <hongjiu.lu@intel.com> * configure.in (AC_CHECK_HEADERS): Add limits.h. * configure: Regenerated. * config.in: Likewise. * i386-gen.c: Include "sysdep.h" instead of <stdlib.h> and <string.h>. Use xstrerror instead of strerror. (initializer): New. (cpu_flag_init): Likewise. (bitfield): Likewise. (BITFIELD): New. (cpu_flags): Likewise. (opcode_modifiers): Likewise. (operand_types): Likewise. (compare): Likewise. (set_cpu_flags): Likewise. (output_cpu_flags): Likewise. (process_i386_cpu_flags): Likewise. (output_opcode_modifier): Likewise. (process_i386_opcode_modifier): Likewise. (output_operand_type): Likewise. (process_i386_operand_type): Likewise. (set_bitfield): Likewise. (operand_type_init): Likewise. (process_i386_initializers): Likewise. (process_i386_opcodes): Call process_i386_opcode_modifier to process opcode_modifier. Call process_i386_operand_type to process operand_types. (process_i386_registers): Call process_i386_operand_type to process reg_type. (main): Check unused bits in i386_cpu_flags and i386_operand_type. Sort cpu_flags, opcode_modifiers and operand_types. Call process_i386_initializers. * i386-init.h: New. * i386-tbl.h: Regenerated. * i386-opc.h: Include <limits.h>. (CHAR_BIT): Define as 8 if not defined. (Cpu186): Changed to position of bitfiled. (Cpu286): Likewise. (Cpu386): Likewise. (Cpu486): Likewise. (Cpu586): Likewise. (Cpu686): Likewise. (CpuP4): Likewise. (CpuK6): Likewise. (CpuK8): Likewise. (CpuMMX): Likewise. (CpuMMX2): Likewise. (CpuSSE): Likewise. (CpuSSE2): Likewise. (Cpu3dnow): Likewise. (Cpu3dnowA): Likewise. (CpuSSE3): Likewise. (CpuPadLock): Likewise. (CpuSVME): Likewise. (CpuVMX): Likewise. (CpuSSSE3): Likewise. (CpuSSE4a): Likewise. (CpuABM): Likewise. (CpuSSE4_1): Likewise. (CpuSSE4_2): Likewise. (Cpu64): Likewise. (CpuNo64): Likewise. (D): Likewise. (W): Likewise. (Modrm): Likewise. (ShortForm): Likewise. (Jump): Likewise. (JumpDword): Likewise. (JumpByte): Likewise. (JumpInterSegment): Likewise. (FloatMF): Likewise. (FloatR): Likewise. (FloatD): Likewise. (Size16): Likewise. (Size32): Likewise. (Size64): Likewise. (IgnoreSize): Likewise. (DefaultSize): Likewise. (No_bSuf): Likewise. (No_wSuf): Likewise. (No_lSuf): Likewise. (No_sSuf): Likewise. (No_qSuf): Likewise. (No_xSuf): Likewise. (FWait): Likewise. (IsString): Likewise. (RegKludge): Likewise. (IsPrefix): Likewise. (ImmExt): Likewise. (NoRex64): Likewise. (Rex64): Likewise. (Ugh): Likewise. (Reg8): Likewise. (Reg16): Likewise. (Reg32): Likewise. (Reg64): Likewise. (FloatReg): Likewise. (RegMMX): Likewise. (RegXMM): Likewise. (Imm8): Likewise. (Imm8S): Likewise. (Imm16): Likewise. (Imm32): Likewise. (Imm32S): Likewise. (Imm64): Likewise. (Imm1): Likewise. (BaseIndex): Likewise. (Disp8): Likewise. (Disp16): Likewise. (Disp32): Likewise. (Disp32S): Likewise. (Disp64): Likewise. (InOutPortReg): Likewise. (ShiftCount): Likewise. (Control): Likewise. (Debug): Likewise. (Test): Likewise. (SReg2): Likewise. (SReg3): Likewise. (Acc): Likewise. (FloatAcc): Likewise. (JumpAbsolute): Likewise. (EsSeg): Likewise. (RegMem): Likewise. (OTMax): Likewise. (Reg): Commented out. (WordReg): Likewise. (ImplicitRegister): Likewise. (Imm): Likewise. (EncImm): Likewise. (Disp): Likewise. (AnyMem): Likewise. (LLongMem): Likewise. (LongMem): Likewise. (ShortMem): Likewise. (WordMem): Likewise. (ByteMem): Likewise. (CpuMax): New (CpuLM): Likewise. (CpuNumOfUints): Likewise. (CpuNumOfBits): Likewise. (CpuUnused): Likewise. (OTNumOfUints): Likewise. (OTNumOfBits): Likewise. (OTUnused): Likewise. (i386_cpu_flags): New type. (i386_operand_type): Likewise. (i386_opcode_modifier): Likewise. (CpuSledgehammer): Removed. (CpuSSE4): Likewise. (CpuUnknownFlags): Likewise. (Reg): Likewise. (WordReg): Likewise. (ImplicitRegister): Likewise. (Imm): Likewise. (EncImm): Likewise. (Disp): Likewise. (AnyMem): Likewise. (LLongMem): Likewise. (LongMem): Likewise. (ShortMem): Likewise. (WordMem): Likewise. (ByteMem): Likewise. (template): Use i386_cpu_flags for cpu_flags, use i386_opcode_modifier for opcode_modifier, use i386_operand_type for operand_types. (reg_entry): Use i386_operand_type for reg_type. * Makefile.am (HFILES): Add i386-init.h. ($(srcdir)/i386-init.h): New rule. ($(srcdir)/i386-tbl.h): Depend on $(srcdir)/i386-init.h instead. * Makefile.in: Regenerated.
2007-09-09 09:22:57 +08:00
i386_cpu_flags flags; /* cpu feature flags */
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}
arch_entry;
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/* The name of the global offset table generated by the compiler. Allow
this to be overridden if need be. */
1999-05-03 15:29:11 +08:00
#ifndef GLOBAL_OFFSET_TABLE_NAME
#define GLOBAL_OFFSET_TABLE_NAME "_GLOBAL_OFFSET_TABLE_"
#endif
#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && !defined (LEX_AT)
2002-08-09 20:37:41 +08:00
#define TC_PARSE_CONS_EXPRESSION(EXP, NBYTES) x86_cons (EXP, NBYTES)
extern void x86_cons (expressionS *, int);
#endif
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#define TC_CONS_FIX_NEW(FRAG,OFF,LEN,EXP) x86_cons_fix_new(FRAG, OFF, LEN, EXP)
extern void x86_cons_fix_new
(fragS *, unsigned int, unsigned int, expressionS *);
2002-08-09 20:37:41 +08:00
#define DIFF_EXPR_OK /* foo-. gets turned into PC relative relocs */
#define NO_RELOC BFD_RELOC_NONE
void i386_validate_fix (struct fix *);
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#define TC_VALIDATE_FIX(FIX,SEGTYPE,SKIP) i386_validate_fix(FIX)
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#define tc_fix_adjustable(X) tc_i386_fix_adjustable(X)
extern int tc_i386_fix_adjustable (struct fix *);
2002-08-09 20:37:41 +08:00
gas: * cgen.c, cgen.h, tc.h, write.c, config/obj-coff.c * config/tc-a29k.c, config/tc-alpha.c, config/tc-alpha.h * config/tc-arc.c, config/tc-arc.h, config/tc-arm.c * config/tc-arm.h, config/tc-avr.c, config/tc-avr.h * config/tc-cris.c, config/tc-crx.c, config/tc-d10v.c * config/tc-d10v.h, config/tc-d30v.c, config/tc-d30v.h * config/tc-dlx.c, config/tc-dlx.h, config/tc-fr30.h * config/tc-frv.c, config/tc-frv.h, config/tc-h8300.c * config/tc-h8500.c, config/tc-hppa.c, config/tc-hppa.h * config/tc-i370.c, config/tc-i370.h, config/tc-i386.c * config/tc-i386.h, config/tc-i860.c, config/tc-i860.h * config/tc-i960.c, config/tc-i960.h, config/tc-ia64.c * config/tc-ip2k.c, config/tc-ip2k.h, config/tc-iq2000.c * config/tc-iq2000.h, config/tc-m32r.c, config/tc-m32r.h * config/tc-m68hc11.c, config/tc-m68hc11.h, config/tc-m68k.c * config/tc-m68k.h, config/tc-m88k.c, config/tc-maxq.c * config/tc-mcore.c, config/tc-mcore.h, config/tc-mips.c * config/tc-mips.h, config/tc-mmix.c, config/tc-mn10200.c * config/tc-mn10300.c, config/tc-msp430.c, config/tc-ns32k.c * config/tc-openrisc.h, config/tc-or32.c, config/tc-or32.h * config/tc-pdp11.c, config/tc-pj.c, config/tc-pj.h * config/tc-ppc.c, config/tc-ppc.h, config/tc-s390.c * config/tc-s390.h, config/tc-sh64.c, config/tc-sh.c * config/tc-sh.h, config/tc-sparc.c, config/tc-sparc.h * config/tc-tahoe.c, config/tc-tic30.c, config/tc-tic4x.c * config/tc-tic54x.c, config/tc-tic80.c, config/tc-v850.c * config/tc-v850.h, config/tc-vax.c, config/tc-vax.h * config/tc-w65.c, config/tc-xstormy16.c, config/tc-xstormy16.h * config/tc-xtensa.c, config/tc-z8k.c: Replace all instances of the string "_apply_fix3" with "_apply_fix". * po/POTFILES.in, po/gas.pot: Regenerate. bfd: * coff-i386.c: Change md_apply_fix3 to md_apply_fix in comment. cgen: * doc/porting.texi: Change all mention of md_apply_fix3 and gas_cgen_md_apply_fix3 to md_apply_fix and gas_cgen_md_apply_fix respectively.
2005-06-08 01:54:22 +08:00
/* Values passed to md_apply_fix don't include the symbol value. */
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#define MD_APPLY_SYM_VALUE(FIX) 0
/* ELF wants external syms kept, as does PE COFF. */
* symbols.c (S_FORCE_RELOC): Add "strict" param. * symbols.h (S_FORCE_RELOC): Likewise. * config/obj-aout.h (S_FORCE_RELOC): Likewise. * config/obj-bout.h (S_FORCE_RELOC): Likewise. * config/obj-coff.h (S_FORCE_RELOC): Likewise. * config/obj-ieee.h (S_FORCE_RELOC): Likewise. * config/obj-vms.h (S_FORCE_RELOC): Likewise. * write.c (generic_force_reloc): New function. (TC_FORCE_RELOCATION): Use it here instead of S_FORCE_RELOC. (TC_FORCE_RELOCATION_SUB_SAME): Test TC_FORCE_RELOCATION too. (adjust_reloc_syms): Adjust S_FORCE_RELOC call. * as.h (generic_force_reloc): Declare. * doc/internals.texi (S_FORCE_RELOC): Update. (TC_FORCE_RELOCATION_SUB_SAME): Update. * config/tc-alpha.c (alpha_force_relocation): Adjust to use generic_force_reloc. (alpha_fix_adjustable): Likewise. * config/tc-arm.c (arm_force_relocation): Likewise. * config/tc-cris.c (md_cris_force_relocation): Likewise. * config/tc-frv.c (frv_force_relocation): Likewise. * config/tc-i386.c (md_apply_fix3): Likewise. * config/tc-ia64.c (ia64_force_relocation): Likewise. * config/tc-ip2k.c (ip2k_force_relocation): Likewise. * config/tc-m32r.c (m32r_force_relocation): Likewise. * config/tc-m68hc11.c (tc_m68hc11_force_relocation): Likewise. * config/tc-mcore.c (mcore_force_relocation): Likewise. * config/tc-mips.c (mips_force_relocation): Likewise. * config/tc-mmix.c (mmix_force_relocation): Likewise. * config/tc-ppc.c (ppc_force_relocation): Likewise. * config/tc-s390.c (tc_s390_force_relocation): Likewise. * config/tc-sh.c (sh_force_relocation): Likewise. (md_pcrel_from_section): Likewise. * config/tc-sparc.c (tc_gen_reloc): Likewise. * config/tc-v850.c (v850_force_relocation): Likewise. * config/tc-xstormy16.c (xstormy16_force_relocation): Likewise. * config/tc-i386.h (TC_FORCE_RELOCATION): Likewise. * config/tc-mcore.h (TC_FORCE_RELOCATION): Likewise. * config/tc-sparc.h (tc_fix_adjustable): Likewise. * config/tc-d10v.c (d10v_force_relocation): Delete. * config/tc-d10v.h (TC_FORCE_RELOCATION): Don't define. * config/tc-dlx.c (md_dlx_force_relocation): Delete. * config/tc-dlx.h (TC_FORCE_RELOCATION): Don't define. * config/tc-fr30.c (fr30_force_relocation): Delete. * config/tc-fr30.h (TC_FORCE_RELOCATION): Don't define. * config/tc-mn10300.c (mn10300_force_relocation): Delete. * config/tc-mn10300.h (TC_FORCE_RELOCATION): Don't define. (TC_FORCE_RELOCATION_SUB_SAME): Test TC_FORCE_RELOCATION too. * config/tc-i960.h (TC_FORCE_RELOCATION_SUB_SAME): Likewise. * config/tc-hppa.c (hppa_force_relocation): Adjust S_FORCE_RELOC call. * config/tc-mips.c (RELAX_BRANCH_TOOFAR): Warning fix. * config/tc-mips.h (TC_FORCE_RELOCATION_SUB_SAME): Don't define. * config/tc-openrisc.c (openrisc_force_relocation): Delete. * config/tc-openrisc.h (TC_FORCE_RELOCATION): Don't define. * config/tc-sparc.c (elf32_sparc_force_relocation): Delete. * config/tc-sparc.h (TC_FORCE_RELOCATION): Don't define for ELF. * config/tc-i386.c (i386_force_relocation): Delete. * config/tc-i386.h (TC_FORCE_RELOCATION): Don't define for BFD_ASSEMBLER. (EXTERN_FORCE_RELOC): Fix TE_PE and STRICT_PE_FORMAT nesting. * config/tc-m68k.h (TC_FORCE_RELOCATION): Don't define. * config/tc-pj.h (TC_FORCE_RELOCATION): Don't define. * config/tc-sh.h (TC_FORCE_RELOCATION_SUB_ABS): Don't call S_FORCE_RELOC. (TC_FORCE_RELOCATION_SUB_SAME): Test TC_FORCE_RELOCATION too. * config/tc-sh64.h (TC_FORCE_RELOCATION_SUB_SAME): Likewise.
2003-01-23 20:51:05 +08:00
#if defined (TE_PE) && defined (STRICT_PE_FORMAT)
#define EXTERN_FORCE_RELOC \
(OUTPUT_FLAVOR == bfd_target_elf_flavour \
|| OUTPUT_FLAVOR == bfd_target_coff_flavour)
#else
#define EXTERN_FORCE_RELOC \
(OUTPUT_FLAVOR == bfd_target_elf_flavour)
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#endif
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/* This expression evaluates to true if the relocation is for a local
object for which we still want to do the relocation at runtime.
False if we are willing to perform this relocation while building
the .o file. GOTOFF does not need to be checked here because it is
not pcrel. I am not sure if some of the others are ever used with
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pcrel, but it is easier to be safe than sorry. */
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#define TC_FORCE_RELOCATION_LOCAL(FIX) \
(!(FIX)->fx_pcrel \
|| (FIX)->fx_r_type == BFD_RELOC_386_PLT32 \
|| (FIX)->fx_r_type == BFD_RELOC_386_GOT32 \
|| (FIX)->fx_r_type == BFD_RELOC_386_GOTPC \
|| TC_FORCE_RELOCATION (FIX))
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extern int i386_parse_name (char *, expressionS *, char *);
#define md_parse_name(s, e, m, c) i386_parse_name (s, e, c)
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#define md_register_arithmetic 0
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extern const struct relax_type md_relax_table[];
#define TC_GENERIC_RELAX_TABLE md_relax_table
extern int optimize_align_code;
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#define md_do_align(n, fill, len, max, around) \
if ((n) \
&& !need_pass_2 \
&& optimize_align_code \
&& (!(fill) \
|| ((char)*(fill) == (char)0x90 && (len) == 1)) \
&& subseg_text_p (now_seg)) \
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{ \
* as.h (rs_align_test): New. * frags.c (NOP_OPCODE): Move default from read.c. (MAX_MEM_FOR_RS_ALIGN_CODE): New default. (frag_align_code): New. * frags.h (frag_align_code): Declare. * read.c (NOP_OPCODE): Remove. (do_align): Use frag_align_code. * write.c (NOP_OPCODE): Remove. (get_recorded_alignment): New. (cvt_frag_to_fill): Handle rs_align_test. (relax_segment): Likewise. (subsegs_finish): Align last subseg in section to the section alignment. Use frag_align_code. * write.h (get_recorded_alignment): Declare. * config/obj-coff.c (size_section): Handle rs_align_test. (fill_section, fixup_mdeps): Likewise. (write_object_file): Use frag_align_code. * config/tc-alpha.c (alpha_align): Use frag_align_code. (alpha_handle_align): New. * config/tc-alpha.h (HANDLE_ALIGN): New. (MAX_MEM_FOR_RS_ALIGN_CODE): New. * config/tc-i386.h (md_do_align): Use frag_align_code. (MAX_MEM_FOR_RS_ALIGN_CODE): New. * config/tc-ia64.c (ia64_md_do_align): Don't do code alignment. (ia64_handle_align): New. * config/tc-ia64.h (HANDLE_ALIGN): New. (MAX_MEM_FOR_RS_ALIGN_CODE): New. * config/tc-m32r.c (m32r_do_align): Remove. (m32r_handle_align): New. (fill_insn): Use frag_align_code. * config/tc-m32r.h (md_do_align): Remove. (HANDLE_ALIGN, MAX_MEM_FOR_RS_ALIGN_CODE): New. * config/tc-m88k.c, config/tc-m88k.h: Similarly. * config/tc-mips.c, config/tc-mips.h: Similarly. * config/tc-sh.c (sh_cons_align): Use rs_align_test. (sh_handle_align): Likewise. Handle rs_align_code. (sh_do_align): Remove. * config/tc-sh.h (md_do_align): Remove. (MAX_MEM_FOR_RS_ALIGN_CODE): New. * config/tc-sparc.c (sparc_cons_align): Use rs_align_test. (sparc_handle_align): Likewise. Handle rs_align_code. * config/tc-sparc.h (md_do_align): Remove. (MAX_MEM_FOR_RS_ALIGN_CODE): New.
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frag_align_code ((n), (max)); \
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goto around; \
}
gas/ 2007-07-23 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (cpu_arch): Change i386 to PROCESSOR_I386. (f32_15): Removed. (jump_31): New. (f32_patt): Remove f32_15. (f16_patt): Likewise. (i386_align_code): Updated to alt_long_patt for 64bit by default. * config/tc-i386.h (processor_type): Add PROCESSOR_I386. 2007-07-23 Evandro Menezes <evandro.menezes@amd.com> * config/tc-i386.c (i386_align_code): Enable alignment up to MAX_MEM_FOR_RS_ALIGN_CODE bytes. Remove special treatment for K8. * config/tc-i386.h (MAX_MEM_FOR_RS_ALIGN_CODE): Changed to 31. gas/testsuite/ 2007-07-23 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/i386.exp: Run nops16-1, nops-1-i386-i686, nops-1-k8, nops-3-i386, nops-4, nops-4-i386, x86-64-nops-2, x86-64-nops-3, x86-64-nops-4, x86-64-nops-4-core2 and x86-64-nops-4-k8. * gas/i386/nops-1-i386-i686.d: New. * gas/i386/nops-1-k8.d: Likewise. * gas/i386/nops-3-i386.d : Likewise. * gas/i386/nops-3-i686.d: Likewise. * gas/i386/nops-4-i386.d: Likewise. * gas/i386/nops-4.d: Likewise. * gas/i386/nops16-1.d: Likewise. * gas/i386/nops16-1.s: Likewise. * gas/i386/x86-64-nops-1-k8.d: Likewise. * gas/i386/x86-64-nops-2.d: Likewise. * gas/i386/x86-64-nops-3.d: Likewise. * gas/i386/x86-64-nops-4-core2.d: Likewise. * gas/i386/x86-64-nops-4-k8.d: Likewise. * gas/i386/x86-64-nops-4.d: Likewise. * gas/i386/nops-1-i386.d: Updated. * gas/i386/nops-1-i686.d: Likewise. * gas/i386/nops-1.d: Likewise. * gas/i386/nops-2-i386.d: Likewise. * gas/i386/nops-2-merom.d : Likewise. * gas/i386/nops-2.d: Likewise. * gas/i386/nops-3.d: Likewise. * gas/i386/x86-64-nops-1-merom.d: Likewise. * gas/i386/x86-64-nops-1-nocona.d: Likewise. * gas/i386/x86-64-nops-1.d: Likewise. * gas/i386/x86-64-nops-1.s: Removed. 2007-07-23 Evandro Menezes <evandro.menezes@amd.com> H.J. Lu <hongjiu.lu@intel.com> * gas/i386/i386.exp: Don't run x86-64-nops-1-k8. Run nops-3-i686 and nops-4-i686. * gas/i386/nops-3-i686.d: New. * gas/i386/nops-4-i686.d: Likewise. * gas/i386/nops-4.s: Likewise. * gas/i386/x86-64-nops-1-k8.d: Removed.
2007-07-24 04:03:23 +08:00
#define MAX_MEM_FOR_RS_ALIGN_CODE 31
* as.h (rs_align_test): New. * frags.c (NOP_OPCODE): Move default from read.c. (MAX_MEM_FOR_RS_ALIGN_CODE): New default. (frag_align_code): New. * frags.h (frag_align_code): Declare. * read.c (NOP_OPCODE): Remove. (do_align): Use frag_align_code. * write.c (NOP_OPCODE): Remove. (get_recorded_alignment): New. (cvt_frag_to_fill): Handle rs_align_test. (relax_segment): Likewise. (subsegs_finish): Align last subseg in section to the section alignment. Use frag_align_code. * write.h (get_recorded_alignment): Declare. * config/obj-coff.c (size_section): Handle rs_align_test. (fill_section, fixup_mdeps): Likewise. (write_object_file): Use frag_align_code. * config/tc-alpha.c (alpha_align): Use frag_align_code. (alpha_handle_align): New. * config/tc-alpha.h (HANDLE_ALIGN): New. (MAX_MEM_FOR_RS_ALIGN_CODE): New. * config/tc-i386.h (md_do_align): Use frag_align_code. (MAX_MEM_FOR_RS_ALIGN_CODE): New. * config/tc-ia64.c (ia64_md_do_align): Don't do code alignment. (ia64_handle_align): New. * config/tc-ia64.h (HANDLE_ALIGN): New. (MAX_MEM_FOR_RS_ALIGN_CODE): New. * config/tc-m32r.c (m32r_do_align): Remove. (m32r_handle_align): New. (fill_insn): Use frag_align_code. * config/tc-m32r.h (md_do_align): Remove. (HANDLE_ALIGN, MAX_MEM_FOR_RS_ALIGN_CODE): New. * config/tc-m88k.c, config/tc-m88k.h: Similarly. * config/tc-mips.c, config/tc-mips.h: Similarly. * config/tc-sh.c (sh_cons_align): Use rs_align_test. (sh_handle_align): Likewise. Handle rs_align_code. (sh_do_align): Remove. * config/tc-sh.h (md_do_align): Remove. (MAX_MEM_FOR_RS_ALIGN_CODE): New. * config/tc-sparc.c (sparc_cons_align): Use rs_align_test. (sparc_handle_align): Likewise. Handle rs_align_code. * config/tc-sparc.h (md_do_align): Remove. (MAX_MEM_FOR_RS_ALIGN_CODE): New.
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extern void i386_align_code (fragS *, int);
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#define HANDLE_ALIGN(fragP) \
if (fragP->fr_type == rs_align_code) \
i386_align_code (fragP, (fragP->fr_next->fr_address \
- fragP->fr_address \
- fragP->fr_fix));
void i386_print_statistics (FILE *);
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#define tc_print_statistics i386_print_statistics
#define md_number_to_chars number_to_chars_littleendian
#ifdef SCO_ELF
#define tc_init_after_args() sco_id ()
extern void sco_id (void);
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#endif
#define WORKING_DOT_WORD 1
/* We want .cfi_* pseudo-ops for generating unwind info. */
#define TARGET_USE_CFIPOP 1
extern unsigned int x86_dwarf2_return_column;
#define DWARF2_DEFAULT_RETURN_COLUMN x86_dwarf2_return_column
extern int x86_cie_data_alignment;
#define DWARF2_CIE_DATA_ALIGNMENT x86_cie_data_alignment
#define tc_regname_to_dw2regnum tc_x86_regname_to_dw2regnum
extern int tc_x86_regname_to_dw2regnum (char *);
#define tc_cfi_frame_initial_instructions tc_x86_frame_initial_instructions
extern void tc_x86_frame_initial_instructions (void);
#define md_elf_section_type(str,len) i386_elf_section_type (str, len)
extern int i386_elf_section_type (const char *, size_t);
bfd/ 2005-07-25 Jan Hubicka <jh@suse.cz> H.J. Lu <hongjiu.lu@intel.com> * elf-bfd.h (_bfd_elf_large_com_section): New. * elf.c (_bfd_elf_large_com_section): New. Defined. * elf64-x86-64.c (elf64_x86_64_add_symbol_hook): New. (elf64_x86_64_elf_section_from_bfd_section): New. (elf64_x86_64_symbol_processing): New. (elf64_x86_64_common_definition): New. (elf64_x86_64_common_section_index): New. (elf64_x86_64_common_section): New. (elf64_x86_64_merge_symbol): New. (elf64_x86_64_additional_program_headers): New. (elf64_x86_64_special_sections): New. (elf_backend_section_from_bfd_section): New. Defined. (elf_backend_add_symbol_hook): Likewise. (elf_backend_common_section_index): Likewise. (elf_backend_common_section): Likewise. (elf_backend_common_definition): Likewise. (elf_backend_merge_symbol): Likewise. (elf_backend_special_sections): Likewise. (elf_backend_additional_program_headers): Likewise. binutils/ 2005-07-25 H.J. Lu <hongjiu.lu@intel.com> * readelf.c (dump_relocations): Handle SHN_X86_64_LCOMMON. (get_symbol_index_type): Likewise. (get_elf_section_flags): Handle SHF_X86_64_LARGE. gas/ 2005-07-25 Jan Hubicka <jh@suse.cz> H.J. Lu <hongjiu.lu@intel.com> * config/obj-elf.c: Include "elf/x86-64.h" if TC_I386 is defined. (elf_com_section_ptr): New. (elf_begin): Set elf_com_section_ptr to bfd_com_section_ptr. (elf_common_parse): Make it global. Use elf_com_section_ptr instead of bfd_com_section_ptr. (obj_elf_change_section): Handle x86-64 large bss sections. * config/obj-elf.h (elf_com_section_ptr): New. (elf_common_parse): New. * config/tc-i386.c (handle_large_common): New. (md_pseudo_table): Add "largecomm". (x86_64_section_letter): New. (x86_64_section_word): New. * config/tc-i386.h (x86_64_section_word): New. (x86_64_section_letter): New. (md_elf_section_letter): New. Defined. (md_elf_section_word): Likewise. include/elf/ 2005-07-25 Jan Hubicka <jh@suse.cz> * x86-64.h (SHN_X86_64_LCOMMON): New. (SHF_X86_64_LARGE): New. ld/ 2005-07-25 Jan Hubicka <jh@suse.cz> H.J. Lu <hongjiu.lu@intel.com> * emulparams/elf_x86_64.sh (LARGE_SECTIONS): New. * scripttempl/elf.sc: Updated for large section support.
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/* Support for SHF_X86_64_LARGE */
extern int x86_64_section_word (char *, size_t);
extern int x86_64_section_letter (int, char **);
bfd/ 2005-07-25 Jan Hubicka <jh@suse.cz> H.J. Lu <hongjiu.lu@intel.com> * elf-bfd.h (_bfd_elf_large_com_section): New. * elf.c (_bfd_elf_large_com_section): New. Defined. * elf64-x86-64.c (elf64_x86_64_add_symbol_hook): New. (elf64_x86_64_elf_section_from_bfd_section): New. (elf64_x86_64_symbol_processing): New. (elf64_x86_64_common_definition): New. (elf64_x86_64_common_section_index): New. (elf64_x86_64_common_section): New. (elf64_x86_64_merge_symbol): New. (elf64_x86_64_additional_program_headers): New. (elf64_x86_64_special_sections): New. (elf_backend_section_from_bfd_section): New. Defined. (elf_backend_add_symbol_hook): Likewise. (elf_backend_common_section_index): Likewise. (elf_backend_common_section): Likewise. (elf_backend_common_definition): Likewise. (elf_backend_merge_symbol): Likewise. (elf_backend_special_sections): Likewise. (elf_backend_additional_program_headers): Likewise. binutils/ 2005-07-25 H.J. Lu <hongjiu.lu@intel.com> * readelf.c (dump_relocations): Handle SHN_X86_64_LCOMMON. (get_symbol_index_type): Likewise. (get_elf_section_flags): Handle SHF_X86_64_LARGE. gas/ 2005-07-25 Jan Hubicka <jh@suse.cz> H.J. Lu <hongjiu.lu@intel.com> * config/obj-elf.c: Include "elf/x86-64.h" if TC_I386 is defined. (elf_com_section_ptr): New. (elf_begin): Set elf_com_section_ptr to bfd_com_section_ptr. (elf_common_parse): Make it global. Use elf_com_section_ptr instead of bfd_com_section_ptr. (obj_elf_change_section): Handle x86-64 large bss sections. * config/obj-elf.h (elf_com_section_ptr): New. (elf_common_parse): New. * config/tc-i386.c (handle_large_common): New. (md_pseudo_table): Add "largecomm". (x86_64_section_letter): New. (x86_64_section_word): New. * config/tc-i386.h (x86_64_section_word): New. (x86_64_section_letter): New. (md_elf_section_letter): New. Defined. (md_elf_section_word): Likewise. include/elf/ 2005-07-25 Jan Hubicka <jh@suse.cz> * x86-64.h (SHN_X86_64_LCOMMON): New. (SHF_X86_64_LARGE): New. ld/ 2005-07-25 Jan Hubicka <jh@suse.cz> H.J. Lu <hongjiu.lu@intel.com> * emulparams/elf_x86_64.sh (LARGE_SECTIONS): New. * scripttempl/elf.sc: Updated for large section support.
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#define md_elf_section_letter(LETTER, PTR_MSG) x86_64_section_letter (LETTER, PTR_MSG)
#define md_elf_section_word(STR, LEN) x86_64_section_word (STR, LEN)
#ifdef TE_PE
#define O_secrel O_md1
#define TC_DWARF2_EMIT_OFFSET tc_pe_dwarf2_emit_offset
void tc_pe_dwarf2_emit_offset (symbolS *, unsigned int);
#endif /* TE_PE */
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#endif /* TC_I386 */