1999-05-03 15:29:11 +08:00
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/* tc-i386.h -- Header file for tc-i386.c
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2001-03-09 07:24:26 +08:00
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Copyright 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
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2007-01-04 06:54:45 +08:00
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2001, 2002, 2003, 2004, 2005, 2006, 2007
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2001-03-09 07:24:26 +08:00
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Free Software Foundation, Inc.
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1999-05-03 15:29:11 +08:00
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This file is part of GAS, the GNU Assembler.
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GAS is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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2007-07-03 19:01:12 +08:00
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the Free Software Foundation; either version 3, or (at your option)
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1999-05-03 15:29:11 +08:00
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any later version.
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GAS is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with GAS; see the file COPYING. If not, write to the Free
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2005-05-05 17:13:19 +08:00
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Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
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02110-1301, USA. */
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1999-05-03 15:29:11 +08:00
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#ifndef TC_I386
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#define TC_I386 1
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2007-03-21 23:37:21 +08:00
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#include "opcodes/i386-opc.h"
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1999-05-03 15:29:11 +08:00
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struct fix;
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#define TARGET_BYTES_BIG_ENDIAN 0
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#define TARGET_ARCH bfd_arch_i386
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2001-01-14 07:37:57 +08:00
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#define TARGET_MACH (i386_mach ())
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2004-10-01 16:38:35 +08:00
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extern unsigned long i386_mach (void);
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1999-05-03 15:29:11 +08:00
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2001-02-19 14:40:29 +08:00
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#ifdef TE_FreeBSD
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#define AOUT_TARGET_FORMAT "a.out-i386-freebsd"
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#endif
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1999-05-03 15:29:11 +08:00
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#ifdef TE_NetBSD
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2000-01-27 06:48:31 +08:00
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#define AOUT_TARGET_FORMAT "a.out-i386-netbsd"
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1999-05-03 15:29:11 +08:00
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#endif
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#ifdef TE_386BSD
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2000-01-27 06:48:31 +08:00
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#define AOUT_TARGET_FORMAT "a.out-i386-bsd"
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1999-05-03 15:29:11 +08:00
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#endif
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#ifdef TE_LINUX
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2000-01-27 06:48:31 +08:00
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#define AOUT_TARGET_FORMAT "a.out-i386-linux"
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1999-05-03 15:29:11 +08:00
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#endif
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#ifdef TE_Mach
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2000-01-27 06:48:31 +08:00
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#define AOUT_TARGET_FORMAT "a.out-mach3"
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1999-05-03 15:29:11 +08:00
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#endif
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#ifdef TE_DYNIX
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2000-01-27 06:48:31 +08:00
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#define AOUT_TARGET_FORMAT "a.out-i386-dynix"
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1999-05-03 15:29:11 +08:00
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#endif
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2000-01-27 06:48:31 +08:00
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#ifndef AOUT_TARGET_FORMAT
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#define AOUT_TARGET_FORMAT "a.out-i386"
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1999-05-03 15:29:11 +08:00
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#endif
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2002-09-17 10:24:40 +08:00
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#ifdef TE_FreeBSD
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#define ELF_TARGET_FORMAT "elf32-i386-freebsd"
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2006-08-03 00:25:14 +08:00
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#define ELF_TARGET_FORMAT64 "elf64-x86-64-freebsd"
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2005-05-05 22:37:27 +08:00
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#elif defined (TE_VXWORKS)
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#define ELF_TARGET_FORMAT "elf32-i386-vxworks"
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2002-09-17 10:24:40 +08:00
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#endif
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2005-05-05 22:37:27 +08:00
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2002-09-17 10:24:40 +08:00
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#ifndef ELF_TARGET_FORMAT
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#define ELF_TARGET_FORMAT "elf32-i386"
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#endif
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2006-08-03 00:25:14 +08:00
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#ifndef ELF_TARGET_FORMAT64
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#define ELF_TARGET_FORMAT64 "elf64-x86-64"
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#endif
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* tc-i386.h (i386_target_format): Define even for ELFs.
(QWORD_MNEM_SUFFIX): New macro.
(CpuK6,CpuAthlon,CpuSledgehammer, Cpu64, CpuNo64, CpuUnknownFlags):
New macros
(CpuMMX,CpuSSE,Cpu3dnow, CpuUnknown): Renumber.
(IgnoreSize, DefaultSize, No_?Suf, FWait, IsString, regKludge, IsPrefix,
ImmExt): Renumber.
(Size64, No_qSuf, NoRex64, Rex64): New macros.
(Reg64, Imm32S, Imm64, Disp32S, Disp64): New macros.
(Imm8, Imm8S, Imm16, Imm32, Imm1, BaseIndex, Disp8, Disp16, Disp32,
InOutPortReg,ShiftCount, Control, Debug, Test, FloatReg, FloatAcc,
SReg2, SReg3, Acc, JumpAbsolute, RegMMX, RegXMM, EsSeg, InvMem): Renumber.
(Reg, WordReg): Add Reg64.
(Imm): Add Imm32S and Imm64.
(EncImm): New.
(Disp): Add Disp64 and Disp32S.
(AnyMem): Add Disp32S.
(RegRex, RegRex64): New macros.
(rex_byte): New type.
* tc-i386.c (set_16bit_code_flag): Kill.
(fits_in_unsigned_long, fits_in_signed_long): New functions.
(reloc): New parameter "signed"; support x86_64.
(set_code_flag): New.
(DEFAULT_ARCH): New macro; default to "i386".
(default_arch): New static variable.
(struct _i386_insn): New fields Operand_PCrel; rex.
(flag_16bit_code): Kill; All tests replaced to "flag_code == CODE_64BIT";
(flag_code): New enum and static variable.
(use_rela_relocations): New static variable.
(flag_code_names): New static variable.
(cpu_arch_flags): Default to CpuUnknownFlags|CpuNo64.
(cpu_arch): Add "sledgehammer"; Add CPUAthlon to Athlon and CpuK6 to
K6 and Athlon.
(i386_align_code): Return plain "nop" for x86_64.
(mode_from_disp_size): Support Disp32S.
(smallest_imm_type): Support Imm32S and Imm64.
(offset_in_range): Support size of 8.
(set_cpu_arch): Do not clobber to Cpu64/CpuNo64.
(md_pseudo_table): Add "code64"; use set_code_flat.
(md_begin): Emit sane error message on hash failure.
(tc_i386_fix_adjustable): Support x86_64 relocations.
(md_assemble): Support QWORD_MNEM_SUFFIX, REX registers,
instructions supported on particular arch just partially,
output of 64bit immediates, handling of Imm32S and Disp32S type.
(i386_immedaite): Support x86_64 relocations; support 64bit constants.
(i386_displacement): Likewise.
(i386_index_check): Cleanup; support 64bit addresses.
(md_apply_fix3): Support x86_64 relocation and rela.
(md_longopts): Add "32" and "64".
(md_parse_option): Add OPTION_32 and OPTION_64.
(i386_target_format): Call even for ELFs; choose between
elf64-x86-64 and elf32-i386.
(i386_validate_fix): Refuse GOTOFF in 64bit mode.
(tc_gen_reloc): Support rela relocations and x86_64.
(intel_e09_1): Support QWORD.
* i386.h (i386_optab): Replace "Imm" with "EncImm".
(i386_regtab): Add flags field.
2000-12-20 21:24:13 +08:00
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#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
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|| defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
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2007-01-04 06:36:19 +08:00
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extern const char *i386_target_format (void);
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2000-01-27 06:48:31 +08:00
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#define TARGET_FORMAT i386_target_format ()
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#else
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1999-05-03 15:29:11 +08:00
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#ifdef OBJ_ELF
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2002-09-17 10:24:40 +08:00
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#define TARGET_FORMAT ELF_TARGET_FORMAT
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1999-05-03 15:29:11 +08:00
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#endif
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2000-01-27 06:48:31 +08:00
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#ifdef OBJ_AOUT
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#define TARGET_FORMAT AOUT_TARGET_FORMAT
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1999-05-03 15:29:11 +08:00
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#endif
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#endif
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2001-11-15 21:19:46 +08:00
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#if (defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF))
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#define md_end i386_elf_emit_arch_note
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2007-01-04 06:36:19 +08:00
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extern void i386_elf_emit_arch_note (void);
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2001-11-15 21:19:46 +08:00
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#endif
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2002-05-23 16:08:48 +08:00
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#define SUB_SEGMENT_ALIGN(SEG, FRCHAIN) 0
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2002-08-09 20:37:41 +08:00
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#define LOCAL_LABELS_FB 1
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1999-05-03 15:29:11 +08:00
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extern const char extra_symbol_chars[];
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#define tc_symbol_chars extra_symbol_chars
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2005-11-07 14:01:18 +08:00
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extern const char *i386_comment_chars;
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#define tc_comment_chars i386_comment_chars
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1999-05-03 15:29:11 +08:00
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/* Prefixes will be emitted in the order defined below.
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WAIT_PREFIX must be the first prefix since FWAIT is really is an
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2006-12-07 02:15:45 +08:00
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instruction, and so must come before any prefixes.
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The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
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LOCKREP_PREFIX. */
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1999-05-03 15:29:11 +08:00
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#define WAIT_PREFIX 0
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2006-12-07 02:15:45 +08:00
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#define SEG_PREFIX 1
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1999-05-03 15:29:11 +08:00
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#define ADDR_PREFIX 2
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#define DATA_PREFIX 3
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2006-12-07 02:15:45 +08:00
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#define LOCKREP_PREFIX 4
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* tc-i386.h (i386_target_format): Define even for ELFs.
(QWORD_MNEM_SUFFIX): New macro.
(CpuK6,CpuAthlon,CpuSledgehammer, Cpu64, CpuNo64, CpuUnknownFlags):
New macros
(CpuMMX,CpuSSE,Cpu3dnow, CpuUnknown): Renumber.
(IgnoreSize, DefaultSize, No_?Suf, FWait, IsString, regKludge, IsPrefix,
ImmExt): Renumber.
(Size64, No_qSuf, NoRex64, Rex64): New macros.
(Reg64, Imm32S, Imm64, Disp32S, Disp64): New macros.
(Imm8, Imm8S, Imm16, Imm32, Imm1, BaseIndex, Disp8, Disp16, Disp32,
InOutPortReg,ShiftCount, Control, Debug, Test, FloatReg, FloatAcc,
SReg2, SReg3, Acc, JumpAbsolute, RegMMX, RegXMM, EsSeg, InvMem): Renumber.
(Reg, WordReg): Add Reg64.
(Imm): Add Imm32S and Imm64.
(EncImm): New.
(Disp): Add Disp64 and Disp32S.
(AnyMem): Add Disp32S.
(RegRex, RegRex64): New macros.
(rex_byte): New type.
* tc-i386.c (set_16bit_code_flag): Kill.
(fits_in_unsigned_long, fits_in_signed_long): New functions.
(reloc): New parameter "signed"; support x86_64.
(set_code_flag): New.
(DEFAULT_ARCH): New macro; default to "i386".
(default_arch): New static variable.
(struct _i386_insn): New fields Operand_PCrel; rex.
(flag_16bit_code): Kill; All tests replaced to "flag_code == CODE_64BIT";
(flag_code): New enum and static variable.
(use_rela_relocations): New static variable.
(flag_code_names): New static variable.
(cpu_arch_flags): Default to CpuUnknownFlags|CpuNo64.
(cpu_arch): Add "sledgehammer"; Add CPUAthlon to Athlon and CpuK6 to
K6 and Athlon.
(i386_align_code): Return plain "nop" for x86_64.
(mode_from_disp_size): Support Disp32S.
(smallest_imm_type): Support Imm32S and Imm64.
(offset_in_range): Support size of 8.
(set_cpu_arch): Do not clobber to Cpu64/CpuNo64.
(md_pseudo_table): Add "code64"; use set_code_flat.
(md_begin): Emit sane error message on hash failure.
(tc_i386_fix_adjustable): Support x86_64 relocations.
(md_assemble): Support QWORD_MNEM_SUFFIX, REX registers,
instructions supported on particular arch just partially,
output of 64bit immediates, handling of Imm32S and Disp32S type.
(i386_immedaite): Support x86_64 relocations; support 64bit constants.
(i386_displacement): Likewise.
(i386_index_check): Cleanup; support 64bit addresses.
(md_apply_fix3): Support x86_64 relocation and rela.
(md_longopts): Add "32" and "64".
(md_parse_option): Add OPTION_32 and OPTION_64.
(i386_target_format): Call even for ELFs; choose between
elf64-x86-64 and elf32-i386.
(i386_validate_fix): Refuse GOTOFF in 64bit mode.
(tc_gen_reloc): Support rela relocations and x86_64.
(intel_e09_1): Support QWORD.
* i386.h (i386_optab): Replace "Imm" with "EncImm".
(i386_regtab): Add flags field.
2000-12-20 21:24:13 +08:00
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#define REX_PREFIX 5 /* must come last. */
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#define MAX_PREFIXES 6 /* max prefixes per opcode */
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1999-05-03 15:29:11 +08:00
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/* we define the syntax here (modulo base,index,scale syntax) */
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#define REGISTER_PREFIX '%'
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#define IMMEDIATE_PREFIX '$'
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#define ABSOLUTE_PREFIX '*'
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/* these are the instruction mnemonic suffixes. */
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#define WORD_MNEM_SUFFIX 'w'
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#define BYTE_MNEM_SUFFIX 'b'
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#define SHORT_MNEM_SUFFIX 's'
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#define LONG_MNEM_SUFFIX 'l'
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* tc-i386.h (i386_target_format): Define even for ELFs.
(QWORD_MNEM_SUFFIX): New macro.
(CpuK6,CpuAthlon,CpuSledgehammer, Cpu64, CpuNo64, CpuUnknownFlags):
New macros
(CpuMMX,CpuSSE,Cpu3dnow, CpuUnknown): Renumber.
(IgnoreSize, DefaultSize, No_?Suf, FWait, IsString, regKludge, IsPrefix,
ImmExt): Renumber.
(Size64, No_qSuf, NoRex64, Rex64): New macros.
(Reg64, Imm32S, Imm64, Disp32S, Disp64): New macros.
(Imm8, Imm8S, Imm16, Imm32, Imm1, BaseIndex, Disp8, Disp16, Disp32,
InOutPortReg,ShiftCount, Control, Debug, Test, FloatReg, FloatAcc,
SReg2, SReg3, Acc, JumpAbsolute, RegMMX, RegXMM, EsSeg, InvMem): Renumber.
(Reg, WordReg): Add Reg64.
(Imm): Add Imm32S and Imm64.
(EncImm): New.
(Disp): Add Disp64 and Disp32S.
(AnyMem): Add Disp32S.
(RegRex, RegRex64): New macros.
(rex_byte): New type.
* tc-i386.c (set_16bit_code_flag): Kill.
(fits_in_unsigned_long, fits_in_signed_long): New functions.
(reloc): New parameter "signed"; support x86_64.
(set_code_flag): New.
(DEFAULT_ARCH): New macro; default to "i386".
(default_arch): New static variable.
(struct _i386_insn): New fields Operand_PCrel; rex.
(flag_16bit_code): Kill; All tests replaced to "flag_code == CODE_64BIT";
(flag_code): New enum and static variable.
(use_rela_relocations): New static variable.
(flag_code_names): New static variable.
(cpu_arch_flags): Default to CpuUnknownFlags|CpuNo64.
(cpu_arch): Add "sledgehammer"; Add CPUAthlon to Athlon and CpuK6 to
K6 and Athlon.
(i386_align_code): Return plain "nop" for x86_64.
(mode_from_disp_size): Support Disp32S.
(smallest_imm_type): Support Imm32S and Imm64.
(offset_in_range): Support size of 8.
(set_cpu_arch): Do not clobber to Cpu64/CpuNo64.
(md_pseudo_table): Add "code64"; use set_code_flat.
(md_begin): Emit sane error message on hash failure.
(tc_i386_fix_adjustable): Support x86_64 relocations.
(md_assemble): Support QWORD_MNEM_SUFFIX, REX registers,
instructions supported on particular arch just partially,
output of 64bit immediates, handling of Imm32S and Disp32S type.
(i386_immedaite): Support x86_64 relocations; support 64bit constants.
(i386_displacement): Likewise.
(i386_index_check): Cleanup; support 64bit addresses.
(md_apply_fix3): Support x86_64 relocation and rela.
(md_longopts): Add "32" and "64".
(md_parse_option): Add OPTION_32 and OPTION_64.
(i386_target_format): Call even for ELFs; choose between
elf64-x86-64 and elf32-i386.
(i386_validate_fix): Refuse GOTOFF in 64bit mode.
(tc_gen_reloc): Support rela relocations and x86_64.
(intel_e09_1): Support QWORD.
* i386.h (i386_optab): Replace "Imm" with "EncImm".
(i386_regtab): Add flags field.
2000-12-20 21:24:13 +08:00
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#define QWORD_MNEM_SUFFIX 'q'
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1999-05-03 15:29:11 +08:00
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/* Intel Syntax */
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#define LONG_DOUBLE_MNEM_SUFFIX 'x'
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#define END_OF_INSN '\0'
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/*
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'templates' is for grouping together 'template' structures for opcodes
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of the same name. This is only used for storing the insns in the grand
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ole hash table of insns.
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The templates themselves start at START and range up to (but not including)
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END.
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*/
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typedef struct
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2000-05-13 17:26:23 +08:00
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{
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2007-03-21 23:37:21 +08:00
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const template *start;
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const template *end;
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2000-05-13 17:26:23 +08:00
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}
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2007-03-15 22:31:24 +08:00
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templates;
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1999-05-03 15:29:11 +08:00
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2000-09-16 08:56:47 +08:00
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/* 386 operand encoding bytes: see 386 book for details of this. */
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1999-05-03 15:29:11 +08:00
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typedef struct
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2000-05-13 17:26:23 +08:00
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{
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unsigned int regmem; /* codes register or memory operand */
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unsigned int reg; /* codes register operand (or extended opcode) */
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unsigned int mode; /* how to interpret regmem & reg */
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}
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1999-05-03 15:29:11 +08:00
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modrm_byte;
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* tc-i386.h (i386_target_format): Define even for ELFs.
(QWORD_MNEM_SUFFIX): New macro.
(CpuK6,CpuAthlon,CpuSledgehammer, Cpu64, CpuNo64, CpuUnknownFlags):
New macros
(CpuMMX,CpuSSE,Cpu3dnow, CpuUnknown): Renumber.
(IgnoreSize, DefaultSize, No_?Suf, FWait, IsString, regKludge, IsPrefix,
ImmExt): Renumber.
(Size64, No_qSuf, NoRex64, Rex64): New macros.
(Reg64, Imm32S, Imm64, Disp32S, Disp64): New macros.
(Imm8, Imm8S, Imm16, Imm32, Imm1, BaseIndex, Disp8, Disp16, Disp32,
InOutPortReg,ShiftCount, Control, Debug, Test, FloatReg, FloatAcc,
SReg2, SReg3, Acc, JumpAbsolute, RegMMX, RegXMM, EsSeg, InvMem): Renumber.
(Reg, WordReg): Add Reg64.
(Imm): Add Imm32S and Imm64.
(EncImm): New.
(Disp): Add Disp64 and Disp32S.
(AnyMem): Add Disp32S.
(RegRex, RegRex64): New macros.
(rex_byte): New type.
* tc-i386.c (set_16bit_code_flag): Kill.
(fits_in_unsigned_long, fits_in_signed_long): New functions.
(reloc): New parameter "signed"; support x86_64.
(set_code_flag): New.
(DEFAULT_ARCH): New macro; default to "i386".
(default_arch): New static variable.
(struct _i386_insn): New fields Operand_PCrel; rex.
(flag_16bit_code): Kill; All tests replaced to "flag_code == CODE_64BIT";
(flag_code): New enum and static variable.
(use_rela_relocations): New static variable.
(flag_code_names): New static variable.
(cpu_arch_flags): Default to CpuUnknownFlags|CpuNo64.
(cpu_arch): Add "sledgehammer"; Add CPUAthlon to Athlon and CpuK6 to
K6 and Athlon.
(i386_align_code): Return plain "nop" for x86_64.
(mode_from_disp_size): Support Disp32S.
(smallest_imm_type): Support Imm32S and Imm64.
(offset_in_range): Support size of 8.
(set_cpu_arch): Do not clobber to Cpu64/CpuNo64.
(md_pseudo_table): Add "code64"; use set_code_flat.
(md_begin): Emit sane error message on hash failure.
(tc_i386_fix_adjustable): Support x86_64 relocations.
(md_assemble): Support QWORD_MNEM_SUFFIX, REX registers,
instructions supported on particular arch just partially,
output of 64bit immediates, handling of Imm32S and Disp32S type.
(i386_immedaite): Support x86_64 relocations; support 64bit constants.
(i386_displacement): Likewise.
(i386_index_check): Cleanup; support 64bit addresses.
(md_apply_fix3): Support x86_64 relocation and rela.
(md_longopts): Add "32" and "64".
(md_parse_option): Add OPTION_32 and OPTION_64.
(i386_target_format): Call even for ELFs; choose between
elf64-x86-64 and elf32-i386.
(i386_validate_fix): Refuse GOTOFF in 64bit mode.
(tc_gen_reloc): Support rela relocations and x86_64.
(intel_e09_1): Support QWORD.
* i386.h (i386_optab): Replace "Imm" with "EncImm".
(i386_regtab): Add flags field.
2000-12-20 21:24:13 +08:00
|
|
|
/* x86-64 extension prefix. */
|
2002-03-09 13:36:51 +08:00
|
|
|
typedef int rex_byte;
|
* tc-i386.h (i386_target_format): Define even for ELFs.
(QWORD_MNEM_SUFFIX): New macro.
(CpuK6,CpuAthlon,CpuSledgehammer, Cpu64, CpuNo64, CpuUnknownFlags):
New macros
(CpuMMX,CpuSSE,Cpu3dnow, CpuUnknown): Renumber.
(IgnoreSize, DefaultSize, No_?Suf, FWait, IsString, regKludge, IsPrefix,
ImmExt): Renumber.
(Size64, No_qSuf, NoRex64, Rex64): New macros.
(Reg64, Imm32S, Imm64, Disp32S, Disp64): New macros.
(Imm8, Imm8S, Imm16, Imm32, Imm1, BaseIndex, Disp8, Disp16, Disp32,
InOutPortReg,ShiftCount, Control, Debug, Test, FloatReg, FloatAcc,
SReg2, SReg3, Acc, JumpAbsolute, RegMMX, RegXMM, EsSeg, InvMem): Renumber.
(Reg, WordReg): Add Reg64.
(Imm): Add Imm32S and Imm64.
(EncImm): New.
(Disp): Add Disp64 and Disp32S.
(AnyMem): Add Disp32S.
(RegRex, RegRex64): New macros.
(rex_byte): New type.
* tc-i386.c (set_16bit_code_flag): Kill.
(fits_in_unsigned_long, fits_in_signed_long): New functions.
(reloc): New parameter "signed"; support x86_64.
(set_code_flag): New.
(DEFAULT_ARCH): New macro; default to "i386".
(default_arch): New static variable.
(struct _i386_insn): New fields Operand_PCrel; rex.
(flag_16bit_code): Kill; All tests replaced to "flag_code == CODE_64BIT";
(flag_code): New enum and static variable.
(use_rela_relocations): New static variable.
(flag_code_names): New static variable.
(cpu_arch_flags): Default to CpuUnknownFlags|CpuNo64.
(cpu_arch): Add "sledgehammer"; Add CPUAthlon to Athlon and CpuK6 to
K6 and Athlon.
(i386_align_code): Return plain "nop" for x86_64.
(mode_from_disp_size): Support Disp32S.
(smallest_imm_type): Support Imm32S and Imm64.
(offset_in_range): Support size of 8.
(set_cpu_arch): Do not clobber to Cpu64/CpuNo64.
(md_pseudo_table): Add "code64"; use set_code_flat.
(md_begin): Emit sane error message on hash failure.
(tc_i386_fix_adjustable): Support x86_64 relocations.
(md_assemble): Support QWORD_MNEM_SUFFIX, REX registers,
instructions supported on particular arch just partially,
output of 64bit immediates, handling of Imm32S and Disp32S type.
(i386_immedaite): Support x86_64 relocations; support 64bit constants.
(i386_displacement): Likewise.
(i386_index_check): Cleanup; support 64bit addresses.
(md_apply_fix3): Support x86_64 relocation and rela.
(md_longopts): Add "32" and "64".
(md_parse_option): Add OPTION_32 and OPTION_64.
(i386_target_format): Call even for ELFs; choose between
elf64-x86-64 and elf32-i386.
(i386_validate_fix): Refuse GOTOFF in 64bit mode.
(tc_gen_reloc): Support rela relocations and x86_64.
(intel_e09_1): Support QWORD.
* i386.h (i386_optab): Replace "Imm" with "EncImm".
(i386_regtab): Add flags field.
2000-12-20 21:24:13 +08:00
|
|
|
|
2007-09-15 02:21:09 +08:00
|
|
|
/* The SSE5 instructions have a two bit instruction modifier (OC) that
|
|
|
|
is stored in two separate bytes in the instruction. Pick apart OC
|
|
|
|
into the 2 separate bits for instruction. */
|
|
|
|
#define DREX_OC0(x) (((x) & 1) != 0)
|
|
|
|
#define DREX_OC1(x) (((x) & 2) != 0)
|
|
|
|
|
|
|
|
#define DREX_OC0_MASK (1 << 3) /* set OC0 in byte 4 */
|
|
|
|
#define DREX_OC1_MASK (1 << 2) /* set OC1 in byte 3 */
|
|
|
|
|
|
|
|
/* OC mappings */
|
|
|
|
#define DREX_XMEM_X1_X2_X2 0 /* 4 op insn, dest = src3, src1 = reg/mem */
|
|
|
|
#define DREX_X1_XMEM_X2_X2 1 /* 4 op insn, dest = src3, src2 = reg/mem */
|
|
|
|
#define DREX_X1_XMEM_X2_X1 2 /* 4 op insn, dest = src1, src2 = reg/mem */
|
|
|
|
#define DREX_X1_X2_XMEM_X1 3 /* 4 op insn, dest = src1, src3 = reg/mem */
|
|
|
|
|
|
|
|
#define DREX_XMEM_X1_X2 0 /* 3 op insn, src1 = reg/mem */
|
|
|
|
#define DREX_X1_XMEM_X2 1 /* 3 op insn, src1 = reg/mem */
|
|
|
|
|
|
|
|
/* Information needed to create the DREX byte in SSE5 instructions. */
|
|
|
|
typedef struct
|
|
|
|
{
|
|
|
|
unsigned int reg; /* register */
|
|
|
|
unsigned int rex; /* REX flags */
|
|
|
|
unsigned int modrm_reg; /* which arg goes in the modrm.reg field */
|
|
|
|
unsigned int modrm_regmem; /* which arg goes in the modrm.regmem field */
|
|
|
|
} drex_byte;
|
|
|
|
|
2000-09-16 08:56:47 +08:00
|
|
|
/* 386 opcode byte to code indirect addressing. */
|
1999-05-03 15:29:11 +08:00
|
|
|
typedef struct
|
2000-05-13 17:26:23 +08:00
|
|
|
{
|
|
|
|
unsigned base;
|
|
|
|
unsigned index;
|
|
|
|
unsigned scale;
|
|
|
|
}
|
1999-05-03 15:29:11 +08:00
|
|
|
sib_byte;
|
|
|
|
|
2006-06-16 23:46:11 +08:00
|
|
|
enum processor_type
|
|
|
|
{
|
|
|
|
PROCESSOR_UNKNOWN,
|
2007-07-24 04:03:23 +08:00
|
|
|
PROCESSOR_I386,
|
2006-06-16 23:46:11 +08:00
|
|
|
PROCESSOR_I486,
|
|
|
|
PROCESSOR_PENTIUM,
|
|
|
|
PROCESSOR_PENTIUMPRO,
|
|
|
|
PROCESSOR_PENTIUM4,
|
|
|
|
PROCESSOR_NOCONA,
|
2006-09-28 22:06:36 +08:00
|
|
|
PROCESSOR_CORE,
|
|
|
|
PROCESSOR_CORE2,
|
2006-06-16 23:46:11 +08:00
|
|
|
PROCESSOR_K6,
|
|
|
|
PROCESSOR_ATHLON,
|
|
|
|
PROCESSOR_K8,
|
|
|
|
PROCESSOR_GENERIC32,
|
2006-07-14 06:25:48 +08:00
|
|
|
PROCESSOR_GENERIC64,
|
|
|
|
PROCESSOR_AMDFAM10
|
2006-06-16 23:46:11 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
/* x86 arch names, types and features */
|
2000-05-13 17:26:23 +08:00
|
|
|
typedef struct
|
|
|
|
{
|
2006-06-16 23:46:11 +08:00
|
|
|
const char *name; /* arch name */
|
|
|
|
enum processor_type type; /* arch type */
|
2007-09-09 09:22:57 +08:00
|
|
|
i386_cpu_flags flags; /* cpu feature flags */
|
2000-05-13 17:26:23 +08:00
|
|
|
}
|
|
|
|
arch_entry;
|
|
|
|
|
1999-05-03 15:29:11 +08:00
|
|
|
/* The name of the global offset table generated by the compiler. Allow
|
2000-09-16 08:56:47 +08:00
|
|
|
this to be overridden if need be. */
|
1999-05-03 15:29:11 +08:00
|
|
|
#ifndef GLOBAL_OFFSET_TABLE_NAME
|
|
|
|
#define GLOBAL_OFFSET_TABLE_NAME "_GLOBAL_OFFSET_TABLE_"
|
|
|
|
#endif
|
|
|
|
|
2005-07-18 23:24:41 +08:00
|
|
|
#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && !defined (LEX_AT)
|
2002-08-09 20:37:41 +08:00
|
|
|
#define TC_PARSE_CONS_EXPRESSION(EXP, NBYTES) x86_cons (EXP, NBYTES)
|
2007-01-04 06:36:19 +08:00
|
|
|
extern void x86_cons (expressionS *, int);
|
2005-09-28 22:44:25 +08:00
|
|
|
#endif
|
2002-08-09 20:37:41 +08:00
|
|
|
|
|
|
|
#define TC_CONS_FIX_NEW(FRAG,OFF,LEN,EXP) x86_cons_fix_new(FRAG, OFF, LEN, EXP)
|
|
|
|
extern void x86_cons_fix_new
|
2007-01-04 06:36:19 +08:00
|
|
|
(fragS *, unsigned int, unsigned int, expressionS *);
|
2002-08-09 20:37:41 +08:00
|
|
|
|
|
|
|
#define DIFF_EXPR_OK /* foo-. gets turned into PC relative relocs */
|
|
|
|
|
|
|
|
#define NO_RELOC BFD_RELOC_NONE
|
|
|
|
|
2007-01-04 06:36:19 +08:00
|
|
|
void i386_validate_fix (struct fix *);
|
2002-09-05 08:01:18 +08:00
|
|
|
#define TC_VALIDATE_FIX(FIX,SEGTYPE,SKIP) i386_validate_fix(FIX)
|
2002-08-09 20:37:41 +08:00
|
|
|
|
|
|
|
#define tc_fix_adjustable(X) tc_i386_fix_adjustable(X)
|
2007-01-04 06:36:19 +08:00
|
|
|
extern int tc_i386_fix_adjustable (struct fix *);
|
2002-08-09 20:37:41 +08:00
|
|
|
|
gas:
* cgen.c, cgen.h, tc.h, write.c, config/obj-coff.c
* config/tc-a29k.c, config/tc-alpha.c, config/tc-alpha.h
* config/tc-arc.c, config/tc-arc.h, config/tc-arm.c
* config/tc-arm.h, config/tc-avr.c, config/tc-avr.h
* config/tc-cris.c, config/tc-crx.c, config/tc-d10v.c
* config/tc-d10v.h, config/tc-d30v.c, config/tc-d30v.h
* config/tc-dlx.c, config/tc-dlx.h, config/tc-fr30.h
* config/tc-frv.c, config/tc-frv.h, config/tc-h8300.c
* config/tc-h8500.c, config/tc-hppa.c, config/tc-hppa.h
* config/tc-i370.c, config/tc-i370.h, config/tc-i386.c
* config/tc-i386.h, config/tc-i860.c, config/tc-i860.h
* config/tc-i960.c, config/tc-i960.h, config/tc-ia64.c
* config/tc-ip2k.c, config/tc-ip2k.h, config/tc-iq2000.c
* config/tc-iq2000.h, config/tc-m32r.c, config/tc-m32r.h
* config/tc-m68hc11.c, config/tc-m68hc11.h, config/tc-m68k.c
* config/tc-m68k.h, config/tc-m88k.c, config/tc-maxq.c
* config/tc-mcore.c, config/tc-mcore.h, config/tc-mips.c
* config/tc-mips.h, config/tc-mmix.c, config/tc-mn10200.c
* config/tc-mn10300.c, config/tc-msp430.c, config/tc-ns32k.c
* config/tc-openrisc.h, config/tc-or32.c, config/tc-or32.h
* config/tc-pdp11.c, config/tc-pj.c, config/tc-pj.h
* config/tc-ppc.c, config/tc-ppc.h, config/tc-s390.c
* config/tc-s390.h, config/tc-sh64.c, config/tc-sh.c
* config/tc-sh.h, config/tc-sparc.c, config/tc-sparc.h
* config/tc-tahoe.c, config/tc-tic30.c, config/tc-tic4x.c
* config/tc-tic54x.c, config/tc-tic80.c, config/tc-v850.c
* config/tc-v850.h, config/tc-vax.c, config/tc-vax.h
* config/tc-w65.c, config/tc-xstormy16.c, config/tc-xstormy16.h
* config/tc-xtensa.c, config/tc-z8k.c:
Replace all instances of the string "_apply_fix3" with
"_apply_fix".
* po/POTFILES.in, po/gas.pot: Regenerate.
bfd:
* coff-i386.c: Change md_apply_fix3 to md_apply_fix in comment.
cgen:
* doc/porting.texi: Change all mention of md_apply_fix3 and
gas_cgen_md_apply_fix3 to md_apply_fix and gas_cgen_md_apply_fix
respectively.
2005-06-08 01:54:22 +08:00
|
|
|
/* Values passed to md_apply_fix don't include the symbol value. */
|
2002-09-05 08:01:18 +08:00
|
|
|
#define MD_APPLY_SYM_VALUE(FIX) 0
|
2002-10-15 10:20:53 +08:00
|
|
|
|
|
|
|
/* ELF wants external syms kept, as does PE COFF. */
|
2003-01-23 20:51:05 +08:00
|
|
|
#if defined (TE_PE) && defined (STRICT_PE_FORMAT)
|
|
|
|
#define EXTERN_FORCE_RELOC \
|
2002-10-15 10:20:53 +08:00
|
|
|
(OUTPUT_FLAVOR == bfd_target_elf_flavour \
|
|
|
|
|| OUTPUT_FLAVOR == bfd_target_coff_flavour)
|
|
|
|
#else
|
|
|
|
#define EXTERN_FORCE_RELOC \
|
|
|
|
(OUTPUT_FLAVOR == bfd_target_elf_flavour)
|
1999-05-03 15:29:11 +08:00
|
|
|
#endif
|
|
|
|
|
2002-09-05 08:01:18 +08:00
|
|
|
/* This expression evaluates to true if the relocation is for a local
|
|
|
|
object for which we still want to do the relocation at runtime.
|
|
|
|
False if we are willing to perform this relocation while building
|
|
|
|
the .o file. GOTOFF does not need to be checked here because it is
|
|
|
|
not pcrel. I am not sure if some of the others are ever used with
|
2002-08-09 20:37:41 +08:00
|
|
|
pcrel, but it is easier to be safe than sorry. */
|
|
|
|
|
2002-09-05 08:01:18 +08:00
|
|
|
#define TC_FORCE_RELOCATION_LOCAL(FIX) \
|
|
|
|
(!(FIX)->fx_pcrel \
|
|
|
|
|| (FIX)->fx_r_type == BFD_RELOC_386_PLT32 \
|
|
|
|
|| (FIX)->fx_r_type == BFD_RELOC_386_GOT32 \
|
|
|
|
|| (FIX)->fx_r_type == BFD_RELOC_386_GOTPC \
|
|
|
|
|| TC_FORCE_RELOCATION (FIX))
|
2002-08-09 20:37:41 +08:00
|
|
|
|
2005-10-26 20:29:44 +08:00
|
|
|
extern int i386_parse_name (char *, expressionS *, char *);
|
|
|
|
#define md_parse_name(s, e, m, c) i386_parse_name (s, e, c)
|
1999-05-03 15:29:11 +08:00
|
|
|
|
2007-09-26 16:34:24 +08:00
|
|
|
#define md_register_arithmetic 0
|
|
|
|
|
1999-05-03 15:29:11 +08:00
|
|
|
extern const struct relax_type md_relax_table[];
|
|
|
|
#define TC_GENERIC_RELAX_TABLE md_relax_table
|
|
|
|
|
2003-06-10 14:46:34 +08:00
|
|
|
extern int optimize_align_code;
|
|
|
|
|
1999-05-03 15:29:11 +08:00
|
|
|
#define md_do_align(n, fill, len, max, around) \
|
2003-06-10 14:46:34 +08:00
|
|
|
if ((n) \
|
|
|
|
&& !need_pass_2 \
|
|
|
|
&& optimize_align_code \
|
|
|
|
&& (!(fill) \
|
|
|
|
|| ((char)*(fill) == (char)0x90 && (len) == 1)) \
|
1999-06-13 00:49:51 +08:00
|
|
|
&& subseg_text_p (now_seg)) \
|
1999-05-03 15:29:11 +08:00
|
|
|
{ \
|
2000-12-28 18:07:56 +08:00
|
|
|
frag_align_code ((n), (max)); \
|
1999-05-03 15:29:11 +08:00
|
|
|
goto around; \
|
|
|
|
}
|
|
|
|
|
2007-07-24 04:03:23 +08:00
|
|
|
#define MAX_MEM_FOR_RS_ALIGN_CODE 31
|
2000-12-28 18:07:56 +08:00
|
|
|
|
2007-01-04 06:36:19 +08:00
|
|
|
extern void i386_align_code (fragS *, int);
|
1999-05-03 15:29:11 +08:00
|
|
|
|
|
|
|
#define HANDLE_ALIGN(fragP) \
|
|
|
|
if (fragP->fr_type == rs_align_code) \
|
|
|
|
i386_align_code (fragP, (fragP->fr_next->fr_address \
|
|
|
|
- fragP->fr_address \
|
|
|
|
- fragP->fr_fix));
|
|
|
|
|
2007-01-04 06:36:19 +08:00
|
|
|
void i386_print_statistics (FILE *);
|
1999-05-03 15:29:11 +08:00
|
|
|
#define tc_print_statistics i386_print_statistics
|
|
|
|
|
|
|
|
#define md_number_to_chars number_to_chars_littleendian
|
|
|
|
|
|
|
|
#ifdef SCO_ELF
|
|
|
|
#define tc_init_after_args() sco_id ()
|
2007-01-04 06:36:19 +08:00
|
|
|
extern void sco_id (void);
|
1999-05-03 15:29:11 +08:00
|
|
|
#endif
|
|
|
|
|
2007-03-09 20:35:37 +08:00
|
|
|
#define WORKING_DOT_WORD 1
|
|
|
|
|
2003-05-20 15:58:07 +08:00
|
|
|
/* We want .cfi_* pseudo-ops for generating unwind info. */
|
2003-05-28 00:52:49 +08:00
|
|
|
#define TARGET_USE_CFIPOP 1
|
2003-05-20 15:58:07 +08:00
|
|
|
|
2003-05-28 00:52:49 +08:00
|
|
|
extern unsigned int x86_dwarf2_return_column;
|
|
|
|
#define DWARF2_DEFAULT_RETURN_COLUMN x86_dwarf2_return_column
|
|
|
|
|
|
|
|
extern int x86_cie_data_alignment;
|
|
|
|
#define DWARF2_CIE_DATA_ALIGNMENT x86_cie_data_alignment
|
2003-05-20 15:58:07 +08:00
|
|
|
|
|
|
|
#define tc_regname_to_dw2regnum tc_x86_regname_to_dw2regnum
|
2007-01-04 06:36:19 +08:00
|
|
|
extern int tc_x86_regname_to_dw2regnum (char *);
|
2003-05-20 15:58:07 +08:00
|
|
|
|
|
|
|
#define tc_cfi_frame_initial_instructions tc_x86_frame_initial_instructions
|
2007-01-04 06:36:19 +08:00
|
|
|
extern void tc_x86_frame_initial_instructions (void);
|
2003-05-20 15:58:07 +08:00
|
|
|
|
2004-10-08 21:55:11 +08:00
|
|
|
#define md_elf_section_type(str,len) i386_elf_section_type (str, len)
|
2007-01-04 06:36:19 +08:00
|
|
|
extern int i386_elf_section_type (const char *, size_t);
|
2004-10-08 21:55:11 +08:00
|
|
|
|
2005-07-25 23:41:08 +08:00
|
|
|
/* Support for SHF_X86_64_LARGE */
|
2007-01-04 06:36:19 +08:00
|
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extern int x86_64_section_word (char *, size_t);
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extern int x86_64_section_letter (int, char **);
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2005-07-25 23:41:08 +08:00
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#define md_elf_section_letter(LETTER, PTR_MSG) x86_64_section_letter (LETTER, PTR_MSG)
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#define md_elf_section_word(STR, LEN) x86_64_section_word (STR, LEN)
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2004-10-18 20:32:13 +08:00
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#ifdef TE_PE
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#define O_secrel O_md1
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#define TC_DWARF2_EMIT_OFFSET tc_pe_dwarf2_emit_offset
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void tc_pe_dwarf2_emit_offset (symbolS *, unsigned int);
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#endif /* TE_PE */
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2002-08-09 20:37:41 +08:00
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#endif /* TC_I386 */
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