1999-05-03 15:29:11 +08:00
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/* Table of opcodes for the sparc.
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2017-01-02 11:36:43 +08:00
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Copyright (C) 1989-2017 Free Software Foundation, Inc.
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1999-05-03 15:29:11 +08:00
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2007-07-05 17:49:03 +08:00
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This file is part of the GNU opcodes library.
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1999-05-03 15:29:11 +08:00
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2007-07-05 17:49:03 +08:00
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This library is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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1999-05-03 15:29:11 +08:00
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2007-07-05 17:49:03 +08:00
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It is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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1999-05-03 15:29:11 +08:00
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2005-07-01 19:16:33 +08:00
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You should have received a copy of the GNU General Public License
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2007-07-05 17:49:03 +08:00
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along with this file; see the file COPYING. If not, write to the
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Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
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MA 02110-1301, USA. */
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1999-05-03 15:29:11 +08:00
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/* FIXME-someday: perhaps the ,a's and such should be embedded in the
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instruction's name rather than the args. This would make gas faster, pinsn
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slower, but would mess up some macros a bit. xoxorich. */
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2000-04-14 12:16:58 +08:00
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#include "sysdep.h"
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2012-05-17 23:13:28 +08:00
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#include <stdio.h>
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1999-05-03 15:29:11 +08:00
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#include "opcode/sparc.h"
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/* Some defines to make life easy. */
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#define MASK_V6 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V6)
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#define MASK_V7 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V7)
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#define MASK_V8 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8)
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2013-08-06 00:11:07 +08:00
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#define MASK_LEON SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_LEON)
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1999-05-03 15:29:11 +08:00
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#define MASK_SPARCLET SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLET)
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#define MASK_SPARCLITE SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLITE)
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#define MASK_V9 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9)
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#define MASK_V9A SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A)
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2000-10-20 18:38:47 +08:00
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#define MASK_V9B SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9B)
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bfd,opcodes: sparc: new opcode v9{c,d,e,v,m} architectures and bfd machine numbers.
This patch adds support for the opcode architectures
SPARC_OPCODE_ARCH_V9{C,D,E,V,M} and its associated BFD machine numbers
bfd_mach_sparc_v9{c,d,e,v,m} and bfd_mach_sparc_v8plus{c,d,e,v,m}.
Note that for arches up to v9b (UltraSPARC III), the detection of the
BFD machine type was based on the bits in the e_machine field of the ELF
header. However, there are no more available bits in that field, so
this patch takes the approach of using the hardware capabilities stored
in the object attributes HWCAPS/HWCAPS2 in order to characterize the
machine the object was built for.
bfd/ChangeLog:
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* archures.c (bfd_mach_sparc_v8plusc): Define.
(bfd_mach_sparc_v9c): Likewise.
(bfd_mach_sparc_v8plusd): Likewise.
(bfd_mach_sparc_v9d): Likewise.
(bfd_mach_sparc_v8pluse): Likewise.
(bfd_mach_sparc_v9e): Likewise.
(bfd_mach_sparc_v8plusv): Likewise
(bfd_mach_sparc_v9v): Likewise.
(bfd_mach_sparc_v8plusm): Likewise.
(bfd_mach_sparc_v9m): Likewise.
(bfd_mach_sparc_v9_p): Adapt to v8plusm and v9m.
(bfd_mach_sparc_64bit_p): Likewise.
* bfd-in2.h: Regenerate.
* cpu-sparc.c (arch_info_struct): Add entries for
bfd_mach_sparc_v8plus{c,d,e,v,m} and bfd_mach_sparc_v9{c,d,e,v,m}.
* aoutx.h (machine_type): Handle bfd_mach_sparc_v8plus{c,d,e,v,m}
and bfd_mach_sparc_v9{c,d,e,v,m}.
* elf32-sparc.c (elf32_sparc_final_write_processing): Likewise.
* elfxx-sparc.c (_bfd_sparc_elf_object_p): Likewise.
include/ChangeLog:
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* opcode/sparc.h (enum sparc_opcode_arch_val): Add
SPARC_OPCODE_ARCH_V9C, SPARC_OPCODE_ARCH_V9D,
SPARC_OPCODE_ARCH_V9E, SPARC_OPCODE_ARCH_V9V and
SPARC_OPCODE_ARCH_V9M.
opcodes/ChangeLog:
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
(compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
bfd_mach_sparc_v9{c,d,e,v,m}.
* sparc-opc.c (MASK_V9C): Define.
(MASK_V9D): Likewise.
(MASK_V9E): Likewise.
(MASK_V9V): Likewise.
(MASK_V9M): Likewise.
(v6): Add MASK_V9{C,D,E,V,M}.
(v6notlet): Likewise.
(v7): Likewise.
(v8): Likewise.
(v9): Likewise.
(v9andleon): Likewise.
(v9a): Likewise.
(v9b): Likewise.
(v9c): Define.
(v9d): Likewise.
(v9e): Likewise.
(v9v): Likewise.
(v9m): Likewise.
(sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
2016-06-17 17:12:48 +08:00
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#define MASK_V9C SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9C)
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#define MASK_V9D SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9D)
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#define MASK_V9E SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9E)
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#define MASK_V9V SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9V)
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#define MASK_V9M SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9M)
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1999-05-03 15:29:11 +08:00
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/* Bit masks of architectures supporting the insn. */
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2013-08-06 00:11:07 +08:00
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#define v6 (MASK_V6 | MASK_V7 | MASK_V8 | MASK_LEON \
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| MASK_SPARCLET | MASK_SPARCLITE \
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bfd,opcodes: sparc: new opcode v9{c,d,e,v,m} architectures and bfd machine numbers.
This patch adds support for the opcode architectures
SPARC_OPCODE_ARCH_V9{C,D,E,V,M} and its associated BFD machine numbers
bfd_mach_sparc_v9{c,d,e,v,m} and bfd_mach_sparc_v8plus{c,d,e,v,m}.
Note that for arches up to v9b (UltraSPARC III), the detection of the
BFD machine type was based on the bits in the e_machine field of the ELF
header. However, there are no more available bits in that field, so
this patch takes the approach of using the hardware capabilities stored
in the object attributes HWCAPS/HWCAPS2 in order to characterize the
machine the object was built for.
bfd/ChangeLog:
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* archures.c (bfd_mach_sparc_v8plusc): Define.
(bfd_mach_sparc_v9c): Likewise.
(bfd_mach_sparc_v8plusd): Likewise.
(bfd_mach_sparc_v9d): Likewise.
(bfd_mach_sparc_v8pluse): Likewise.
(bfd_mach_sparc_v9e): Likewise.
(bfd_mach_sparc_v8plusv): Likewise
(bfd_mach_sparc_v9v): Likewise.
(bfd_mach_sparc_v8plusm): Likewise.
(bfd_mach_sparc_v9m): Likewise.
(bfd_mach_sparc_v9_p): Adapt to v8plusm and v9m.
(bfd_mach_sparc_64bit_p): Likewise.
* bfd-in2.h: Regenerate.
* cpu-sparc.c (arch_info_struct): Add entries for
bfd_mach_sparc_v8plus{c,d,e,v,m} and bfd_mach_sparc_v9{c,d,e,v,m}.
* aoutx.h (machine_type): Handle bfd_mach_sparc_v8plus{c,d,e,v,m}
and bfd_mach_sparc_v9{c,d,e,v,m}.
* elf32-sparc.c (elf32_sparc_final_write_processing): Likewise.
* elfxx-sparc.c (_bfd_sparc_elf_object_p): Likewise.
include/ChangeLog:
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* opcode/sparc.h (enum sparc_opcode_arch_val): Add
SPARC_OPCODE_ARCH_V9C, SPARC_OPCODE_ARCH_V9D,
SPARC_OPCODE_ARCH_V9E, SPARC_OPCODE_ARCH_V9V and
SPARC_OPCODE_ARCH_V9M.
opcodes/ChangeLog:
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
(compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
bfd_mach_sparc_v9{c,d,e,v,m}.
* sparc-opc.c (MASK_V9C): Define.
(MASK_V9D): Likewise.
(MASK_V9E): Likewise.
(MASK_V9V): Likewise.
(MASK_V9M): Likewise.
(v6): Add MASK_V9{C,D,E,V,M}.
(v6notlet): Likewise.
(v7): Likewise.
(v8): Likewise.
(v9): Likewise.
(v9andleon): Likewise.
(v9a): Likewise.
(v9b): Likewise.
(v9c): Define.
(v9d): Likewise.
(v9e): Likewise.
(v9v): Likewise.
(v9m): Likewise.
(sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
2016-06-17 17:12:48 +08:00
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| MASK_V9 | MASK_V9A | MASK_V9B \
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| MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M)
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2005-07-01 19:16:33 +08:00
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/* v6 insns not supported on the sparclet. */
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2013-08-06 00:11:07 +08:00
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#define v6notlet (MASK_V6 | MASK_V7 | MASK_V8 | MASK_LEON \
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bfd,opcodes: sparc: new opcode v9{c,d,e,v,m} architectures and bfd machine numbers.
This patch adds support for the opcode architectures
SPARC_OPCODE_ARCH_V9{C,D,E,V,M} and its associated BFD machine numbers
bfd_mach_sparc_v9{c,d,e,v,m} and bfd_mach_sparc_v8plus{c,d,e,v,m}.
Note that for arches up to v9b (UltraSPARC III), the detection of the
BFD machine type was based on the bits in the e_machine field of the ELF
header. However, there are no more available bits in that field, so
this patch takes the approach of using the hardware capabilities stored
in the object attributes HWCAPS/HWCAPS2 in order to characterize the
machine the object was built for.
bfd/ChangeLog:
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* archures.c (bfd_mach_sparc_v8plusc): Define.
(bfd_mach_sparc_v9c): Likewise.
(bfd_mach_sparc_v8plusd): Likewise.
(bfd_mach_sparc_v9d): Likewise.
(bfd_mach_sparc_v8pluse): Likewise.
(bfd_mach_sparc_v9e): Likewise.
(bfd_mach_sparc_v8plusv): Likewise
(bfd_mach_sparc_v9v): Likewise.
(bfd_mach_sparc_v8plusm): Likewise.
(bfd_mach_sparc_v9m): Likewise.
(bfd_mach_sparc_v9_p): Adapt to v8plusm and v9m.
(bfd_mach_sparc_64bit_p): Likewise.
* bfd-in2.h: Regenerate.
* cpu-sparc.c (arch_info_struct): Add entries for
bfd_mach_sparc_v8plus{c,d,e,v,m} and bfd_mach_sparc_v9{c,d,e,v,m}.
* aoutx.h (machine_type): Handle bfd_mach_sparc_v8plus{c,d,e,v,m}
and bfd_mach_sparc_v9{c,d,e,v,m}.
* elf32-sparc.c (elf32_sparc_final_write_processing): Likewise.
* elfxx-sparc.c (_bfd_sparc_elf_object_p): Likewise.
include/ChangeLog:
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* opcode/sparc.h (enum sparc_opcode_arch_val): Add
SPARC_OPCODE_ARCH_V9C, SPARC_OPCODE_ARCH_V9D,
SPARC_OPCODE_ARCH_V9E, SPARC_OPCODE_ARCH_V9V and
SPARC_OPCODE_ARCH_V9M.
opcodes/ChangeLog:
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
(compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
bfd_mach_sparc_v9{c,d,e,v,m}.
* sparc-opc.c (MASK_V9C): Define.
(MASK_V9D): Likewise.
(MASK_V9E): Likewise.
(MASK_V9V): Likewise.
(MASK_V9M): Likewise.
(v6): Add MASK_V9{C,D,E,V,M}.
(v6notlet): Likewise.
(v7): Likewise.
(v8): Likewise.
(v9): Likewise.
(v9andleon): Likewise.
(v9a): Likewise.
(v9b): Likewise.
(v9c): Define.
(v9d): Likewise.
(v9e): Likewise.
(v9v): Likewise.
(v9m): Likewise.
(sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
2016-06-17 17:12:48 +08:00
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| MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B \
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| MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M)
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2013-08-06 00:11:07 +08:00
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#define v7 (MASK_V7 | MASK_V8 | MASK_LEON | MASK_SPARCLET \
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bfd,opcodes: sparc: new opcode v9{c,d,e,v,m} architectures and bfd machine numbers.
This patch adds support for the opcode architectures
SPARC_OPCODE_ARCH_V9{C,D,E,V,M} and its associated BFD machine numbers
bfd_mach_sparc_v9{c,d,e,v,m} and bfd_mach_sparc_v8plus{c,d,e,v,m}.
Note that for arches up to v9b (UltraSPARC III), the detection of the
BFD machine type was based on the bits in the e_machine field of the ELF
header. However, there are no more available bits in that field, so
this patch takes the approach of using the hardware capabilities stored
in the object attributes HWCAPS/HWCAPS2 in order to characterize the
machine the object was built for.
bfd/ChangeLog:
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* archures.c (bfd_mach_sparc_v8plusc): Define.
(bfd_mach_sparc_v9c): Likewise.
(bfd_mach_sparc_v8plusd): Likewise.
(bfd_mach_sparc_v9d): Likewise.
(bfd_mach_sparc_v8pluse): Likewise.
(bfd_mach_sparc_v9e): Likewise.
(bfd_mach_sparc_v8plusv): Likewise
(bfd_mach_sparc_v9v): Likewise.
(bfd_mach_sparc_v8plusm): Likewise.
(bfd_mach_sparc_v9m): Likewise.
(bfd_mach_sparc_v9_p): Adapt to v8plusm and v9m.
(bfd_mach_sparc_64bit_p): Likewise.
* bfd-in2.h: Regenerate.
* cpu-sparc.c (arch_info_struct): Add entries for
bfd_mach_sparc_v8plus{c,d,e,v,m} and bfd_mach_sparc_v9{c,d,e,v,m}.
* aoutx.h (machine_type): Handle bfd_mach_sparc_v8plus{c,d,e,v,m}
and bfd_mach_sparc_v9{c,d,e,v,m}.
* elf32-sparc.c (elf32_sparc_final_write_processing): Likewise.
* elfxx-sparc.c (_bfd_sparc_elf_object_p): Likewise.
include/ChangeLog:
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* opcode/sparc.h (enum sparc_opcode_arch_val): Add
SPARC_OPCODE_ARCH_V9C, SPARC_OPCODE_ARCH_V9D,
SPARC_OPCODE_ARCH_V9E, SPARC_OPCODE_ARCH_V9V and
SPARC_OPCODE_ARCH_V9M.
opcodes/ChangeLog:
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
(compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
bfd_mach_sparc_v9{c,d,e,v,m}.
* sparc-opc.c (MASK_V9C): Define.
(MASK_V9D): Likewise.
(MASK_V9E): Likewise.
(MASK_V9V): Likewise.
(MASK_V9M): Likewise.
(v6): Add MASK_V9{C,D,E,V,M}.
(v6notlet): Likewise.
(v7): Likewise.
(v8): Likewise.
(v9): Likewise.
(v9andleon): Likewise.
(v9a): Likewise.
(v9b): Likewise.
(v9c): Define.
(v9d): Likewise.
(v9e): Likewise.
(v9v): Likewise.
(v9m): Likewise.
(sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
2016-06-17 17:12:48 +08:00
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| MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B \
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| MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M)
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1999-05-03 15:29:11 +08:00
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/* Although not all insns are implemented in hardware, sparclite is defined
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to be a superset of v8. Unimplemented insns trap and are then theoretically
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implemented in software.
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It's not clear that the same is true for sparclet, although the docs
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suggest it is. Rather than complicating things, the sparclet assembler
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recognizes all v8 insns. */
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2013-08-06 00:11:07 +08:00
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#define v8 (MASK_V8 | MASK_LEON | MASK_SPARCLET | MASK_SPARCLITE \
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bfd,opcodes: sparc: new opcode v9{c,d,e,v,m} architectures and bfd machine numbers.
This patch adds support for the opcode architectures
SPARC_OPCODE_ARCH_V9{C,D,E,V,M} and its associated BFD machine numbers
bfd_mach_sparc_v9{c,d,e,v,m} and bfd_mach_sparc_v8plus{c,d,e,v,m}.
Note that for arches up to v9b (UltraSPARC III), the detection of the
BFD machine type was based on the bits in the e_machine field of the ELF
header. However, there are no more available bits in that field, so
this patch takes the approach of using the hardware capabilities stored
in the object attributes HWCAPS/HWCAPS2 in order to characterize the
machine the object was built for.
bfd/ChangeLog:
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* archures.c (bfd_mach_sparc_v8plusc): Define.
(bfd_mach_sparc_v9c): Likewise.
(bfd_mach_sparc_v8plusd): Likewise.
(bfd_mach_sparc_v9d): Likewise.
(bfd_mach_sparc_v8pluse): Likewise.
(bfd_mach_sparc_v9e): Likewise.
(bfd_mach_sparc_v8plusv): Likewise
(bfd_mach_sparc_v9v): Likewise.
(bfd_mach_sparc_v8plusm): Likewise.
(bfd_mach_sparc_v9m): Likewise.
(bfd_mach_sparc_v9_p): Adapt to v8plusm and v9m.
(bfd_mach_sparc_64bit_p): Likewise.
* bfd-in2.h: Regenerate.
* cpu-sparc.c (arch_info_struct): Add entries for
bfd_mach_sparc_v8plus{c,d,e,v,m} and bfd_mach_sparc_v9{c,d,e,v,m}.
* aoutx.h (machine_type): Handle bfd_mach_sparc_v8plus{c,d,e,v,m}
and bfd_mach_sparc_v9{c,d,e,v,m}.
* elf32-sparc.c (elf32_sparc_final_write_processing): Likewise.
* elfxx-sparc.c (_bfd_sparc_elf_object_p): Likewise.
include/ChangeLog:
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* opcode/sparc.h (enum sparc_opcode_arch_val): Add
SPARC_OPCODE_ARCH_V9C, SPARC_OPCODE_ARCH_V9D,
SPARC_OPCODE_ARCH_V9E, SPARC_OPCODE_ARCH_V9V and
SPARC_OPCODE_ARCH_V9M.
opcodes/ChangeLog:
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
(compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
bfd_mach_sparc_v9{c,d,e,v,m}.
* sparc-opc.c (MASK_V9C): Define.
(MASK_V9D): Likewise.
(MASK_V9E): Likewise.
(MASK_V9V): Likewise.
(MASK_V9M): Likewise.
(v6): Add MASK_V9{C,D,E,V,M}.
(v6notlet): Likewise.
(v7): Likewise.
(v8): Likewise.
(v9): Likewise.
(v9andleon): Likewise.
(v9a): Likewise.
(v9b): Likewise.
(v9c): Define.
(v9d): Likewise.
(v9e): Likewise.
(v9v): Likewise.
(v9m): Likewise.
(sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
2016-06-17 17:12:48 +08:00
|
|
|
|
| MASK_V9 | MASK_V9A | MASK_V9B \
|
|
|
|
|
| MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M)
|
1999-05-03 15:29:11 +08:00
|
|
|
|
#define sparclet (MASK_SPARCLET)
|
2013-08-06 00:11:07 +08:00
|
|
|
|
/* sparclet insns supported by leon. */
|
|
|
|
|
#define letandleon (MASK_SPARCLET | MASK_LEON)
|
1999-05-03 15:29:11 +08:00
|
|
|
|
#define sparclite (MASK_SPARCLITE)
|
bfd,opcodes: sparc: new opcode v9{c,d,e,v,m} architectures and bfd machine numbers.
This patch adds support for the opcode architectures
SPARC_OPCODE_ARCH_V9{C,D,E,V,M} and its associated BFD machine numbers
bfd_mach_sparc_v9{c,d,e,v,m} and bfd_mach_sparc_v8plus{c,d,e,v,m}.
Note that for arches up to v9b (UltraSPARC III), the detection of the
BFD machine type was based on the bits in the e_machine field of the ELF
header. However, there are no more available bits in that field, so
this patch takes the approach of using the hardware capabilities stored
in the object attributes HWCAPS/HWCAPS2 in order to characterize the
machine the object was built for.
bfd/ChangeLog:
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* archures.c (bfd_mach_sparc_v8plusc): Define.
(bfd_mach_sparc_v9c): Likewise.
(bfd_mach_sparc_v8plusd): Likewise.
(bfd_mach_sparc_v9d): Likewise.
(bfd_mach_sparc_v8pluse): Likewise.
(bfd_mach_sparc_v9e): Likewise.
(bfd_mach_sparc_v8plusv): Likewise
(bfd_mach_sparc_v9v): Likewise.
(bfd_mach_sparc_v8plusm): Likewise.
(bfd_mach_sparc_v9m): Likewise.
(bfd_mach_sparc_v9_p): Adapt to v8plusm and v9m.
(bfd_mach_sparc_64bit_p): Likewise.
* bfd-in2.h: Regenerate.
* cpu-sparc.c (arch_info_struct): Add entries for
bfd_mach_sparc_v8plus{c,d,e,v,m} and bfd_mach_sparc_v9{c,d,e,v,m}.
* aoutx.h (machine_type): Handle bfd_mach_sparc_v8plus{c,d,e,v,m}
and bfd_mach_sparc_v9{c,d,e,v,m}.
* elf32-sparc.c (elf32_sparc_final_write_processing): Likewise.
* elfxx-sparc.c (_bfd_sparc_elf_object_p): Likewise.
include/ChangeLog:
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* opcode/sparc.h (enum sparc_opcode_arch_val): Add
SPARC_OPCODE_ARCH_V9C, SPARC_OPCODE_ARCH_V9D,
SPARC_OPCODE_ARCH_V9E, SPARC_OPCODE_ARCH_V9V and
SPARC_OPCODE_ARCH_V9M.
opcodes/ChangeLog:
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
(compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
bfd_mach_sparc_v9{c,d,e,v,m}.
* sparc-opc.c (MASK_V9C): Define.
(MASK_V9D): Likewise.
(MASK_V9E): Likewise.
(MASK_V9V): Likewise.
(MASK_V9M): Likewise.
(v6): Add MASK_V9{C,D,E,V,M}.
(v6notlet): Likewise.
(v7): Likewise.
(v8): Likewise.
(v9): Likewise.
(v9andleon): Likewise.
(v9a): Likewise.
(v9b): Likewise.
(v9c): Define.
(v9d): Likewise.
(v9e): Likewise.
(v9v): Likewise.
(v9m): Likewise.
(sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
2016-06-17 17:12:48 +08:00
|
|
|
|
#define v9 (MASK_V9 | MASK_V9A | MASK_V9B \
|
|
|
|
|
| MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M)
|
2013-08-06 01:04:08 +08:00
|
|
|
|
/* v9 insns supported by leon. */
|
bfd,opcodes: sparc: new opcode v9{c,d,e,v,m} architectures and bfd machine numbers.
This patch adds support for the opcode architectures
SPARC_OPCODE_ARCH_V9{C,D,E,V,M} and its associated BFD machine numbers
bfd_mach_sparc_v9{c,d,e,v,m} and bfd_mach_sparc_v8plus{c,d,e,v,m}.
Note that for arches up to v9b (UltraSPARC III), the detection of the
BFD machine type was based on the bits in the e_machine field of the ELF
header. However, there are no more available bits in that field, so
this patch takes the approach of using the hardware capabilities stored
in the object attributes HWCAPS/HWCAPS2 in order to characterize the
machine the object was built for.
bfd/ChangeLog:
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* archures.c (bfd_mach_sparc_v8plusc): Define.
(bfd_mach_sparc_v9c): Likewise.
(bfd_mach_sparc_v8plusd): Likewise.
(bfd_mach_sparc_v9d): Likewise.
(bfd_mach_sparc_v8pluse): Likewise.
(bfd_mach_sparc_v9e): Likewise.
(bfd_mach_sparc_v8plusv): Likewise
(bfd_mach_sparc_v9v): Likewise.
(bfd_mach_sparc_v8plusm): Likewise.
(bfd_mach_sparc_v9m): Likewise.
(bfd_mach_sparc_v9_p): Adapt to v8plusm and v9m.
(bfd_mach_sparc_64bit_p): Likewise.
* bfd-in2.h: Regenerate.
* cpu-sparc.c (arch_info_struct): Add entries for
bfd_mach_sparc_v8plus{c,d,e,v,m} and bfd_mach_sparc_v9{c,d,e,v,m}.
* aoutx.h (machine_type): Handle bfd_mach_sparc_v8plus{c,d,e,v,m}
and bfd_mach_sparc_v9{c,d,e,v,m}.
* elf32-sparc.c (elf32_sparc_final_write_processing): Likewise.
* elfxx-sparc.c (_bfd_sparc_elf_object_p): Likewise.
include/ChangeLog:
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* opcode/sparc.h (enum sparc_opcode_arch_val): Add
SPARC_OPCODE_ARCH_V9C, SPARC_OPCODE_ARCH_V9D,
SPARC_OPCODE_ARCH_V9E, SPARC_OPCODE_ARCH_V9V and
SPARC_OPCODE_ARCH_V9M.
opcodes/ChangeLog:
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
(compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
bfd_mach_sparc_v9{c,d,e,v,m}.
* sparc-opc.c (MASK_V9C): Define.
(MASK_V9D): Likewise.
(MASK_V9E): Likewise.
(MASK_V9V): Likewise.
(MASK_V9M): Likewise.
(v6): Add MASK_V9{C,D,E,V,M}.
(v6notlet): Likewise.
(v7): Likewise.
(v8): Likewise.
(v9): Likewise.
(v9andleon): Likewise.
(v9a): Likewise.
(v9b): Likewise.
(v9c): Define.
(v9d): Likewise.
(v9e): Likewise.
(v9v): Likewise.
(v9m): Likewise.
(sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
2016-06-17 17:12:48 +08:00
|
|
|
|
#define v9andleon (MASK_V9 | MASK_V9A | MASK_V9B \
|
|
|
|
|
| MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M \
|
|
|
|
|
| MASK_LEON)
|
|
|
|
|
#define v9a (MASK_V9A | MASK_V9B \
|
|
|
|
|
| MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M)
|
|
|
|
|
#define v9b (MASK_V9B \
|
|
|
|
|
| MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M)
|
|
|
|
|
#define v9c (MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M)
|
|
|
|
|
#define v9d (MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M)
|
|
|
|
|
#define v9e (MASK_V9E | MASK_V9V | MASK_V9M)
|
|
|
|
|
#define v9v (MASK_V9V | MASK_V9M)
|
|
|
|
|
#define v9m (MASK_V9M)
|
|
|
|
|
|
2005-07-01 19:16:33 +08:00
|
|
|
|
/* v6 insns not supported by v9. */
|
2013-08-06 00:11:07 +08:00
|
|
|
|
#define v6notv9 (MASK_V6 | MASK_V7 | MASK_V8 | MASK_LEON \
|
1999-05-03 15:29:11 +08:00
|
|
|
|
| MASK_SPARCLET | MASK_SPARCLITE)
|
|
|
|
|
/* v9a instructions which would appear to be aliases to v9's impdep's
|
2005-07-01 19:16:33 +08:00
|
|
|
|
otherwise. */
|
1999-05-03 15:29:11 +08:00
|
|
|
|
#define v9notv9a (MASK_V9)
|
|
|
|
|
|
gas,opcodes: fix hardware capabilities bumping in the sparc assembler.
When the assembler finds an instruction which is part of a higher
opcode architecture it bumps the current opcode architecture. For
example:
$ echo "mwait" | as -bump
{standard input}: Assembler messages:
{standard input}:1: Warning: architecture bumped from "v6" to "v9m" on "mwait"
However, when two instructions pertaining to the same opcode
architecture but associated to different SPARC hardware capabilities
are found in the input stream, and no GAS architecture is specified in
the command line, the assembler bangs:
$ echo "mwait; wr %g0,%g1,%mcdper" | as -bump
{standard input}: Assembler messages:
{standard input}:1: Warning: architecture bumped from "v6" to "v9m" on "mwait"
{standard input}:1: Error: Hardware capability "sparc5" not enabled for "wr".
... and it should'nt, as WRMCDPER pertains to the same architecture
level than MWAIT.
This patch fixes this by extending the definition of sparc opcode
architectures to contain a set of hardware capabilities and making the
assembler to take these capabilities into account when updating the
set of allowed hwcaps when an architecture bump is triggered by some
instruction.
This way, hwcaps associated to architecture levels are maintained in
opcodes, while the assembler keeps the flexibiity of defining GAS
architectures including additional hwcaps (like -Asparcfmaf or the
v8plus* variants).
A test covering this failure case is included.
gas/ChangeLog:
2016-11-22 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-sparc.c: Move HWS_* and HWS2_* definitions to
opcodes/sparc-opc.c.
(sparc_arch): Clarify the new role of the hwcap_allowed and
hwcap2_allowed fields.
(sparc_arch_table): Remove HWS_* and HWS2_* instances from
hwcap_allowed and hwcap2_allowed respectively.
(md_parse_option): Include the opcode arch hwcaps when processing
-A.
(sparc_ip): Use the current opcode arch hwcaps to update
hwcap_allowed, as well of the hwcaps of the instruction triggering
the bump.
* testsuite/gas/sparc/hwcaps-bump.s: New file.
* testsuite/gas/sparc/hwcaps-bump.l: Likewise.
* testsuite/gas/sparc/sparc.exp (gas_64_check): Run tests in
hwcaps-bump.
include/ChangeLog:
2016-11-22 Jose E. Marchesi <jose.marchesi@oracle.com>
* opcode/sparc.h (sparc_opcode_arch): New fields hwcaps and
hwcaps2.
opcodes/ChangeLog:
2016-11-22 Jose E. Marchesi <jose.marchesi@oracle.com>
* sparc-opc.c (HWS_V8): Definition moved from
gas/config/tc-sparc.c.
(HWS_V9): Likewise.
(HWS_VA): Likewise.
(HWS_VB): Likewise.
(HWS_VC): Likewise.
(HWS_VD): Likewise.
(HWS_VE): Likewise.
(HWS_VV): Likewise.
(HWS_VM): Likewise.
(HWS2_VM): Likewise.
(sparc_opcode_archs): Initialize hwcaps and hwcaps2 fields of
existing entries.
2016-11-22 20:40:37 +08:00
|
|
|
|
/* Hardware capability sets, used to keep sparc_opcode_archs easy to
|
|
|
|
|
read. */
|
|
|
|
|
#define HWS_V8 HWCAP_MUL32 | HWCAP_DIV32 | HWCAP_FSMULD
|
|
|
|
|
#define HWS_V9 HWS_V8 | HWCAP_POPC
|
|
|
|
|
#define HWS_VA HWS_V9 | HWCAP_VIS
|
|
|
|
|
#define HWS_VB HWS_VA | HWCAP_VIS2
|
|
|
|
|
#define HWS_VC HWS_VB | HWCAP_ASI_BLK_INIT
|
|
|
|
|
#define HWS_VD HWS_VC | HWCAP_FMAF | HWCAP_VIS3 | HWCAP_HPC
|
|
|
|
|
#define HWS_VE HWS_VD \
|
|
|
|
|
| HWCAP_AES | HWCAP_DES | HWCAP_KASUMI | HWCAP_CAMELLIA \
|
|
|
|
|
| HWCAP_MD5 | HWCAP_SHA1 | HWCAP_SHA256 |HWCAP_SHA512 | HWCAP_MPMUL \
|
|
|
|
|
| HWCAP_MONT | HWCAP_CRC32C | HWCAP_CBCOND | HWCAP_PAUSE
|
|
|
|
|
#define HWS_VV HWS_VE | HWCAP_FJFMAU | HWCAP_IMA
|
|
|
|
|
#define HWS_VM HWS_VV
|
|
|
|
|
|
|
|
|
|
#define HWS2_VM \
|
|
|
|
|
HWCAP2_VIS3B | HWCAP2_ADP | HWCAP2_SPARC5 | HWCAP2_MWAIT \
|
|
|
|
|
| HWCAP2_XMPMUL | HWCAP2_XMONT
|
|
|
|
|
|
1999-05-03 15:29:11 +08:00
|
|
|
|
/* Table of opcode architectures.
|
|
|
|
|
The order is defined in opcode/sparc.h. */
|
|
|
|
|
|
2005-07-01 19:16:33 +08:00
|
|
|
|
const struct sparc_opcode_arch sparc_opcode_archs[] =
|
|
|
|
|
{
|
gas,opcodes: fix hardware capabilities bumping in the sparc assembler.
When the assembler finds an instruction which is part of a higher
opcode architecture it bumps the current opcode architecture. For
example:
$ echo "mwait" | as -bump
{standard input}: Assembler messages:
{standard input}:1: Warning: architecture bumped from "v6" to "v9m" on "mwait"
However, when two instructions pertaining to the same opcode
architecture but associated to different SPARC hardware capabilities
are found in the input stream, and no GAS architecture is specified in
the command line, the assembler bangs:
$ echo "mwait; wr %g0,%g1,%mcdper" | as -bump
{standard input}: Assembler messages:
{standard input}:1: Warning: architecture bumped from "v6" to "v9m" on "mwait"
{standard input}:1: Error: Hardware capability "sparc5" not enabled for "wr".
... and it should'nt, as WRMCDPER pertains to the same architecture
level than MWAIT.
This patch fixes this by extending the definition of sparc opcode
architectures to contain a set of hardware capabilities and making the
assembler to take these capabilities into account when updating the
set of allowed hwcaps when an architecture bump is triggered by some
instruction.
This way, hwcaps associated to architecture levels are maintained in
opcodes, while the assembler keeps the flexibiity of defining GAS
architectures including additional hwcaps (like -Asparcfmaf or the
v8plus* variants).
A test covering this failure case is included.
gas/ChangeLog:
2016-11-22 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-sparc.c: Move HWS_* and HWS2_* definitions to
opcodes/sparc-opc.c.
(sparc_arch): Clarify the new role of the hwcap_allowed and
hwcap2_allowed fields.
(sparc_arch_table): Remove HWS_* and HWS2_* instances from
hwcap_allowed and hwcap2_allowed respectively.
(md_parse_option): Include the opcode arch hwcaps when processing
-A.
(sparc_ip): Use the current opcode arch hwcaps to update
hwcap_allowed, as well of the hwcaps of the instruction triggering
the bump.
* testsuite/gas/sparc/hwcaps-bump.s: New file.
* testsuite/gas/sparc/hwcaps-bump.l: Likewise.
* testsuite/gas/sparc/sparc.exp (gas_64_check): Run tests in
hwcaps-bump.
include/ChangeLog:
2016-11-22 Jose E. Marchesi <jose.marchesi@oracle.com>
* opcode/sparc.h (sparc_opcode_arch): New fields hwcaps and
hwcaps2.
opcodes/ChangeLog:
2016-11-22 Jose E. Marchesi <jose.marchesi@oracle.com>
* sparc-opc.c (HWS_V8): Definition moved from
gas/config/tc-sparc.c.
(HWS_V9): Likewise.
(HWS_VA): Likewise.
(HWS_VB): Likewise.
(HWS_VC): Likewise.
(HWS_VD): Likewise.
(HWS_VE): Likewise.
(HWS_VV): Likewise.
(HWS_VM): Likewise.
(HWS2_VM): Likewise.
(sparc_opcode_archs): Initialize hwcaps and hwcaps2 fields of
existing entries.
2016-11-22 20:40:37 +08:00
|
|
|
|
{ "v6", MASK_V6, 0, 0 },
|
|
|
|
|
{ "v7", MASK_V6 | MASK_V7, 0, 0 },
|
|
|
|
|
{ "v8", MASK_V6 | MASK_V7 | MASK_V8, HWS_V8, 0 },
|
|
|
|
|
{ "leon", MASK_V6 | MASK_V7 | MASK_V8 | MASK_LEON, HWS_V8, 0 },
|
|
|
|
|
{ "sparclet", MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLET, HWS_V8, 0 },
|
|
|
|
|
{ "sparclite", MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLITE, HWS_V8, 0 },
|
1999-05-03 15:29:11 +08:00
|
|
|
|
/* ??? Don't some v8 priviledged insns conflict with v9? */
|
gas,opcodes: fix hardware capabilities bumping in the sparc assembler.
When the assembler finds an instruction which is part of a higher
opcode architecture it bumps the current opcode architecture. For
example:
$ echo "mwait" | as -bump
{standard input}: Assembler messages:
{standard input}:1: Warning: architecture bumped from "v6" to "v9m" on "mwait"
However, when two instructions pertaining to the same opcode
architecture but associated to different SPARC hardware capabilities
are found in the input stream, and no GAS architecture is specified in
the command line, the assembler bangs:
$ echo "mwait; wr %g0,%g1,%mcdper" | as -bump
{standard input}: Assembler messages:
{standard input}:1: Warning: architecture bumped from "v6" to "v9m" on "mwait"
{standard input}:1: Error: Hardware capability "sparc5" not enabled for "wr".
... and it should'nt, as WRMCDPER pertains to the same architecture
level than MWAIT.
This patch fixes this by extending the definition of sparc opcode
architectures to contain a set of hardware capabilities and making the
assembler to take these capabilities into account when updating the
set of allowed hwcaps when an architecture bump is triggered by some
instruction.
This way, hwcaps associated to architecture levels are maintained in
opcodes, while the assembler keeps the flexibiity of defining GAS
architectures including additional hwcaps (like -Asparcfmaf or the
v8plus* variants).
A test covering this failure case is included.
gas/ChangeLog:
2016-11-22 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-sparc.c: Move HWS_* and HWS2_* definitions to
opcodes/sparc-opc.c.
(sparc_arch): Clarify the new role of the hwcap_allowed and
hwcap2_allowed fields.
(sparc_arch_table): Remove HWS_* and HWS2_* instances from
hwcap_allowed and hwcap2_allowed respectively.
(md_parse_option): Include the opcode arch hwcaps when processing
-A.
(sparc_ip): Use the current opcode arch hwcaps to update
hwcap_allowed, as well of the hwcaps of the instruction triggering
the bump.
* testsuite/gas/sparc/hwcaps-bump.s: New file.
* testsuite/gas/sparc/hwcaps-bump.l: Likewise.
* testsuite/gas/sparc/sparc.exp (gas_64_check): Run tests in
hwcaps-bump.
include/ChangeLog:
2016-11-22 Jose E. Marchesi <jose.marchesi@oracle.com>
* opcode/sparc.h (sparc_opcode_arch): New fields hwcaps and
hwcaps2.
opcodes/ChangeLog:
2016-11-22 Jose E. Marchesi <jose.marchesi@oracle.com>
* sparc-opc.c (HWS_V8): Definition moved from
gas/config/tc-sparc.c.
(HWS_V9): Likewise.
(HWS_VA): Likewise.
(HWS_VB): Likewise.
(HWS_VC): Likewise.
(HWS_VD): Likewise.
(HWS_VE): Likewise.
(HWS_VV): Likewise.
(HWS_VM): Likewise.
(HWS2_VM): Likewise.
(sparc_opcode_archs): Initialize hwcaps and hwcaps2 fields of
existing entries.
2016-11-22 20:40:37 +08:00
|
|
|
|
{ "v9", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9, HWS_V9, 0 },
|
1999-05-03 15:29:11 +08:00
|
|
|
|
/* v9 with ultrasparc additions */
|
gas,opcodes: fix hardware capabilities bumping in the sparc assembler.
When the assembler finds an instruction which is part of a higher
opcode architecture it bumps the current opcode architecture. For
example:
$ echo "mwait" | as -bump
{standard input}: Assembler messages:
{standard input}:1: Warning: architecture bumped from "v6" to "v9m" on "mwait"
However, when two instructions pertaining to the same opcode
architecture but associated to different SPARC hardware capabilities
are found in the input stream, and no GAS architecture is specified in
the command line, the assembler bangs:
$ echo "mwait; wr %g0,%g1,%mcdper" | as -bump
{standard input}: Assembler messages:
{standard input}:1: Warning: architecture bumped from "v6" to "v9m" on "mwait"
{standard input}:1: Error: Hardware capability "sparc5" not enabled for "wr".
... and it should'nt, as WRMCDPER pertains to the same architecture
level than MWAIT.
This patch fixes this by extending the definition of sparc opcode
architectures to contain a set of hardware capabilities and making the
assembler to take these capabilities into account when updating the
set of allowed hwcaps when an architecture bump is triggered by some
instruction.
This way, hwcaps associated to architecture levels are maintained in
opcodes, while the assembler keeps the flexibiity of defining GAS
architectures including additional hwcaps (like -Asparcfmaf or the
v8plus* variants).
A test covering this failure case is included.
gas/ChangeLog:
2016-11-22 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-sparc.c: Move HWS_* and HWS2_* definitions to
opcodes/sparc-opc.c.
(sparc_arch): Clarify the new role of the hwcap_allowed and
hwcap2_allowed fields.
(sparc_arch_table): Remove HWS_* and HWS2_* instances from
hwcap_allowed and hwcap2_allowed respectively.
(md_parse_option): Include the opcode arch hwcaps when processing
-A.
(sparc_ip): Use the current opcode arch hwcaps to update
hwcap_allowed, as well of the hwcaps of the instruction triggering
the bump.
* testsuite/gas/sparc/hwcaps-bump.s: New file.
* testsuite/gas/sparc/hwcaps-bump.l: Likewise.
* testsuite/gas/sparc/sparc.exp (gas_64_check): Run tests in
hwcaps-bump.
include/ChangeLog:
2016-11-22 Jose E. Marchesi <jose.marchesi@oracle.com>
* opcode/sparc.h (sparc_opcode_arch): New fields hwcaps and
hwcaps2.
opcodes/ChangeLog:
2016-11-22 Jose E. Marchesi <jose.marchesi@oracle.com>
* sparc-opc.c (HWS_V8): Definition moved from
gas/config/tc-sparc.c.
(HWS_V9): Likewise.
(HWS_VA): Likewise.
(HWS_VB): Likewise.
(HWS_VC): Likewise.
(HWS_VD): Likewise.
(HWS_VE): Likewise.
(HWS_VV): Likewise.
(HWS_VM): Likewise.
(HWS2_VM): Likewise.
(sparc_opcode_archs): Initialize hwcaps and hwcaps2 fields of
existing entries.
2016-11-22 20:40:37 +08:00
|
|
|
|
{ "v9a", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A, HWS_VA, 0 },
|
2000-10-20 18:38:47 +08:00
|
|
|
|
/* v9 with cheetah additions */
|
gas,opcodes: fix hardware capabilities bumping in the sparc assembler.
When the assembler finds an instruction which is part of a higher
opcode architecture it bumps the current opcode architecture. For
example:
$ echo "mwait" | as -bump
{standard input}: Assembler messages:
{standard input}:1: Warning: architecture bumped from "v6" to "v9m" on "mwait"
However, when two instructions pertaining to the same opcode
architecture but associated to different SPARC hardware capabilities
are found in the input stream, and no GAS architecture is specified in
the command line, the assembler bangs:
$ echo "mwait; wr %g0,%g1,%mcdper" | as -bump
{standard input}: Assembler messages:
{standard input}:1: Warning: architecture bumped from "v6" to "v9m" on "mwait"
{standard input}:1: Error: Hardware capability "sparc5" not enabled for "wr".
... and it should'nt, as WRMCDPER pertains to the same architecture
level than MWAIT.
This patch fixes this by extending the definition of sparc opcode
architectures to contain a set of hardware capabilities and making the
assembler to take these capabilities into account when updating the
set of allowed hwcaps when an architecture bump is triggered by some
instruction.
This way, hwcaps associated to architecture levels are maintained in
opcodes, while the assembler keeps the flexibiity of defining GAS
architectures including additional hwcaps (like -Asparcfmaf or the
v8plus* variants).
A test covering this failure case is included.
gas/ChangeLog:
2016-11-22 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-sparc.c: Move HWS_* and HWS2_* definitions to
opcodes/sparc-opc.c.
(sparc_arch): Clarify the new role of the hwcap_allowed and
hwcap2_allowed fields.
(sparc_arch_table): Remove HWS_* and HWS2_* instances from
hwcap_allowed and hwcap2_allowed respectively.
(md_parse_option): Include the opcode arch hwcaps when processing
-A.
(sparc_ip): Use the current opcode arch hwcaps to update
hwcap_allowed, as well of the hwcaps of the instruction triggering
the bump.
* testsuite/gas/sparc/hwcaps-bump.s: New file.
* testsuite/gas/sparc/hwcaps-bump.l: Likewise.
* testsuite/gas/sparc/sparc.exp (gas_64_check): Run tests in
hwcaps-bump.
include/ChangeLog:
2016-11-22 Jose E. Marchesi <jose.marchesi@oracle.com>
* opcode/sparc.h (sparc_opcode_arch): New fields hwcaps and
hwcaps2.
opcodes/ChangeLog:
2016-11-22 Jose E. Marchesi <jose.marchesi@oracle.com>
* sparc-opc.c (HWS_V8): Definition moved from
gas/config/tc-sparc.c.
(HWS_V9): Likewise.
(HWS_VA): Likewise.
(HWS_VB): Likewise.
(HWS_VC): Likewise.
(HWS_VD): Likewise.
(HWS_VE): Likewise.
(HWS_VV): Likewise.
(HWS_VM): Likewise.
(HWS2_VM): Likewise.
(sparc_opcode_archs): Initialize hwcaps and hwcaps2 fields of
existing entries.
2016-11-22 20:40:37 +08:00
|
|
|
|
{ "v9b", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A | MASK_V9B, HWS_VB, 0 },
|
bfd,opcodes: sparc: new opcode v9{c,d,e,v,m} architectures and bfd machine numbers.
This patch adds support for the opcode architectures
SPARC_OPCODE_ARCH_V9{C,D,E,V,M} and its associated BFD machine numbers
bfd_mach_sparc_v9{c,d,e,v,m} and bfd_mach_sparc_v8plus{c,d,e,v,m}.
Note that for arches up to v9b (UltraSPARC III), the detection of the
BFD machine type was based on the bits in the e_machine field of the ELF
header. However, there are no more available bits in that field, so
this patch takes the approach of using the hardware capabilities stored
in the object attributes HWCAPS/HWCAPS2 in order to characterize the
machine the object was built for.
bfd/ChangeLog:
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* archures.c (bfd_mach_sparc_v8plusc): Define.
(bfd_mach_sparc_v9c): Likewise.
(bfd_mach_sparc_v8plusd): Likewise.
(bfd_mach_sparc_v9d): Likewise.
(bfd_mach_sparc_v8pluse): Likewise.
(bfd_mach_sparc_v9e): Likewise.
(bfd_mach_sparc_v8plusv): Likewise
(bfd_mach_sparc_v9v): Likewise.
(bfd_mach_sparc_v8plusm): Likewise.
(bfd_mach_sparc_v9m): Likewise.
(bfd_mach_sparc_v9_p): Adapt to v8plusm and v9m.
(bfd_mach_sparc_64bit_p): Likewise.
* bfd-in2.h: Regenerate.
* cpu-sparc.c (arch_info_struct): Add entries for
bfd_mach_sparc_v8plus{c,d,e,v,m} and bfd_mach_sparc_v9{c,d,e,v,m}.
* aoutx.h (machine_type): Handle bfd_mach_sparc_v8plus{c,d,e,v,m}
and bfd_mach_sparc_v9{c,d,e,v,m}.
* elf32-sparc.c (elf32_sparc_final_write_processing): Likewise.
* elfxx-sparc.c (_bfd_sparc_elf_object_p): Likewise.
include/ChangeLog:
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* opcode/sparc.h (enum sparc_opcode_arch_val): Add
SPARC_OPCODE_ARCH_V9C, SPARC_OPCODE_ARCH_V9D,
SPARC_OPCODE_ARCH_V9E, SPARC_OPCODE_ARCH_V9V and
SPARC_OPCODE_ARCH_V9M.
opcodes/ChangeLog:
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
(compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
bfd_mach_sparc_v9{c,d,e,v,m}.
* sparc-opc.c (MASK_V9C): Define.
(MASK_V9D): Likewise.
(MASK_V9E): Likewise.
(MASK_V9V): Likewise.
(MASK_V9M): Likewise.
(v6): Add MASK_V9{C,D,E,V,M}.
(v6notlet): Likewise.
(v7): Likewise.
(v8): Likewise.
(v9): Likewise.
(v9andleon): Likewise.
(v9a): Likewise.
(v9b): Likewise.
(v9c): Define.
(v9d): Likewise.
(v9e): Likewise.
(v9v): Likewise.
(v9m): Likewise.
(sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
2016-06-17 17:12:48 +08:00
|
|
|
|
/* v9 with UA2005 and T1 additions. */
|
|
|
|
|
{ "v9c", (MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A | MASK_V9B
|
gas,opcodes: fix hardware capabilities bumping in the sparc assembler.
When the assembler finds an instruction which is part of a higher
opcode architecture it bumps the current opcode architecture. For
example:
$ echo "mwait" | as -bump
{standard input}: Assembler messages:
{standard input}:1: Warning: architecture bumped from "v6" to "v9m" on "mwait"
However, when two instructions pertaining to the same opcode
architecture but associated to different SPARC hardware capabilities
are found in the input stream, and no GAS architecture is specified in
the command line, the assembler bangs:
$ echo "mwait; wr %g0,%g1,%mcdper" | as -bump
{standard input}: Assembler messages:
{standard input}:1: Warning: architecture bumped from "v6" to "v9m" on "mwait"
{standard input}:1: Error: Hardware capability "sparc5" not enabled for "wr".
... and it should'nt, as WRMCDPER pertains to the same architecture
level than MWAIT.
This patch fixes this by extending the definition of sparc opcode
architectures to contain a set of hardware capabilities and making the
assembler to take these capabilities into account when updating the
set of allowed hwcaps when an architecture bump is triggered by some
instruction.
This way, hwcaps associated to architecture levels are maintained in
opcodes, while the assembler keeps the flexibiity of defining GAS
architectures including additional hwcaps (like -Asparcfmaf or the
v8plus* variants).
A test covering this failure case is included.
gas/ChangeLog:
2016-11-22 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-sparc.c: Move HWS_* and HWS2_* definitions to
opcodes/sparc-opc.c.
(sparc_arch): Clarify the new role of the hwcap_allowed and
hwcap2_allowed fields.
(sparc_arch_table): Remove HWS_* and HWS2_* instances from
hwcap_allowed and hwcap2_allowed respectively.
(md_parse_option): Include the opcode arch hwcaps when processing
-A.
(sparc_ip): Use the current opcode arch hwcaps to update
hwcap_allowed, as well of the hwcaps of the instruction triggering
the bump.
* testsuite/gas/sparc/hwcaps-bump.s: New file.
* testsuite/gas/sparc/hwcaps-bump.l: Likewise.
* testsuite/gas/sparc/sparc.exp (gas_64_check): Run tests in
hwcaps-bump.
include/ChangeLog:
2016-11-22 Jose E. Marchesi <jose.marchesi@oracle.com>
* opcode/sparc.h (sparc_opcode_arch): New fields hwcaps and
hwcaps2.
opcodes/ChangeLog:
2016-11-22 Jose E. Marchesi <jose.marchesi@oracle.com>
* sparc-opc.c (HWS_V8): Definition moved from
gas/config/tc-sparc.c.
(HWS_V9): Likewise.
(HWS_VA): Likewise.
(HWS_VB): Likewise.
(HWS_VC): Likewise.
(HWS_VD): Likewise.
(HWS_VE): Likewise.
(HWS_VV): Likewise.
(HWS_VM): Likewise.
(HWS2_VM): Likewise.
(sparc_opcode_archs): Initialize hwcaps and hwcaps2 fields of
existing entries.
2016-11-22 20:40:37 +08:00
|
|
|
|
| MASK_V9C), HWS_VC, 0 },
|
bfd,opcodes: sparc: new opcode v9{c,d,e,v,m} architectures and bfd machine numbers.
This patch adds support for the opcode architectures
SPARC_OPCODE_ARCH_V9{C,D,E,V,M} and its associated BFD machine numbers
bfd_mach_sparc_v9{c,d,e,v,m} and bfd_mach_sparc_v8plus{c,d,e,v,m}.
Note that for arches up to v9b (UltraSPARC III), the detection of the
BFD machine type was based on the bits in the e_machine field of the ELF
header. However, there are no more available bits in that field, so
this patch takes the approach of using the hardware capabilities stored
in the object attributes HWCAPS/HWCAPS2 in order to characterize the
machine the object was built for.
bfd/ChangeLog:
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* archures.c (bfd_mach_sparc_v8plusc): Define.
(bfd_mach_sparc_v9c): Likewise.
(bfd_mach_sparc_v8plusd): Likewise.
(bfd_mach_sparc_v9d): Likewise.
(bfd_mach_sparc_v8pluse): Likewise.
(bfd_mach_sparc_v9e): Likewise.
(bfd_mach_sparc_v8plusv): Likewise
(bfd_mach_sparc_v9v): Likewise.
(bfd_mach_sparc_v8plusm): Likewise.
(bfd_mach_sparc_v9m): Likewise.
(bfd_mach_sparc_v9_p): Adapt to v8plusm and v9m.
(bfd_mach_sparc_64bit_p): Likewise.
* bfd-in2.h: Regenerate.
* cpu-sparc.c (arch_info_struct): Add entries for
bfd_mach_sparc_v8plus{c,d,e,v,m} and bfd_mach_sparc_v9{c,d,e,v,m}.
* aoutx.h (machine_type): Handle bfd_mach_sparc_v8plus{c,d,e,v,m}
and bfd_mach_sparc_v9{c,d,e,v,m}.
* elf32-sparc.c (elf32_sparc_final_write_processing): Likewise.
* elfxx-sparc.c (_bfd_sparc_elf_object_p): Likewise.
include/ChangeLog:
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* opcode/sparc.h (enum sparc_opcode_arch_val): Add
SPARC_OPCODE_ARCH_V9C, SPARC_OPCODE_ARCH_V9D,
SPARC_OPCODE_ARCH_V9E, SPARC_OPCODE_ARCH_V9V and
SPARC_OPCODE_ARCH_V9M.
opcodes/ChangeLog:
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
(compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
bfd_mach_sparc_v9{c,d,e,v,m}.
* sparc-opc.c (MASK_V9C): Define.
(MASK_V9D): Likewise.
(MASK_V9E): Likewise.
(MASK_V9V): Likewise.
(MASK_V9M): Likewise.
(v6): Add MASK_V9{C,D,E,V,M}.
(v6notlet): Likewise.
(v7): Likewise.
(v8): Likewise.
(v9): Likewise.
(v9andleon): Likewise.
(v9a): Likewise.
(v9b): Likewise.
(v9c): Define.
(v9d): Likewise.
(v9e): Likewise.
(v9v): Likewise.
(v9m): Likewise.
(sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
2016-06-17 17:12:48 +08:00
|
|
|
|
/* v9 with UA2007 and T3 additions. */
|
|
|
|
|
{ "v9d", (MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A | MASK_V9B
|
gas,opcodes: fix hardware capabilities bumping in the sparc assembler.
When the assembler finds an instruction which is part of a higher
opcode architecture it bumps the current opcode architecture. For
example:
$ echo "mwait" | as -bump
{standard input}: Assembler messages:
{standard input}:1: Warning: architecture bumped from "v6" to "v9m" on "mwait"
However, when two instructions pertaining to the same opcode
architecture but associated to different SPARC hardware capabilities
are found in the input stream, and no GAS architecture is specified in
the command line, the assembler bangs:
$ echo "mwait; wr %g0,%g1,%mcdper" | as -bump
{standard input}: Assembler messages:
{standard input}:1: Warning: architecture bumped from "v6" to "v9m" on "mwait"
{standard input}:1: Error: Hardware capability "sparc5" not enabled for "wr".
... and it should'nt, as WRMCDPER pertains to the same architecture
level than MWAIT.
This patch fixes this by extending the definition of sparc opcode
architectures to contain a set of hardware capabilities and making the
assembler to take these capabilities into account when updating the
set of allowed hwcaps when an architecture bump is triggered by some
instruction.
This way, hwcaps associated to architecture levels are maintained in
opcodes, while the assembler keeps the flexibiity of defining GAS
architectures including additional hwcaps (like -Asparcfmaf or the
v8plus* variants).
A test covering this failure case is included.
gas/ChangeLog:
2016-11-22 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-sparc.c: Move HWS_* and HWS2_* definitions to
opcodes/sparc-opc.c.
(sparc_arch): Clarify the new role of the hwcap_allowed and
hwcap2_allowed fields.
(sparc_arch_table): Remove HWS_* and HWS2_* instances from
hwcap_allowed and hwcap2_allowed respectively.
(md_parse_option): Include the opcode arch hwcaps when processing
-A.
(sparc_ip): Use the current opcode arch hwcaps to update
hwcap_allowed, as well of the hwcaps of the instruction triggering
the bump.
* testsuite/gas/sparc/hwcaps-bump.s: New file.
* testsuite/gas/sparc/hwcaps-bump.l: Likewise.
* testsuite/gas/sparc/sparc.exp (gas_64_check): Run tests in
hwcaps-bump.
include/ChangeLog:
2016-11-22 Jose E. Marchesi <jose.marchesi@oracle.com>
* opcode/sparc.h (sparc_opcode_arch): New fields hwcaps and
hwcaps2.
opcodes/ChangeLog:
2016-11-22 Jose E. Marchesi <jose.marchesi@oracle.com>
* sparc-opc.c (HWS_V8): Definition moved from
gas/config/tc-sparc.c.
(HWS_V9): Likewise.
(HWS_VA): Likewise.
(HWS_VB): Likewise.
(HWS_VC): Likewise.
(HWS_VD): Likewise.
(HWS_VE): Likewise.
(HWS_VV): Likewise.
(HWS_VM): Likewise.
(HWS2_VM): Likewise.
(sparc_opcode_archs): Initialize hwcaps and hwcaps2 fields of
existing entries.
2016-11-22 20:40:37 +08:00
|
|
|
|
| MASK_V9C | MASK_V9D), HWS_VD, 0 },
|
bfd,opcodes: sparc: new opcode v9{c,d,e,v,m} architectures and bfd machine numbers.
This patch adds support for the opcode architectures
SPARC_OPCODE_ARCH_V9{C,D,E,V,M} and its associated BFD machine numbers
bfd_mach_sparc_v9{c,d,e,v,m} and bfd_mach_sparc_v8plus{c,d,e,v,m}.
Note that for arches up to v9b (UltraSPARC III), the detection of the
BFD machine type was based on the bits in the e_machine field of the ELF
header. However, there are no more available bits in that field, so
this patch takes the approach of using the hardware capabilities stored
in the object attributes HWCAPS/HWCAPS2 in order to characterize the
machine the object was built for.
bfd/ChangeLog:
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* archures.c (bfd_mach_sparc_v8plusc): Define.
(bfd_mach_sparc_v9c): Likewise.
(bfd_mach_sparc_v8plusd): Likewise.
(bfd_mach_sparc_v9d): Likewise.
(bfd_mach_sparc_v8pluse): Likewise.
(bfd_mach_sparc_v9e): Likewise.
(bfd_mach_sparc_v8plusv): Likewise
(bfd_mach_sparc_v9v): Likewise.
(bfd_mach_sparc_v8plusm): Likewise.
(bfd_mach_sparc_v9m): Likewise.
(bfd_mach_sparc_v9_p): Adapt to v8plusm and v9m.
(bfd_mach_sparc_64bit_p): Likewise.
* bfd-in2.h: Regenerate.
* cpu-sparc.c (arch_info_struct): Add entries for
bfd_mach_sparc_v8plus{c,d,e,v,m} and bfd_mach_sparc_v9{c,d,e,v,m}.
* aoutx.h (machine_type): Handle bfd_mach_sparc_v8plus{c,d,e,v,m}
and bfd_mach_sparc_v9{c,d,e,v,m}.
* elf32-sparc.c (elf32_sparc_final_write_processing): Likewise.
* elfxx-sparc.c (_bfd_sparc_elf_object_p): Likewise.
include/ChangeLog:
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* opcode/sparc.h (enum sparc_opcode_arch_val): Add
SPARC_OPCODE_ARCH_V9C, SPARC_OPCODE_ARCH_V9D,
SPARC_OPCODE_ARCH_V9E, SPARC_OPCODE_ARCH_V9V and
SPARC_OPCODE_ARCH_V9M.
opcodes/ChangeLog:
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
(compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
bfd_mach_sparc_v9{c,d,e,v,m}.
* sparc-opc.c (MASK_V9C): Define.
(MASK_V9D): Likewise.
(MASK_V9E): Likewise.
(MASK_V9V): Likewise.
(MASK_V9M): Likewise.
(v6): Add MASK_V9{C,D,E,V,M}.
(v6notlet): Likewise.
(v7): Likewise.
(v8): Likewise.
(v9): Likewise.
(v9andleon): Likewise.
(v9a): Likewise.
(v9b): Likewise.
(v9c): Define.
(v9d): Likewise.
(v9e): Likewise.
(v9v): Likewise.
(v9m): Likewise.
(sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
2016-06-17 17:12:48 +08:00
|
|
|
|
/* v9 with OSA2011 and T4 additions modulus integer multiply-add. */
|
|
|
|
|
{ "v9e", (MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A | MASK_V9B
|
gas,opcodes: fix hardware capabilities bumping in the sparc assembler.
When the assembler finds an instruction which is part of a higher
opcode architecture it bumps the current opcode architecture. For
example:
$ echo "mwait" | as -bump
{standard input}: Assembler messages:
{standard input}:1: Warning: architecture bumped from "v6" to "v9m" on "mwait"
However, when two instructions pertaining to the same opcode
architecture but associated to different SPARC hardware capabilities
are found in the input stream, and no GAS architecture is specified in
the command line, the assembler bangs:
$ echo "mwait; wr %g0,%g1,%mcdper" | as -bump
{standard input}: Assembler messages:
{standard input}:1: Warning: architecture bumped from "v6" to "v9m" on "mwait"
{standard input}:1: Error: Hardware capability "sparc5" not enabled for "wr".
... and it should'nt, as WRMCDPER pertains to the same architecture
level than MWAIT.
This patch fixes this by extending the definition of sparc opcode
architectures to contain a set of hardware capabilities and making the
assembler to take these capabilities into account when updating the
set of allowed hwcaps when an architecture bump is triggered by some
instruction.
This way, hwcaps associated to architecture levels are maintained in
opcodes, while the assembler keeps the flexibiity of defining GAS
architectures including additional hwcaps (like -Asparcfmaf or the
v8plus* variants).
A test covering this failure case is included.
gas/ChangeLog:
2016-11-22 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-sparc.c: Move HWS_* and HWS2_* definitions to
opcodes/sparc-opc.c.
(sparc_arch): Clarify the new role of the hwcap_allowed and
hwcap2_allowed fields.
(sparc_arch_table): Remove HWS_* and HWS2_* instances from
hwcap_allowed and hwcap2_allowed respectively.
(md_parse_option): Include the opcode arch hwcaps when processing
-A.
(sparc_ip): Use the current opcode arch hwcaps to update
hwcap_allowed, as well of the hwcaps of the instruction triggering
the bump.
* testsuite/gas/sparc/hwcaps-bump.s: New file.
* testsuite/gas/sparc/hwcaps-bump.l: Likewise.
* testsuite/gas/sparc/sparc.exp (gas_64_check): Run tests in
hwcaps-bump.
include/ChangeLog:
2016-11-22 Jose E. Marchesi <jose.marchesi@oracle.com>
* opcode/sparc.h (sparc_opcode_arch): New fields hwcaps and
hwcaps2.
opcodes/ChangeLog:
2016-11-22 Jose E. Marchesi <jose.marchesi@oracle.com>
* sparc-opc.c (HWS_V8): Definition moved from
gas/config/tc-sparc.c.
(HWS_V9): Likewise.
(HWS_VA): Likewise.
(HWS_VB): Likewise.
(HWS_VC): Likewise.
(HWS_VD): Likewise.
(HWS_VE): Likewise.
(HWS_VV): Likewise.
(HWS_VM): Likewise.
(HWS2_VM): Likewise.
(sparc_opcode_archs): Initialize hwcaps and hwcaps2 fields of
existing entries.
2016-11-22 20:40:37 +08:00
|
|
|
|
| MASK_V9C | MASK_V9D | MASK_V9E), HWS_VE, 0 },
|
bfd,opcodes: sparc: new opcode v9{c,d,e,v,m} architectures and bfd machine numbers.
This patch adds support for the opcode architectures
SPARC_OPCODE_ARCH_V9{C,D,E,V,M} and its associated BFD machine numbers
bfd_mach_sparc_v9{c,d,e,v,m} and bfd_mach_sparc_v8plus{c,d,e,v,m}.
Note that for arches up to v9b (UltraSPARC III), the detection of the
BFD machine type was based on the bits in the e_machine field of the ELF
header. However, there are no more available bits in that field, so
this patch takes the approach of using the hardware capabilities stored
in the object attributes HWCAPS/HWCAPS2 in order to characterize the
machine the object was built for.
bfd/ChangeLog:
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* archures.c (bfd_mach_sparc_v8plusc): Define.
(bfd_mach_sparc_v9c): Likewise.
(bfd_mach_sparc_v8plusd): Likewise.
(bfd_mach_sparc_v9d): Likewise.
(bfd_mach_sparc_v8pluse): Likewise.
(bfd_mach_sparc_v9e): Likewise.
(bfd_mach_sparc_v8plusv): Likewise
(bfd_mach_sparc_v9v): Likewise.
(bfd_mach_sparc_v8plusm): Likewise.
(bfd_mach_sparc_v9m): Likewise.
(bfd_mach_sparc_v9_p): Adapt to v8plusm and v9m.
(bfd_mach_sparc_64bit_p): Likewise.
* bfd-in2.h: Regenerate.
* cpu-sparc.c (arch_info_struct): Add entries for
bfd_mach_sparc_v8plus{c,d,e,v,m} and bfd_mach_sparc_v9{c,d,e,v,m}.
* aoutx.h (machine_type): Handle bfd_mach_sparc_v8plus{c,d,e,v,m}
and bfd_mach_sparc_v9{c,d,e,v,m}.
* elf32-sparc.c (elf32_sparc_final_write_processing): Likewise.
* elfxx-sparc.c (_bfd_sparc_elf_object_p): Likewise.
include/ChangeLog:
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* opcode/sparc.h (enum sparc_opcode_arch_val): Add
SPARC_OPCODE_ARCH_V9C, SPARC_OPCODE_ARCH_V9D,
SPARC_OPCODE_ARCH_V9E, SPARC_OPCODE_ARCH_V9V and
SPARC_OPCODE_ARCH_V9M.
opcodes/ChangeLog:
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
(compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
bfd_mach_sparc_v9{c,d,e,v,m}.
* sparc-opc.c (MASK_V9C): Define.
(MASK_V9D): Likewise.
(MASK_V9E): Likewise.
(MASK_V9V): Likewise.
(MASK_V9M): Likewise.
(v6): Add MASK_V9{C,D,E,V,M}.
(v6notlet): Likewise.
(v7): Likewise.
(v8): Likewise.
(v9): Likewise.
(v9andleon): Likewise.
(v9a): Likewise.
(v9b): Likewise.
(v9c): Define.
(v9d): Likewise.
(v9e): Likewise.
(v9v): Likewise.
(v9m): Likewise.
(sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
2016-06-17 17:12:48 +08:00
|
|
|
|
/* V9 with OSA2011 and T4 additions, integer multiply and Fujitsu fp
|
|
|
|
|
multiply-add. */
|
|
|
|
|
{ "v9v", (MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A | MASK_V9B
|
gas,opcodes: fix hardware capabilities bumping in the sparc assembler.
When the assembler finds an instruction which is part of a higher
opcode architecture it bumps the current opcode architecture. For
example:
$ echo "mwait" | as -bump
{standard input}: Assembler messages:
{standard input}:1: Warning: architecture bumped from "v6" to "v9m" on "mwait"
However, when two instructions pertaining to the same opcode
architecture but associated to different SPARC hardware capabilities
are found in the input stream, and no GAS architecture is specified in
the command line, the assembler bangs:
$ echo "mwait; wr %g0,%g1,%mcdper" | as -bump
{standard input}: Assembler messages:
{standard input}:1: Warning: architecture bumped from "v6" to "v9m" on "mwait"
{standard input}:1: Error: Hardware capability "sparc5" not enabled for "wr".
... and it should'nt, as WRMCDPER pertains to the same architecture
level than MWAIT.
This patch fixes this by extending the definition of sparc opcode
architectures to contain a set of hardware capabilities and making the
assembler to take these capabilities into account when updating the
set of allowed hwcaps when an architecture bump is triggered by some
instruction.
This way, hwcaps associated to architecture levels are maintained in
opcodes, while the assembler keeps the flexibiity of defining GAS
architectures including additional hwcaps (like -Asparcfmaf or the
v8plus* variants).
A test covering this failure case is included.
gas/ChangeLog:
2016-11-22 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-sparc.c: Move HWS_* and HWS2_* definitions to
opcodes/sparc-opc.c.
(sparc_arch): Clarify the new role of the hwcap_allowed and
hwcap2_allowed fields.
(sparc_arch_table): Remove HWS_* and HWS2_* instances from
hwcap_allowed and hwcap2_allowed respectively.
(md_parse_option): Include the opcode arch hwcaps when processing
-A.
(sparc_ip): Use the current opcode arch hwcaps to update
hwcap_allowed, as well of the hwcaps of the instruction triggering
the bump.
* testsuite/gas/sparc/hwcaps-bump.s: New file.
* testsuite/gas/sparc/hwcaps-bump.l: Likewise.
* testsuite/gas/sparc/sparc.exp (gas_64_check): Run tests in
hwcaps-bump.
include/ChangeLog:
2016-11-22 Jose E. Marchesi <jose.marchesi@oracle.com>
* opcode/sparc.h (sparc_opcode_arch): New fields hwcaps and
hwcaps2.
opcodes/ChangeLog:
2016-11-22 Jose E. Marchesi <jose.marchesi@oracle.com>
* sparc-opc.c (HWS_V8): Definition moved from
gas/config/tc-sparc.c.
(HWS_V9): Likewise.
(HWS_VA): Likewise.
(HWS_VB): Likewise.
(HWS_VC): Likewise.
(HWS_VD): Likewise.
(HWS_VE): Likewise.
(HWS_VV): Likewise.
(HWS_VM): Likewise.
(HWS2_VM): Likewise.
(sparc_opcode_archs): Initialize hwcaps and hwcaps2 fields of
existing entries.
2016-11-22 20:40:37 +08:00
|
|
|
|
| MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V), HWS_VV, 0 },
|
bfd,opcodes: sparc: new opcode v9{c,d,e,v,m} architectures and bfd machine numbers.
This patch adds support for the opcode architectures
SPARC_OPCODE_ARCH_V9{C,D,E,V,M} and its associated BFD machine numbers
bfd_mach_sparc_v9{c,d,e,v,m} and bfd_mach_sparc_v8plus{c,d,e,v,m}.
Note that for arches up to v9b (UltraSPARC III), the detection of the
BFD machine type was based on the bits in the e_machine field of the ELF
header. However, there are no more available bits in that field, so
this patch takes the approach of using the hardware capabilities stored
in the object attributes HWCAPS/HWCAPS2 in order to characterize the
machine the object was built for.
bfd/ChangeLog:
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* archures.c (bfd_mach_sparc_v8plusc): Define.
(bfd_mach_sparc_v9c): Likewise.
(bfd_mach_sparc_v8plusd): Likewise.
(bfd_mach_sparc_v9d): Likewise.
(bfd_mach_sparc_v8pluse): Likewise.
(bfd_mach_sparc_v9e): Likewise.
(bfd_mach_sparc_v8plusv): Likewise
(bfd_mach_sparc_v9v): Likewise.
(bfd_mach_sparc_v8plusm): Likewise.
(bfd_mach_sparc_v9m): Likewise.
(bfd_mach_sparc_v9_p): Adapt to v8plusm and v9m.
(bfd_mach_sparc_64bit_p): Likewise.
* bfd-in2.h: Regenerate.
* cpu-sparc.c (arch_info_struct): Add entries for
bfd_mach_sparc_v8plus{c,d,e,v,m} and bfd_mach_sparc_v9{c,d,e,v,m}.
* aoutx.h (machine_type): Handle bfd_mach_sparc_v8plus{c,d,e,v,m}
and bfd_mach_sparc_v9{c,d,e,v,m}.
* elf32-sparc.c (elf32_sparc_final_write_processing): Likewise.
* elfxx-sparc.c (_bfd_sparc_elf_object_p): Likewise.
include/ChangeLog:
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* opcode/sparc.h (enum sparc_opcode_arch_val): Add
SPARC_OPCODE_ARCH_V9C, SPARC_OPCODE_ARCH_V9D,
SPARC_OPCODE_ARCH_V9E, SPARC_OPCODE_ARCH_V9V and
SPARC_OPCODE_ARCH_V9M.
opcodes/ChangeLog:
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
(compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
bfd_mach_sparc_v9{c,d,e,v,m}.
* sparc-opc.c (MASK_V9C): Define.
(MASK_V9D): Likewise.
(MASK_V9E): Likewise.
(MASK_V9V): Likewise.
(MASK_V9M): Likewise.
(v6): Add MASK_V9{C,D,E,V,M}.
(v6notlet): Likewise.
(v7): Likewise.
(v8): Likewise.
(v9): Likewise.
(v9andleon): Likewise.
(v9a): Likewise.
(v9b): Likewise.
(v9c): Define.
(v9d): Likewise.
(v9e): Likewise.
(v9v): Likewise.
(v9m): Likewise.
(sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
2016-06-17 17:12:48 +08:00
|
|
|
|
/* v9 with OSA2015 and M7 additions. */
|
|
|
|
|
{ "v9m", (MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A | MASK_V9B
|
gas,opcodes: fix hardware capabilities bumping in the sparc assembler.
When the assembler finds an instruction which is part of a higher
opcode architecture it bumps the current opcode architecture. For
example:
$ echo "mwait" | as -bump
{standard input}: Assembler messages:
{standard input}:1: Warning: architecture bumped from "v6" to "v9m" on "mwait"
However, when two instructions pertaining to the same opcode
architecture but associated to different SPARC hardware capabilities
are found in the input stream, and no GAS architecture is specified in
the command line, the assembler bangs:
$ echo "mwait; wr %g0,%g1,%mcdper" | as -bump
{standard input}: Assembler messages:
{standard input}:1: Warning: architecture bumped from "v6" to "v9m" on "mwait"
{standard input}:1: Error: Hardware capability "sparc5" not enabled for "wr".
... and it should'nt, as WRMCDPER pertains to the same architecture
level than MWAIT.
This patch fixes this by extending the definition of sparc opcode
architectures to contain a set of hardware capabilities and making the
assembler to take these capabilities into account when updating the
set of allowed hwcaps when an architecture bump is triggered by some
instruction.
This way, hwcaps associated to architecture levels are maintained in
opcodes, while the assembler keeps the flexibiity of defining GAS
architectures including additional hwcaps (like -Asparcfmaf or the
v8plus* variants).
A test covering this failure case is included.
gas/ChangeLog:
2016-11-22 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-sparc.c: Move HWS_* and HWS2_* definitions to
opcodes/sparc-opc.c.
(sparc_arch): Clarify the new role of the hwcap_allowed and
hwcap2_allowed fields.
(sparc_arch_table): Remove HWS_* and HWS2_* instances from
hwcap_allowed and hwcap2_allowed respectively.
(md_parse_option): Include the opcode arch hwcaps when processing
-A.
(sparc_ip): Use the current opcode arch hwcaps to update
hwcap_allowed, as well of the hwcaps of the instruction triggering
the bump.
* testsuite/gas/sparc/hwcaps-bump.s: New file.
* testsuite/gas/sparc/hwcaps-bump.l: Likewise.
* testsuite/gas/sparc/sparc.exp (gas_64_check): Run tests in
hwcaps-bump.
include/ChangeLog:
2016-11-22 Jose E. Marchesi <jose.marchesi@oracle.com>
* opcode/sparc.h (sparc_opcode_arch): New fields hwcaps and
hwcaps2.
opcodes/ChangeLog:
2016-11-22 Jose E. Marchesi <jose.marchesi@oracle.com>
* sparc-opc.c (HWS_V8): Definition moved from
gas/config/tc-sparc.c.
(HWS_V9): Likewise.
(HWS_VA): Likewise.
(HWS_VB): Likewise.
(HWS_VC): Likewise.
(HWS_VD): Likewise.
(HWS_VE): Likewise.
(HWS_VV): Likewise.
(HWS_VM): Likewise.
(HWS2_VM): Likewise.
(sparc_opcode_archs): Initialize hwcaps and hwcaps2 fields of
existing entries.
2016-11-22 20:40:37 +08:00
|
|
|
|
| MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M), HWS_VM, HWS2_VM },
|
|
|
|
|
{ NULL, 0, 0, 0 }
|
1999-05-03 15:29:11 +08:00
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
/* Given NAME, return it's architecture entry. */
|
|
|
|
|
|
|
|
|
|
enum sparc_opcode_arch_val
|
2005-07-01 19:16:33 +08:00
|
|
|
|
sparc_opcode_lookup_arch (const char *name)
|
1999-05-03 15:29:11 +08:00
|
|
|
|
{
|
|
|
|
|
const struct sparc_opcode_arch *p;
|
|
|
|
|
|
|
|
|
|
for (p = &sparc_opcode_archs[0]; p->name; ++p)
|
2005-07-01 19:16:33 +08:00
|
|
|
|
if (strcmp (name, p->name) == 0)
|
|
|
|
|
return (enum sparc_opcode_arch_val) (p - &sparc_opcode_archs[0]);
|
1999-05-03 15:29:11 +08:00
|
|
|
|
|
|
|
|
|
return SPARC_OPCODE_ARCH_BAD;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Branch condition field. */
|
2005-07-01 19:16:33 +08:00
|
|
|
|
#define COND(x) (((x) & 0xf) << 25)
|
1999-05-03 15:29:11 +08:00
|
|
|
|
|
2012-04-28 02:03:13 +08:00
|
|
|
|
/* Compare And Branch condition field. */
|
|
|
|
|
#define CBCOND(x) (((x) & 0x1f) << 25)
|
|
|
|
|
|
1999-05-03 15:29:11 +08:00
|
|
|
|
/* v9: Move (MOVcc and FMOVcc) condition field. */
|
2005-07-01 19:16:33 +08:00
|
|
|
|
#define MCOND(x,i_or_f) ((((i_or_f) & 1) << 18) | (((x) >> 11) & (0xf << 14))) /* v9 */
|
1999-05-03 15:29:11 +08:00
|
|
|
|
|
|
|
|
|
/* v9: Move register (MOVRcc and FMOVRcc) condition field. */
|
2005-07-01 19:16:33 +08:00
|
|
|
|
#define RCOND(x) (((x) & 0x7) << 10) /* v9 */
|
|
|
|
|
|
|
|
|
|
#define CONDA (COND (0x8))
|
|
|
|
|
#define CONDCC (COND (0xd))
|
|
|
|
|
#define CONDCS (COND (0x5))
|
|
|
|
|
#define CONDE (COND (0x1))
|
|
|
|
|
#define CONDG (COND (0xa))
|
|
|
|
|
#define CONDGE (COND (0xb))
|
|
|
|
|
#define CONDGU (COND (0xc))
|
|
|
|
|
#define CONDL (COND (0x3))
|
|
|
|
|
#define CONDLE (COND (0x2))
|
|
|
|
|
#define CONDLEU (COND (0x4))
|
|
|
|
|
#define CONDN (COND (0x0))
|
|
|
|
|
#define CONDNE (COND (0x9))
|
|
|
|
|
#define CONDNEG (COND (0x6))
|
|
|
|
|
#define CONDPOS (COND (0xe))
|
|
|
|
|
#define CONDVC (COND (0xf))
|
|
|
|
|
#define CONDVS (COND (0x7))
|
1999-05-03 15:29:11 +08:00
|
|
|
|
|
|
|
|
|
#define CONDNZ CONDNE
|
|
|
|
|
#define CONDZ CONDE
|
|
|
|
|
#define CONDGEU CONDCC
|
|
|
|
|
#define CONDLU CONDCS
|
|
|
|
|
|
2005-07-01 19:16:33 +08:00
|
|
|
|
#define FCONDA (COND (0x8))
|
|
|
|
|
#define FCONDE (COND (0x9))
|
|
|
|
|
#define FCONDG (COND (0x6))
|
|
|
|
|
#define FCONDGE (COND (0xb))
|
|
|
|
|
#define FCONDL (COND (0x4))
|
|
|
|
|
#define FCONDLE (COND (0xd))
|
|
|
|
|
#define FCONDLG (COND (0x2))
|
|
|
|
|
#define FCONDN (COND (0x0))
|
|
|
|
|
#define FCONDNE (COND (0x1))
|
|
|
|
|
#define FCONDO (COND (0xf))
|
|
|
|
|
#define FCONDU (COND (0x7))
|
|
|
|
|
#define FCONDUE (COND (0xa))
|
|
|
|
|
#define FCONDUG (COND (0x5))
|
|
|
|
|
#define FCONDUGE (COND (0xc))
|
|
|
|
|
#define FCONDUL (COND (0x3))
|
|
|
|
|
#define FCONDULE (COND (0xe))
|
1999-05-03 15:29:11 +08:00
|
|
|
|
|
|
|
|
|
#define FCONDNZ FCONDNE
|
|
|
|
|
#define FCONDZ FCONDE
|
|
|
|
|
|
2005-07-01 19:16:33 +08:00
|
|
|
|
#define ICC (0) /* v9 */
|
|
|
|
|
#define XCC (1 << 12) /* v9 */
|
2012-04-28 02:03:13 +08:00
|
|
|
|
#define CBCOND_XCC (1 << 21)
|
2005-07-01 19:16:33 +08:00
|
|
|
|
#define FCC(x) (((x) & 0x3) << 11) /* v9 */
|
|
|
|
|
#define FBFCC(x) (((x) & 0x3) << 20) /* v9 */
|
1999-05-03 15:29:11 +08:00
|
|
|
|
|
|
|
|
|
/* The order of the opcodes in the table is significant:
|
2005-07-01 19:16:33 +08:00
|
|
|
|
|
1999-05-03 15:29:11 +08:00
|
|
|
|
* The assembler requires that all instances of the same mnemonic must
|
|
|
|
|
be consecutive. If they aren't, the assembler will bomb at runtime.
|
|
|
|
|
|
2005-07-01 19:16:33 +08:00
|
|
|
|
* The disassembler should not care about the order of the opcodes. */
|
1999-05-03 15:29:11 +08:00
|
|
|
|
|
|
|
|
|
/* Entries for commutative arithmetic operations. */
|
|
|
|
|
/* ??? More entries can make use of this. */
|
|
|
|
|
#define COMMUTEOP(opcode, op3, arch_mask) \
|
2014-10-09 20:16:53 +08:00
|
|
|
|
{ opcode, F3(2, op3, 0), F3(~2, ~op3, ~0)|ASI(~0), "1,2,d", 0, 0, 0, arch_mask }, \
|
|
|
|
|
{ opcode, F3(2, op3, 1), F3(~2, ~op3, ~1), "1,i,d", 0, 0, 0, arch_mask }, \
|
|
|
|
|
{ opcode, F3(2, op3, 1), F3(~2, ~op3, ~1), "i,1,d", 0, 0, 0, arch_mask }
|
1999-05-03 15:29:11 +08:00
|
|
|
|
|
|
|
|
|
const struct sparc_opcode sparc_opcodes[] = {
|
|
|
|
|
|
2014-10-09 20:16:53 +08:00
|
|
|
|
{ "ld", F3(3, 0x00, 0), F3(~3, ~0x00, ~0), "[1+2],d", 0, 0, 0, v6 },
|
|
|
|
|
{ "ld", F3(3, 0x00, 0), F3(~3, ~0x00, ~0)|RS2_G0, "[1],d", 0, 0, 0, v6 }, /* ld [rs1+%g0],d */
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|
|
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|
{ "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[1+i],d", 0, 0, 0, v6 },
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|
|
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|
{ "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[i+1],d", 0, 0, 0, v6 },
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|
|
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|
{ "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|RS1_G0, "[i],d", 0, 0, 0, v6 },
|
|
|
|
|
{ "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|SIMM13(~0), "[1],d", 0, 0, 0, v6 }, /* ld [rs1+0],d */
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|
|
|
|
{ "ld", F3(3, 0x20, 0), F3(~3, ~0x20, ~0), "[1+2],g", 0, 0, 0, v6 },
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|
|
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|
{ "ld", F3(3, 0x20, 0), F3(~3, ~0x20, ~0)|RS2_G0, "[1],g", 0, 0, 0, v6 }, /* ld [rs1+%g0],d */
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|
|
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|
{ "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1), "[1+i],g", 0, 0, 0, v6 },
|
|
|
|
|
{ "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1), "[i+1],g", 0, 0, 0, v6 },
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|
|
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|
{ "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1)|RS1_G0, "[i],g", 0, 0, 0, v6 },
|
|
|
|
|
{ "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1)|SIMM13(~0), "[1],g", 0, 0, 0, v6 }, /* ld [rs1+0],d */
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|
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|
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|
{ "ld", F3(3, 0x21, 0), F3(~3, ~0x21, ~0)|RD(~0), "[1+2],F", 0, 0, 0, v6 },
|
|
|
|
|
{ "ld", F3(3, 0x21, 0), F3(~3, ~0x21, ~0)|RS2_G0|RD(~0),"[1],F", 0, 0, 0, v6 }, /* ld [rs1+%g0],d */
|
|
|
|
|
{ "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RD(~0), "[1+i],F", 0, 0, 0, v6 },
|
|
|
|
|
{ "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RD(~0), "[i+1],F", 0, 0, 0, v6 },
|
|
|
|
|
{ "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RS1_G0|RD(~0),"[i],F", 0, 0, 0, v6 },
|
|
|
|
|
{ "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|SIMM13(~0)|RD(~0),"[1],F", 0, 0, 0, v6 }, /* ld [rs1+0],d */
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|
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|
{ "ld", F3(3, 0x30, 0), F3(~3, ~0x30, ~0), "[1+2],D", 0, 0, 0, v6notv9 },
|
|
|
|
|
{ "ld", F3(3, 0x30, 0), F3(~3, ~0x30, ~0)|RS2_G0, "[1],D", 0, 0, 0, v6notv9 }, /* ld [rs1+%g0],d */
|
|
|
|
|
{ "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[1+i],D", 0, 0, 0, v6notv9 },
|
|
|
|
|
{ "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[i+1],D", 0, 0, 0, v6notv9 },
|
|
|
|
|
{ "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|RS1_G0, "[i],D", 0, 0, 0, v6notv9 },
|
|
|
|
|
{ "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|SIMM13(~0), "[1],D", 0, 0, 0, v6notv9 }, /* ld [rs1+0],d */
|
|
|
|
|
{ "ld", F3(3, 0x31, 0), F3(~3, ~0x31, ~0), "[1+2],C", 0, 0, 0, v6notv9 },
|
|
|
|
|
{ "ld", F3(3, 0x31, 0), F3(~3, ~0x31, ~0)|RS2_G0, "[1],C", 0, 0, 0, v6notv9 }, /* ld [rs1+%g0],d */
|
|
|
|
|
{ "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1), "[1+i],C", 0, 0, 0, v6notv9 },
|
|
|
|
|
{ "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1), "[i+1],C", 0, 0, 0, v6notv9 },
|
|
|
|
|
{ "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1)|RS1_G0, "[i],C", 0, 0, 0, v6notv9 },
|
|
|
|
|
{ "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1)|SIMM13(~0), "[1],C", 0, 0, 0, v6notv9 }, /* ld [rs1+0],d */
|
1999-05-03 15:29:11 +08:00
|
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|
|
/* The v9 LDUW is the same as the old 'ld' opcode, it is not the same as the
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|
'ld' pseudo-op in v9. */
|
2014-10-09 20:16:53 +08:00
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|
{ "lduw", F3(3, 0x00, 0), F3(~3, ~0x00, ~0), "[1+2],d", F_ALIAS, 0, 0, v9 },
|
|
|
|
|
{ "lduw", F3(3, 0x00, 0), F3(~3, ~0x00, ~0)|RS2_G0, "[1],d", F_ALIAS, 0, 0, v9 }, /* ld [rs1+%g0],d */
|
|
|
|
|
{ "lduw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[1+i],d", F_ALIAS, 0, 0, v9 },
|
|
|
|
|
{ "lduw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[i+1],d", F_ALIAS, 0, 0, v9 },
|
|
|
|
|
{ "lduw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|RS1_G0, "[i],d", F_ALIAS, 0, 0, v9 },
|
|
|
|
|
{ "lduw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|SIMM13(~0), "[1],d", F_ALIAS, 0, 0, v9 }, /* ld [rs1+0],d */
|
|
|
|
|
|
|
|
|
|
{ "ldtw", F3(3, 0x03, 0), F3(~3, ~0x03, ~0)|ASI(~0), "[1+2],d", 0, 0, 0, v9 },
|
|
|
|
|
{ "ldtw", F3(3, 0x03, 0), F3(~3, ~0x03, ~0)|ASI_RS2(~0), "[1],d", 0, 0, 0, v9 }, /* ldd [rs1+%g0],d */
|
|
|
|
|
{ "ldtw", F3(3, 0x03, 1), F3(~3, ~0x03, ~1), "[1+i],d", 0, 0, 0, v9 },
|
|
|
|
|
{ "ldtw", F3(3, 0x03, 1), F3(~3, ~0x03, ~1), "[i+1],d", 0, 0, 0, v9 },
|
|
|
|
|
{ "ldtw", F3(3, 0x03, 1), F3(~3, ~0x03, ~1)|RS1_G0, "[i],d", 0, 0, 0, v9 },
|
|
|
|
|
{ "ldtw", F3(3, 0x03, 1), F3(~3, ~0x03, ~1)|SIMM13(~0), "[1],d", 0, 0, 0, v9 }, /* ldd [rs1+0],d */
|
|
|
|
|
|
|
|
|
|
{ "ldd", F3(3, 0x03, 0), F3(~3, ~0x03, ~0)|ASI(~0), "[1+2],d", F_ALIAS, 0, 0, v6 },
|
|
|
|
|
{ "ldd", F3(3, 0x03, 0), F3(~3, ~0x03, ~0)|ASI_RS2(~0), "[1],d", F_ALIAS, 0, 0, v6 }, /* ldd [rs1+%g0],d */
|
|
|
|
|
{ "ldd", F3(3, 0x03, 1), F3(~3, ~0x03, ~1), "[1+i],d", F_ALIAS, 0, 0, v6 },
|
|
|
|
|
{ "ldd", F3(3, 0x03, 1), F3(~3, ~0x03, ~1), "[i+1],d", F_ALIAS, 0, 0, v6 },
|
|
|
|
|
{ "ldd", F3(3, 0x03, 1), F3(~3, ~0x03, ~1)|RS1_G0, "[i],d", F_ALIAS, 0, 0, v6 },
|
|
|
|
|
{ "ldd", F3(3, 0x03, 1), F3(~3, ~0x03, ~1)|SIMM13(~0), "[1],d", F_ALIAS, 0, 0, v6 }, /* ldd [rs1+0],d */
|
|
|
|
|
{ "ldd", F3(3, 0x23, 0), F3(~3, ~0x23, ~0)|ASI(~0), "[1+2],H", F_ALIAS, 0, 0, v6 },
|
|
|
|
|
{ "ldd", F3(3, 0x23, 0), F3(~3, ~0x23, ~0)|ASI_RS2(~0), "[1],H", F_ALIAS, 0, 0, v6 }, /* ldd [rs1+%g0],d */
|
|
|
|
|
{ "ldd", F3(3, 0x23, 1), F3(~3, ~0x23, ~1), "[1+i],H", F_ALIAS, 0, 0, v6 },
|
|
|
|
|
{ "ldd", F3(3, 0x23, 1), F3(~3, ~0x23, ~1), "[i+1],H", F_ALIAS, 0, 0, v6 },
|
|
|
|
|
{ "ldd", F3(3, 0x23, 1), F3(~3, ~0x23, ~1)|RS1_G0, "[i],H", F_ALIAS, 0, 0, v6 },
|
|
|
|
|
{ "ldd", F3(3, 0x23, 1), F3(~3, ~0x23, ~1)|SIMM13(~0), "[1],H", F_ALIAS, 0, 0, v6 }, /* ldd [rs1+0],d */
|
|
|
|
|
|
|
|
|
|
{ "ldd", F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|ASI(~0), "[1+2],D", 0, 0, 0, v6notv9 },
|
|
|
|
|
{ "ldd", F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|ASI_RS2(~0), "[1],D", 0, 0, 0, v6notv9 }, /* ldd [rs1+%g0],d */
|
|
|
|
|
{ "ldd", F3(3, 0x33, 1), F3(~3, ~0x33, ~1), "[1+i],D", 0, 0, 0, v6notv9 },
|
|
|
|
|
{ "ldd", F3(3, 0x33, 1), F3(~3, ~0x33, ~1), "[i+1],D", 0, 0, 0, v6notv9 },
|
|
|
|
|
{ "ldd", F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|RS1_G0, "[i],D", 0, 0, 0, v6notv9 },
|
|
|
|
|
{ "ldd", F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|SIMM13(~0), "[1],D", 0, 0, 0, v6notv9 }, /* ldd [rs1+0],d */
|
|
|
|
|
|
|
|
|
|
{ "ldq", F3(3, 0x22, 0), F3(~3, ~0x22, ~0)|ASI(~0), "[1+2],J", 0, 0, 0, v9 },
|
|
|
|
|
{ "ldq", F3(3, 0x22, 0), F3(~3, ~0x22, ~0)|ASI_RS2(~0), "[1],J", 0, 0, 0, v9 }, /* ldd [rs1+%g0],d */
|
|
|
|
|
{ "ldq", F3(3, 0x22, 1), F3(~3, ~0x22, ~1), "[1+i],J", 0, 0, 0, v9 },
|
|
|
|
|
{ "ldq", F3(3, 0x22, 1), F3(~3, ~0x22, ~1), "[i+1],J", 0, 0, 0, v9 },
|
|
|
|
|
{ "ldq", F3(3, 0x22, 1), F3(~3, ~0x22, ~1)|RS1_G0, "[i],J", 0, 0, 0, v9 },
|
|
|
|
|
{ "ldq", F3(3, 0x22, 1), F3(~3, ~0x22, ~1)|SIMM13(~0), "[1],J", 0, 0, 0, v9 }, /* ldd [rs1+0],d */
|
|
|
|
|
|
|
|
|
|
{ "ldsb", F3(3, 0x09, 0), F3(~3, ~0x09, ~0)|ASI(~0), "[1+2],d", 0, 0, 0, v6 },
|
|
|
|
|
{ "ldsb", F3(3, 0x09, 0), F3(~3, ~0x09, ~0)|ASI_RS2(~0), "[1],d", 0, 0, 0, v6 }, /* ldsb [rs1+%g0],d */
|
|
|
|
|
{ "ldsb", F3(3, 0x09, 1), F3(~3, ~0x09, ~1), "[1+i],d", 0, 0, 0, v6 },
|
|
|
|
|
{ "ldsb", F3(3, 0x09, 1), F3(~3, ~0x09, ~1), "[i+1],d", 0, 0, 0, v6 },
|
|
|
|
|
{ "ldsb", F3(3, 0x09, 1), F3(~3, ~0x09, ~1)|RS1_G0, "[i],d", 0, 0, 0, v6 },
|
|
|
|
|
{ "ldsb", F3(3, 0x09, 1), F3(~3, ~0x09, ~1)|SIMM13(~0), "[1],d", 0, 0, 0, v6 }, /* ldsb [rs1+0],d */
|
|
|
|
|
|
|
|
|
|
{ "ldsh", F3(3, 0x0a, 0), F3(~3, ~0x0a, ~0)|ASI_RS2(~0), "[1],d", 0, 0, 0, v6 }, /* ldsh [rs1+%g0],d */
|
|
|
|
|
{ "ldsh", F3(3, 0x0a, 0), F3(~3, ~0x0a, ~0)|ASI(~0), "[1+2],d", 0, 0, 0, v6 },
|
|
|
|
|
{ "ldsh", F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1), "[1+i],d", 0, 0, 0, v6 },
|
|
|
|
|
{ "ldsh", F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1), "[i+1],d", 0, 0, 0, v6 },
|
|
|
|
|
{ "ldsh", F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1)|RS1_G0, "[i],d", 0, 0, 0, v6 },
|
|
|
|
|
{ "ldsh", F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1)|SIMM13(~0), "[1],d", 0, 0, 0, v6 }, /* ldsh [rs1+0],d */
|
|
|
|
|
|
|
|
|
|
{ "ldstub", F3(3, 0x0d, 0), F3(~3, ~0x0d, ~0)|ASI(~0), "[1+2],d", 0, 0, 0, v6 },
|
|
|
|
|
{ "ldstub", F3(3, 0x0d, 0), F3(~3, ~0x0d, ~0)|ASI_RS2(~0), "[1],d", 0, 0, 0, v6 }, /* ldstub [rs1+%g0],d */
|
|
|
|
|
{ "ldstub", F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1), "[1+i],d", 0, 0, 0, v6 },
|
|
|
|
|
{ "ldstub", F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1), "[i+1],d", 0, 0, 0, v6 },
|
|
|
|
|
{ "ldstub", F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1)|RS1_G0, "[i],d", 0, 0, 0, v6 },
|
|
|
|
|
{ "ldstub", F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1)|SIMM13(~0), "[1],d", 0, 0, 0, v6 }, /* ldstub [rs1+0],d */
|
|
|
|
|
|
|
|
|
|
{ "ldsw", F3(3, 0x08, 0), F3(~3, ~0x08, ~0)|ASI(~0), "[1+2],d", 0, 0, 0, v9 },
|
|
|
|
|
{ "ldsw", F3(3, 0x08, 0), F3(~3, ~0x08, ~0)|ASI_RS2(~0), "[1],d", 0, 0, 0, v9 }, /* ldsw [rs1+%g0],d */
|
|
|
|
|
{ "ldsw", F3(3, 0x08, 1), F3(~3, ~0x08, ~1), "[1+i],d", 0, 0, 0, v9 },
|
|
|
|
|
{ "ldsw", F3(3, 0x08, 1), F3(~3, ~0x08, ~1), "[i+1],d", 0, 0, 0, v9 },
|
|
|
|
|
{ "ldsw", F3(3, 0x08, 1), F3(~3, ~0x08, ~1)|RS1_G0, "[i],d", 0, 0, 0, v9 },
|
|
|
|
|
{ "ldsw", F3(3, 0x08, 1), F3(~3, ~0x08, ~1)|SIMM13(~0), "[1],d", 0, 0, 0, v9 }, /* ldsw [rs1+0],d */
|
|
|
|
|
|
|
|
|
|
{ "ldub", F3(3, 0x01, 0), F3(~3, ~0x01, ~0)|ASI(~0), "[1+2],d", 0, 0, 0, v6 },
|
|
|
|
|
{ "ldub", F3(3, 0x01, 0), F3(~3, ~0x01, ~0)|ASI_RS2(~0), "[1],d", 0, 0, 0, v6 }, /* ldub [rs1+%g0],d */
|
|
|
|
|
{ "ldub", F3(3, 0x01, 1), F3(~3, ~0x01, ~1), "[1+i],d", 0, 0, 0, v6 },
|
|
|
|
|
{ "ldub", F3(3, 0x01, 1), F3(~3, ~0x01, ~1), "[i+1],d", 0, 0, 0, v6 },
|
|
|
|
|
{ "ldub", F3(3, 0x01, 1), F3(~3, ~0x01, ~1)|RS1_G0, "[i],d", 0, 0, 0, v6 },
|
|
|
|
|
{ "ldub", F3(3, 0x01, 1), F3(~3, ~0x01, ~1)|SIMM13(~0), "[1],d", 0, 0, 0, v6 }, /* ldub [rs1+0],d */
|
|
|
|
|
|
|
|
|
|
{ "lduh", F3(3, 0x02, 0), F3(~3, ~0x02, ~0)|ASI(~0), "[1+2],d", 0, 0, 0, v6 },
|
|
|
|
|
{ "lduh", F3(3, 0x02, 0), F3(~3, ~0x02, ~0)|ASI_RS2(~0), "[1],d", 0, 0, 0, v6 }, /* lduh [rs1+%g0],d */
|
|
|
|
|
{ "lduh", F3(3, 0x02, 1), F3(~3, ~0x02, ~1), "[1+i],d", 0, 0, 0, v6 },
|
|
|
|
|
{ "lduh", F3(3, 0x02, 1), F3(~3, ~0x02, ~1), "[i+1],d", 0, 0, 0, v6 },
|
|
|
|
|
{ "lduh", F3(3, 0x02, 1), F3(~3, ~0x02, ~1)|RS1_G0, "[i],d", 0, 0, 0, v6 },
|
|
|
|
|
{ "lduh", F3(3, 0x02, 1), F3(~3, ~0x02, ~1)|SIMM13(~0), "[1],d", 0, 0, 0, v6 }, /* lduh [rs1+0],d */
|
|
|
|
|
|
|
|
|
|
{ "ldx", F3(3, 0x0b, 0), F3(~3, ~0x0b, ~0)|ASI(~0), "[1+2],d", 0, 0, 0, v9 },
|
|
|
|
|
{ "ldx", F3(3, 0x0b, 0), F3(~3, ~0x0b, ~0)|ASI_RS2(~0), "[1],d", 0, 0, 0, v9 }, /* ldx [rs1+%g0],d */
|
|
|
|
|
{ "ldx", F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1), "[1+i],d", 0, 0, 0, v9 },
|
|
|
|
|
{ "ldx", F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1), "[i+1],d", 0, 0, 0, v9 },
|
|
|
|
|
{ "ldx", F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1)|RS1_G0, "[i],d", 0, 0, 0, v9 },
|
|
|
|
|
{ "ldx", F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1)|SIMM13(~0), "[1],d", 0, 0, 0, v9 }, /* ldx [rs1+0],d */
|
|
|
|
|
|
|
|
|
|
{ "ldx", F3(3, 0x21, 0)|RD(1), F3(~3, ~0x21, ~0)|RD(~1), "[1+2],F", 0, 0, 0, v9 },
|
|
|
|
|
{ "ldx", F3(3, 0x21, 0)|RD(1), F3(~3, ~0x21, ~0)|RS2_G0|RD(~1), "[1],F", 0, 0, 0, v9 }, /* ld [rs1+%g0],d */
|
|
|
|
|
{ "ldx", F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|RD(~1), "[1+i],F", 0, 0, 0, v9 },
|
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|
{ "ldx", F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|RD(~1), "[i+1],F", 0, 0, 0, v9 },
|
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|
|
{ "ldx", F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|RS1_G0|RD(~1), "[i],F", 0, 0, 0, v9 },
|
|
|
|
|
{ "ldx", F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|SIMM13(~0)|RD(~1),"[1],F", 0, 0, 0, v9 }, /* ld [rs1+0],d */
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|
opcodes,gas: adjust sparc insns and make GAS aware of it
This patch marks the SPARC instructions in the opcodes table with their
proper opcode architectures, and makes the assembler aware of them.
This allows the assembler to properly realize when a new instruction
needs a higher architecture (after v9b) and to react accordingly
emitting an error message or bumping the architecture.
It also expands architecture mismatch tests to cover architectures
higher than v9b, and fixes a couple of minor bugs in the GAS testsuite.
opcodes/ChangeLog:
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* sparc-opc.c (sparc_opcodes): Adjust instructions opcode
architecture according to the hardware capabilities they require.
(sparc_priv_regs): New table.
(sparc_hpriv_regs): Likewise.
(sparc_asr_regs): Likewise.
(v9anotv9m): Define.
gas/ChangeLog:
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-sparc.c (sparc_arch_table): adjust the GAS
architectures to use the right opcode architecture.
(sparc_md_end): Handle v9{c,d,e,v,m}.
(sparc_ip): Fix some comments.
* testsuite/gas/sparc/ldx_efsr.d: Fix the architecture of this
instruction, which is v9d.
* testsuite/gas/sparc/mwait.s: Remove the `rd %mwait,%g1'
instruction from the test, as %mwait is not readable.
* testsuite/gas/sparc/mwait.d: Likewise.
* testsuite/gas/sparc/mism-1.s: Expand to check v9b and v9e
mismatch architecture errors.
* testsuite/gas/sparc/mism-2.s: New file.
2016-06-17 17:14:18 +08:00
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|
{ "ldx", F3(3, 0x21, 0)|RD(3), F3(~3, ~0x21, ~0)|RD(~3), "[1+2],(", 0, HWCAP_VIS3, HWCAP2_VIS3B, v9d }, /* ldx [rs1+rs2],%efsr */
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|
{ "ldx", F3(3, 0x21, 0)|RD(3), F3(~3, ~0x21, ~0)|RS2_G0|RD(~3),"[1],(", 0, HWCAP_VIS3, HWCAP2_VIS3B, v9d }, /* ldx [rs1],%efsr */
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|
{ "ldx", F3(3, 0x21, 1)|RD(3), F3(~3, ~0x21, ~1)|RD(~3), "[1+i],(", 0, HWCAP_VIS3, HWCAP2_VIS3B, v9d }, /* ldx [%rs1+0],%efsr */
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|
{ "ldx", F3(3, 0x21, 1)|RD(3), F3(~3, ~0x21, ~1)|RD(~3), "[i+1],(", 0, HWCAP_VIS3, HWCAP2_VIS3B, v9d }, /* ldx [0+%rs1],%efsr */
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|
{ "ldx", F3(3, 0x21, 1)|RD(3), F3(~3, ~0x21, ~1)|RS1_G0|RD(~3),"[i],(", 0, HWCAP_VIS3, HWCAP2_VIS3B, v9d }, /* ldx [0],%efsr */
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|
{ "ldx", F3(3, 0x21, 1)|RD(3), F3(~3, ~0x21, ~1)|SIMM13(~0)|RD(~3),"[1],(", 0, HWCAP_VIS3, HWCAP2_VIS3B, v9d }, /* ldx [%rs1], %efsr */
|
2014-10-09 20:16:53 +08:00
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{ "lda", F3(3, 0x10, 0), F3(~3, ~0x10, ~0), "[1+2]A,d", 0, 0, 0, v6 },
|
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|
{ "lda", F3(3, 0x10, 0), F3(~3, ~0x10, ~0)|RS2_G0, "[1]A,d", 0, 0, 0, v6 }, /* lda [rs1+%g0],d */
|
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|
{ "lda", F3(3, 0x10, 1), F3(~3, ~0x10, ~1), "[1+i]o,d", 0, 0, 0, v9 },
|
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|
{ "lda", F3(3, 0x10, 1), F3(~3, ~0x10, ~1), "[i+1]o,d", 0, 0, 0, v9 },
|
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|
|
{ "lda", F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|RS1_G0, "[i]o,d", 0, 0, 0, v9 },
|
|
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|
|
{ "lda", F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|SIMM13(~0), "[1]o,d", 0, 0, 0, v9 }, /* ld [rs1+0],d */
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|
{ "lda", F3(3, 0x30, 0), F3(~3, ~0x30, ~0), "[1+2]A,g", 0, 0, 0, v9 },
|
|
|
|
|
{ "lda", F3(3, 0x30, 0), F3(~3, ~0x30, ~0)|RS2_G0, "[1]A,g", 0, 0, 0, v9 }, /* lda [rs1+%g0],d */
|
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|
{ "lda", F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[1+i]o,g", 0, 0, 0, v9 },
|
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|
{ "lda", F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[i+1]o,g", 0, 0, 0, v9 },
|
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|
{ "lda", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|RS1_G0, "[i]o,g", 0, 0, 0, v9 },
|
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|
{ "lda", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|SIMM13(~0), "[1]o,g", 0, 0, 0, v9 }, /* ld [rs1+0],d */
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2016-07-13 16:42:28 +08:00
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/* Note that the LDTXA instructions share an opcode with the
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|
(deprecated) LDTWA instructions below. They are differenciated by
|
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|
the combination of the `i' instruction field and the ASI used in
|
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|
the instruction. */
|
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|
#define ldtxa(asi) \
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|
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|
|
{ "ldtxa", F3(3, 0x13, 0)|ASI((asi)), F3(~3, ~0x13, ~0)|ASI(~(asi)), "[1+2]A,d", 0, HWCAP_ASI_BLK_INIT, 0, v9c }, \
|
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|
|
{ "ldtxa", F3(3, 0x13, 0)|ASI((asi)), F3(~3, ~0x13, ~0)|ASI(~(asi))|RS2_G0, "[1]A,d", 0, HWCAP_ASI_BLK_INIT, 0, v9c }
|
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|
ldtxa (0x22), /* #ASI_TWINX_AIUP */
|
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|
ldtxa (0x23), /* #ASI_TWINX_AIUS */
|
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|
ldtxa (0x26), /* #ASI_TWINX_REAL */
|
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|
ldtxa (0x27), /* #ASI_TWINX_N */
|
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|
ldtxa (0x2A), /* #ASI_TWINX_AIUP_L */
|
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|
ldtxa (0x2B), /* #ASI_TWINX_AIUS_L */
|
|
|
|
|
ldtxa (0x2E), /* #ASI_TWINX_REAL_L */
|
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|
|
ldtxa (0x2F), /* #ASI_TWINX_NL */
|
|
|
|
|
ldtxa (0xE2), /* #ASI_TWINX_P */
|
|
|
|
|
ldtxa (0xE3), /* #ASI_TWINX_S */
|
|
|
|
|
ldtxa (0xEA), /* #ASI_TWINX_PL */
|
|
|
|
|
ldtxa (0xEB), /* #ASI_TWINX_SL */
|
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|
2014-10-09 20:16:53 +08:00
|
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|
|
{ "ldtwa", F3(3, 0x13, 0), F3(~3, ~0x13, ~0), "[1+2]A,d", 0, 0, 0, v9 },
|
|
|
|
|
{ "ldtwa", F3(3, 0x13, 0), F3(~3, ~0x13, ~0)|RS2_G0, "[1]A,d", 0, 0, 0, v9 }, /* ldda [rs1+%g0],d */
|
|
|
|
|
{ "ldtwa", F3(3, 0x13, 1), F3(~3, ~0x13, ~1), "[1+i]o,d", 0, 0, 0, v9 },
|
|
|
|
|
{ "ldtwa", F3(3, 0x13, 1), F3(~3, ~0x13, ~1), "[i+1]o,d", 0, 0, 0, v9 },
|
|
|
|
|
{ "ldtwa", F3(3, 0x13, 1), F3(~3, ~0x13, ~1)|RS1_G0, "[i]o,d", 0, 0, 0, v9 },
|
|
|
|
|
{ "ldtwa", F3(3, 0x13, 1), F3(~3, ~0x13, ~1)|SIMM13(~0), "[1]o,d", 0, 0, 0, v9 }, /* ld [rs1+0],d */
|
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|
|
|
|
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|
{ "ldda", F3(3, 0x13, 0), F3(~3, ~0x13, ~0), "[1+2]A,d", F_ALIAS, 0, 0, v6 },
|
|
|
|
|
{ "ldda", F3(3, 0x13, 0), F3(~3, ~0x13, ~0)|RS2_G0, "[1]A,d", F_ALIAS, 0, 0, v6 }, /* ldda [rs1+%g0],d */
|
|
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|
|
{ "ldda", F3(3, 0x13, 1), F3(~3, ~0x13, ~1), "[1+i]o,d", F_ALIAS, 0, 0, v9 },
|
|
|
|
|
{ "ldda", F3(3, 0x13, 1), F3(~3, ~0x13, ~1), "[i+1]o,d", F_ALIAS, 0, 0, v9 },
|
|
|
|
|
{ "ldda", F3(3, 0x13, 1), F3(~3, ~0x13, ~1)|RS1_G0, "[i]o,d", F_ALIAS, 0, 0, v9 },
|
|
|
|
|
{ "ldda", F3(3, 0x13, 1), F3(~3, ~0x13, ~1)|SIMM13(~0), "[1]o,d", F_ALIAS, 0, 0, v9 }, /* ld [rs1+0],d */
|
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|
|
|
|
|
|
|
|
{ "ldda", F3(3, 0x33, 0), F3(~3, ~0x33, ~0), "[1+2]A,H", 0, 0, 0, v9 },
|
|
|
|
|
{ "ldda", F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|RS2_G0, "[1]A,H", 0, 0, 0, v9 }, /* ldda [rs1+%g0],d */
|
|
|
|
|
{ "ldda", F3(3, 0x33, 1), F3(~3, ~0x33, ~1), "[1+i]o,H", 0, 0, 0, v9 },
|
|
|
|
|
{ "ldda", F3(3, 0x33, 1), F3(~3, ~0x33, ~1), "[i+1]o,H", 0, 0, 0, v9 },
|
|
|
|
|
{ "ldda", F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|RS1_G0, "[i]o,H", 0, 0, 0, v9 },
|
|
|
|
|
{ "ldda", F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|SIMM13(~0), "[1]o,H", 0, 0, 0, v9 }, /* ld [rs1+0],d */
|
|
|
|
|
|
|
|
|
|
{ "ldqa", F3(3, 0x32, 0), F3(~3, ~0x32, ~0), "[1+2]A,J", 0, 0, 0, v9 },
|
|
|
|
|
{ "ldqa", F3(3, 0x32, 0), F3(~3, ~0x32, ~0)|RS2_G0, "[1]A,J", 0, 0, 0, v9 }, /* ldd [rs1+%g0],d */
|
|
|
|
|
{ "ldqa", F3(3, 0x32, 1), F3(~3, ~0x32, ~1), "[1+i]o,J", 0, 0, 0, v9 },
|
|
|
|
|
{ "ldqa", F3(3, 0x32, 1), F3(~3, ~0x32, ~1), "[i+1]o,J", 0, 0, 0, v9 },
|
|
|
|
|
{ "ldqa", F3(3, 0x32, 1), F3(~3, ~0x32, ~1)|RS1_G0, "[i]o,J", 0, 0, 0, v9 },
|
|
|
|
|
{ "ldqa", F3(3, 0x32, 1), F3(~3, ~0x32, ~1)|SIMM13(~0), "[1]o,J", 0, 0, 0, v9 }, /* ldd [rs1+0],d */
|
|
|
|
|
|
|
|
|
|
{ "ldsba", F3(3, 0x19, 0), F3(~3, ~0x19, ~0), "[1+2]A,d", 0, 0, 0, v6 },
|
|
|
|
|
{ "ldsba", F3(3, 0x19, 0), F3(~3, ~0x19, ~0)|RS2_G0, "[1]A,d", 0, 0, 0, v6 }, /* ldsba [rs1+%g0],d */
|
|
|
|
|
{ "ldsba", F3(3, 0x19, 1), F3(~3, ~0x19, ~1), "[1+i]o,d", 0, 0, 0, v9 },
|
|
|
|
|
{ "ldsba", F3(3, 0x19, 1), F3(~3, ~0x19, ~1), "[i+1]o,d", 0, 0, 0, v9 },
|
|
|
|
|
{ "ldsba", F3(3, 0x19, 1), F3(~3, ~0x19, ~1)|RS1_G0, "[i]o,d", 0, 0, 0, v9 },
|
|
|
|
|
{ "ldsba", F3(3, 0x19, 1), F3(~3, ~0x19, ~1)|SIMM13(~0), "[1]o,d", 0, 0, 0, v9 }, /* ld [rs1+0],d */
|
|
|
|
|
|
|
|
|
|
{ "ldsha", F3(3, 0x1a, 0), F3(~3, ~0x1a, ~0), "[1+2]A,d", 0, 0, 0, v6 },
|
|
|
|
|
{ "ldsha", F3(3, 0x1a, 0), F3(~3, ~0x1a, ~0)|RS2_G0, "[1]A,d", 0, 0, 0, v6 }, /* ldsha [rs1+%g0],d */
|
|
|
|
|
{ "ldsha", F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1), "[1+i]o,d", 0, 0, 0, v9 },
|
|
|
|
|
{ "ldsha", F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1), "[i+1]o,d", 0, 0, 0, v9 },
|
|
|
|
|
{ "ldsha", F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1)|RS1_G0, "[i]o,d", 0, 0, 0, v9 },
|
|
|
|
|
{ "ldsha", F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1)|SIMM13(~0), "[1]o,d", 0, 0, 0, v9 }, /* ld [rs1+0],d */
|
|
|
|
|
|
|
|
|
|
{ "ldstuba", F3(3, 0x1d, 0), F3(~3, ~0x1d, ~0), "[1+2]A,d", 0, 0, 0, v6 },
|
|
|
|
|
{ "ldstuba", F3(3, 0x1d, 0), F3(~3, ~0x1d, ~0)|RS2_G0, "[1]A,d", 0, 0, 0, v6 }, /* ldstuba [rs1+%g0],d */
|
|
|
|
|
{ "ldstuba", F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1), "[1+i]o,d", 0, 0, 0, v9 },
|
|
|
|
|
{ "ldstuba", F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1), "[i+1]o,d", 0, 0, 0, v9 },
|
|
|
|
|
{ "ldstuba", F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1)|RS1_G0, "[i]o,d", 0, 0, 0, v9 },
|
|
|
|
|
{ "ldstuba", F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1)|SIMM13(~0), "[1]o,d", 0, 0, 0, v9 }, /* ld [rs1+0],d */
|
|
|
|
|
|
|
|
|
|
{ "ldswa", F3(3, 0x18, 0), F3(~3, ~0x18, ~0), "[1+2]A,d", 0, 0, 0, v9 },
|
|
|
|
|
{ "ldswa", F3(3, 0x18, 0), F3(~3, ~0x18, ~0)|RS2_G0, "[1]A,d", 0, 0, 0, v9 }, /* lda [rs1+%g0],d */
|
|
|
|
|
{ "ldswa", F3(3, 0x18, 1), F3(~3, ~0x18, ~1), "[1+i]o,d", 0, 0, 0, v9 },
|
|
|
|
|
{ "ldswa", F3(3, 0x18, 1), F3(~3, ~0x18, ~1), "[i+1]o,d", 0, 0, 0, v9 },
|
|
|
|
|
{ "ldswa", F3(3, 0x18, 1), F3(~3, ~0x18, ~1)|RS1_G0, "[i]o,d", 0, 0, 0, v9 },
|
|
|
|
|
{ "ldswa", F3(3, 0x18, 1), F3(~3, ~0x18, ~1)|SIMM13(~0), "[1]o,d", 0, 0, 0, v9 }, /* ld [rs1+0],d */
|
|
|
|
|
|
|
|
|
|
{ "lduba", F3(3, 0x11, 0), F3(~3, ~0x11, ~0), "[1+2]A,d", 0, 0, 0, v6 },
|
|
|
|
|
{ "lduba", F3(3, 0x11, 0), F3(~3, ~0x11, ~0)|RS2_G0, "[1]A,d", 0, 0, 0, v6 }, /* lduba [rs1+%g0],d */
|
|
|
|
|
{ "lduba", F3(3, 0x11, 1), F3(~3, ~0x11, ~1), "[1+i]o,d", 0, 0, 0, v9 },
|
|
|
|
|
{ "lduba", F3(3, 0x11, 1), F3(~3, ~0x11, ~1), "[i+1]o,d", 0, 0, 0, v9 },
|
|
|
|
|
{ "lduba", F3(3, 0x11, 1), F3(~3, ~0x11, ~1)|RS1_G0, "[i]o,d", 0, 0, 0, v9 },
|
|
|
|
|
{ "lduba", F3(3, 0x11, 1), F3(~3, ~0x11, ~1)|SIMM13(~0), "[1]o,d", 0, 0, 0, v9 }, /* ld [rs1+0],d */
|
|
|
|
|
|
|
|
|
|
{ "lduha", F3(3, 0x12, 0), F3(~3, ~0x12, ~0), "[1+2]A,d", 0, 0, 0, v6 },
|
|
|
|
|
{ "lduha", F3(3, 0x12, 0), F3(~3, ~0x12, ~0)|RS2_G0, "[1]A,d", 0, 0, 0, v6 }, /* lduha [rs1+%g0],d */
|
|
|
|
|
{ "lduha", F3(3, 0x12, 1), F3(~3, ~0x12, ~1), "[1+i]o,d", 0, 0, 0, v9 },
|
|
|
|
|
{ "lduha", F3(3, 0x12, 1), F3(~3, ~0x12, ~1), "[i+1]o,d", 0, 0, 0, v9 },
|
|
|
|
|
{ "lduha", F3(3, 0x12, 1), F3(~3, ~0x12, ~1)|RS1_G0, "[i]o,d", 0, 0, 0, v9 },
|
|
|
|
|
{ "lduha", F3(3, 0x12, 1), F3(~3, ~0x12, ~1)|SIMM13(~0), "[1]o,d", 0, 0, 0, v9 }, /* ld [rs1+0],d */
|
|
|
|
|
|
|
|
|
|
{ "lduwa", F3(3, 0x10, 0), F3(~3, ~0x10, ~0), "[1+2]A,d", F_ALIAS, 0, 0, v9 }, /* lduwa === lda */
|
|
|
|
|
{ "lduwa", F3(3, 0x10, 0), F3(~3, ~0x10, ~0)|RS2_G0, "[1]A,d", F_ALIAS, 0, 0, v9 }, /* lda [rs1+%g0],d */
|
|
|
|
|
{ "lduwa", F3(3, 0x10, 1), F3(~3, ~0x10, ~1), "[1+i]o,d", F_ALIAS, 0, 0, v9 },
|
|
|
|
|
{ "lduwa", F3(3, 0x10, 1), F3(~3, ~0x10, ~1), "[i+1]o,d", F_ALIAS, 0, 0, v9 },
|
|
|
|
|
{ "lduwa", F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|RS1_G0, "[i]o,d", F_ALIAS, 0, 0, v9 },
|
|
|
|
|
{ "lduwa", F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|SIMM13(~0), "[1]o,d", F_ALIAS, 0, 0, v9 }, /* ld [rs1+0],d */
|
|
|
|
|
|
|
|
|
|
{ "ldxa", F3(3, 0x1b, 0), F3(~3, ~0x1b, ~0), "[1+2]A,d", 0, 0, 0, v9 },
|
|
|
|
|
{ "ldxa", F3(3, 0x1b, 0), F3(~3, ~0x1b, ~0)|RS2_G0, "[1]A,d", 0, 0, 0, v9 }, /* lda [rs1+%g0],d */
|
|
|
|
|
{ "ldxa", F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1), "[1+i]o,d", 0, 0, 0, v9 },
|
|
|
|
|
{ "ldxa", F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1), "[i+1]o,d", 0, 0, 0, v9 },
|
|
|
|
|
{ "ldxa", F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1)|RS1_G0, "[i]o,d", 0, 0, 0, v9 },
|
|
|
|
|
{ "ldxa", F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1)|SIMM13(~0), "[1]o,d", 0, 0, 0, v9 }, /* ld [rs1+0],d */
|
|
|
|
|
|
|
|
|
|
{ "st", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", 0, 0, 0, v6 },
|
|
|
|
|
{ "st", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", 0, 0, 0, v6 }, /* st d,[rs1+%g0] */
|
|
|
|
|
{ "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", 0, 0, 0, v6 },
|
|
|
|
|
{ "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", 0, 0, 0, v6 },
|
|
|
|
|
{ "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]", 0, 0, 0, v6 },
|
|
|
|
|
{ "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", 0, 0, 0, v6 }, /* st d,[rs1+0] */
|
|
|
|
|
{ "st", F3(3, 0x24, 0), F3(~3, ~0x24, ~0)|ASI(~0), "g,[1+2]", 0, 0, 0, v6 },
|
|
|
|
|
{ "st", F3(3, 0x24, 0), F3(~3, ~0x24, ~0)|ASI_RS2(~0), "g,[1]", 0, 0, 0, v6 }, /* st d[rs1+%g0] */
|
|
|
|
|
{ "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1), "g,[1+i]", 0, 0, 0, v6 },
|
|
|
|
|
{ "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1), "g,[i+1]", 0, 0, 0, v6 },
|
|
|
|
|
{ "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1)|RS1_G0, "g,[i]", 0, 0, 0, v6 },
|
|
|
|
|
{ "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1)|SIMM13(~0), "g,[1]", 0, 0, 0, v6 }, /* st d,[rs1+0] */
|
|
|
|
|
|
|
|
|
|
{ "st", F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|ASI(~0), "D,[1+2]", 0, 0, 0, v6notv9 },
|
|
|
|
|
{ "st", F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|ASI_RS2(~0), "D,[1]", 0, 0, 0, v6notv9 }, /* st d,[rs1+%g0] */
|
|
|
|
|
{ "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "D,[1+i]", 0, 0, 0, v6notv9 },
|
|
|
|
|
{ "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "D,[i+1]", 0, 0, 0, v6notv9 },
|
|
|
|
|
{ "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|RS1_G0, "D,[i]", 0, 0, 0, v6notv9 },
|
|
|
|
|
{ "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|SIMM13(~0), "D,[1]", 0, 0, 0, v6notv9 }, /* st d,[rs1+0] */
|
|
|
|
|
{ "st", F3(3, 0x35, 0), F3(~3, ~0x35, ~0)|ASI(~0), "C,[1+2]", 0, 0, 0, v6notv9 },
|
|
|
|
|
{ "st", F3(3, 0x35, 0), F3(~3, ~0x35, ~0)|ASI_RS2(~0), "C,[1]", 0, 0, 0, v6notv9 }, /* st d,[rs1+%g0] */
|
|
|
|
|
{ "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1), "C,[1+i]", 0, 0, 0, v6notv9 },
|
|
|
|
|
{ "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1), "C,[i+1]", 0, 0, 0, v6notv9 },
|
|
|
|
|
{ "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1)|RS1_G0, "C,[i]", 0, 0, 0, v6notv9 },
|
|
|
|
|
{ "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1)|SIMM13(~0), "C,[1]", 0, 0, 0, v6notv9 }, /* st d,[rs1+0] */
|
|
|
|
|
|
|
|
|
|
{ "st", F3(3, 0x25, 0), F3(~3, ~0x25, ~0)|RD_G0|ASI(~0), "F,[1+2]", 0, 0, 0, v6 },
|
|
|
|
|
{ "st", F3(3, 0x25, 0), F3(~3, ~0x25, ~0)|RD_G0|ASI_RS2(~0), "F,[1]", 0, 0, 0, v6 }, /* st d,[rs1+%g0] */
|
|
|
|
|
{ "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0, "F,[1+i]", 0, 0, 0, v6 },
|
|
|
|
|
{ "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0, "F,[i+1]", 0, 0, 0, v6 },
|
|
|
|
|
{ "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0|RS1_G0, "F,[i]", 0, 0, 0, v6 },
|
|
|
|
|
{ "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0|SIMM13(~0), "F,[1]", 0, 0, 0, v6 }, /* st d,[rs1+0] */
|
|
|
|
|
|
|
|
|
|
{ "stw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, 0, 0, v9 },
|
|
|
|
|
{ "stw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, 0, 0, v9 }, /* st d,[rs1+%g0] */
|
|
|
|
|
{ "stw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", F_ALIAS, 0, 0, v9 },
|
|
|
|
|
{ "stw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", F_ALIAS, 0, 0, v9 },
|
|
|
|
|
{ "stw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]", F_ALIAS, 0, 0, v9 },
|
|
|
|
|
{ "stw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, 0, 0, v9 }, /* st d,[rs1+0] */
|
|
|
|
|
{ "stsw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, 0, 0, v9 },
|
|
|
|
|
{ "stsw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, 0, 0, v9 }, /* st d,[rs1+%g0] */
|
|
|
|
|
{ "stsw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", F_ALIAS, 0, 0, v9 },
|
|
|
|
|
{ "stsw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", F_ALIAS, 0, 0, v9 },
|
|
|
|
|
{ "stsw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]", F_ALIAS, 0, 0, v9 },
|
|
|
|
|
{ "stsw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, 0, 0, v9 }, /* st d,[rs1+0] */
|
|
|
|
|
{ "stuw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, 0, 0, v9 },
|
|
|
|
|
{ "stuw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, 0, 0, v9 }, /* st d,[rs1+%g0] */
|
|
|
|
|
{ "stuw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", F_ALIAS, 0, 0, v9 },
|
|
|
|
|
{ "stuw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", F_ALIAS, 0, 0, v9 },
|
|
|
|
|
{ "stuw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]", F_ALIAS, 0, 0, v9 },
|
|
|
|
|
{ "stuw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, 0, 0, v9 }, /* st d,[rs1+0] */
|
|
|
|
|
|
|
|
|
|
{ "spill", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, 0, 0, v6 },
|
|
|
|
|
{ "spill", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, 0, 0, v6 }, /* st d,[rs1+%g0] */
|
|
|
|
|
{ "spill", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", F_ALIAS, 0, 0, v6 },
|
|
|
|
|
{ "spill", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", F_ALIAS, 0, 0, v6 },
|
|
|
|
|
{ "spill", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]", F_ALIAS, 0, 0, v6 },
|
|
|
|
|
{ "spill", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, 0, 0, v6 }, /* st d,[rs1+0] */
|
|
|
|
|
|
|
|
|
|
{ "sta", F3(3, 0x14, 0), F3(~3, ~0x14, ~0), "d,[1+2]A", 0, 0, 0, v6 },
|
|
|
|
|
{ "sta", F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0), "d,[1]A", 0, 0, 0, v6 }, /* sta d,[rs1+%g0] */
|
|
|
|
|
{ "sta", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[1+i]o", 0, 0, 0, v9 },
|
|
|
|
|
{ "sta", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[i+1]o", 0, 0, 0, v9 },
|
|
|
|
|
{ "sta", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0, "d,[i]o", 0, 0, 0, v9 },
|
|
|
|
|
{ "sta", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0), "d,[1]o", 0, 0, 0, v9 }, /* st d,[rs1+0] */
|
|
|
|
|
|
|
|
|
|
{ "sta", F3(3, 0x34, 0), F3(~3, ~0x34, ~0), "g,[1+2]A", 0, 0, 0, v9 },
|
|
|
|
|
{ "sta", F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|RS2(~0), "g,[1]A", 0, 0, 0, v9 }, /* sta d,[rs1+%g0] */
|
|
|
|
|
{ "sta", F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "g,[1+i]o", 0, 0, 0, v9 },
|
|
|
|
|
{ "sta", F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "g,[i+1]o", 0, 0, 0, v9 },
|
|
|
|
|
{ "sta", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|RS1_G0, "g,[i]o", 0, 0, 0, v9 },
|
|
|
|
|
{ "sta", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|SIMM13(~0), "g,[1]o", 0, 0, 0, v9 }, /* st d,[rs1+0] */
|
|
|
|
|
|
|
|
|
|
{ "stwa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0), "d,[1+2]A", F_ALIAS, 0, 0, v9 },
|
|
|
|
|
{ "stwa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0), "d,[1]A", F_ALIAS, 0, 0, v9 }, /* sta d,[rs1+%g0] */
|
|
|
|
|
{ "stwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[1+i]o", F_ALIAS, 0, 0, v9 },
|
|
|
|
|
{ "stwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[i+1]o", F_ALIAS, 0, 0, v9 },
|
|
|
|
|
{ "stwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0, "d,[i]o", F_ALIAS, 0, 0, v9 },
|
|
|
|
|
{ "stwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, 0, 0, v9 }, /* st d,[rs1+0] */
|
|
|
|
|
{ "stswa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0), "d,[1+2]A", F_ALIAS, 0, 0, v9 },
|
|
|
|
|
{ "stswa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0), "d,[1]A", F_ALIAS, 0, 0, v9 }, /* sta d,[rs1+%g0] */
|
|
|
|
|
{ "stswa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[1+i]o", F_ALIAS, 0, 0, v9 },
|
|
|
|
|
{ "stswa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[i+1]o", F_ALIAS, 0, 0, v9 },
|
|
|
|
|
{ "stswa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0, "d,[i]o", F_ALIAS, 0, 0, v9 },
|
|
|
|
|
{ "stswa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, 0, 0, v9 }, /* st d,[rs1+0] */
|
|
|
|
|
{ "stuwa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0), "d,[1+2]A", F_ALIAS, 0, 0, v9 },
|
|
|
|
|
{ "stuwa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0), "d,[1]A", F_ALIAS, 0, 0, v9 }, /* sta d,[rs1+%g0] */
|
|
|
|
|
{ "stuwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[1+i]o", F_ALIAS, 0, 0, v9 },
|
|
|
|
|
{ "stuwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[i+1]o", F_ALIAS, 0, 0, v9 },
|
|
|
|
|
{ "stuwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0, "d,[i]o", F_ALIAS, 0, 0, v9 },
|
|
|
|
|
{ "stuwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, 0, 0, v9 }, /* st d,[rs1+0] */
|
|
|
|
|
|
|
|
|
|
{ "stb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI(~0), "d,[1+2]", 0, 0, 0, v6 },
|
|
|
|
|
{ "stb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI_RS2(~0), "d,[1]", 0, 0, 0, v6 }, /* stb d,[rs1+%g0] */
|
|
|
|
|
{ "stb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[1+i]", 0, 0, 0, v6 },
|
|
|
|
|
{ "stb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[i+1]", 0, 0, 0, v6 },
|
|
|
|
|
{ "stb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RS1_G0, "d,[i]", 0, 0, 0, v6 },
|
|
|
|
|
{ "stb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|SIMM13(~0), "d,[1]", 0, 0, 0, v6 }, /* stb d,[rs1+0] */
|
|
|
|
|
|
|
|
|
|
{ "stsb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, 0, 0, v6 },
|
|
|
|
|
{ "stsb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, 0, 0, v6 }, /* stb d,[rs1+%g0] */
|
|
|
|
|
{ "stsb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[1+i]", F_ALIAS, 0, 0, v6 },
|
|
|
|
|
{ "stsb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[i+1]", F_ALIAS, 0, 0, v6 },
|
|
|
|
|
{ "stsb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RS1_G0, "d,[i]", F_ALIAS, 0, 0, v6 },
|
|
|
|
|
{ "stsb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, 0, 0, v6 }, /* stb d,[rs1+0] */
|
|
|
|
|
{ "stub", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, 0, 0, v6 },
|
|
|
|
|
{ "stub", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, 0, 0, v6 }, /* stb d,[rs1+%g0] */
|
|
|
|
|
{ "stub", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[1+i]", F_ALIAS, 0, 0, v6 },
|
|
|
|
|
{ "stub", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[i+1]", F_ALIAS, 0, 0, v6 },
|
|
|
|
|
{ "stub", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RS1_G0, "d,[i]", F_ALIAS, 0, 0, v6 },
|
|
|
|
|
{ "stub", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, 0, 0, v6 }, /* stb d,[rs1+0] */
|
|
|
|
|
|
|
|
|
|
{ "stba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0), "d,[1+2]A", 0, 0, 0, v6 },
|
|
|
|
|
{ "stba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0)|RS2(~0), "d,[1]A", 0, 0, 0, v6 }, /* stba d,[rs1+%g0] */
|
|
|
|
|
{ "stba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[1+i]o", 0, 0, 0, v9 },
|
|
|
|
|
{ "stba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[i+1]o", 0, 0, 0, v9 },
|
|
|
|
|
{ "stba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|RS1_G0, "d,[i]o", 0, 0, 0, v9 },
|
|
|
|
|
{ "stba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|SIMM13(~0), "d,[1]o", 0, 0, 0, v9 }, /* stb d,[rs1+0] */
|
|
|
|
|
|
|
|
|
|
{ "stsba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0), "d,[1+2]A", F_ALIAS, 0, 0, v6 },
|
|
|
|
|
{ "stsba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0)|RS2(~0), "d,[1]A", F_ALIAS, 0, 0, v6 }, /* stba d,[rs1+%g0] */
|
|
|
|
|
{ "stsba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[1+i]o", F_ALIAS, 0, 0, v9 },
|
|
|
|
|
{ "stsba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[i+1]o", F_ALIAS, 0, 0, v9 },
|
|
|
|
|
{ "stsba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|RS1_G0, "d,[i]o", F_ALIAS, 0, 0, v9 },
|
|
|
|
|
{ "stsba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, 0, 0, v9 }, /* stb d,[rs1+0] */
|
|
|
|
|
{ "stuba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0), "d,[1+2]A", F_ALIAS, 0, 0, v6 },
|
|
|
|
|
{ "stuba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0)|RS2(~0), "d,[1]A", F_ALIAS, 0, 0, v6 }, /* stba d,[rs1+%g0] */
|
|
|
|
|
{ "stuba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[1+i]o", F_ALIAS, 0, 0, v9 },
|
|
|
|
|
{ "stuba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[i+1]o", F_ALIAS, 0, 0, v9 },
|
|
|
|
|
{ "stuba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|RS1_G0, "d,[i]o", F_ALIAS, 0, 0, v9 },
|
|
|
|
|
{ "stuba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, 0, 0, v9 }, /* stb d,[rs1+0] */
|
|
|
|
|
|
|
|
|
|
{ "sttw", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI(~0), "d,[1+2]", 0, 0, 0, v9 },
|
|
|
|
|
{ "sttw", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI_RS2(~0), "d,[1]", 0, 0, 0, v9 }, /* std d,[rs1+%g0] */
|
|
|
|
|
{ "sttw", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[1+i]", 0, 0, 0, v9 },
|
|
|
|
|
{ "sttw", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[i+1]", 0, 0, 0, v9 },
|
|
|
|
|
{ "sttw", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|RS1_G0, "d,[i]", 0, 0, 0, v9 },
|
|
|
|
|
{ "sttw", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|SIMM13(~0), "d,[1]", 0, 0, 0, v9 }, /* std d,[rs1+0] */
|
|
|
|
|
|
|
|
|
|
{ "std", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI(~0), "d,[1+2]", F_PREF_ALIAS, 0, 0, v6 },
|
|
|
|
|
{ "std", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI_RS2(~0), "d,[1]", F_PREF_ALIAS, 0, 0, v6 }, /* std d,[rs1+%g0] */
|
|
|
|
|
{ "std", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[1+i]", F_PREF_ALIAS, 0, 0, v6 },
|
|
|
|
|
{ "std", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[i+1]", F_PREF_ALIAS, 0, 0, v6 },
|
|
|
|
|
{ "std", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|RS1_G0, "d,[i]", F_PREF_ALIAS, 0, 0, v6 },
|
|
|
|
|
{ "std", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|SIMM13(~0), "d,[1]", F_PREF_ALIAS, 0, 0, v6 }, /* std d,[rs1+0] */
|
|
|
|
|
|
|
|
|
|
{ "std", F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI(~0), "q,[1+2]", 0, 0, 0, v6notv9 },
|
|
|
|
|
{ "std", F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI_RS2(~0), "q,[1]", 0, 0, 0, v6notv9 }, /* std d,[rs1+%g0] */
|
|
|
|
|
{ "std", F3(3, 0x26, 1), F3(~3, ~0x26, ~1), "q,[1+i]", 0, 0, 0, v6notv9 },
|
|
|
|
|
{ "std", F3(3, 0x26, 1), F3(~3, ~0x26, ~1), "q,[i+1]", 0, 0, 0, v6notv9 },
|
|
|
|
|
{ "std", F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|RS1_G0, "q,[i]", 0, 0, 0, v6notv9 },
|
|
|
|
|
{ "std", F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|SIMM13(~0), "q,[1]", 0, 0, 0, v6notv9 }, /* std d,[rs1+0] */
|
|
|
|
|
{ "std", F3(3, 0x27, 0), F3(~3, ~0x27, ~0)|ASI(~0), "H,[1+2]", 0, 0, 0, v6 },
|
|
|
|
|
{ "std", F3(3, 0x27, 0), F3(~3, ~0x27, ~0)|ASI_RS2(~0), "H,[1]", 0, 0, 0, v6 }, /* std d,[rs1+%g0] */
|
|
|
|
|
{ "std", F3(3, 0x27, 1), F3(~3, ~0x27, ~1), "H,[1+i]", 0, 0, 0, v6 },
|
|
|
|
|
{ "std", F3(3, 0x27, 1), F3(~3, ~0x27, ~1), "H,[i+1]", 0, 0, 0, v6 },
|
|
|
|
|
{ "std", F3(3, 0x27, 1), F3(~3, ~0x27, ~1)|RS1_G0, "H,[i]", 0, 0, 0, v6 },
|
|
|
|
|
{ "std", F3(3, 0x27, 1), F3(~3, ~0x27, ~1)|SIMM13(~0), "H,[1]", 0, 0, 0, v6 }, /* std d,[rs1+0] */
|
|
|
|
|
|
|
|
|
|
{ "std", F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI(~0), "Q,[1+2]", 0, 0, 0, v6notv9 },
|
|
|
|
|
{ "std", F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI_RS2(~0), "Q,[1]", 0, 0, 0, v6notv9 }, /* std d,[rs1+%g0] */
|
|
|
|
|
{ "std", F3(3, 0x36, 1), F3(~3, ~0x36, ~1), "Q,[1+i]", 0, 0, 0, v6notv9 },
|
|
|
|
|
{ "std", F3(3, 0x36, 1), F3(~3, ~0x36, ~1), "Q,[i+1]", 0, 0, 0, v6notv9 },
|
|
|
|
|
{ "std", F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|RS1_G0, "Q,[i]", 0, 0, 0, v6notv9 },
|
|
|
|
|
{ "std", F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|SIMM13(~0), "Q,[1]", 0, 0, 0, v6notv9 }, /* std d,[rs1+0] */
|
|
|
|
|
{ "std", F3(3, 0x37, 0), F3(~3, ~0x37, ~0)|ASI(~0), "D,[1+2]", 0, 0, 0, v6notv9 },
|
|
|
|
|
{ "std", F3(3, 0x37, 0), F3(~3, ~0x37, ~0)|ASI_RS2(~0), "D,[1]", 0, 0, 0, v6notv9 }, /* std d,[rs1+%g0] */
|
|
|
|
|
{ "std", F3(3, 0x37, 1), F3(~3, ~0x37, ~1), "D,[1+i]", 0, 0, 0, v6notv9 },
|
|
|
|
|
{ "std", F3(3, 0x37, 1), F3(~3, ~0x37, ~1), "D,[i+1]", 0, 0, 0, v6notv9 },
|
|
|
|
|
{ "std", F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|RS1_G0, "D,[i]", 0, 0, 0, v6notv9 },
|
|
|
|
|
{ "std", F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|SIMM13(~0), "D,[1]", 0, 0, 0, v6notv9 }, /* std d,[rs1+0] */
|
|
|
|
|
|
|
|
|
|
{ "spilld", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, 0, 0, v6 },
|
|
|
|
|
{ "spilld", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, 0, 0, v6 }, /* std d,[rs1+%g0] */
|
|
|
|
|
{ "spilld", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[1+i]", F_ALIAS, 0, 0, v6 },
|
|
|
|
|
{ "spilld", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[i+1]", F_ALIAS, 0, 0, v6 },
|
|
|
|
|
{ "spilld", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|RS1_G0, "d,[i]", F_ALIAS, 0, 0, v6 },
|
|
|
|
|
{ "spilld", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, 0, 0, v6 }, /* std d,[rs1+0] */
|
|
|
|
|
|
|
|
|
|
{ "sttwa", F3(3, 0x17, 0), F3(~3, ~0x17, ~0), "d,[1+2]A", 0, 0, 0, v9 },
|
|
|
|
|
{ "sttwa", F3(3, 0x17, 0), F3(~3, ~0x17, ~0)|RS2(~0), "d,[1]A", 0, 0, 0, v9 }, /* stda d,[rs1+%g0] */
|
|
|
|
|
{ "sttwa", F3(3, 0x17, 1), F3(~3, ~0x17, ~1), "d,[1+i]o", 0, 0, 0, v9 },
|
|
|
|
|
{ "sttwa", F3(3, 0x17, 1), F3(~3, ~0x17, ~1), "d,[i+1]o", 0, 0, 0, v9 },
|
|
|
|
|
{ "sttwa", F3(3, 0x17, 1), F3(~3, ~0x17, ~1)|RS1_G0, "d,[i]o", 0, 0, 0, v9 },
|
|
|
|
|
{ "sttwa", F3(3, 0x17, 1), F3(~3, ~0x17, ~1)|SIMM13(~0), "d,[1]o", 0, 0, 0, v9 }, /* std d,[rs1+0] */
|
|
|
|
|
|
|
|
|
|
{ "stda", F3(3, 0x17, 0), F3(~3, ~0x17, ~0), "d,[1+2]A", F_ALIAS, 0, 0, v6 },
|
|
|
|
|
{ "stda", F3(3, 0x17, 0), F3(~3, ~0x17, ~0)|RS2(~0), "d,[1]A", F_ALIAS, 0, 0, v6 }, /* stda d,[rs1+%g0] */
|
|
|
|
|
{ "stda", F3(3, 0x17, 1), F3(~3, ~0x17, ~1), "d,[1+i]o", F_ALIAS, 0, 0, v9 },
|
|
|
|
|
{ "stda", F3(3, 0x17, 1), F3(~3, ~0x17, ~1), "d,[i+1]o", F_ALIAS, 0, 0, v9 },
|
|
|
|
|
{ "stda", F3(3, 0x17, 1), F3(~3, ~0x17, ~1)|RS1_G0, "d,[i]o", F_ALIAS, 0, 0, v9 },
|
|
|
|
|
{ "stda", F3(3, 0x17, 1), F3(~3, ~0x17, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, 0, 0, v9 }, /* std d,[rs1+0] */
|
|
|
|
|
{ "stda", F3(3, 0x37, 0), F3(~3, ~0x37, ~0), "H,[1+2]A", 0, 0, 0, v9 },
|
|
|
|
|
{ "stda", F3(3, 0x37, 0), F3(~3, ~0x37, ~0)|RS2(~0), "H,[1]A", 0, 0, 0, v9 }, /* stda d,[rs1+%g0] */
|
|
|
|
|
{ "stda", F3(3, 0x37, 1), F3(~3, ~0x37, ~1), "H,[1+i]o", 0, 0, 0, v9 },
|
|
|
|
|
{ "stda", F3(3, 0x37, 1), F3(~3, ~0x37, ~1), "H,[i+1]o", 0, 0, 0, v9 },
|
|
|
|
|
{ "stda", F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|RS1_G0, "H,[i]o", 0, 0, 0, v9 },
|
|
|
|
|
{ "stda", F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|SIMM13(~0), "H,[1]o", 0, 0, 0, v9 }, /* std d,[rs1+0] */
|
|
|
|
|
|
|
|
|
|
{ "sth", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI(~0), "d,[1+2]", 0, 0, 0, v6 },
|
|
|
|
|
{ "sth", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI_RS2(~0), "d,[1]", 0, 0, 0, v6 }, /* sth d,[rs1+%g0] */
|
|
|
|
|
{ "sth", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[1+i]", 0, 0, 0, v6 },
|
|
|
|
|
{ "sth", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[i+1]", 0, 0, 0, v6 },
|
|
|
|
|
{ "sth", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RS1_G0, "d,[i]", 0, 0, 0, v6 },
|
|
|
|
|
{ "sth", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|SIMM13(~0), "d,[1]", 0, 0, 0, v6 }, /* sth d,[rs1+0] */
|
|
|
|
|
|
|
|
|
|
{ "stsh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, 0, 0, v6 },
|
|
|
|
|
{ "stsh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, 0, 0, v6 }, /* sth d,[rs1+%g0] */
|
|
|
|
|
{ "stsh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[1+i]", F_ALIAS, 0, 0, v6 },
|
|
|
|
|
{ "stsh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[i+1]", F_ALIAS, 0, 0, v6 },
|
|
|
|
|
{ "stsh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RS1_G0, "d,[i]", F_ALIAS, 0, 0, v6 },
|
|
|
|
|
{ "stsh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, 0, 0, v6 }, /* sth d,[rs1+0] */
|
|
|
|
|
{ "stuh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, 0, 0, v6 },
|
|
|
|
|
{ "stuh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, 0, 0, v6 }, /* sth d,[rs1+%g0] */
|
|
|
|
|
{ "stuh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[1+i]", F_ALIAS, 0, 0, v6 },
|
|
|
|
|
{ "stuh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[i+1]", F_ALIAS, 0, 0, v6 },
|
|
|
|
|
{ "stuh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RS1_G0, "d,[i]", F_ALIAS, 0, 0, v6 },
|
|
|
|
|
{ "stuh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, 0, 0, v6 }, /* sth d,[rs1+0] */
|
|
|
|
|
|
|
|
|
|
{ "stha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0), "d,[1+2]A", 0, 0, 0, v6 },
|
|
|
|
|
{ "stha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0)|RS2(~0), "d,[1]A", 0, 0, 0, v6 }, /* stha ,[rs1+%g0] */
|
|
|
|
|
{ "stha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[1+i]o", 0, 0, 0, v9 },
|
|
|
|
|
{ "stha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[i+1]o", 0, 0, 0, v9 },
|
|
|
|
|
{ "stha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|RS1_G0, "d,[i]o", 0, 0, 0, v9 },
|
|
|
|
|
{ "stha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|SIMM13(~0), "d,[1]o", 0, 0, 0, v9 }, /* sth d,[rs1+0] */
|
|
|
|
|
|
|
|
|
|
{ "stsha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0), "d,[1+2]A", F_ALIAS, 0, 0, v6 },
|
|
|
|
|
{ "stsha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0)|RS2(~0), "d,[1]A", F_ALIAS, 0, 0, v6 }, /* stha ,[rs1+%g0] */
|
|
|
|
|
{ "stsha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[1+i]o", F_ALIAS, 0, 0, v9 },
|
|
|
|
|
{ "stsha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[i+1]o", F_ALIAS, 0, 0, v9 },
|
|
|
|
|
{ "stsha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|RS1_G0, "d,[i]o", F_ALIAS, 0, 0, v9 },
|
|
|
|
|
{ "stsha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, 0, 0, v9 }, /* sth d,[rs1+0] */
|
|
|
|
|
{ "stuha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0), "d,[1+2]A", F_ALIAS, 0, 0, v6 },
|
|
|
|
|
{ "stuha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0)|RS2(~0), "d,[1]A", F_ALIAS, 0, 0, v6 }, /* stha ,[rs1+%g0] */
|
|
|
|
|
{ "stuha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[1+i]o", F_ALIAS, 0, 0, v9 },
|
|
|
|
|
{ "stuha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[i+1]o", F_ALIAS, 0, 0, v9 },
|
|
|
|
|
{ "stuha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|RS1_G0, "d,[i]o", F_ALIAS, 0, 0, v9 },
|
|
|
|
|
{ "stuha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, 0, 0, v9 }, /* sth d,[rs1+0] */
|
|
|
|
|
|
|
|
|
|
{ "stx", F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|ASI(~0), "d,[1+2]", 0, 0, 0, v9 },
|
|
|
|
|
{ "stx", F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|ASI_RS2(~0), "d,[1]", 0, 0, 0, v9 }, /* stx d,[rs1+%g0] */
|
|
|
|
|
{ "stx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1), "d,[1+i]", 0, 0, 0, v9 },
|
|
|
|
|
{ "stx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1), "d,[i+1]", 0, 0, 0, v9 },
|
|
|
|
|
{ "stx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RS1_G0, "d,[i]", 0, 0, 0, v9 },
|
|
|
|
|
{ "stx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|SIMM13(~0), "d,[1]", 0, 0, 0, v9 }, /* stx d,[rs1+0] */
|
|
|
|
|
|
|
|
|
|
{ "stx", F3(3, 0x25, 0)|RD(1), F3(~3, ~0x25, ~0)|ASI(~0)|RD(~1), "F,[1+2]", 0, 0, 0, v9 },
|
|
|
|
|
{ "stx", F3(3, 0x25, 0)|RD(1), F3(~3, ~0x25, ~0)|ASI_RS2(~0)|RD(~1),"F,[1]", 0, 0, 0, v9 }, /* stx d,[rs1+%g0] */
|
|
|
|
|
{ "stx", F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|RD(~1), "F,[1+i]", 0, 0, 0, v9 },
|
|
|
|
|
{ "stx", F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|RD(~1), "F,[i+1]", 0, 0, 0, v9 },
|
|
|
|
|
{ "stx", F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|RS1_G0|RD(~1), "F,[i]", 0, 0, 0, v9 },
|
|
|
|
|
{ "stx", F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|SIMM13(~0)|RD(~1),"F,[1]", 0, 0, 0, v9 }, /* stx d,[rs1+0] */
|
|
|
|
|
|
|
|
|
|
{ "stxa", F3(3, 0x1e, 0), F3(~3, ~0x1e, ~0), "d,[1+2]A", 0, 0, 0, v9 },
|
|
|
|
|
{ "stxa", F3(3, 0x1e, 0), F3(~3, ~0x1e, ~0)|RS2(~0), "d,[1]A", 0, 0, 0, v9 }, /* stxa d,[rs1+%g0] */
|
|
|
|
|
{ "stxa", F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1), "d,[1+i]o", 0, 0, 0, v9 },
|
|
|
|
|
{ "stxa", F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1), "d,[i+1]o", 0, 0, 0, v9 },
|
|
|
|
|
{ "stxa", F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1)|RS1_G0, "d,[i]o", 0, 0, 0, v9 },
|
|
|
|
|
{ "stxa", F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1)|SIMM13(~0), "d,[1]o", 0, 0, 0, v9 }, /* stx d,[rs1+0] */
|
|
|
|
|
|
|
|
|
|
{ "stq", F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI(~0), "J,[1+2]", 0, 0, 0, v9 },
|
|
|
|
|
{ "stq", F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI_RS2(~0), "J,[1]", 0, 0, 0, v9 }, /* stq [rs1+%g0] */
|
|
|
|
|
{ "stq", F3(3, 0x26, 1), F3(~3, ~0x26, ~1), "J,[1+i]", 0, 0, 0, v9 },
|
|
|
|
|
{ "stq", F3(3, 0x26, 1), F3(~3, ~0x26, ~1), "J,[i+1]", 0, 0, 0, v9 },
|
|
|
|
|
{ "stq", F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|RS1_G0, "J,[i]", 0, 0, 0, v9 },
|
|
|
|
|
{ "stq", F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|SIMM13(~0), "J,[1]", 0, 0, 0, v9 }, /* stq [rs1+0] */
|
|
|
|
|
|
|
|
|
|
{ "stqa", F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI(~0), "J,[1+2]A", 0, 0, 0, v9 },
|
|
|
|
|
{ "stqa", F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI_RS2(~0), "J,[1]A", 0, 0, 0, v9 }, /* stqa [rs1+%g0] */
|
|
|
|
|
{ "stqa", F3(3, 0x36, 1), F3(~3, ~0x36, ~1), "J,[1+i]o", 0, 0, 0, v9 },
|
|
|
|
|
{ "stqa", F3(3, 0x36, 1), F3(~3, ~0x36, ~1), "J,[i+1]o", 0, 0, 0, v9 },
|
|
|
|
|
{ "stqa", F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|RS1_G0, "J,[i]o", 0, 0, 0, v9 },
|
|
|
|
|
{ "stqa", F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|SIMM13(~0), "J,[1]o", 0, 0, 0, v9 }, /* stqa [rs1+0] */
|
|
|
|
|
|
|
|
|
|
{ "swap", F3(3, 0x0f, 0), F3(~3, ~0x0f, ~0)|ASI(~0), "[1+2],d", 0, 0, 0, v7 },
|
|
|
|
|
{ "swap", F3(3, 0x0f, 0), F3(~3, ~0x0f, ~0)|ASI_RS2(~0), "[1],d", 0, 0, 0, v7 }, /* swap [rs1+%g0],d */
|
|
|
|
|
{ "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1), "[1+i],d", 0, 0, 0, v7 },
|
|
|
|
|
{ "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1), "[i+1],d", 0, 0, 0, v7 },
|
|
|
|
|
{ "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1)|RS1_G0, "[i],d", 0, 0, 0, v7 },
|
|
|
|
|
{ "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1)|SIMM13(~0), "[1],d", 0, 0, 0, v7 }, /* swap [rs1+0],d */
|
|
|
|
|
|
|
|
|
|
{ "swapa", F3(3, 0x1f, 0), F3(~3, ~0x1f, ~0), "[1+2]A,d", 0, 0, 0, v7 },
|
|
|
|
|
{ "swapa", F3(3, 0x1f, 0), F3(~3, ~0x1f, ~0)|RS2(~0), "[1]A,d", 0, 0, 0, v7 }, /* swapa [rs1+%g0],d */
|
|
|
|
|
{ "swapa", F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1), "[1+i]o,d", 0, 0, 0, v9 },
|
|
|
|
|
{ "swapa", F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1), "[i+1]o,d", 0, 0, 0, v9 },
|
|
|
|
|
{ "swapa", F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1)|RS1_G0, "[i]o,d", 0, 0, 0, v9 },
|
|
|
|
|
{ "swapa", F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1)|SIMM13(~0), "[1]o,d", 0, 0, 0, v9 }, /* swap [rs1+0],d */
|
|
|
|
|
|
|
|
|
|
{ "restore", F3(2, 0x3d, 0), F3(~2, ~0x3d, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6 },
|
|
|
|
|
{ "restore", F3(2, 0x3d, 0), F3(~2, ~0x3d, ~0)|RD_G0|RS1_G0|ASI_RS2(~0), "", 0, 0, 0, v6 }, /* restore %g0,%g0,%g0 */
|
|
|
|
|
{ "restore", F3(2, 0x3d, 1), F3(~2, ~0x3d, ~1), "1,i,d", 0, 0, 0, v6 },
|
|
|
|
|
{ "restore", F3(2, 0x3d, 1), F3(~2, ~0x3d, ~1)|RD_G0|RS1_G0|SIMM13(~0), "", 0, 0, 0, v6 }, /* restore %g0,0,%g0 */
|
|
|
|
|
|
|
|
|
|
{ "rett", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|RD_G0|ASI(~0), "1+2", F_UNBR|F_DELAYED, 0, 0, v6 }, /* rett rs1+rs2 */
|
|
|
|
|
{ "rett", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|RD_G0|ASI_RS2(~0), "1", F_UNBR|F_DELAYED, 0, 0, v6 }, /* rett rs1,%g0 */
|
|
|
|
|
{ "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0, "1+i", F_UNBR|F_DELAYED, 0, 0, v6 }, /* rett rs1+X */
|
|
|
|
|
{ "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0, "i+1", F_UNBR|F_DELAYED, 0, 0, v6 }, /* rett X+rs1 */
|
|
|
|
|
{ "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|RS1_G0, "i", F_UNBR|F_DELAYED, 0, 0, v6 }, /* rett X+rs1 */
|
|
|
|
|
{ "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|RS1_G0, "i", F_UNBR|F_DELAYED, 0, 0, v6 }, /* rett X */
|
|
|
|
|
{ "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|SIMM13(~0), "1", F_UNBR|F_DELAYED, 0, 0, v6 }, /* rett rs1+0 */
|
|
|
|
|
|
|
|
|
|
{ "save", F3(2, 0x3c, 0), F3(~2, ~0x3c, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6 },
|
|
|
|
|
{ "save", F3(2, 0x3c, 1), F3(~2, ~0x3c, ~1), "1,i,d", 0, 0, 0, v6 },
|
|
|
|
|
{ "save", F3(2, 0x3c, 1), F3(~2, ~0x3c, ~1), "i,1,d", 0, 0, 0, v6 }, /* Sun assembler compatibility */
|
|
|
|
|
{ "save", 0x81e00000, ~0x81e00000, "", F_ALIAS, 0, 0, v6 },
|
|
|
|
|
|
|
|
|
|
{ "ret", F3(2, 0x38, 1)|RS1(0x1f)|SIMM13(8), F3(~2, ~0x38, ~1)|SIMM13(~8), "", F_UNBR|F_DELAYED, 0, 0, v6 }, /* jmpl %i7+8,%g0 */
|
|
|
|
|
{ "retl", F3(2, 0x38, 1)|RS1(0x0f)|SIMM13(8), F3(~2, ~0x38, ~1)|RS1(~0x0f)|SIMM13(~8), "", F_UNBR|F_DELAYED, 0, 0, v6 }, /* jmpl %o7+8,%g0 */
|
|
|
|
|
|
|
|
|
|
{ "jmpl", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|ASI(~0), "1+2,d", F_JSR|F_DELAYED, 0, 0, v6 },
|
|
|
|
|
{ "jmpl", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|ASI_RS2(~0), "1,d", F_JSR|F_DELAYED, 0, 0, v6 }, /* jmpl rs1+%g0,d */
|
|
|
|
|
{ "jmpl", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|SIMM13(~0), "1,d", F_JSR|F_DELAYED, 0, 0, v6 }, /* jmpl rs1+0,d */
|
|
|
|
|
{ "jmpl", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RS1_G0, "i,d", F_JSR|F_DELAYED, 0, 0, v6 }, /* jmpl %g0+i,d */
|
|
|
|
|
{ "jmpl", F3(2, 0x38, 1), F3(~2, ~0x38, ~1), "1+i,d", F_JSR|F_DELAYED, 0, 0, v6 },
|
|
|
|
|
{ "jmpl", F3(2, 0x38, 1), F3(~2, ~0x38, ~1), "i+1,d", F_JSR|F_DELAYED, 0, 0, v6 },
|
|
|
|
|
|
|
|
|
|
{ "done", F3(2, 0x3e, 0)|RD(0), F3(~2, ~0x3e, ~0)|RD(~0)|RS1_G0|SIMM13(~0), "", 0, 0, 0, v9 },
|
|
|
|
|
{ "retry", F3(2, 0x3e, 0)|RD(1), F3(~2, ~0x3e, ~0)|RD(~1)|RS1_G0|SIMM13(~0), "", 0, 0, 0, v9 },
|
|
|
|
|
{ "saved", F3(2, 0x31, 0)|RD(0), F3(~2, ~0x31, ~0)|RD(~0)|RS1_G0|SIMM13(~0), "", 0, 0, 0, v9 },
|
|
|
|
|
{ "restored", F3(2, 0x31, 0)|RD(1), F3(~2, ~0x31, ~0)|RD(~1)|RS1_G0|SIMM13(~0), "", 0, 0, 0, v9 },
|
|
|
|
|
{ "allclean", F3(2, 0x31, 0)|RD(2), F3(~2, ~0x31, ~0)|RD(~2)|RS1_G0|SIMM13(~0), "", 0, 0, 0, v9 },
|
|
|
|
|
{ "otherw", F3(2, 0x31, 0)|RD(3), F3(~2, ~0x31, ~0)|RD(~3)|RS1_G0|SIMM13(~0), "", 0, 0, 0, v9 },
|
|
|
|
|
{ "normalw", F3(2, 0x31, 0)|RD(4), F3(~2, ~0x31, ~0)|RD(~4)|RS1_G0|SIMM13(~0), "", 0, 0, 0, v9 },
|
|
|
|
|
{ "invalw", F3(2, 0x31, 0)|RD(5), F3(~2, ~0x31, ~0)|RD(~5)|RS1_G0|SIMM13(~0), "", 0, 0, 0, v9 },
|
|
|
|
|
{ "sir", F3(2, 0x30, 1)|RD(0xf), F3(~2, ~0x30, ~1)|RD(~0xf)|RS1_G0, "i", 0, 0, 0, v9 },
|
|
|
|
|
|
|
|
|
|
{ "flush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI(~0), "[1+2]", 0, 0, 0, v9 },
|
|
|
|
|
{ "flush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI_RS2(~0), "[1]", 0, 0, 0, v9 }, /* flush rs1+%g0 */
|
|
|
|
|
{ "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|SIMM13(~0), "[1]", 0, 0, 0, v9 }, /* flush rs1+0 */
|
|
|
|
|
{ "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|RS1_G0, "[i]", 0, 0, 0, v9 }, /* flush %g0+i */
|
|
|
|
|
{ "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "[1+i]", 0, 0, 0, v9 },
|
|
|
|
|
{ "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "[i+1]", 0, 0, 0, v9 },
|
|
|
|
|
|
|
|
|
|
{ "flush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI(~0), "1+2", F_ALIAS, 0, 0, v8 },
|
|
|
|
|
{ "flush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI_RS2(~0), "1", F_ALIAS, 0, 0, v8 }, /* flush rs1+%g0 */
|
|
|
|
|
{ "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|SIMM13(~0), "1", F_ALIAS, 0, 0, v8 }, /* flush rs1+0 */
|
|
|
|
|
{ "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|RS1_G0, "i", F_ALIAS, 0, 0, v8 }, /* flush %g0+i */
|
|
|
|
|
{ "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "1+i", F_ALIAS, 0, 0, v8 },
|
|
|
|
|
{ "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "i+1", F_ALIAS, 0, 0, v8 },
|
1999-05-03 15:29:11 +08:00
|
|
|
|
|
|
|
|
|
/* IFLUSH was renamed to FLUSH in v8. */
|
2014-10-09 20:16:53 +08:00
|
|
|
|
{ "iflush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI(~0), "1+2", F_ALIAS, 0, 0, v6 },
|
|
|
|
|
{ "iflush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI_RS2(~0), "1", F_ALIAS, 0, 0, v6 }, /* flush rs1+%g0 */
|
|
|
|
|
{ "iflush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|SIMM13(~0), "1", F_ALIAS, 0, 0, v6 }, /* flush rs1+0 */
|
|
|
|
|
{ "iflush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|RS1_G0, "i", F_ALIAS, 0, 0, v6 },
|
|
|
|
|
{ "iflush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "1+i", F_ALIAS, 0, 0, v6 },
|
|
|
|
|
{ "iflush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "i+1", F_ALIAS, 0, 0, v6 },
|
|
|
|
|
|
|
|
|
|
{ "return", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|ASI(~0), "1+2", 0, 0, 0, v9 },
|
|
|
|
|
{ "return", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|ASI_RS2(~0), "1", 0, 0, 0, v9 }, /* return rs1+%g0 */
|
|
|
|
|
{ "return", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|SIMM13(~0), "1", 0, 0, 0, v9 }, /* return rs1+0 */
|
|
|
|
|
{ "return", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RS1_G0, "i", 0, 0, 0, v9 }, /* return %g0+i */
|
|
|
|
|
{ "return", F3(2, 0x39, 1), F3(~2, ~0x39, ~1), "1+i", 0, 0, 0, v9 },
|
|
|
|
|
{ "return", F3(2, 0x39, 1), F3(~2, ~0x39, ~1), "i+1", 0, 0, 0, v9 },
|
|
|
|
|
|
|
|
|
|
{ "flushw", F3(2, 0x2b, 0), F3(~2, ~0x2b, ~0)|RD_G0|RS1_G0|ASI_RS2(~0), "", 0, 0, 0, v9 },
|
|
|
|
|
|
|
|
|
|
{ "membar", F3(2, 0x28, 1)|RS1(0xf), F3(~2, ~0x28, ~1)|RD_G0|RS1(~0xf)|SIMM13(~127), "K", 0, 0, 0, v9 },
|
|
|
|
|
{ "stbar", F3(2, 0x28, 0)|RS1(0xf), F3(~2, ~0x28, ~0)|RD_G0|RS1(~0xf)|SIMM13(~0), "", 0, 0, 0, v8 },
|
|
|
|
|
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|
|
|
|
{ "prefetch", F3(3, 0x2d, 0), F3(~3, ~0x2d, ~0), "[1+2],*", 0, 0, 0, v9 },
|
|
|
|
|
{ "prefetch", F3(3, 0x2d, 0), F3(~3, ~0x2d, ~0)|RS2_G0, "[1],*", 0, 0, 0, v9 }, /* prefetch [rs1+%g0],prefetch_fcn */
|
|
|
|
|
{ "prefetch", F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1), "[1+i],*", 0, 0, 0, v9 },
|
|
|
|
|
{ "prefetch", F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1), "[i+1],*", 0, 0, 0, v9 },
|
|
|
|
|
{ "prefetch", F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1)|RS1_G0, "[i],*", 0, 0, 0, v9 },
|
|
|
|
|
{ "prefetch", F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1)|SIMM13(~0), "[1],*", 0, 0, 0, v9 }, /* prefetch [rs1+0],prefetch_fcn */
|
|
|
|
|
{ "prefetcha", F3(3, 0x3d, 0), F3(~3, ~0x3d, ~0), "[1+2]A,*", 0, 0, 0, v9 },
|
|
|
|
|
{ "prefetcha", F3(3, 0x3d, 0), F3(~3, ~0x3d, ~0)|RS2_G0, "[1]A,*", 0, 0, 0, v9 }, /* prefetcha [rs1+%g0],prefetch_fcn */
|
|
|
|
|
{ "prefetcha", F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1), "[1+i]o,*", 0, 0, 0, v9 },
|
|
|
|
|
{ "prefetcha", F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1), "[i+1]o,*", 0, 0, 0, v9 },
|
|
|
|
|
{ "prefetcha", F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1)|RS1_G0, "[i]o,*", 0, 0, 0, v9 },
|
|
|
|
|
{ "prefetcha", F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1)|SIMM13(~0), "[1]o,*", 0, 0, 0, v9 }, /* prefetcha [rs1+0],d */
|
|
|
|
|
|
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|
{ "sll", F3(2, 0x25, 0), F3(~2, ~0x25, ~0)|(1<<12)|(0x7f<<5), "1,2,d", 0, 0, 0, v6 },
|
|
|
|
|
{ "sll", F3(2, 0x25, 1), F3(~2, ~0x25, ~1)|(1<<12)|(0x7f<<5), "1,X,d", 0, 0, 0, v6 },
|
|
|
|
|
{ "sra", F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|(0x7f<<5), "1,2,d", 0, 0, 0, v6 },
|
|
|
|
|
{ "sra", F3(2, 0x27, 1), F3(~2, ~0x27, ~1)|(1<<12)|(0x7f<<5), "1,X,d", 0, 0, 0, v6 },
|
|
|
|
|
{ "srl", F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|(0x7f<<5), "1,2,d", 0, 0, 0, v6 },
|
|
|
|
|
{ "srl", F3(2, 0x26, 1), F3(~2, ~0x26, ~1)|(1<<12)|(0x7f<<5), "1,X,d", 0, 0, 0, v6 },
|
|
|
|
|
|
|
|
|
|
{ "sllx", F3(2, 0x25, 0)|(1<<12), F3(~2, ~0x25, ~0)|(0x7f<<5), "1,2,d", 0, 0, 0, v9 },
|
|
|
|
|
{ "sllx", F3(2, 0x25, 1)|(1<<12), F3(~2, ~0x25, ~1)|(0x3f<<6), "1,Y,d", 0, 0, 0, v9 },
|
|
|
|
|
{ "srax", F3(2, 0x27, 0)|(1<<12), F3(~2, ~0x27, ~0)|(0x7f<<5), "1,2,d", 0, 0, 0, v9 },
|
|
|
|
|
{ "srax", F3(2, 0x27, 1)|(1<<12), F3(~2, ~0x27, ~1)|(0x3f<<6), "1,Y,d", 0, 0, 0, v9 },
|
|
|
|
|
{ "srlx", F3(2, 0x26, 0)|(1<<12), F3(~2, ~0x26, ~0)|(0x7f<<5), "1,2,d", 0, 0, 0, v9 },
|
|
|
|
|
{ "srlx", F3(2, 0x26, 1)|(1<<12), F3(~2, ~0x26, ~1)|(0x3f<<6), "1,Y,d", 0, 0, 0, v9 },
|
|
|
|
|
|
|
|
|
|
{ "mulscc", F3(2, 0x24, 0), F3(~2, ~0x24, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6 },
|
|
|
|
|
{ "mulscc", F3(2, 0x24, 1), F3(~2, ~0x24, ~1), "1,i,d", 0, 0, 0, v6 },
|
|
|
|
|
|
|
|
|
|
{ "divscc", F3(2, 0x1d, 0), F3(~2, ~0x1d, ~0)|ASI(~0), "1,2,d", 0, 0, 0, sparclite },
|
|
|
|
|
{ "divscc", F3(2, 0x1d, 1), F3(~2, ~0x1d, ~1), "1,i,d", 0, 0, 0, sparclite },
|
|
|
|
|
|
|
|
|
|
{ "scan", F3(2, 0x2c, 0), F3(~2, ~0x2c, ~0)|ASI(~0), "1,2,d", 0, 0, 0, sparclet|sparclite },
|
|
|
|
|
{ "scan", F3(2, 0x2c, 1), F3(~2, ~0x2c, ~1), "1,i,d", 0, 0, 0, sparclet|sparclite },
|
|
|
|
|
|
|
|
|
|
{ "popc", F3(2, 0x2e, 0), F3(~2, ~0x2e, ~0)|RS1_G0|ASI(~0),"2,d", 0, HWCAP_POPC, 0, v9 },
|
|
|
|
|
{ "popc", F3(2, 0x2e, 1), F3(~2, ~0x2e, ~1)|RS1_G0, "i,d", 0, HWCAP_POPC, 0, v9 },
|
|
|
|
|
|
|
|
|
|
{ "clr", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|RD_G0|RS1_G0|ASI_RS2(~0), "d", F_ALIAS, 0, 0, v6 }, /* or %g0,%g0,d */
|
|
|
|
|
{ "clr", F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|RS1_G0|SIMM13(~0), "d", F_ALIAS, 0, 0, v6 }, /* or %g0,0,d */
|
|
|
|
|
{ "clr", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|RD_G0|ASI(~0), "[1+2]", F_ALIAS, 0, 0, v6 },
|
|
|
|
|
{ "clr", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|RD_G0|ASI_RS2(~0), "[1]", F_ALIAS, 0, 0, v6 }, /* st %g0,[rs1+%g0] */
|
|
|
|
|
{ "clr", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0, "[1+i]", F_ALIAS, 0, 0, v6 },
|
|
|
|
|
{ "clr", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0, "[i+1]", F_ALIAS, 0, 0, v6 },
|
|
|
|
|
{ "clr", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0|RS1_G0, "[i]", F_ALIAS, 0, 0, v6 },
|
|
|
|
|
{ "clr", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0|SIMM13(~0), "[1]", F_ALIAS, 0, 0, v6 }, /* st %g0,[rs1+0] */
|
|
|
|
|
|
|
|
|
|
{ "clrb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|RD_G0|ASI(~0), "[1+2]", F_ALIAS, 0, 0, v6 },
|
|
|
|
|
{ "clrb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|RD_G0|ASI_RS2(~0), "[1]", F_ALIAS, 0, 0, v6 }, /* stb %g0,[rs1+%g0] */
|
|
|
|
|
{ "clrb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0, "[1+i]", F_ALIAS, 0, 0, v6 },
|
|
|
|
|
{ "clrb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0, "[i+1]", F_ALIAS, 0, 0, v6 },
|
|
|
|
|
{ "clrb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0|RS1_G0, "[i]", F_ALIAS, 0, 0, v6 },
|
|
|
|
|
{ "clrb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0|SIMM13(~0), "[1]", F_ALIAS, 0, 0, v6 }, /* stb %g0,[rs1+0] */
|
|
|
|
|
|
|
|
|
|
{ "clrh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|RD_G0|ASI(~0), "[1+2]", F_ALIAS, 0, 0, v6 },
|
|
|
|
|
{ "clrh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|RD_G0|ASI_RS2(~0), "[1]", F_ALIAS, 0, 0, v6 }, /* sth %g0,[rs1+%g0] */
|
|
|
|
|
{ "clrh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0, "[1+i]", F_ALIAS, 0, 0, v6 },
|
|
|
|
|
{ "clrh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0, "[i+1]", F_ALIAS, 0, 0, v6 },
|
|
|
|
|
{ "clrh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0|RS1_G0, "[i]", F_ALIAS, 0, 0, v6 },
|
|
|
|
|
{ "clrh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0|SIMM13(~0), "[1]", F_ALIAS, 0, 0, v6 }, /* sth %g0,[rs1+0] */
|
|
|
|
|
|
|
|
|
|
{ "clrx", F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|RD_G0|ASI(~0), "[1+2]", F_ALIAS, 0, 0, v9 },
|
|
|
|
|
{ "clrx", F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|RD_G0|ASI_RS2(~0), "[1]", F_ALIAS, 0, 0, v9 }, /* stx %g0,[rs1+%g0] */
|
|
|
|
|
{ "clrx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0, "[1+i]", F_ALIAS, 0, 0, v9 },
|
|
|
|
|
{ "clrx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0, "[i+1]", F_ALIAS, 0, 0, v9 },
|
|
|
|
|
{ "clrx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0|RS1_G0, "[i]", F_ALIAS, 0, 0, v9 },
|
|
|
|
|
{ "clrx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0|SIMM13(~0), "[1]", F_ALIAS, 0, 0, v9 }, /* stx %g0,[rs1+0] */
|
|
|
|
|
|
|
|
|
|
{ "orcc", F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6 },
|
|
|
|
|
{ "orcc", F3(2, 0x12, 1), F3(~2, ~0x12, ~1), "1,i,d", 0, 0, 0, v6 },
|
|
|
|
|
{ "orcc", F3(2, 0x12, 1), F3(~2, ~0x12, ~1), "i,1,d", 0, 0, 0, v6 },
|
1999-05-03 15:29:11 +08:00
|
|
|
|
|
|
|
|
|
/* This is not a commutative instruction. */
|
2014-10-09 20:16:53 +08:00
|
|
|
|
{ "orncc", F3(2, 0x16, 0), F3(~2, ~0x16, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6 },
|
|
|
|
|
{ "orncc", F3(2, 0x16, 1), F3(~2, ~0x16, ~1), "1,i,d", 0, 0, 0, v6 },
|
1999-05-03 15:29:11 +08:00
|
|
|
|
|
|
|
|
|
/* This is not a commutative instruction. */
|
2014-10-09 20:16:53 +08:00
|
|
|
|
{ "orn", F3(2, 0x06, 0), F3(~2, ~0x06, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6 },
|
|
|
|
|
{ "orn", F3(2, 0x06, 1), F3(~2, ~0x06, ~1), "1,i,d", 0, 0, 0, v6 },
|
|
|
|
|
|
|
|
|
|
{ "tst", F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|RD_G0|ASI_RS2(~0), "1", 0, 0, 0, v6 }, /* orcc rs1, %g0, %g0 */
|
|
|
|
|
{ "tst", F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|RD_G0|RS1_G0|ASI(~0), "2", 0, 0, 0, v6 }, /* orcc %g0, rs2, %g0 */
|
|
|
|
|
{ "tst", F3(2, 0x12, 1), F3(~2, ~0x12, ~1)|RD_G0|SIMM13(~0), "1", 0, 0, 0, v6 }, /* orcc rs1, 0, %g0 */
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
{ "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI(~0), "1,2,m", 0, 0, 0, v8 }, /* wr r,r,%asrX */
|
|
|
|
|
{ "wr", F3(2, 0x30, 1), F3(~2, ~0x30, ~1), "1,i,m", 0, 0, 0, v8 }, /* wr r,i,%asrX */
|
|
|
|
|
{ "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RS1_G0|ASI(~0), "2,m", F_PREF_ALIAS, 0, 0, v8 }, /* wr %g0,rs2,%asrX */
|
|
|
|
|
{ "wr", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RS1_G0, "i,m", F_PREF_ALIAS, 0, 0, v8 }, /* wr %g0,i,%asrX */
|
|
|
|
|
{ "wr", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|SIMM13(~0), "1,m", F_PREF_ALIAS, 0, 0, v8 }, /* wr rs1,%asrX */
|
|
|
|
|
{ "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI_RS2(~0), "1,m", F_PREF_ALIAS, 0, 0, v8 }, /* wr rs1,%g0,%asrX */
|
|
|
|
|
{ "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|ASI(~0), "1,2,y", 0, 0, 0, v6 }, /* wr r,r,%y */
|
|
|
|
|
{ "wr", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0, "1,i,y", 0, 0, 0, v6 }, /* wr r,i,%y */
|
|
|
|
|
{ "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|RS1_G0|ASI(~0), "2,y", F_PREF_ALIAS, 0, 0, v6 }, /* wr %g0,rs2,%y */
|
|
|
|
|
{ "wr", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0|RS1_G0, "i,y", F_PREF_ALIAS, 0, 0, v6 }, /* wr %g0,i,%y */
|
|
|
|
|
{ "wr", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0|SIMM13(~0), "1,y", F_PREF_ALIAS, 0, 0, v6 }, /* wr rs1,0,%y */
|
|
|
|
|
{ "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|ASI_RS2(~0), "1,y", F_PREF_ALIAS, 0, 0, v6 }, /* wr rs1,%g0,%y */
|
|
|
|
|
{ "wr", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|ASI(~0), "1,2,p", 0, 0, 0, v6notv9 }, /* wr r,r,%psr */
|
|
|
|
|
{ "wr", F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0, "1,i,p", 0, 0, 0, v6notv9 }, /* wr r,i,%psr */
|
|
|
|
|
{ "wr", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|RS1_G0|ASI(~0), "2,p", F_PREF_ALIAS, 0, 0, v6notv9 }, /* wr %g0,rs2,%psr */
|
|
|
|
|
{ "wr", F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0|RS1_G0, "i,p", F_PREF_ALIAS, 0, 0, v6notv9 }, /* wr %g0,i,%psr */
|
|
|
|
|
{ "wr", F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0|SIMM13(~0), "1,p", F_PREF_ALIAS, 0, 0, v6notv9 }, /* wr rs1,0,%psr */
|
|
|
|
|
{ "wr", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|ASI_RS2(~0), "1,p", F_PREF_ALIAS, 0, 0, v6notv9 }, /* wr rs1,%g0,%psr */
|
|
|
|
|
{ "wr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|ASI(~0), "1,2,w", 0, 0, 0, v6notv9 }, /* wr r,r,%wim */
|
|
|
|
|
{ "wr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0, "1,i,w", 0, 0, 0, v6notv9 }, /* wr r,i,%wim */
|
|
|
|
|
{ "wr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|RS1_G0|ASI(~0), "2,w", F_PREF_ALIAS, 0, 0, v6notv9 }, /* wr %g0,rs2,%wim */
|
|
|
|
|
{ "wr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0|RS1_G0, "i,w", F_PREF_ALIAS, 0, 0, v6notv9 }, /* wr %g0,i,%wim */
|
|
|
|
|
{ "wr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0|SIMM13(~0), "1,w", F_PREF_ALIAS, 0, 0, v6notv9 }, /* wr rs1,0,%wim */
|
|
|
|
|
{ "wr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|ASI_RS2(~0), "1,w", F_PREF_ALIAS, 0, 0, v6notv9 }, /* wr rs1,%g0,%wim */
|
|
|
|
|
{ "wr", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|ASI(~0), "1,2,t", 0, 0, 0, v6notv9 }, /* wr r,r,%tbr */
|
|
|
|
|
{ "wr", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0, "1,i,t", 0, 0, 0, v6notv9 }, /* wr r,i,%tbr */
|
|
|
|
|
{ "wr", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|RS1_G0|ASI(~0), "2,t", F_PREF_ALIAS, 0, 0, v6notv9 }, /* wr %g0,rs2,%tbr */
|
|
|
|
|
{ "wr", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0|RS1_G0, "i,t", F_PREF_ALIAS, 0, 0, v6notv9 }, /* wr %g0,i,%tbr */
|
|
|
|
|
{ "wr", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0|SIMM13(~0), "1,t", F_PREF_ALIAS, 0, 0, v6notv9 }, /* wr rs1,0,%tbr */
|
|
|
|
|
{ "wr", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|ASI_RS2(~0), "1,t", F_PREF_ALIAS, 0, 0, v6notv9 }, /* wr rs1,%g0,%tbr */
|
|
|
|
|
|
|
|
|
|
{ "wr", F3(2, 0x30, 0)|RD(2), F3(~2, ~0x30, ~0)|RD(~2)|ASI(~0), "1,2,E", 0, 0, 0, v9 }, /* wr r,r,%ccr */
|
|
|
|
|
{ "wr", F3(2, 0x30, 1)|RD(2), F3(~2, ~0x30, ~1)|RD(~2), "1,i,E", 0, 0, 0, v9 }, /* wr r,i,%ccr */
|
|
|
|
|
{ "wr", F3(2, 0x30, 0)|RD(3), F3(~2, ~0x30, ~0)|RD(~3)|ASI(~0), "1,2,o", 0, 0, 0, v9 }, /* wr r,r,%asi */
|
|
|
|
|
{ "wr", F3(2, 0x30, 1)|RD(3), F3(~2, ~0x30, ~1)|RD(~3), "1,i,o", 0, 0, 0, v9 }, /* wr r,i,%asi */
|
|
|
|
|
{ "wr", F3(2, 0x30, 0)|RD(6), F3(~2, ~0x30, ~0)|RD(~6)|ASI(~0), "1,2,s", 0, 0, 0, v9 }, /* wr r,r,%fprs */
|
|
|
|
|
{ "wr", F3(2, 0x30, 1)|RD(6), F3(~2, ~0x30, ~1)|RD(~6), "1,i,s", 0, 0, 0, v9 }, /* wr r,i,%fprs */
|
opcodes,gas: adjust sparc insns and make GAS aware of it
This patch marks the SPARC instructions in the opcodes table with their
proper opcode architectures, and makes the assembler aware of them.
This allows the assembler to properly realize when a new instruction
needs a higher architecture (after v9b) and to react accordingly
emitting an error message or bumping the architecture.
It also expands architecture mismatch tests to cover architectures
higher than v9b, and fixes a couple of minor bugs in the GAS testsuite.
opcodes/ChangeLog:
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* sparc-opc.c (sparc_opcodes): Adjust instructions opcode
architecture according to the hardware capabilities they require.
(sparc_priv_regs): New table.
(sparc_hpriv_regs): Likewise.
(sparc_asr_regs): Likewise.
(v9anotv9m): Define.
gas/ChangeLog:
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-sparc.c (sparc_arch_table): adjust the GAS
architectures to use the right opcode architecture.
(sparc_md_end): Handle v9{c,d,e,v,m}.
(sparc_ip): Fix some comments.
* testsuite/gas/sparc/ldx_efsr.d: Fix the architecture of this
instruction, which is v9d.
* testsuite/gas/sparc/mwait.s: Remove the `rd %mwait,%g1'
instruction from the test, as %mwait is not readable.
* testsuite/gas/sparc/mwait.d: Likewise.
* testsuite/gas/sparc/mism-1.s: Expand to check v9b and v9e
mismatch architecture errors.
* testsuite/gas/sparc/mism-2.s: New file.
2016-06-17 17:14:18 +08:00
|
|
|
|
{ "wr", F3(2, 0x30, 0)|RD(14), F3(~2, ~0x30, ~0)|RD(~14), "1,2,{", 0, 0, HWCAP2_SPARC5, v9m }, /* wr r,r,%mcdper */
|
|
|
|
|
{ "wr", F3(2, 0x30, 1)|RD(14), F3(~2, ~0x30, ~1)|RD(~14), "1,i,{", 0, 0, HWCAP2_SPARC5, v9m }, /* wr r,i,%mcdper */
|
2014-10-09 20:16:53 +08:00
|
|
|
|
|
opcodes,gas: sparc: fix rdasr,wrasr,rdpr,wrpr,rdhpr,wrhpr insns.
This patch fixes and expands the definition of the read/write
instructions for ancillary-state, privileged and hyperprivileged
registers in opcodes.
It also adds support for three new v9m hyperprivileged registers:
%hmcdper, %hmcddfr and %hva_mask_nz.
Finally, the patch expands existing tests (and adds several new ones) in
order to cover all the read/write instructions in all its variants.
opcodes/ChangeLog:
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* sparc-opc.c (rdasr): New macro.
(wrasr): Likewise.
(rdpr): Likewise.
(wrpr): Likewise.
(rdhpr): Likewise.
(wrhpr): Likewise.
(sparc_opcodes): Use the macros above to fix and expand the
definition of read/write instructions from/to
asr/privileged/hyperprivileged instructions.
* sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
%hva_mask_nz. Prefer softint_set and softint_clear over
set_softint and clear_softint.
(print_insn_sparc): Support %ver in Rd.
gas/ChangeLog:
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-sparc.c (hpriv_reg_table): Add registers %hmcdper,
%hmcddfr and %hva_mask_nz.
(sparc_ip): New handling of asr/privileged/hyperprivileged
registers, adapted to the new form of the sparc opcodes table.
* testsuite/gas/sparc/rdasr.s: New file.
* testsuite/gas/sparc/rdasr.d: Likewise.
* testsuite/gas/sparc/wrasr.s: Likewise.
* testsuite/gas/sparc/wrasr.d: Likewise.
* testsuite/gas/sparc/sparc.exp (sparc_elf_setup): Add rdasr and
wrasr tests.
* testsuite/gas/sparc/rdpr.d: Use -Av9m, as some privileged
registers require it.
* testsuite/gas/sparc/wrpr.s: Complete to cover all privileged
registers and write instruction modalities.
* testsuite/gas/sparc/wrpr.d: Likewise.
* testsuite/gas/sparc/rdhpr.s: Likewise for hyperprivileged
registers.
* testsuite/gas/sparc/rdhpr.d: Likewise.
* testsuite/gas/sparc/wrhpr.s: Likewise.
* testsuite/gas/sparc/wrhpr.d: Likewise.
2016-06-17 17:15:43 +08:00
|
|
|
|
/* Write to ASR registers 16..31, which is the range defined in SPARC
|
|
|
|
|
V9 for implementation-dependent uses. Note that the read-only ASR
|
|
|
|
|
registers can't be used in a `wr' instruction. */
|
|
|
|
|
|
|
|
|
|
#define wrasr(asr,hwcap,hwcap2,arch) \
|
|
|
|
|
{ "wr", F3(2, 0x30, 0)|RD((asr)), F3(~2, ~0x30, ~0)|RD(~(asr))|ASI(~0), "1,2,_", 0, (hwcap), (hwcap2), (arch) }, /* wr r,r,%asr */ \
|
|
|
|
|
{ "wr", F3(2, 0x30, 1)|RD((asr)), F3(~2, ~0x30, ~1)|RD(~(asr)), "1,i,_", 0, (hwcap), (hwcap2), (arch) }, /* wr r,i,%asr */ \
|
|
|
|
|
{ "wr", F3(2, 0x30, 1)|RD((asr)), F3(~2, ~0x30, ~1)|RD(~(asr)), "i,1,_", F_ALIAS, (hwcap), (hwcap2), (arch) } /* wr i,r,%asr */
|
|
|
|
|
|
|
|
|
|
wrasr (16, HWCAP_VIS, 0, v9a), /* wr ...,%pcr */
|
|
|
|
|
wrasr (17, HWCAP_VIS, 0, v9a), /* wr ...,%pic */
|
|
|
|
|
wrasr (18, HWCAP_VIS, 0, v9a), /* wr ...,%dcr */
|
|
|
|
|
wrasr (19, HWCAP_VIS, 0, v9a), /* wr ...,%gsr */
|
|
|
|
|
wrasr (20, HWCAP_VIS, 0, v9a), /* wr ...,%softint_set */
|
|
|
|
|
wrasr (21, HWCAP_VIS, 0, v9a), /* wr ...,%softint_clear */
|
|
|
|
|
wrasr (22, HWCAP_VIS, 0, v9a), /* wr ...,%softint */
|
|
|
|
|
wrasr (23, HWCAP_VIS, 0, v9a), /* wr ...,%tick_cmpr */
|
|
|
|
|
wrasr (24, HWCAP_VIS2, 0, v9b), /* wr ...,%sys_tick */
|
|
|
|
|
wrasr (25, HWCAP_VIS2, 0, v9b), /* wr ...,%sys_tick_cmpr */
|
|
|
|
|
wrasr (26, HWCAP_CBCOND, 0, v9e), /* wr ...,%cfr */
|
|
|
|
|
wrasr (27, HWCAP_PAUSE, 0, v9e), /* wr ...,%pause */
|
|
|
|
|
wrasr (28, 0, HWCAP2_MWAIT, v9m), /* wr ...,%mwait */
|
2014-10-09 20:16:53 +08:00
|
|
|
|
|
opcodes,gas: adjust sparc insns and make GAS aware of it
This patch marks the SPARC instructions in the opcodes table with their
proper opcode architectures, and makes the assembler aware of them.
This allows the assembler to properly realize when a new instruction
needs a higher architecture (after v9b) and to react accordingly
emitting an error message or bumping the architecture.
It also expands architecture mismatch tests to cover architectures
higher than v9b, and fixes a couple of minor bugs in the GAS testsuite.
opcodes/ChangeLog:
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* sparc-opc.c (sparc_opcodes): Adjust instructions opcode
architecture according to the hardware capabilities they require.
(sparc_priv_regs): New table.
(sparc_hpriv_regs): Likewise.
(sparc_asr_regs): Likewise.
(v9anotv9m): Define.
gas/ChangeLog:
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-sparc.c (sparc_arch_table): adjust the GAS
architectures to use the right opcode architecture.
(sparc_md_end): Handle v9{c,d,e,v,m}.
(sparc_ip): Fix some comments.
* testsuite/gas/sparc/ldx_efsr.d: Fix the architecture of this
instruction, which is v9d.
* testsuite/gas/sparc/mwait.s: Remove the `rd %mwait,%g1'
instruction from the test, as %mwait is not readable.
* testsuite/gas/sparc/mwait.d: Likewise.
* testsuite/gas/sparc/mism-1.s: Expand to check v9b and v9e
mismatch architecture errors.
* testsuite/gas/sparc/mism-2.s: New file.
2016-06-17 17:14:18 +08:00
|
|
|
|
{ "pause", F3(2, 0x30, 1)|RD(27)|RS1(0), F3(~2, ~0x30, ~1)|RD(~27)|RS1(~0), "i", 0, HWCAP_PAUSE, 0, v9e }, /* wr %g0,i,%pause */
|
2014-10-09 20:16:53 +08:00
|
|
|
|
|
|
|
|
|
{ "rd", F3(2, 0x28, 0)|RS1(2), F3(~2, ~0x28, ~0)|RS1(~2)|SIMM13(~0), "E,d", 0, 0, 0, v9 }, /* rd %ccr,r */
|
|
|
|
|
{ "rd", F3(2, 0x28, 0)|RS1(3), F3(~2, ~0x28, ~0)|RS1(~3)|SIMM13(~0), "o,d", 0, 0, 0, v9 }, /* rd %asi,r */
|
|
|
|
|
{ "rd", F3(2, 0x28, 0)|RS1(4), F3(~2, ~0x28, ~0)|RS1(~4)|SIMM13(~0), "W,d", 0, 0, 0, v9 }, /* rd %tick,r */
|
|
|
|
|
{ "rd", F3(2, 0x28, 0)|RS1(5), F3(~2, ~0x28, ~0)|RS1(~5)|SIMM13(~0), "P,d", 0, 0, 0, v9 }, /* rd %pc,r */
|
|
|
|
|
{ "rd", F3(2, 0x28, 0)|RS1(6), F3(~2, ~0x28, ~0)|RS1(~6)|SIMM13(~0), "s,d", 0, 0, 0, v9 }, /* rd %fprs,r */
|
opcodes,gas: adjust sparc insns and make GAS aware of it
This patch marks the SPARC instructions in the opcodes table with their
proper opcode architectures, and makes the assembler aware of them.
This allows the assembler to properly realize when a new instruction
needs a higher architecture (after v9b) and to react accordingly
emitting an error message or bumping the architecture.
It also expands architecture mismatch tests to cover architectures
higher than v9b, and fixes a couple of minor bugs in the GAS testsuite.
opcodes/ChangeLog:
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* sparc-opc.c (sparc_opcodes): Adjust instructions opcode
architecture according to the hardware capabilities they require.
(sparc_priv_regs): New table.
(sparc_hpriv_regs): Likewise.
(sparc_asr_regs): Likewise.
(v9anotv9m): Define.
gas/ChangeLog:
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-sparc.c (sparc_arch_table): adjust the GAS
architectures to use the right opcode architecture.
(sparc_md_end): Handle v9{c,d,e,v,m}.
(sparc_ip): Fix some comments.
* testsuite/gas/sparc/ldx_efsr.d: Fix the architecture of this
instruction, which is v9d.
* testsuite/gas/sparc/mwait.s: Remove the `rd %mwait,%g1'
instruction from the test, as %mwait is not readable.
* testsuite/gas/sparc/mwait.d: Likewise.
* testsuite/gas/sparc/mism-1.s: Expand to check v9b and v9e
mismatch architecture errors.
* testsuite/gas/sparc/mism-2.s: New file.
2016-06-17 17:14:18 +08:00
|
|
|
|
{ "rd", F3(2, 0x28, 0)|RS1(14), F3(~2, ~0x28, ~0)|RS1(~14)|SIMM13(~0), "{,d", 0, 0, HWCAP2_SPARC5, v9m }, /* rd %mcdper,r */
|
2014-10-09 20:16:53 +08:00
|
|
|
|
|
opcodes,gas: sparc: fix rdasr,wrasr,rdpr,wrpr,rdhpr,wrhpr insns.
This patch fixes and expands the definition of the read/write
instructions for ancillary-state, privileged and hyperprivileged
registers in opcodes.
It also adds support for three new v9m hyperprivileged registers:
%hmcdper, %hmcddfr and %hva_mask_nz.
Finally, the patch expands existing tests (and adds several new ones) in
order to cover all the read/write instructions in all its variants.
opcodes/ChangeLog:
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* sparc-opc.c (rdasr): New macro.
(wrasr): Likewise.
(rdpr): Likewise.
(wrpr): Likewise.
(rdhpr): Likewise.
(wrhpr): Likewise.
(sparc_opcodes): Use the macros above to fix and expand the
definition of read/write instructions from/to
asr/privileged/hyperprivileged instructions.
* sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
%hva_mask_nz. Prefer softint_set and softint_clear over
set_softint and clear_softint.
(print_insn_sparc): Support %ver in Rd.
gas/ChangeLog:
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-sparc.c (hpriv_reg_table): Add registers %hmcdper,
%hmcddfr and %hva_mask_nz.
(sparc_ip): New handling of asr/privileged/hyperprivileged
registers, adapted to the new form of the sparc opcodes table.
* testsuite/gas/sparc/rdasr.s: New file.
* testsuite/gas/sparc/rdasr.d: Likewise.
* testsuite/gas/sparc/wrasr.s: Likewise.
* testsuite/gas/sparc/wrasr.d: Likewise.
* testsuite/gas/sparc/sparc.exp (sparc_elf_setup): Add rdasr and
wrasr tests.
* testsuite/gas/sparc/rdpr.d: Use -Av9m, as some privileged
registers require it.
* testsuite/gas/sparc/wrpr.s: Complete to cover all privileged
registers and write instruction modalities.
* testsuite/gas/sparc/wrpr.d: Likewise.
* testsuite/gas/sparc/rdhpr.s: Likewise for hyperprivileged
registers.
* testsuite/gas/sparc/rdhpr.d: Likewise.
* testsuite/gas/sparc/wrhpr.s: Likewise.
* testsuite/gas/sparc/wrhpr.d: Likewise.
2016-06-17 17:15:43 +08:00
|
|
|
|
/* Read from ASR registers 16..31, which is the range defined in SPARC
|
|
|
|
|
V9 for implementation-dependent uses. Note that the write-only ASR
|
|
|
|
|
registers can't be used in a `rd' instruction. */
|
|
|
|
|
|
|
|
|
|
#define rdasr(asr,hwcap,hwcap2,arch) \
|
|
|
|
|
{ "rd", F3(2, 0x28, 0)|RS1((asr)), F3(~2, ~0x28, ~0)|RS1(~(asr))|SIMM13(~0), "/,d", 0, (hwcap), (hwcap2), (arch) }
|
|
|
|
|
|
|
|
|
|
rdasr (16, HWCAP_VIS, 0, v9a), /* rd %pcr,r */
|
|
|
|
|
rdasr (17, HWCAP_VIS, 0, v9a), /* rd %pic,r */
|
|
|
|
|
rdasr (18, HWCAP_VIS, 0, v9a), /* rd %dcr,r */
|
|
|
|
|
rdasr (19, HWCAP_VIS, 0, v9a), /* rd %gsr,r */
|
|
|
|
|
rdasr (22, HWCAP_VIS, 0, v9a), /* rd %softint,r */
|
|
|
|
|
rdasr (23, HWCAP_VIS, 0, v9a), /* rd %tick_cmpr,r */
|
|
|
|
|
rdasr (24, HWCAP_VIS2, 0, v9b), /* rd %sys_tick,r */
|
|
|
|
|
rdasr (25, HWCAP_VIS2, 0, v9b), /* rd %sys_tick_cmpr,r */
|
|
|
|
|
rdasr (26, HWCAP_CBCOND, 0, v9e), /* rd %cfr,r */
|
2014-10-09 20:16:53 +08:00
|
|
|
|
|
2016-03-25 01:20:45 +08:00
|
|
|
|
{ "rd", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|SIMM13(~0), "M,d", 0, 0, 0, v8 }, /* rd %asrX,r */
|
|
|
|
|
{ "rd", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|RS1_G0|SIMM13(~0), "y,d", 0, 0, 0, v6 }, /* rd %y,r */
|
|
|
|
|
{ "rd", F3(2, 0x29, 0), F3(~2, ~0x29, ~0)|RS1_G0|SIMM13(~0), "p,d", 0, 0, 0, v6notv9 }, /* rd %psr,r */
|
|
|
|
|
{ "rd", F3(2, 0x2a, 0), F3(~2, ~0x2a, ~0)|RS1_G0|SIMM13(~0), "w,d", 0, 0, 0, v6notv9 }, /* rd %wim,r */
|
|
|
|
|
{ "rd", F3(2, 0x2b, 0), F3(~2, ~0x2b, ~0)|RS1_G0|SIMM13(~0), "t,d", 0, 0, 0, v6notv9 }, /* rd %tbr,r */
|
|
|
|
|
|
opcodes,gas: sparc: fix rdasr,wrasr,rdpr,wrpr,rdhpr,wrhpr insns.
This patch fixes and expands the definition of the read/write
instructions for ancillary-state, privileged and hyperprivileged
registers in opcodes.
It also adds support for three new v9m hyperprivileged registers:
%hmcdper, %hmcddfr and %hva_mask_nz.
Finally, the patch expands existing tests (and adds several new ones) in
order to cover all the read/write instructions in all its variants.
opcodes/ChangeLog:
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* sparc-opc.c (rdasr): New macro.
(wrasr): Likewise.
(rdpr): Likewise.
(wrpr): Likewise.
(rdhpr): Likewise.
(wrhpr): Likewise.
(sparc_opcodes): Use the macros above to fix and expand the
definition of read/write instructions from/to
asr/privileged/hyperprivileged instructions.
* sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
%hva_mask_nz. Prefer softint_set and softint_clear over
set_softint and clear_softint.
(print_insn_sparc): Support %ver in Rd.
gas/ChangeLog:
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-sparc.c (hpriv_reg_table): Add registers %hmcdper,
%hmcddfr and %hva_mask_nz.
(sparc_ip): New handling of asr/privileged/hyperprivileged
registers, adapted to the new form of the sparc opcodes table.
* testsuite/gas/sparc/rdasr.s: New file.
* testsuite/gas/sparc/rdasr.d: Likewise.
* testsuite/gas/sparc/wrasr.s: Likewise.
* testsuite/gas/sparc/wrasr.d: Likewise.
* testsuite/gas/sparc/sparc.exp (sparc_elf_setup): Add rdasr and
wrasr tests.
* testsuite/gas/sparc/rdpr.d: Use -Av9m, as some privileged
registers require it.
* testsuite/gas/sparc/wrpr.s: Complete to cover all privileged
registers and write instruction modalities.
* testsuite/gas/sparc/wrpr.d: Likewise.
* testsuite/gas/sparc/rdhpr.s: Likewise for hyperprivileged
registers.
* testsuite/gas/sparc/rdhpr.d: Likewise.
* testsuite/gas/sparc/wrhpr.s: Likewise.
* testsuite/gas/sparc/wrhpr.d: Likewise.
2016-06-17 17:15:43 +08:00
|
|
|
|
/* Instructions to read and write from/to privileged registers. */
|
|
|
|
|
|
|
|
|
|
#define rdpr(reg,hwcap,hwcap2,arch) \
|
|
|
|
|
{ "rdpr", F3(2, 0x2a, 0)|RS1((reg)), F3(~2, ~0x2a, ~0)|RS1(~(reg))|SIMM13(~0),"?,d", 0, (hwcap), (hwcap2), (arch) } /* rdpr %priv,r */
|
|
|
|
|
|
|
|
|
|
rdpr (0, 0, 0, v9), /* rdpr %tpc,r */
|
|
|
|
|
rdpr (1, 0, 0, v9), /* rdpr %tnpc,r */
|
|
|
|
|
rdpr (2, 0, 0, v9), /* rdpr %tstate,r */
|
|
|
|
|
rdpr (3, 0, 0, v9), /* rdpr %tt,r */
|
|
|
|
|
rdpr (4, 0, 0, v9), /* rdpr %tick,r */
|
|
|
|
|
rdpr (5, 0, 0, v9), /* rdpr %tba,r */
|
|
|
|
|
rdpr (6, 0, 0, v9), /* rdpr %pstate,r */
|
|
|
|
|
rdpr (7, 0, 0, v9), /* rdpr %tl,r */
|
|
|
|
|
rdpr (8, 0, 0, v9), /* rdpr %pil,r */
|
|
|
|
|
rdpr (9, 0, 0, v9), /* rdpr %cwp,r */
|
|
|
|
|
rdpr (10, 0, 0, v9), /* rdpr %cansave,r */
|
|
|
|
|
rdpr (11, 0, 0, v9), /* rdpr %canrestore,r */
|
|
|
|
|
rdpr (12, 0, 0, v9), /* rdpr %cleanwin,r */
|
|
|
|
|
rdpr (13, 0, 0, v9), /* rdpr %otherwin,r */
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rdpr (14, 0, 0, v9), /* rdpr %wstate,r */
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rdpr (15, 0, 0, v9), /* rdpr %fq,r */
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rdpr (16, 0, 0, v9), /* rdpr %gl,r */
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rdpr (23, 0, HWCAP2_SPARC5, v9m), /* rdpr %pmcdper,r */
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rdpr (31, 0, 0, v9), /* rdpr %ver,r */
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#define wrpr(reg,hwcap,hwcap2,arch) \
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{ "wrpr", F3(2, 0x32, 0)|RD((reg)), F3(~2, ~0x32, ~0)|RD(~(reg)), "1,2,!", 0, (hwcap), (hwcap2), (arch) }, /* wrpr r1,r2,%priv */ \
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{ "wrpr", F3(2, 0x32, 0)|RD((reg)), F3(~2, ~0x32, ~0)|RD(~(reg))|SIMM13(~0), "1,!", 0, (hwcap), (hwcap2), (arch) }, /* wrpr r1,%priv */ \
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{ "wrpr", F3(2, 0x32, 1)|RD((reg)), F3(~2, ~0x32, ~1)|RD(~(reg)), "1,i,!", 0, (hwcap), (hwcap2), (arch) }, /* wrpr r1,i,%priv */ \
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{ "wrpr", F3(2, 0x32, 1)|RD((reg)), F3(~2, ~0x32, ~1)|RD(~(reg)), "i,1,!", F_ALIAS, (hwcap), (hwcap2), (arch) }, /* wrpr i,r1,%priv */ \
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{ "wrpr", F3(2, 0x32, 1)|RD((reg)), F3(~2, ~0x32, ~1)|RD(~(reg))|RS1(~0), "i,!", 0, (hwcap), (hwcap2), (arch) } /* wrpr i,%priv */
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wrpr (0, 0, 0, v9), /* wrpr ...,%tpc */
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wrpr (1, 0, 0, v9), /* wrpr ...,%tnpc */
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wrpr (2, 0, 0, v9), /* wrpr ...,%tstate */
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wrpr (3, 0, 0, v9), /* wrpr ...,%tt */
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wrpr (4, 0, 0, v9), /* wrpr ...,%tick */
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wrpr (5, 0, 0, v9), /* wrpr ...,%tba */
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wrpr (6, 0, 0, v9), /* wrpr ...,%pstate */
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wrpr (7, 0, 0, v9), /* wrpr ...,%tl */
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wrpr (8, 0, 0, v9), /* wrpr ...,%pil */
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wrpr (9, 0, 0, v9), /* wrpr ...,%cwp */
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wrpr (10, 0, 0, v9), /* wrpr ...,%cansave */
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wrpr (11, 0, 0, v9), /* wrpr ...,%canrestore */
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wrpr (12, 0, 0, v9), /* wrpr ...,%cleanwin */
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wrpr (13, 0, 0, v9), /* wrpr ...,%otherwin */
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wrpr (14, 0, 0, v9), /* wrpr ...,%wstate */
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wrpr (15, 0, 0, v9), /* wrpr ...,%fq */
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wrpr (16, 0, 0, v9), /* wrpr ...,%gl */
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wrpr (23, 0, HWCAP2_SPARC5, v9m), /* wdpr ...,%pmcdper */
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wrpr (31, 0, 0, v9), /* wrpr ...,%ver */
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/* Instructions to read and write from/to hyperprivileged
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registers. */
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#define rdhpr(reg,hwcap,hwcap2,arch) \
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{ "rdhpr", F3(2, 0x29, 0)|RS1((reg)), F3(~2, ~0x29, ~0)|RS1(~(reg))|SIMM13(~0), "$,d", 0, (hwcap), (hwcap2), (arch) }
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rdhpr (0, HWCAP_VIS, 0, v9a), /* rdhpr %hpstate,r */
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rdhpr (1, HWCAP_VIS, 0, v9a), /* rdhpr %htstate,r */
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rdhpr (3, HWCAP_VIS, 0, v9a), /* rdhpr %hintp,r */
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rdhpr (5, HWCAP_VIS, 0, v9a), /* rdhpr %htba,r */
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rdhpr (6, HWCAP_VIS, 0, v9a), /* rdhpr %hver,r */
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rdhpr (23, 0, HWCAP2_SPARC5, v9m), /* rdhpr %hmcdper,r */
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rdhpr (24, 0, HWCAP2_SPARC5, v9m), /* rdhpr %hmcddfr,r */
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rdhpr (27, 0, HWCAP2_SPARC5, v9m), /* rdhpr %hva_mask_nz,r */
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rdhpr (28, HWCAP_VIS, 0, v9a), /* rdhpr %hstick_offset,r */
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rdhpr (29, HWCAP_VIS, 0, v9a), /* rdhpar %hstick_enable,r */
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rdhpr (31, HWCAP_VIS, 0, v9a), /* rdhpr %hstick_cmpr,r */
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#define wrhpr(reg,hwcap,hwcap2,arch) \
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{ "wrhpr", F3(2, 0x33, 0)|RD((reg)), F3(~2, ~0x33, ~0)|RD(~(reg)),"1,2,%", 0, (hwcap), (hwcap2), (arch) }, /* wrhpr r1,r2,%hpriv */ \
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{ "wrhpr", F3(2, 0x33, 0)|RD((reg)), F3(~2, ~0x33, ~0)|RD(~(reg))|SIMM13(~0), "1,%", 0, (hwcap), (hwcap2), (arch) }, /* wrhpr r1,%hpriv */ \
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{ "wrhpr", F3(2, 0x33, 1)|RD((reg)), F3(~2, ~0x33, ~1)|RD(~(reg)), "1,i,%", 0, (hwcap), (hwcap2), (arch) }, /* wrhpr r1,i,%hpriv */ \
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{ "wrhpr", F3(2, 0x33, 1)|RD((reg)), F3(~2, ~0x33, ~1)|RD(~(reg)), "i,1,%", F_ALIAS, (hwcap), (hwcap2), (arch) }, /* wrhpr i,r1,%hpriv */ \
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{ "wrhpr", F3(2, 0x33, 1)|RD((reg)), F3(~2, ~0x33, ~1)|RD(~(reg))|RS1(~0), "i,%", 0, (hwcap), (hwcap2), (arch) } /* wrhpr i,%hpriv */
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wrhpr (0, HWCAP_VIS, 0, v9a), /* wrhpr ...,%hpstate */
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wrhpr (1, HWCAP_VIS, 0, v9a), /* wrhpr ...,%htstate */
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wrhpr (3, HWCAP_VIS, 0, v9a), /* wrhpr ...,%hintp */
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wrhpr (5, HWCAP_VIS, 0, v9a), /* wrhpr ...,%htba */
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wrhpr (23, 0, HWCAP2_SPARC5, v9m), /* wrhpr ...,%hmcdper */
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wrhpr (24, 0, HWCAP2_SPARC5, v9m), /* wrhpr ...,%hmcddfr */
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wrhpr (27, 0, HWCAP2_SPARC5, v9m), /* wrhpr ...,%hva_mask_nz */
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wrhpr (28, HWCAP_VIS, 0, v9a), /* wrhpr ...,%hstick_offset */
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wrhpr (29, HWCAP_VIS, 0, v9a), /* wrhpr ...,%hstick_enable */
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wrhpr (31, HWCAP_VIS, 0, v9a), /* wrhpr ...,%hstick_cmpr */
|
2014-10-09 20:16:53 +08:00
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{ "mov", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|SIMM13(~0), "M,d", F_ALIAS, 0, 0, v8 }, /* rd %asr1,r */
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{ "mov", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|RS1_G0|SIMM13(~0), "y,d", F_ALIAS, 0, 0, v6 }, /* rd %y,r */
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{ "mov", F3(2, 0x29, 0), F3(~2, ~0x29, ~0)|RS1_G0|SIMM13(~0), "p,d", F_ALIAS, 0, 0, v6notv9 }, /* rd %psr,r */
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{ "mov", F3(2, 0x2a, 0), F3(~2, ~0x2a, ~0)|RS1_G0|SIMM13(~0), "w,d", F_ALIAS, 0, 0, v6notv9 }, /* rd %wim,r */
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{ "mov", F3(2, 0x2b, 0), F3(~2, ~0x2b, ~0)|RS1_G0|SIMM13(~0), "t,d", F_ALIAS, 0, 0, v6notv9 }, /* rd %tbr,r */
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{ "mov", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RS1_G0|ASI(~0), "2,m", F_ALIAS, 0, 0, v8 }, /* wr %g0,rs2,%asrX */
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{ "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RS1_G0, "i,m", F_ALIAS, 0, 0, v8 }, /* wr %g0,i,%asrX */
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{ "mov", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|RS1_G0|ASI(~0), "2,y", F_ALIAS, 0, 0, v6 }, /* wr %g0,rs2,%y */
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{ "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0|RS1_G0, "i,y", F_ALIAS, 0, 0, v6 }, /* wr %g0,i,%y */
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{ "mov", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|RS1_G0|ASI(~0), "2,p", F_ALIAS, 0, 0, v6notv9 }, /* wr %g0,rs2,%psr */
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{ "mov", F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0|RS1_G0, "i,p", F_ALIAS, 0, 0, v6notv9 }, /* wr %g0,i,%psr */
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|
{ "mov", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|RS1_G0|ASI(~0), "2,w", F_ALIAS, 0, 0, v6notv9 }, /* wr %g0,rs2,%wim */
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{ "mov", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0|RS1_G0, "i,w", F_ALIAS, 0, 0, v6notv9 }, /* wr %g0,i,%wim */
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|
{ "mov", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|RS1_G0|ASI(~0), "2,t", F_ALIAS, 0, 0, v6notv9 }, /* wr %g0,rs2,%tbr */
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|
{ "mov", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0|RS1_G0, "i,t", F_ALIAS, 0, 0, v6notv9 }, /* wr %g0,i,%tbr */
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{ "mov", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|RS1_G0|ASI(~0), "2,d", 0, 0, 0, v6 }, /* or %g0,rs2,d */
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{ "mov", F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|RS1_G0, "i,d", 0, 0, 0, v6 }, /* or %g0,i,d */
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|
{ "mov", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|ASI_RS2(~0), "1,d", 0, 0, 0, v6 }, /* or rs1,%g0,d */
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|
|
{ "mov", F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|SIMM13(~0), "1,d", 0, 0, 0, v6 }, /* or rs1,0,d */
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{ "or", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6 },
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|
{ "or", F3(2, 0x02, 1), F3(~2, ~0x02, ~1), "1,i,d", 0, 0, 0, v6 },
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|
{ "or", F3(2, 0x02, 1), F3(~2, ~0x02, ~1), "i,1,d", 0, 0, 0, v6 },
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{ "bset", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|ASI(~0), "2,r", F_ALIAS, 0, 0, v6 }, /* or rd,rs2,rd */
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|
|
{ "bset", F3(2, 0x02, 1), F3(~2, ~0x02, ~1), "i,r", F_ALIAS, 0, 0, v6 }, /* or rd,i,rd */
|
1999-05-03 15:29:11 +08:00
|
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|
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|
|
/* This is not a commutative instruction. */
|
2014-10-09 20:16:53 +08:00
|
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|
|
{ "andn", F3(2, 0x05, 0), F3(~2, ~0x05, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6 },
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|
|
{ "andn", F3(2, 0x05, 1), F3(~2, ~0x05, ~1), "1,i,d", 0, 0, 0, v6 },
|
1999-05-03 15:29:11 +08:00
|
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|
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|
|
/* This is not a commutative instruction. */
|
2014-10-09 20:16:53 +08:00
|
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|
|
{ "andncc", F3(2, 0x15, 0), F3(~2, ~0x15, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6 },
|
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|
|
{ "andncc", F3(2, 0x15, 1), F3(~2, ~0x15, ~1), "1,i,d", 0, 0, 0, v6 },
|
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|
|
{ "bclr", F3(2, 0x05, 0), F3(~2, ~0x05, ~0)|ASI(~0), "2,r", F_ALIAS, 0, 0, v6 }, /* andn rd,rs2,rd */
|
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|
|
{ "bclr", F3(2, 0x05, 1), F3(~2, ~0x05, ~1), "i,r", F_ALIAS, 0, 0, v6 }, /* andn rd,i,rd */
|
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|
|
{ "cmp", F3(2, 0x14, 0), F3(~2, ~0x14, ~0)|RD_G0|ASI(~0), "1,2", 0, 0, 0, v6 }, /* subcc rs1,rs2,%g0 */
|
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|
|
{ "cmp", F3(2, 0x14, 1), F3(~2, ~0x14, ~1)|RD_G0, "1,i", 0, 0, 0, v6 }, /* subcc rs1,i,%g0 */
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|
|
{ "sub", F3(2, 0x04, 0), F3(~2, ~0x04, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6 },
|
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|
|
{ "sub", F3(2, 0x04, 1), F3(~2, ~0x04, ~1), "1,i,d", 0, 0, 0, v6 },
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|
{ "subcc", F3(2, 0x14, 0), F3(~2, ~0x14, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6 },
|
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|
|
{ "subcc", F3(2, 0x14, 1), F3(~2, ~0x14, ~1), "1,i,d", 0, 0, 0, v6 },
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|
{ "subx", F3(2, 0x0c, 0), F3(~2, ~0x0c, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6notv9 },
|
|
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|
|
{ "subx", F3(2, 0x0c, 1), F3(~2, ~0x0c, ~1), "1,i,d", 0, 0, 0, v6notv9 },
|
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|
|
{ "subc", F3(2, 0x0c, 0), F3(~2, ~0x0c, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v9 },
|
|
|
|
|
{ "subc", F3(2, 0x0c, 1), F3(~2, ~0x0c, ~1), "1,i,d", 0, 0, 0, v9 },
|
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|
|
{ "subxcc", F3(2, 0x1c, 0), F3(~2, ~0x1c, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6notv9 },
|
|
|
|
|
{ "subxcc", F3(2, 0x1c, 1), F3(~2, ~0x1c, ~1), "1,i,d", 0, 0, 0, v6notv9 },
|
|
|
|
|
{ "subccc", F3(2, 0x1c, 0), F3(~2, ~0x1c, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v9 },
|
|
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|
|
{ "subccc", F3(2, 0x1c, 1), F3(~2, ~0x1c, ~1), "1,i,d", 0, 0, 0, v9 },
|
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|
{ "and", F3(2, 0x01, 0), F3(~2, ~0x01, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6 },
|
|
|
|
|
{ "and", F3(2, 0x01, 1), F3(~2, ~0x01, ~1), "1,i,d", 0, 0, 0, v6 },
|
|
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|
|
{ "and", F3(2, 0x01, 1), F3(~2, ~0x01, ~1), "i,1,d", 0, 0, 0, v6 },
|
|
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|
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|
|
{ "andcc", F3(2, 0x11, 0), F3(~2, ~0x11, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6 },
|
|
|
|
|
{ "andcc", F3(2, 0x11, 1), F3(~2, ~0x11, ~1), "1,i,d", 0, 0, 0, v6 },
|
|
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|
|
{ "andcc", F3(2, 0x11, 1), F3(~2, ~0x11, ~1), "i,1,d", 0, 0, 0, v6 },
|
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|
|
|
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|
|
{ "dec", F3(2, 0x04, 1)|SIMM13(0x1), F3(~2, ~0x04, ~1)|SIMM13(~0x0001), "r", F_ALIAS, 0, 0, v6 }, /* sub rd,1,rd */
|
|
|
|
|
{ "dec", F3(2, 0x04, 1), F3(~2, ~0x04, ~1), "i,r", F_ALIAS, 0, 0, v8 }, /* sub rd,imm,rd */
|
|
|
|
|
{ "deccc", F3(2, 0x14, 1)|SIMM13(0x1), F3(~2, ~0x14, ~1)|SIMM13(~0x0001), "r", F_ALIAS, 0, 0, v6 }, /* subcc rd,1,rd */
|
|
|
|
|
{ "deccc", F3(2, 0x14, 1), F3(~2, ~0x14, ~1), "i,r", F_ALIAS, 0, 0, v8 }, /* subcc rd,imm,rd */
|
|
|
|
|
{ "inc", F3(2, 0x00, 1)|SIMM13(0x1), F3(~2, ~0x00, ~1)|SIMM13(~0x0001), "r", F_ALIAS, 0, 0, v6 }, /* add rd,1,rd */
|
|
|
|
|
{ "inc", F3(2, 0x00, 1), F3(~2, ~0x00, ~1), "i,r", F_ALIAS, 0, 0, v8 }, /* add rd,imm,rd */
|
|
|
|
|
{ "inccc", F3(2, 0x10, 1)|SIMM13(0x1), F3(~2, ~0x10, ~1)|SIMM13(~0x0001), "r", F_ALIAS, 0, 0, v6 }, /* addcc rd,1,rd */
|
|
|
|
|
{ "inccc", F3(2, 0x10, 1), F3(~2, ~0x10, ~1), "i,r", F_ALIAS, 0, 0, v8 }, /* addcc rd,imm,rd */
|
|
|
|
|
|
|
|
|
|
{ "btst", F3(2, 0x11, 0), F3(~2, ~0x11, ~0)|RD_G0|ASI(~0), "1,2", F_ALIAS, 0, 0, v6 }, /* andcc rs1,rs2,%g0 */
|
|
|
|
|
{ "btst", F3(2, 0x11, 1), F3(~2, ~0x11, ~1)|RD_G0, "i,1", F_ALIAS, 0, 0, v6 }, /* andcc rs1,i,%g0 */
|
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|
|
{ "neg", F3(2, 0x04, 0), F3(~2, ~0x04, ~0)|RS1_G0|ASI(~0), "2,d", F_ALIAS, 0, 0, v6 }, /* sub %g0,rs2,rd */
|
|
|
|
|
{ "neg", F3(2, 0x04, 0), F3(~2, ~0x04, ~0)|RS1_G0|ASI(~0), "O", F_ALIAS, 0, 0, v6 }, /* sub %g0,rd,rd */
|
|
|
|
|
|
|
|
|
|
{ "add", F3(2, 0x00, 0), F3(~2, ~0x00, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6 },
|
|
|
|
|
{ "add", F3(2, 0x00, 1), F3(~2, ~0x00, ~1), "1,i,d", 0, 0, 0, v6 },
|
|
|
|
|
{ "add", F3(2, 0x00, 1), F3(~2, ~0x00, ~1), "i,1,d", 0, 0, 0, v6 },
|
|
|
|
|
{ "addcc", F3(2, 0x10, 0), F3(~2, ~0x10, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6 },
|
|
|
|
|
{ "addcc", F3(2, 0x10, 1), F3(~2, ~0x10, ~1), "1,i,d", 0, 0, 0, v6 },
|
|
|
|
|
{ "addcc", F3(2, 0x10, 1), F3(~2, ~0x10, ~1), "i,1,d", 0, 0, 0, v6 },
|
|
|
|
|
|
|
|
|
|
{ "addx", F3(2, 0x08, 0), F3(~2, ~0x08, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6notv9 },
|
|
|
|
|
{ "addx", F3(2, 0x08, 1), F3(~2, ~0x08, ~1), "1,i,d", 0, 0, 0, v6notv9 },
|
|
|
|
|
{ "addx", F3(2, 0x08, 1), F3(~2, ~0x08, ~1), "i,1,d", 0, 0, 0, v6notv9 },
|
|
|
|
|
{ "addc", F3(2, 0x08, 0), F3(~2, ~0x08, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v9 },
|
|
|
|
|
{ "addc", F3(2, 0x08, 1), F3(~2, ~0x08, ~1), "1,i,d", 0, 0, 0, v9 },
|
|
|
|
|
{ "addc", F3(2, 0x08, 1), F3(~2, ~0x08, ~1), "i,1,d", 0, 0, 0, v9 },
|
|
|
|
|
|
|
|
|
|
{ "addxcc", F3(2, 0x18, 0), F3(~2, ~0x18, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6notv9 },
|
|
|
|
|
{ "addxcc", F3(2, 0x18, 1), F3(~2, ~0x18, ~1), "1,i,d", 0, 0, 0, v6notv9 },
|
|
|
|
|
{ "addxcc", F3(2, 0x18, 1), F3(~2, ~0x18, ~1), "i,1,d", 0, 0, 0, v6notv9 },
|
|
|
|
|
{ "addccc", F3(2, 0x18, 0), F3(~2, ~0x18, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v9 },
|
|
|
|
|
{ "addccc", F3(2, 0x18, 1), F3(~2, ~0x18, ~1), "1,i,d", 0, 0, 0, v9 },
|
|
|
|
|
{ "addccc", F3(2, 0x18, 1), F3(~2, ~0x18, ~1), "i,1,d", 0, 0, 0, v9 },
|
|
|
|
|
|
|
|
|
|
{ "smul", F3(2, 0x0b, 0), F3(~2, ~0x0b, ~0)|ASI(~0), "1,2,d", 0, HWCAP_MUL32, 0, v8 },
|
|
|
|
|
{ "smul", F3(2, 0x0b, 1), F3(~2, ~0x0b, ~1), "1,i,d", 0, HWCAP_MUL32, 0, v8 },
|
|
|
|
|
{ "smul", F3(2, 0x0b, 1), F3(~2, ~0x0b, ~1), "i,1,d", 0, HWCAP_MUL32, 0, v8 },
|
|
|
|
|
{ "smulcc", F3(2, 0x1b, 0), F3(~2, ~0x1b, ~0)|ASI(~0), "1,2,d", 0, HWCAP_MUL32, 0, v8 },
|
|
|
|
|
{ "smulcc", F3(2, 0x1b, 1), F3(~2, ~0x1b, ~1), "1,i,d", 0, HWCAP_MUL32, 0, v8 },
|
|
|
|
|
{ "smulcc", F3(2, 0x1b, 1), F3(~2, ~0x1b, ~1), "i,1,d", 0, HWCAP_MUL32, 0, v8 },
|
|
|
|
|
{ "umul", F3(2, 0x0a, 0), F3(~2, ~0x0a, ~0)|ASI(~0), "1,2,d", 0, HWCAP_MUL32, 0, v8 },
|
|
|
|
|
{ "umul", F3(2, 0x0a, 1), F3(~2, ~0x0a, ~1), "1,i,d", 0, HWCAP_MUL32, 0, v8 },
|
|
|
|
|
{ "umul", F3(2, 0x0a, 1), F3(~2, ~0x0a, ~1), "i,1,d", 0, HWCAP_MUL32, 0, v8 },
|
|
|
|
|
{ "umulcc", F3(2, 0x1a, 0), F3(~2, ~0x1a, ~0)|ASI(~0), "1,2,d", 0, HWCAP_MUL32, 0, v8 },
|
|
|
|
|
{ "umulcc", F3(2, 0x1a, 1), F3(~2, ~0x1a, ~1), "1,i,d", 0, HWCAP_MUL32, 0, v8 },
|
|
|
|
|
{ "umulcc", F3(2, 0x1a, 1), F3(~2, ~0x1a, ~1), "i,1,d", 0, HWCAP_MUL32, 0, v8 },
|
|
|
|
|
{ "sdiv", F3(2, 0x0f, 0), F3(~2, ~0x0f, ~0)|ASI(~0), "1,2,d", 0, HWCAP_DIV32, 0, v8 },
|
|
|
|
|
{ "sdiv", F3(2, 0x0f, 1), F3(~2, ~0x0f, ~1), "1,i,d", 0, HWCAP_DIV32, 0, v8 },
|
|
|
|
|
{ "sdiv", F3(2, 0x0f, 1), F3(~2, ~0x0f, ~1), "i,1,d", 0, HWCAP_DIV32, 0, v8 },
|
|
|
|
|
{ "sdivcc", F3(2, 0x1f, 0), F3(~2, ~0x1f, ~0)|ASI(~0), "1,2,d", 0, HWCAP_DIV32, 0, v8 },
|
|
|
|
|
{ "sdivcc", F3(2, 0x1f, 1), F3(~2, ~0x1f, ~1), "1,i,d", 0, HWCAP_DIV32, 0, v8 },
|
|
|
|
|
{ "sdivcc", F3(2, 0x1f, 1), F3(~2, ~0x1f, ~1), "i,1,d", 0, HWCAP_DIV32, 0, v8 },
|
|
|
|
|
{ "udiv", F3(2, 0x0e, 0), F3(~2, ~0x0e, ~0)|ASI(~0), "1,2,d", 0, HWCAP_DIV32, 0, v8 },
|
|
|
|
|
{ "udiv", F3(2, 0x0e, 1), F3(~2, ~0x0e, ~1), "1,i,d", 0, HWCAP_DIV32, 0, v8 },
|
|
|
|
|
{ "udiv", F3(2, 0x0e, 1), F3(~2, ~0x0e, ~1), "i,1,d", 0, HWCAP_DIV32, 0, v8 },
|
|
|
|
|
{ "udivcc", F3(2, 0x1e, 0), F3(~2, ~0x1e, ~0)|ASI(~0), "1,2,d", 0, HWCAP_DIV32, 0, v8 },
|
|
|
|
|
{ "udivcc", F3(2, 0x1e, 1), F3(~2, ~0x1e, ~1), "1,i,d", 0, HWCAP_DIV32, 0, v8 },
|
|
|
|
|
{ "udivcc", F3(2, 0x1e, 1), F3(~2, ~0x1e, ~1), "i,1,d", 0, HWCAP_DIV32, 0, v8 },
|
|
|
|
|
|
|
|
|
|
{ "mulx", F3(2, 0x09, 0), F3(~2, ~0x09, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v9 },
|
|
|
|
|
{ "mulx", F3(2, 0x09, 1), F3(~2, ~0x09, ~1), "1,i,d", 0, 0, 0, v9 },
|
|
|
|
|
{ "sdivx", F3(2, 0x2d, 0), F3(~2, ~0x2d, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v9 },
|
|
|
|
|
{ "sdivx", F3(2, 0x2d, 1), F3(~2, ~0x2d, ~1), "1,i,d", 0, 0, 0, v9 },
|
|
|
|
|
{ "udivx", F3(2, 0x0d, 0), F3(~2, ~0x0d, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v9 },
|
|
|
|
|
{ "udivx", F3(2, 0x0d, 1), F3(~2, ~0x0d, ~1), "1,i,d", 0, 0, 0, v9 },
|
|
|
|
|
|
|
|
|
|
{ "call", F1(0x1), F1(~0x1), "L", F_JSR|F_DELAYED, 0, 0, v6 },
|
|
|
|
|
{ "call", F1(0x1), F1(~0x1), "L,#", F_JSR|F_DELAYED, 0, 0, v6 },
|
|
|
|
|
|
|
|
|
|
{ "call", F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI(~0), "1+2", F_JSR|F_DELAYED, 0, 0, v6 }, /* jmpl rs1+rs2,%o7 */
|
|
|
|
|
{ "call", F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI(~0), "1+2,#", F_JSR|F_DELAYED, 0, 0, v6 },
|
|
|
|
|
{ "call", F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI_RS2(~0), "1", F_JSR|F_DELAYED, 0, 0, v6 }, /* jmpl rs1+%g0,%o7 */
|
|
|
|
|
{ "call", F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI_RS2(~0), "1,#", F_JSR|F_DELAYED, 0, 0, v6 },
|
|
|
|
|
{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf), "1+i", F_JSR|F_DELAYED, 0, 0, v6 }, /* jmpl rs1+i,%o7 */
|
|
|
|
|
{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf), "1+i,#", F_JSR|F_DELAYED, 0, 0, v6 },
|
|
|
|
|
{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf), "i+1", F_JSR|F_DELAYED, 0, 0, v6 }, /* jmpl i+rs1,%o7 */
|
|
|
|
|
{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf), "i+1,#", F_JSR|F_DELAYED, 0, 0, v6 },
|
|
|
|
|
{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|RS1_G0, "i", F_JSR|F_DELAYED, 0, 0, v6 }, /* jmpl %g0+i,%o7 */
|
|
|
|
|
{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|RS1_G0, "i,#", F_JSR|F_DELAYED, 0, 0, v6 },
|
|
|
|
|
{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|SIMM13(~0), "1", F_JSR|F_DELAYED, 0, 0, v6 }, /* jmpl rs1+0,%o7 */
|
|
|
|
|
{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|SIMM13(~0), "1,#", F_JSR|F_DELAYED, 0, 0, v6 },
|
1999-05-03 15:29:11 +08:00
|
|
|
|
|
|
|
|
|
/* Conditional instructions.
|
|
|
|
|
|
|
|
|
|
Because this part of the table was such a mess earlier, I have
|
|
|
|
|
macrofied it so that all the branches and traps are generated from
|
|
|
|
|
a single-line description of each condition value. John Gilmore. */
|
|
|
|
|
|
|
|
|
|
/* Define branches -- one annulled, one without, etc. */
|
|
|
|
|
#define br(opcode, mask, lose, flags) \
|
2014-10-09 20:16:53 +08:00
|
|
|
|
{ opcode, (mask)|ANNUL, (lose), ",a l", (flags), 0, 0, v6 }, \
|
|
|
|
|
{ opcode, (mask) , (lose)|ANNUL, "l", (flags), 0, 0, v6 }
|
1999-05-03 15:29:11 +08:00
|
|
|
|
|
|
|
|
|
#define brx(opcode, mask, lose, flags) /* v9 */ \
|
2014-10-09 20:16:53 +08:00
|
|
|
|
{ opcode, (mask)|(2<<20)|BPRED, ANNUL|(lose), "Z,G", (flags), 0, 0, v9 }, \
|
|
|
|
|
{ opcode, (mask)|(2<<20)|BPRED, ANNUL|(lose), ",T Z,G", (flags), 0, 0, v9 }, \
|
|
|
|
|
{ opcode, (mask)|(2<<20)|BPRED|ANNUL, (lose), ",a Z,G", (flags), 0, 0, v9 }, \
|
|
|
|
|
{ opcode, (mask)|(2<<20)|BPRED|ANNUL, (lose), ",a,T Z,G", (flags), 0, 0, v9 }, \
|
|
|
|
|
{ opcode, (mask)|(2<<20), ANNUL|BPRED|(lose), ",N Z,G", (flags), 0, 0, v9 }, \
|
|
|
|
|
{ opcode, (mask)|(2<<20)|ANNUL, BPRED|(lose), ",a,N Z,G", (flags), 0, 0, v9 }, \
|
|
|
|
|
{ opcode, (mask)|BPRED, ANNUL|(lose)|(2<<20), "z,G", (flags), 0, 0, v9 }, \
|
|
|
|
|
{ opcode, (mask)|BPRED, ANNUL|(lose)|(2<<20), ",T z,G", (flags), 0, 0, v9 }, \
|
|
|
|
|
{ opcode, (mask)|BPRED|ANNUL, (lose)|(2<<20), ",a z,G", (flags), 0, 0, v9 }, \
|
|
|
|
|
{ opcode, (mask)|BPRED|ANNUL, (lose)|(2<<20), ",a,T z,G", (flags), 0, 0, v9 }, \
|
|
|
|
|
{ opcode, (mask), ANNUL|BPRED|(lose)|(2<<20), ",N z,G", (flags), 0, 0, v9 }, \
|
|
|
|
|
{ opcode, (mask)|ANNUL, BPRED|(lose)|(2<<20), ",a,N z,G", (flags), 0, 0, v9 }
|
1999-05-03 15:29:11 +08:00
|
|
|
|
|
|
|
|
|
/* Define four traps: reg+reg, reg + immediate, immediate alone, reg alone. */
|
|
|
|
|
#define tr(opcode, mask, lose, flags) \
|
2014-10-09 20:16:53 +08:00
|
|
|
|
{ opcode, (mask)|(2<<11)|IMMED, (lose)|RS1_G0, "Z,i", (flags), 0, 0, v9 }, /* %g0 + imm */ \
|
|
|
|
|
{ opcode, (mask)|(2<<11)|IMMED, (lose), "Z,1+i", (flags), 0, 0, v9 }, /* rs1 + imm */ \
|
|
|
|
|
{ opcode, (mask)|(2<<11), IMMED|(lose), "Z,1+2", (flags), 0, 0, v9 }, /* rs1 + rs2 */ \
|
|
|
|
|
{ opcode, (mask)|(2<<11), IMMED|(lose)|RS2_G0, "Z,1", (flags), 0, 0, v9 }, /* rs1 + %g0 */ \
|
|
|
|
|
{ opcode, (mask)|IMMED, (lose)|RS1_G0, "z,i", (flags)|F_ALIAS, 0, 0, v9 }, /* %g0 + imm */ \
|
|
|
|
|
{ opcode, (mask)|IMMED, (lose), "z,1+i", (flags)|F_ALIAS, 0, 0, v9 }, /* rs1 + imm */ \
|
|
|
|
|
{ opcode, (mask), IMMED|(lose), "z,1+2", (flags)|F_ALIAS, 0, 0, v9 }, /* rs1 + rs2 */ \
|
|
|
|
|
{ opcode, (mask), IMMED|(lose)|RS2_G0, "z,1", (flags)|F_ALIAS, 0, 0, v9 }, /* rs1 + %g0 */ \
|
|
|
|
|
{ opcode, (mask)|IMMED, (lose)|RS1_G0, "i", (flags), 0, 0, v6 }, /* %g0 + imm */ \
|
|
|
|
|
{ opcode, (mask)|IMMED, (lose), "1+i", (flags), 0, 0, v6 }, /* rs1 + imm */ \
|
|
|
|
|
{ opcode, (mask)|IMMED, (lose), "i+1", (flags), 0, 0, v6 }, /* imm + rs1 */ \
|
|
|
|
|
{ opcode, (mask), IMMED|(lose), "1+2", (flags), 0, 0, v6 }, /* rs1 + rs2 */ \
|
|
|
|
|
{ opcode, (mask), IMMED|(lose)|RS2_G0, "1", (flags), 0, 0, v6 } /* rs1 + %g0 */
|
1999-05-03 15:29:11 +08:00
|
|
|
|
|
|
|
|
|
/* v9: We must put `brx' before `br', to ensure that we never match something
|
|
|
|
|
v9: against an expression unless it is an expression. Otherwise, we end
|
|
|
|
|
v9: up with undefined symbol tables entries, because they get added, but
|
|
|
|
|
v9: are not deleted if the pattern fails to match. */
|
|
|
|
|
|
|
|
|
|
/* Define both branches and traps based on condition mask */
|
|
|
|
|
#define cond(bop, top, mask, flags) \
|
|
|
|
|
brx(bop, F2(0, 1)|(mask), F2(~0, ~1)|((~mask)&COND(~0)), F_DELAYED|(flags)), /* v9 */ \
|
|
|
|
|
br(bop, F2(0, 2)|(mask), F2(~0, ~2)|((~mask)&COND(~0)), F_DELAYED|(flags)), \
|
|
|
|
|
tr(top, F3(2, 0x3a, 0)|(mask), F3(~2, ~0x3a, 0)|((~mask)&COND(~0)), ((flags) & ~(F_UNBR|F_CONDBR)))
|
|
|
|
|
|
|
|
|
|
/* Define all the conditions, all the branches, all the traps. */
|
|
|
|
|
|
|
|
|
|
/* Standard branch, trap mnemonics */
|
|
|
|
|
cond ("b", "ta", CONDA, F_UNBR),
|
|
|
|
|
/* Alternative form (just for assembly, not for disassembly) */
|
|
|
|
|
cond ("ba", "t", CONDA, F_UNBR|F_ALIAS),
|
|
|
|
|
|
|
|
|
|
cond ("bcc", "tcc", CONDCC, F_CONDBR),
|
|
|
|
|
cond ("bcs", "tcs", CONDCS, F_CONDBR),
|
|
|
|
|
cond ("be", "te", CONDE, F_CONDBR),
|
|
|
|
|
cond ("beq", "teq", CONDE, F_CONDBR|F_ALIAS),
|
|
|
|
|
cond ("bg", "tg", CONDG, F_CONDBR),
|
|
|
|
|
cond ("bgt", "tgt", CONDG, F_CONDBR|F_ALIAS),
|
|
|
|
|
cond ("bge", "tge", CONDGE, F_CONDBR),
|
|
|
|
|
cond ("bgeu", "tgeu", CONDGEU, F_CONDBR|F_ALIAS), /* for cc */
|
|
|
|
|
cond ("bgu", "tgu", CONDGU, F_CONDBR),
|
|
|
|
|
cond ("bl", "tl", CONDL, F_CONDBR),
|
|
|
|
|
cond ("blt", "tlt", CONDL, F_CONDBR|F_ALIAS),
|
|
|
|
|
cond ("ble", "tle", CONDLE, F_CONDBR),
|
|
|
|
|
cond ("bleu", "tleu", CONDLEU, F_CONDBR),
|
|
|
|
|
cond ("blu", "tlu", CONDLU, F_CONDBR|F_ALIAS), /* for cs */
|
|
|
|
|
cond ("bn", "tn", CONDN, F_CONDBR),
|
|
|
|
|
cond ("bne", "tne", CONDNE, F_CONDBR),
|
|
|
|
|
cond ("bneg", "tneg", CONDNEG, F_CONDBR),
|
|
|
|
|
cond ("bnz", "tnz", CONDNZ, F_CONDBR|F_ALIAS), /* for ne */
|
|
|
|
|
cond ("bpos", "tpos", CONDPOS, F_CONDBR),
|
|
|
|
|
cond ("bvc", "tvc", CONDVC, F_CONDBR),
|
|
|
|
|
cond ("bvs", "tvs", CONDVS, F_CONDBR),
|
|
|
|
|
cond ("bz", "tz", CONDZ, F_CONDBR|F_ALIAS), /* for e */
|
|
|
|
|
|
|
|
|
|
#undef cond
|
|
|
|
|
#undef br
|
|
|
|
|
#undef brr /* v9 */
|
|
|
|
|
#undef tr
|
|
|
|
|
|
|
|
|
|
#define brr(opcode, mask, lose, flags) /* v9 */ \
|
2014-10-09 20:16:53 +08:00
|
|
|
|
{ opcode, (mask)|BPRED, ANNUL|(lose), "1,k", F_DELAYED|(flags), 0, 0, v9 }, \
|
|
|
|
|
{ opcode, (mask)|BPRED, ANNUL|(lose), ",T 1,k", F_DELAYED|(flags), 0, 0, v9 }, \
|
|
|
|
|
{ opcode, (mask)|BPRED|ANNUL, (lose), ",a 1,k", F_DELAYED|(flags), 0, 0, v9 }, \
|
|
|
|
|
{ opcode, (mask)|BPRED|ANNUL, (lose), ",a,T 1,k", F_DELAYED|(flags), 0, 0, v9 }, \
|
|
|
|
|
{ opcode, (mask), ANNUL|BPRED|(lose), ",N 1,k", F_DELAYED|(flags), 0, 0, v9 }, \
|
|
|
|
|
{ opcode, (mask)|ANNUL, BPRED|(lose), ",a,N 1,k", F_DELAYED|(flags), 0, 0, v9 }
|
1999-05-03 15:29:11 +08:00
|
|
|
|
|
|
|
|
|
#define condr(bop, mask, flags) /* v9 */ \
|
|
|
|
|
brr(bop, F2(0, 3)|COND(mask), F2(~0, ~3)|COND(~(mask)), (flags)) /* v9 */
|
|
|
|
|
|
|
|
|
|
/* v9 */ condr("brnz", 0x5, F_CONDBR),
|
|
|
|
|
/* v9 */ condr("brz", 0x1, F_CONDBR),
|
|
|
|
|
/* v9 */ condr("brgez", 0x7, F_CONDBR),
|
|
|
|
|
/* v9 */ condr("brlz", 0x3, F_CONDBR),
|
|
|
|
|
/* v9 */ condr("brlez", 0x2, F_CONDBR),
|
|
|
|
|
/* v9 */ condr("brgz", 0x6, F_CONDBR),
|
|
|
|
|
|
Increase the accuracy of sparc instruction aliases.
Make current with UA2011 specification.
Add an F_PREFERRED opcode flag that indicates a preferred alias
when multiple aliases for the same opcode exists.
For 'lzd':
Add 'lzcnt' as primary instruction, and make 'lzd' an alias.
Add 'ldtw', 'ldtwa', 'sttw', 'sttwa':
The modern opcode for for 'ldd', 'ldda', 'std', and 'stda' on
integer registers. Mark the latter now as aliases.
For 'flush':
Support "[address]" syntax as well as plain "address".
Rework 'mov' aliases for 'wr':
Eliminate bogus three operand moves, and encode the
instructions properly for the "mov REG, %ASR" cases,
specifically we should encode the register in rs2 not rs1 as
per The SPARC V8 Architecture Manual.
Add missing cbcond aliases:
c{w,x}bz, c{w,x}blu, c{w,x}bnz, c{w,x}bgeu
Add 'd' suffix VIS logical ops:
The primary opcode for 'fzero' is now 'fzerod' (compare with
'fzeros'), for example. And thus 'fzero' is now an alias.
Add modern opcodes for condition code setting edge instructions:
They are now edgeN{,l}cc instead of plain edgeN{,l}.
Add modern opcodes for VIS comparisons:
All VIS comparisons now start with prefix "fp", retain the
older variants as aliases.
The signed variants for equal and not-equal have "u" aliases
to show that these comparisons are equally suited for unsigned
compares.
Update existing test cases as needed, and add several new ones.
include/opcode/
* sparc.h (F_PREFERRED): Define.
(F_PREF_ALIAS): Define.
opcodes/
* sparc-dis.c (compare_opcodes): When encountering multiple aliases
of an opcode, prefer the one with F_PREFERRED set.
* sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
ops. Make 64-bit VIS logical ops have "d" suffix in their names,
mark existing mnenomics as aliases. Add "cc" suffix to edge
instructions generating condition codes, mark existing mnenomics
as aliases. Add "fp" prefix to VIS compare instructions, mark
existing mnenomics as aliases.
gas/testsuite/
* gas/sparc/cbcond.s: Add tests for new opcode aliases.
* gas/sparc/cbcond.d: Updated.
* gas/sparc/hpcvis3.s: Add tests for new opcode aliases.
* gas/sparc/hpcvis3.d: Updated.
* gas/sparc/v8-movwr-imm.d: Fix expected disassembly.
* gas/sparc/edge.s: New test.
* gas/sparc/edge.d: Expected disassembly.
* gas/sparc/flush.s: New test.
* gas/sparc/flush.d: Expected disassembly.
* gas/sparc/ldd_std.s: New test.
* gas/sparc/ldd_std.d: Expected disassembly.
* gas/sparc/ldtw_sttw.s: New test.
* gas/sparc/ldtw_sttw.d: Expected disassembly.
* gas/sparc/sparc.exp: Run new tests.
2013-04-07 06:22:03 +08:00
|
|
|
|
#define cbcond(cop, cmask, flgs) \
|
2012-04-28 02:03:13 +08:00
|
|
|
|
{ "cw" cop, F2(0, 3)|CBCOND(cmask)|F3I(0),F2(~0,~3)|CBCOND(~(cmask))|F3I(~0)|CBCOND_XCC, \
|
opcodes,gas: adjust sparc insns and make GAS aware of it
This patch marks the SPARC instructions in the opcodes table with their
proper opcode architectures, and makes the assembler aware of them.
This allows the assembler to properly realize when a new instruction
needs a higher architecture (after v9b) and to react accordingly
emitting an error message or bumping the architecture.
It also expands architecture mismatch tests to cover architectures
higher than v9b, and fixes a couple of minor bugs in the GAS testsuite.
opcodes/ChangeLog:
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* sparc-opc.c (sparc_opcodes): Adjust instructions opcode
architecture according to the hardware capabilities they require.
(sparc_priv_regs): New table.
(sparc_hpriv_regs): Likewise.
(sparc_asr_regs): Likewise.
(v9anotv9m): Define.
gas/ChangeLog:
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-sparc.c (sparc_arch_table): adjust the GAS
architectures to use the right opcode architecture.
(sparc_md_end): Handle v9{c,d,e,v,m}.
(sparc_ip): Fix some comments.
* testsuite/gas/sparc/ldx_efsr.d: Fix the architecture of this
instruction, which is v9d.
* testsuite/gas/sparc/mwait.s: Remove the `rd %mwait,%g1'
instruction from the test, as %mwait is not readable.
* testsuite/gas/sparc/mwait.d: Likewise.
* testsuite/gas/sparc/mism-1.s: Expand to check v9b and v9e
mismatch architecture errors.
* testsuite/gas/sparc/mism-2.s: New file.
2016-06-17 17:14:18 +08:00
|
|
|
|
"1,2,=", flgs, HWCAP_CBCOND, 0, v9e}, \
|
2012-04-28 02:03:13 +08:00
|
|
|
|
{ "cw" cop, F2(0, 3)|CBCOND(cmask)|F3I(1),F2(~0,~3)|CBCOND(~(cmask))|F3I(~1)|CBCOND_XCC, \
|
opcodes,gas: adjust sparc insns and make GAS aware of it
This patch marks the SPARC instructions in the opcodes table with their
proper opcode architectures, and makes the assembler aware of them.
This allows the assembler to properly realize when a new instruction
needs a higher architecture (after v9b) and to react accordingly
emitting an error message or bumping the architecture.
It also expands architecture mismatch tests to cover architectures
higher than v9b, and fixes a couple of minor bugs in the GAS testsuite.
opcodes/ChangeLog:
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* sparc-opc.c (sparc_opcodes): Adjust instructions opcode
architecture according to the hardware capabilities they require.
(sparc_priv_regs): New table.
(sparc_hpriv_regs): Likewise.
(sparc_asr_regs): Likewise.
(v9anotv9m): Define.
gas/ChangeLog:
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-sparc.c (sparc_arch_table): adjust the GAS
architectures to use the right opcode architecture.
(sparc_md_end): Handle v9{c,d,e,v,m}.
(sparc_ip): Fix some comments.
* testsuite/gas/sparc/ldx_efsr.d: Fix the architecture of this
instruction, which is v9d.
* testsuite/gas/sparc/mwait.s: Remove the `rd %mwait,%g1'
instruction from the test, as %mwait is not readable.
* testsuite/gas/sparc/mwait.d: Likewise.
* testsuite/gas/sparc/mism-1.s: Expand to check v9b and v9e
mismatch architecture errors.
* testsuite/gas/sparc/mism-2.s: New file.
2016-06-17 17:14:18 +08:00
|
|
|
|
"1,X,=", flgs, HWCAP_CBCOND, 0, v9e}, \
|
2012-04-28 02:03:13 +08:00
|
|
|
|
{ "cx" cop, F2(0, 3)|CBCOND(cmask)|F3I(0)|CBCOND_XCC,F2(~0,~3)|CBCOND(~(cmask))|F3I(~0), \
|
opcodes,gas: adjust sparc insns and make GAS aware of it
This patch marks the SPARC instructions in the opcodes table with their
proper opcode architectures, and makes the assembler aware of them.
This allows the assembler to properly realize when a new instruction
needs a higher architecture (after v9b) and to react accordingly
emitting an error message or bumping the architecture.
It also expands architecture mismatch tests to cover architectures
higher than v9b, and fixes a couple of minor bugs in the GAS testsuite.
opcodes/ChangeLog:
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* sparc-opc.c (sparc_opcodes): Adjust instructions opcode
architecture according to the hardware capabilities they require.
(sparc_priv_regs): New table.
(sparc_hpriv_regs): Likewise.
(sparc_asr_regs): Likewise.
(v9anotv9m): Define.
gas/ChangeLog:
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-sparc.c (sparc_arch_table): adjust the GAS
architectures to use the right opcode architecture.
(sparc_md_end): Handle v9{c,d,e,v,m}.
(sparc_ip): Fix some comments.
* testsuite/gas/sparc/ldx_efsr.d: Fix the architecture of this
instruction, which is v9d.
* testsuite/gas/sparc/mwait.s: Remove the `rd %mwait,%g1'
instruction from the test, as %mwait is not readable.
* testsuite/gas/sparc/mwait.d: Likewise.
* testsuite/gas/sparc/mism-1.s: Expand to check v9b and v9e
mismatch architecture errors.
* testsuite/gas/sparc/mism-2.s: New file.
2016-06-17 17:14:18 +08:00
|
|
|
|
"1,2,=", flgs, HWCAP_CBCOND, 0, v9e}, \
|
2012-04-28 02:03:13 +08:00
|
|
|
|
{ "cx" cop, F2(0, 3)|CBCOND(cmask)|F3I(1)|CBCOND_XCC,F2(~0,~3)|CBCOND(~(cmask))|F3I(~1), \
|
opcodes,gas: adjust sparc insns and make GAS aware of it
This patch marks the SPARC instructions in the opcodes table with their
proper opcode architectures, and makes the assembler aware of them.
This allows the assembler to properly realize when a new instruction
needs a higher architecture (after v9b) and to react accordingly
emitting an error message or bumping the architecture.
It also expands architecture mismatch tests to cover architectures
higher than v9b, and fixes a couple of minor bugs in the GAS testsuite.
opcodes/ChangeLog:
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* sparc-opc.c (sparc_opcodes): Adjust instructions opcode
architecture according to the hardware capabilities they require.
(sparc_priv_regs): New table.
(sparc_hpriv_regs): Likewise.
(sparc_asr_regs): Likewise.
(v9anotv9m): Define.
gas/ChangeLog:
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-sparc.c (sparc_arch_table): adjust the GAS
architectures to use the right opcode architecture.
(sparc_md_end): Handle v9{c,d,e,v,m}.
(sparc_ip): Fix some comments.
* testsuite/gas/sparc/ldx_efsr.d: Fix the architecture of this
instruction, which is v9d.
* testsuite/gas/sparc/mwait.s: Remove the `rd %mwait,%g1'
instruction from the test, as %mwait is not readable.
* testsuite/gas/sparc/mwait.d: Likewise.
* testsuite/gas/sparc/mism-1.s: Expand to check v9b and v9e
mismatch architecture errors.
* testsuite/gas/sparc/mism-2.s: New file.
2016-06-17 17:14:18 +08:00
|
|
|
|
"1,X,=", flgs, HWCAP_CBCOND, 0, v9e},
|
Increase the accuracy of sparc instruction aliases.
Make current with UA2011 specification.
Add an F_PREFERRED opcode flag that indicates a preferred alias
when multiple aliases for the same opcode exists.
For 'lzd':
Add 'lzcnt' as primary instruction, and make 'lzd' an alias.
Add 'ldtw', 'ldtwa', 'sttw', 'sttwa':
The modern opcode for for 'ldd', 'ldda', 'std', and 'stda' on
integer registers. Mark the latter now as aliases.
For 'flush':
Support "[address]" syntax as well as plain "address".
Rework 'mov' aliases for 'wr':
Eliminate bogus three operand moves, and encode the
instructions properly for the "mov REG, %ASR" cases,
specifically we should encode the register in rs2 not rs1 as
per The SPARC V8 Architecture Manual.
Add missing cbcond aliases:
c{w,x}bz, c{w,x}blu, c{w,x}bnz, c{w,x}bgeu
Add 'd' suffix VIS logical ops:
The primary opcode for 'fzero' is now 'fzerod' (compare with
'fzeros'), for example. And thus 'fzero' is now an alias.
Add modern opcodes for condition code setting edge instructions:
They are now edgeN{,l}cc instead of plain edgeN{,l}.
Add modern opcodes for VIS comparisons:
All VIS comparisons now start with prefix "fp", retain the
older variants as aliases.
The signed variants for equal and not-equal have "u" aliases
to show that these comparisons are equally suited for unsigned
compares.
Update existing test cases as needed, and add several new ones.
include/opcode/
* sparc.h (F_PREFERRED): Define.
(F_PREF_ALIAS): Define.
opcodes/
* sparc-dis.c (compare_opcodes): When encountering multiple aliases
of an opcode, prefer the one with F_PREFERRED set.
* sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
ops. Make 64-bit VIS logical ops have "d" suffix in their names,
mark existing mnenomics as aliases. Add "cc" suffix to edge
instructions generating condition codes, mark existing mnenomics
as aliases. Add "fp" prefix to VIS compare instructions, mark
existing mnenomics as aliases.
gas/testsuite/
* gas/sparc/cbcond.s: Add tests for new opcode aliases.
* gas/sparc/cbcond.d: Updated.
* gas/sparc/hpcvis3.s: Add tests for new opcode aliases.
* gas/sparc/hpcvis3.d: Updated.
* gas/sparc/v8-movwr-imm.d: Fix expected disassembly.
* gas/sparc/edge.s: New test.
* gas/sparc/edge.d: Expected disassembly.
* gas/sparc/flush.s: New test.
* gas/sparc/flush.d: Expected disassembly.
* gas/sparc/ldd_std.s: New test.
* gas/sparc/ldd_std.d: Expected disassembly.
* gas/sparc/ldtw_sttw.s: New test.
* gas/sparc/ldtw_sttw.d: Expected disassembly.
* gas/sparc/sparc.exp: Run new tests.
2013-04-07 06:22:03 +08:00
|
|
|
|
|
|
|
|
|
cbcond("be", 0x09, F_CONDBR)
|
|
|
|
|
cbcond("bz", 0x09, F_CONDBR|F_ALIAS)
|
|
|
|
|
cbcond("ble", 0x0a, F_CONDBR)
|
|
|
|
|
cbcond("bl", 0x0b, F_CONDBR)
|
|
|
|
|
cbcond("bleu", 0x0c, F_CONDBR)
|
|
|
|
|
cbcond("bcs", 0x0d, F_CONDBR)
|
|
|
|
|
cbcond("blu", 0x0d, F_CONDBR|F_ALIAS)
|
|
|
|
|
cbcond("bneg", 0x0e, F_CONDBR)
|
|
|
|
|
cbcond("bvs", 0x0f, F_CONDBR)
|
|
|
|
|
cbcond("bne", 0x19, F_CONDBR)
|
|
|
|
|
cbcond("bnz", 0x19, F_CONDBR|F_ALIAS)
|
|
|
|
|
cbcond("bg", 0x1a, F_CONDBR)
|
|
|
|
|
cbcond("bge", 0x1b, F_CONDBR)
|
|
|
|
|
cbcond("bgu", 0x1c, F_CONDBR)
|
|
|
|
|
cbcond("bcc", 0x1d, F_CONDBR)
|
|
|
|
|
cbcond("bgeu", 0x1d, F_CONDBR|F_ALIAS)
|
|
|
|
|
cbcond("bpos", 0x1e, F_CONDBR)
|
|
|
|
|
cbcond("bvc", 0x1f, F_CONDBR)
|
2012-04-28 02:03:13 +08:00
|
|
|
|
|
|
|
|
|
#undef cbcond
|
1999-05-03 15:29:11 +08:00
|
|
|
|
#undef condr /* v9 */
|
|
|
|
|
#undef brr /* v9 */
|
|
|
|
|
|
|
|
|
|
#define movr(opcode, mask, flags) /* v9 */ \
|
2014-10-09 20:16:53 +08:00
|
|
|
|
{ opcode, F3(2, 0x2f, 0)|RCOND(mask), F3(~2, ~0x2f, ~0)|RCOND(~(mask)), "1,2,d", (flags), 0, 0, v9 }, \
|
|
|
|
|
{ opcode, F3(2, 0x2f, 1)|RCOND(mask), F3(~2, ~0x2f, ~1)|RCOND(~(mask)), "1,j,d", (flags), 0, 0, v9 }
|
1999-05-03 15:29:11 +08:00
|
|
|
|
|
|
|
|
|
#define fmrrs(opcode, mask, lose, flags) /* v9 */ \
|
2014-10-09 20:16:53 +08:00
|
|
|
|
{ opcode, (mask), (lose), "1,f,g", (flags) | F_FLOAT, 0, 0, v9 }
|
1999-05-03 15:29:11 +08:00
|
|
|
|
#define fmrrd(opcode, mask, lose, flags) /* v9 */ \
|
2014-10-09 20:16:53 +08:00
|
|
|
|
{ opcode, (mask), (lose), "1,B,H", (flags) | F_FLOAT, 0, 0, v9 }
|
1999-05-03 15:29:11 +08:00
|
|
|
|
#define fmrrq(opcode, mask, lose, flags) /* v9 */ \
|
2014-10-09 20:16:53 +08:00
|
|
|
|
{ opcode, (mask), (lose), "1,R,J", (flags) | F_FLOAT, 0, 0, v9 }
|
1999-05-03 15:29:11 +08:00
|
|
|
|
|
|
|
|
|
#define fmovrs(mop, mask, flags) /* v9 */ \
|
|
|
|
|
fmrrs(mop, F3(2, 0x35, 0)|OPF_LOW5(5)|RCOND(mask), F3(~2, ~0x35, 0)|OPF_LOW5(~5)|RCOND(~(mask)), (flags)) /* v9 */
|
|
|
|
|
#define fmovrd(mop, mask, flags) /* v9 */ \
|
|
|
|
|
fmrrd(mop, F3(2, 0x35, 0)|OPF_LOW5(6)|RCOND(mask), F3(~2, ~0x35, 0)|OPF_LOW5(~6)|RCOND(~(mask)), (flags)) /* v9 */
|
|
|
|
|
#define fmovrq(mop, mask, flags) /* v9 */ \
|
|
|
|
|
fmrrq(mop, F3(2, 0x35, 0)|OPF_LOW5(7)|RCOND(mask), F3(~2, ~0x35, 0)|OPF_LOW5(~7)|RCOND(~(mask)), (flags)) /* v9 */
|
|
|
|
|
|
|
|
|
|
/* v9 */ movr("movrne", 0x5, 0),
|
|
|
|
|
/* v9 */ movr("movre", 0x1, 0),
|
|
|
|
|
/* v9 */ movr("movrgez", 0x7, 0),
|
|
|
|
|
/* v9 */ movr("movrlz", 0x3, 0),
|
|
|
|
|
/* v9 */ movr("movrlez", 0x2, 0),
|
|
|
|
|
/* v9 */ movr("movrgz", 0x6, 0),
|
|
|
|
|
/* v9 */ movr("movrnz", 0x5, F_ALIAS),
|
|
|
|
|
/* v9 */ movr("movrz", 0x1, F_ALIAS),
|
|
|
|
|
|
|
|
|
|
/* v9 */ fmovrs("fmovrsne", 0x5, 0),
|
|
|
|
|
/* v9 */ fmovrs("fmovrse", 0x1, 0),
|
|
|
|
|
/* v9 */ fmovrs("fmovrsgez", 0x7, 0),
|
|
|
|
|
/* v9 */ fmovrs("fmovrslz", 0x3, 0),
|
|
|
|
|
/* v9 */ fmovrs("fmovrslez", 0x2, 0),
|
|
|
|
|
/* v9 */ fmovrs("fmovrsgz", 0x6, 0),
|
|
|
|
|
/* v9 */ fmovrs("fmovrsnz", 0x5, F_ALIAS),
|
|
|
|
|
/* v9 */ fmovrs("fmovrsz", 0x1, F_ALIAS),
|
|
|
|
|
|
|
|
|
|
/* v9 */ fmovrd("fmovrdne", 0x5, 0),
|
|
|
|
|
/* v9 */ fmovrd("fmovrde", 0x1, 0),
|
|
|
|
|
/* v9 */ fmovrd("fmovrdgez", 0x7, 0),
|
|
|
|
|
/* v9 */ fmovrd("fmovrdlz", 0x3, 0),
|
|
|
|
|
/* v9 */ fmovrd("fmovrdlez", 0x2, 0),
|
|
|
|
|
/* v9 */ fmovrd("fmovrdgz", 0x6, 0),
|
|
|
|
|
/* v9 */ fmovrd("fmovrdnz", 0x5, F_ALIAS),
|
|
|
|
|
/* v9 */ fmovrd("fmovrdz", 0x1, F_ALIAS),
|
|
|
|
|
|
|
|
|
|
/* v9 */ fmovrq("fmovrqne", 0x5, 0),
|
|
|
|
|
/* v9 */ fmovrq("fmovrqe", 0x1, 0),
|
|
|
|
|
/* v9 */ fmovrq("fmovrqgez", 0x7, 0),
|
|
|
|
|
/* v9 */ fmovrq("fmovrqlz", 0x3, 0),
|
|
|
|
|
/* v9 */ fmovrq("fmovrqlez", 0x2, 0),
|
|
|
|
|
/* v9 */ fmovrq("fmovrqgz", 0x6, 0),
|
|
|
|
|
/* v9 */ fmovrq("fmovrqnz", 0x5, F_ALIAS),
|
|
|
|
|
/* v9 */ fmovrq("fmovrqz", 0x1, F_ALIAS),
|
|
|
|
|
|
|
|
|
|
#undef movr /* v9 */
|
|
|
|
|
#undef fmovr /* v9 */
|
|
|
|
|
#undef fmrr /* v9 */
|
|
|
|
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|
|
#define movicc(opcode, cond, flags) /* v9 */ \
|
2014-10-09 20:16:53 +08:00
|
|
|
|
{ opcode, F3(2, 0x2c, 0)|MCOND(cond,1)|ICC, F3(~2, ~0x2c, ~0)|MCOND(~cond,~1)|XCC|(1<<11), "z,2,d", flags, 0, 0, v9 }, \
|
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|
|
{ opcode, F3(2, 0x2c, 1)|MCOND(cond,1)|ICC, F3(~2, ~0x2c, ~1)|MCOND(~cond,~1)|XCC|(1<<11), "z,I,d", flags, 0, 0, v9 }, \
|
|
|
|
|
{ opcode, F3(2, 0x2c, 0)|MCOND(cond,1)|XCC, F3(~2, ~0x2c, ~0)|MCOND(~cond,~1)|(1<<11), "Z,2,d", flags, 0, 0, v9 }, \
|
|
|
|
|
{ opcode, F3(2, 0x2c, 1)|MCOND(cond,1)|XCC, F3(~2, ~0x2c, ~1)|MCOND(~cond,~1)|(1<<11), "Z,I,d", flags, 0, 0, v9 }
|
1999-05-03 15:29:11 +08:00
|
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|
#define movfcc(opcode, fcond, flags) /* v9 */ \
|
2014-10-09 20:16:53 +08:00
|
|
|
|
{ opcode, F3(2, 0x2c, 0)|FCC(0)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~0)|F3(~2, ~0x2c, ~0), "6,2,d", flags, 0, 0, v9 }, \
|
|
|
|
|
{ opcode, F3(2, 0x2c, 1)|FCC(0)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~0)|F3(~2, ~0x2c, ~1), "6,I,d", flags, 0, 0, v9 }, \
|
|
|
|
|
{ opcode, F3(2, 0x2c, 0)|FCC(1)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~1)|F3(~2, ~0x2c, ~0), "7,2,d", flags, 0, 0, v9 }, \
|
|
|
|
|
{ opcode, F3(2, 0x2c, 1)|FCC(1)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~1)|F3(~2, ~0x2c, ~1), "7,I,d", flags, 0, 0, v9 }, \
|
|
|
|
|
{ opcode, F3(2, 0x2c, 0)|FCC(2)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~2)|F3(~2, ~0x2c, ~0), "8,2,d", flags, 0, 0, v9 }, \
|
|
|
|
|
{ opcode, F3(2, 0x2c, 1)|FCC(2)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~2)|F3(~2, ~0x2c, ~1), "8,I,d", flags, 0, 0, v9 }, \
|
|
|
|
|
{ opcode, F3(2, 0x2c, 0)|FCC(3)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~3)|F3(~2, ~0x2c, ~0), "9,2,d", flags, 0, 0, v9 }, \
|
|
|
|
|
{ opcode, F3(2, 0x2c, 1)|FCC(3)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~3)|F3(~2, ~0x2c, ~1), "9,I,d", flags, 0, 0, v9 }
|
1999-05-03 15:29:11 +08:00
|
|
|
|
|
|
|
|
|
#define movcc(opcode, cond, fcond, flags) /* v9 */ \
|
|
|
|
|
movfcc (opcode, fcond, flags), /* v9 */ \
|
|
|
|
|
movicc (opcode, cond, flags) /* v9 */
|
|
|
|
|
|
|
|
|
|
/* v9 */ movcc ("mova", CONDA, FCONDA, 0),
|
|
|
|
|
/* v9 */ movicc ("movcc", CONDCC, 0),
|
|
|
|
|
/* v9 */ movicc ("movgeu", CONDGEU, F_ALIAS),
|
|
|
|
|
/* v9 */ movicc ("movcs", CONDCS, 0),
|
|
|
|
|
/* v9 */ movicc ("movlu", CONDLU, F_ALIAS),
|
|
|
|
|
/* v9 */ movcc ("move", CONDE, FCONDE, 0),
|
|
|
|
|
/* v9 */ movcc ("movg", CONDG, FCONDG, 0),
|
|
|
|
|
/* v9 */ movcc ("movge", CONDGE, FCONDGE, 0),
|
|
|
|
|
/* v9 */ movicc ("movgu", CONDGU, 0),
|
|
|
|
|
/* v9 */ movcc ("movl", CONDL, FCONDL, 0),
|
|
|
|
|
/* v9 */ movcc ("movle", CONDLE, FCONDLE, 0),
|
|
|
|
|
/* v9 */ movicc ("movleu", CONDLEU, 0),
|
|
|
|
|
/* v9 */ movfcc ("movlg", FCONDLG, 0),
|
|
|
|
|
/* v9 */ movcc ("movn", CONDN, FCONDN, 0),
|
|
|
|
|
/* v9 */ movcc ("movne", CONDNE, FCONDNE, 0),
|
|
|
|
|
/* v9 */ movicc ("movneg", CONDNEG, 0),
|
|
|
|
|
/* v9 */ movcc ("movnz", CONDNZ, FCONDNZ, F_ALIAS),
|
|
|
|
|
/* v9 */ movfcc ("movo", FCONDO, 0),
|
|
|
|
|
/* v9 */ movicc ("movpos", CONDPOS, 0),
|
|
|
|
|
/* v9 */ movfcc ("movu", FCONDU, 0),
|
|
|
|
|
/* v9 */ movfcc ("movue", FCONDUE, 0),
|
|
|
|
|
/* v9 */ movfcc ("movug", FCONDUG, 0),
|
|
|
|
|
/* v9 */ movfcc ("movuge", FCONDUGE, 0),
|
|
|
|
|
/* v9 */ movfcc ("movul", FCONDUL, 0),
|
|
|
|
|
/* v9 */ movfcc ("movule", FCONDULE, 0),
|
|
|
|
|
/* v9 */ movicc ("movvc", CONDVC, 0),
|
|
|
|
|
/* v9 */ movicc ("movvs", CONDVS, 0),
|
|
|
|
|
/* v9 */ movcc ("movz", CONDZ, FCONDZ, F_ALIAS),
|
|
|
|
|
|
|
|
|
|
#undef movicc /* v9 */
|
|
|
|
|
#undef movfcc /* v9 */
|
|
|
|
|
#undef movcc /* v9 */
|
|
|
|
|
|
|
|
|
|
#define FM_SF 1 /* v9 - values for fpsize */
|
|
|
|
|
#define FM_DF 2 /* v9 */
|
|
|
|
|
#define FM_QF 3 /* v9 */
|
|
|
|
|
|
2004-04-20 18:23:51 +08:00
|
|
|
|
#define fmoviccx(opcode, fpsize, args, cond, flags) /* v9 */ \
|
2014-10-09 20:16:53 +08:00
|
|
|
|
{ opcode, F3F(2, 0x35, 0x100+fpsize)|MCOND(cond,0), F3F(~2, ~0x35, ~(0x100+fpsize))|MCOND(~cond,~0), "z," args, flags, 0, 0, v9 }, \
|
|
|
|
|
{ opcode, F3F(2, 0x35, 0x180+fpsize)|MCOND(cond,0), F3F(~2, ~0x35, ~(0x180+fpsize))|MCOND(~cond,~0), "Z," args, flags, 0, 0, v9 }
|
1999-05-03 15:29:11 +08:00
|
|
|
|
|
2004-04-20 18:23:51 +08:00
|
|
|
|
#define fmovfccx(opcode, fpsize, args, fcond, flags) /* v9 */ \
|
2014-10-09 20:16:53 +08:00
|
|
|
|
{ opcode, F3F(2, 0x35, 0x000+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x000+fpsize))|MCOND(~fcond,~0), "6," args, flags, 0, 0, v9 }, \
|
|
|
|
|
{ opcode, F3F(2, 0x35, 0x040+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x040+fpsize))|MCOND(~fcond,~0), "7," args, flags, 0, 0, v9 }, \
|
|
|
|
|
{ opcode, F3F(2, 0x35, 0x080+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x080+fpsize))|MCOND(~fcond,~0), "8," args, flags, 0, 0, v9 }, \
|
|
|
|
|
{ opcode, F3F(2, 0x35, 0x0c0+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x0c0+fpsize))|MCOND(~fcond,~0), "9," args, flags, 0, 0, v9 }
|
1999-05-03 15:29:11 +08:00
|
|
|
|
|
|
|
|
|
/* FIXME: use fmovicc/fmovfcc? */ /* v9 */
|
2004-04-20 18:23:51 +08:00
|
|
|
|
#define fmovccx(opcode, fpsize, args, cond, fcond, flags) /* v9 */ \
|
2014-10-09 20:16:53 +08:00
|
|
|
|
{ opcode, F3F(2, 0x35, 0x100+fpsize)|MCOND(cond,0), F3F(~2, ~0x35, ~(0x100+fpsize))|MCOND(~cond,~0), "z," args, flags | F_FLOAT, 0, 0, v9 }, \
|
|
|
|
|
{ opcode, F3F(2, 0x35, 0x000+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x000+fpsize))|MCOND(~fcond,~0), "6," args, flags | F_FLOAT, 0, 0, v9 }, \
|
|
|
|
|
{ opcode, F3F(2, 0x35, 0x180+fpsize)|MCOND(cond,0), F3F(~2, ~0x35, ~(0x180+fpsize))|MCOND(~cond,~0), "Z," args, flags | F_FLOAT, 0, 0, v9 }, \
|
|
|
|
|
{ opcode, F3F(2, 0x35, 0x040+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x040+fpsize))|MCOND(~fcond,~0), "7," args, flags | F_FLOAT, 0, 0, v9 }, \
|
|
|
|
|
{ opcode, F3F(2, 0x35, 0x080+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x080+fpsize))|MCOND(~fcond,~0), "8," args, flags | F_FLOAT, 0, 0, v9 }, \
|
|
|
|
|
{ opcode, F3F(2, 0x35, 0x0c0+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x0c0+fpsize))|MCOND(~fcond,~0), "9," args, flags | F_FLOAT, 0, 0, v9 }
|
2004-04-20 18:23:51 +08:00
|
|
|
|
|
|
|
|
|
#define fmovicc(suffix, cond, flags) /* v9 */ \
|
|
|
|
|
fmoviccx("fmovd" suffix, FM_DF, "B,H", cond, flags), \
|
|
|
|
|
fmoviccx("fmovq" suffix, FM_QF, "R,J", cond, flags), \
|
|
|
|
|
fmoviccx("fmovs" suffix, FM_SF, "f,g", cond, flags)
|
|
|
|
|
|
|
|
|
|
#define fmovfcc(suffix, fcond, flags) /* v9 */ \
|
|
|
|
|
fmovfccx("fmovd" suffix, FM_DF, "B,H", fcond, flags), \
|
|
|
|
|
fmovfccx("fmovq" suffix, FM_QF, "R,J", fcond, flags), \
|
|
|
|
|
fmovfccx("fmovs" suffix, FM_SF, "f,g", fcond, flags)
|
|
|
|
|
|
|
|
|
|
#define fmovcc(suffix, cond, fcond, flags) /* v9 */ \
|
|
|
|
|
fmovccx("fmovd" suffix, FM_DF, "B,H", cond, fcond, flags), \
|
|
|
|
|
fmovccx("fmovq" suffix, FM_QF, "R,J", cond, fcond, flags), \
|
|
|
|
|
fmovccx("fmovs" suffix, FM_SF, "f,g", cond, fcond, flags)
|
|
|
|
|
|
|
|
|
|
/* v9 */ fmovcc ("a", CONDA, FCONDA, 0),
|
|
|
|
|
/* v9 */ fmovicc ("cc", CONDCC, 0),
|
|
|
|
|
/* v9 */ fmovicc ("cs", CONDCS, 0),
|
|
|
|
|
/* v9 */ fmovcc ("e", CONDE, FCONDE, 0),
|
|
|
|
|
/* v9 */ fmovcc ("g", CONDG, FCONDG, 0),
|
|
|
|
|
/* v9 */ fmovcc ("ge", CONDGE, FCONDGE, 0),
|
|
|
|
|
/* v9 */ fmovicc ("geu", CONDGEU, F_ALIAS),
|
|
|
|
|
/* v9 */ fmovicc ("gu", CONDGU, 0),
|
|
|
|
|
/* v9 */ fmovcc ("l", CONDL, FCONDL, 0),
|
|
|
|
|
/* v9 */ fmovcc ("le", CONDLE, FCONDLE, 0),
|
|
|
|
|
/* v9 */ fmovicc ("leu", CONDLEU, 0),
|
|
|
|
|
/* v9 */ fmovfcc ("lg", FCONDLG, 0),
|
|
|
|
|
/* v9 */ fmovicc ("lu", CONDLU, F_ALIAS),
|
|
|
|
|
/* v9 */ fmovcc ("n", CONDN, FCONDN, 0),
|
|
|
|
|
/* v9 */ fmovcc ("ne", CONDNE, FCONDNE, 0),
|
|
|
|
|
/* v9 */ fmovicc ("neg", CONDNEG, 0),
|
|
|
|
|
/* v9 */ fmovcc ("nz", CONDNZ, FCONDNZ, F_ALIAS),
|
|
|
|
|
/* v9 */ fmovfcc ("o", FCONDO, 0),
|
|
|
|
|
/* v9 */ fmovicc ("pos", CONDPOS, 0),
|
|
|
|
|
/* v9 */ fmovfcc ("u", FCONDU, 0),
|
|
|
|
|
/* v9 */ fmovfcc ("ue", FCONDUE, 0),
|
|
|
|
|
/* v9 */ fmovfcc ("ug", FCONDUG, 0),
|
|
|
|
|
/* v9 */ fmovfcc ("uge", FCONDUGE, 0),
|
|
|
|
|
/* v9 */ fmovfcc ("ul", FCONDUL, 0),
|
|
|
|
|
/* v9 */ fmovfcc ("ule", FCONDULE, 0),
|
|
|
|
|
/* v9 */ fmovicc ("vc", CONDVC, 0),
|
|
|
|
|
/* v9 */ fmovicc ("vs", CONDVS, 0),
|
|
|
|
|
/* v9 */ fmovcc ("z", CONDZ, FCONDZ, F_ALIAS),
|
|
|
|
|
|
|
|
|
|
#undef fmoviccx /* v9 */
|
|
|
|
|
#undef fmovfccx /* v9 */
|
|
|
|
|
#undef fmovccx /* v9 */
|
1999-05-03 15:29:11 +08:00
|
|
|
|
#undef fmovicc /* v9 */
|
|
|
|
|
#undef fmovfcc /* v9 */
|
|
|
|
|
#undef fmovcc /* v9 */
|
|
|
|
|
#undef FM_DF /* v9 */
|
|
|
|
|
#undef FM_QF /* v9 */
|
|
|
|
|
#undef FM_SF /* v9 */
|
|
|
|
|
|
|
|
|
|
/* Coprocessor branches. */
|
|
|
|
|
#define CBR(opcode, mask, lose, flags, arch) \
|
2014-10-09 20:16:53 +08:00
|
|
|
|
{ opcode, (mask), ANNUL | (lose), "l", flags | F_DELAYED, 0, 0, arch }, \
|
|
|
|
|
{ opcode, (mask) | ANNUL, (lose), ",a l", flags | F_DELAYED, 0, 0, arch }
|
1999-05-03 15:29:11 +08:00
|
|
|
|
|
|
|
|
|
/* Floating point branches. */
|
|
|
|
|
#define FBR(opcode, mask, lose, flags) \
|
2014-10-09 20:16:53 +08:00
|
|
|
|
{ opcode, (mask), ANNUL | (lose), "l", flags | F_DELAYED | F_FBR, 0, 0, v6 }, \
|
|
|
|
|
{ opcode, (mask) | ANNUL, (lose), ",a l", flags | F_DELAYED | F_FBR, 0, 0, v6 }
|
1999-05-03 15:29:11 +08:00
|
|
|
|
|
|
|
|
|
/* V9 extended floating point branches. */
|
|
|
|
|
#define FBRX(opcode, mask, lose, flags) /* v9 */ \
|
2014-10-09 20:16:53 +08:00
|
|
|
|
{ opcode, FBFCC(0)|(mask)|BPRED, ANNUL|FBFCC(~0)|(lose), "6,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \
|
|
|
|
|
{ opcode, FBFCC(0)|(mask)|BPRED, ANNUL|FBFCC(~0)|(lose), ",T 6,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \
|
|
|
|
|
{ opcode, FBFCC(0)|(mask)|BPRED|ANNUL, FBFCC(~0)|(lose), ",a 6,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \
|
|
|
|
|
{ opcode, FBFCC(0)|(mask)|BPRED|ANNUL, FBFCC(~0)|(lose), ",a,T 6,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \
|
|
|
|
|
{ opcode, FBFCC(0)|(mask), ANNUL|BPRED|FBFCC(~0)|(lose), ",N 6,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \
|
|
|
|
|
{ opcode, FBFCC(0)|(mask)|ANNUL, BPRED|FBFCC(~0)|(lose), ",a,N 6,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \
|
|
|
|
|
{ opcode, FBFCC(1)|(mask)|BPRED, ANNUL|FBFCC(~1)|(lose), "7,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \
|
|
|
|
|
{ opcode, FBFCC(1)|(mask)|BPRED, ANNUL|FBFCC(~1)|(lose), ",T 7,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \
|
|
|
|
|
{ opcode, FBFCC(1)|(mask)|BPRED|ANNUL, FBFCC(~1)|(lose), ",a 7,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \
|
|
|
|
|
{ opcode, FBFCC(1)|(mask)|BPRED|ANNUL, FBFCC(~1)|(lose), ",a,T 7,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \
|
|
|
|
|
{ opcode, FBFCC(1)|(mask), ANNUL|BPRED|FBFCC(~1)|(lose), ",N 7,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \
|
|
|
|
|
{ opcode, FBFCC(1)|(mask)|ANNUL, BPRED|FBFCC(~1)|(lose), ",a,N 7,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \
|
|
|
|
|
{ opcode, FBFCC(2)|(mask)|BPRED, ANNUL|FBFCC(~2)|(lose), "8,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \
|
|
|
|
|
{ opcode, FBFCC(2)|(mask)|BPRED, ANNUL|FBFCC(~2)|(lose), ",T 8,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \
|
|
|
|
|
{ opcode, FBFCC(2)|(mask)|BPRED|ANNUL, FBFCC(~2)|(lose), ",a 8,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \
|
|
|
|
|
{ opcode, FBFCC(2)|(mask)|BPRED|ANNUL, FBFCC(~2)|(lose), ",a,T 8,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \
|
|
|
|
|
{ opcode, FBFCC(2)|(mask), ANNUL|BPRED|FBFCC(~2)|(lose), ",N 8,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \
|
|
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|
{ opcode, FBFCC(2)|(mask)|ANNUL, BPRED|FBFCC(~2)|(lose), ",a,N 8,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \
|
|
|
|
|
{ opcode, FBFCC(3)|(mask)|BPRED, ANNUL|FBFCC(~3)|(lose), "9,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \
|
|
|
|
|
{ opcode, FBFCC(3)|(mask)|BPRED, ANNUL|FBFCC(~3)|(lose), ",T 9,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \
|
|
|
|
|
{ opcode, FBFCC(3)|(mask)|BPRED|ANNUL, FBFCC(~3)|(lose), ",a 9,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \
|
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|
|
|
{ opcode, FBFCC(3)|(mask)|BPRED|ANNUL, FBFCC(~3)|(lose), ",a,T 9,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \
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|
|
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|
{ opcode, FBFCC(3)|(mask), ANNUL|BPRED|FBFCC(~3)|(lose), ",N 9,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \
|
|
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|
|
{ opcode, FBFCC(3)|(mask)|ANNUL, BPRED|FBFCC(~3)|(lose), ",a,N 9,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }
|
1999-05-03 15:29:11 +08:00
|
|
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|
/* v9: We must put `FBRX' before `FBR', to ensure that we never match
|
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|
v9: something against an expression unless it is an expression. Otherwise,
|
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|
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|
v9: we end up with undefined symbol tables entries, because they get added,
|
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|
|
|
v9: but are not deleted if the pattern fails to match. */
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|
|
#define CONDFC(fop, cop, mask, flags) \
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|
FBRX(fop, F2(0, 5)|COND(mask), F2(~0, ~5)|COND(~(mask)), flags), /* v9 */ \
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|
FBR(fop, F2(0, 6)|COND(mask), F2(~0, ~6)|COND(~(mask)), flags), \
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|
CBR(cop, F2(0, 7)|COND(mask), F2(~0, ~7)|COND(~(mask)), flags, v6notlet)
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|
#define CONDFCL(fop, cop, mask, flags) \
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|
FBRX(fop, F2(0, 5)|COND(mask), F2(~0, ~5)|COND(~(mask)), flags), /* v9 */ \
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|
FBR(fop, F2(0, 6)|COND(mask), F2(~0, ~6)|COND(~(mask)), flags), \
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|
CBR(cop, F2(0, 7)|COND(mask), F2(~0, ~7)|COND(~(mask)), flags, v6)
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|
#define CONDF(fop, mask, flags) \
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|
FBRX(fop, F2(0, 5)|COND(mask), F2(~0, ~5)|COND(~(mask)), flags), /* v9 */ \
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|
FBR(fop, F2(0, 6)|COND(mask), F2(~0, ~6)|COND(~(mask)), flags)
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|
2002-10-23 23:45:49 +08:00
|
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|
CONDFC ("fb", "cb", 0x8, F_UNBR),
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|
CONDFCL ("fba", "cba", 0x8, F_UNBR|F_ALIAS),
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|
CONDFC ("fbe", "cb0", 0x9, F_CONDBR),
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|
CONDF ("fbz", 0x9, F_CONDBR|F_ALIAS),
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|
CONDFC ("fbg", "cb2", 0x6, F_CONDBR),
|
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|
CONDFC ("fbge", "cb02", 0xb, F_CONDBR),
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|
|
CONDFC ("fbl", "cb1", 0x4, F_CONDBR),
|
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|
|
|
CONDFC ("fble", "cb01", 0xd, F_CONDBR),
|
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|
|
|
CONDFC ("fblg", "cb12", 0x2, F_CONDBR),
|
|
|
|
|
CONDFCL ("fbn", "cbn", 0x0, F_UNBR),
|
|
|
|
|
CONDFC ("fbne", "cb123", 0x1, F_CONDBR),
|
|
|
|
|
CONDF ("fbnz", 0x1, F_CONDBR|F_ALIAS),
|
|
|
|
|
CONDFC ("fbo", "cb012", 0xf, F_CONDBR),
|
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|
|
|
CONDFC ("fbu", "cb3", 0x7, F_CONDBR),
|
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|
|
|
CONDFC ("fbue", "cb03", 0xa, F_CONDBR),
|
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|
|
|
CONDFC ("fbug", "cb23", 0x5, F_CONDBR),
|
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|
|
|
CONDFC ("fbuge", "cb023", 0xc, F_CONDBR),
|
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|
|
|
CONDFC ("fbul", "cb13", 0x3, F_CONDBR),
|
|
|
|
|
CONDFC ("fbule", "cb013", 0xe, F_CONDBR),
|
1999-05-03 15:29:11 +08:00
|
|
|
|
|
|
|
|
|
#undef CONDFC
|
|
|
|
|
#undef CONDFCL
|
|
|
|
|
#undef CONDF
|
|
|
|
|
#undef CBR
|
|
|
|
|
#undef FBR
|
|
|
|
|
#undef FBRX /* v9 */
|
|
|
|
|
|
2014-10-09 20:16:53 +08:00
|
|
|
|
{ "jmp", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|RD_G0|ASI(~0), "1+2", F_UNBR|F_DELAYED, 0, 0, v6 }, /* jmpl rs1+rs2,%g0 */
|
|
|
|
|
{ "jmp", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|RD_G0|ASI_RS2(~0), "1", F_UNBR|F_DELAYED, 0, 0, v6 }, /* jmpl rs1+%g0,%g0 */
|
|
|
|
|
{ "jmp", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0, "1+i", F_UNBR|F_DELAYED, 0, 0, v6 }, /* jmpl rs1+i,%g0 */
|
|
|
|
|
{ "jmp", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0, "i+1", F_UNBR|F_DELAYED, 0, 0, v6 }, /* jmpl i+rs1,%g0 */
|
|
|
|
|
{ "jmp", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0|RS1_G0, "i", F_UNBR|F_DELAYED, 0, 0, v6 }, /* jmpl %g0+i,%g0 */
|
|
|
|
|
{ "jmp", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0|SIMM13(~0), "1", F_UNBR|F_DELAYED, 0, 0, v6 }, /* jmpl rs1+0,%g0 */
|
1999-05-03 15:29:11 +08:00
|
|
|
|
|
2014-10-09 20:16:53 +08:00
|
|
|
|
{ "nop", F2(0, 4), 0xfeffffff, "", 0, 0, 0, v6 }, /* sethi 0, %g0 */
|
1999-05-03 15:29:11 +08:00
|
|
|
|
|
2014-10-09 20:16:53 +08:00
|
|
|
|
{ "set", F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,d", F_ALIAS, 0, 0, v6 },
|
|
|
|
|
{ "setuw", F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,d", F_ALIAS, 0, 0, v9 },
|
|
|
|
|
{ "setsw", F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,d", F_ALIAS, 0, 0, v9 },
|
|
|
|
|
{ "setx", F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,1,d", F_ALIAS, 0, 0, v9 },
|
1999-05-03 15:29:11 +08:00
|
|
|
|
|
2014-10-09 20:16:53 +08:00
|
|
|
|
{ "sethi", F2(0x0, 0x4), F2(~0x0, ~0x4), "h,d", 0, 0, 0, v6 },
|
1999-05-03 15:29:11 +08:00
|
|
|
|
|
2014-10-09 20:16:53 +08:00
|
|
|
|
{ "taddcc", F3(2, 0x20, 0), F3(~2, ~0x20, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6 },
|
|
|
|
|
{ "taddcc", F3(2, 0x20, 1), F3(~2, ~0x20, ~1), "1,i,d", 0, 0, 0, v6 },
|
|
|
|
|
{ "taddcc", F3(2, 0x20, 1), F3(~2, ~0x20, ~1), "i,1,d", 0, 0, 0, v6 },
|
|
|
|
|
{ "taddcctv", F3(2, 0x22, 0), F3(~2, ~0x22, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6 },
|
|
|
|
|
{ "taddcctv", F3(2, 0x22, 1), F3(~2, ~0x22, ~1), "1,i,d", 0, 0, 0, v6 },
|
|
|
|
|
{ "taddcctv", F3(2, 0x22, 1), F3(~2, ~0x22, ~1), "i,1,d", 0, 0, 0, v6 },
|
1999-05-03 15:29:11 +08:00
|
|
|
|
|
2014-10-09 20:16:53 +08:00
|
|
|
|
{ "tsubcc", F3(2, 0x21, 0), F3(~2, ~0x21, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6 },
|
|
|
|
|
{ "tsubcc", F3(2, 0x21, 1), F3(~2, ~0x21, ~1), "1,i,d", 0, 0, 0, v6 },
|
|
|
|
|
{ "tsubcctv", F3(2, 0x23, 0), F3(~2, ~0x23, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6 },
|
|
|
|
|
{ "tsubcctv", F3(2, 0x23, 1), F3(~2, ~0x23, ~1), "1,i,d", 0, 0, 0, v6 },
|
1999-05-03 15:29:11 +08:00
|
|
|
|
|
2014-10-09 20:16:53 +08:00
|
|
|
|
{ "unimp", F2(0x0, 0x0), 0xffc00000, "n", 0, 0, 0, v6notv9 },
|
|
|
|
|
{ "illtrap", F2(0, 0), F2(~0, ~0)|RD_G0, "n", 0, 0, 0, v9 },
|
1999-05-03 15:29:11 +08:00
|
|
|
|
|
|
|
|
|
/* This *is* a commutative instruction. */
|
2014-10-09 20:16:53 +08:00
|
|
|
|
{ "xnor", F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6 },
|
|
|
|
|
{ "xnor", F3(2, 0x07, 1), F3(~2, ~0x07, ~1), "1,i,d", 0, 0, 0, v6 },
|
|
|
|
|
{ "xnor", F3(2, 0x07, 1), F3(~2, ~0x07, ~1), "i,1,d", 0, 0, 0, v6 },
|
1999-05-03 15:29:11 +08:00
|
|
|
|
/* This *is* a commutative instruction. */
|
2014-10-09 20:16:53 +08:00
|
|
|
|
{ "xnorcc", F3(2, 0x17, 0), F3(~2, ~0x17, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6 },
|
|
|
|
|
{ "xnorcc", F3(2, 0x17, 1), F3(~2, ~0x17, ~1), "1,i,d", 0, 0, 0, v6 },
|
|
|
|
|
{ "xnorcc", F3(2, 0x17, 1), F3(~2, ~0x17, ~1), "i,1,d", 0, 0, 0, v6 },
|
|
|
|
|
{ "xor", F3(2, 0x03, 0), F3(~2, ~0x03, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6 },
|
|
|
|
|
{ "xor", F3(2, 0x03, 1), F3(~2, ~0x03, ~1), "1,i,d", 0, 0, 0, v6 },
|
|
|
|
|
{ "xor", F3(2, 0x03, 1), F3(~2, ~0x03, ~1), "i,1,d", 0, 0, 0, v6 },
|
|
|
|
|
{ "xorcc", F3(2, 0x13, 0), F3(~2, ~0x13, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6 },
|
|
|
|
|
{ "xorcc", F3(2, 0x13, 1), F3(~2, ~0x13, ~1), "1,i,d", 0, 0, 0, v6 },
|
|
|
|
|
{ "xorcc", F3(2, 0x13, 1), F3(~2, ~0x13, ~1), "i,1,d", 0, 0, 0, v6 },
|
|
|
|
|
|
|
|
|
|
{ "not", F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0), "1,d", F_ALIAS, 0, 0, v6 }, /* xnor rs1,%0,rd */
|
|
|
|
|
{ "not", F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0), "r", F_ALIAS, 0, 0, v6 }, /* xnor rd,%0,rd */
|
|
|
|
|
|
|
|
|
|
{ "btog", F3(2, 0x03, 0), F3(~2, ~0x03, ~0)|ASI(~0), "2,r", F_ALIAS, 0, 0, v6 }, /* xor rd,rs2,rd */
|
|
|
|
|
{ "btog", F3(2, 0x03, 1), F3(~2, ~0x03, ~1), "i,r", F_ALIAS, 0, 0, v6 }, /* xor rd,i,rd */
|
1999-05-03 15:29:11 +08:00
|
|
|
|
|
|
|
|
|
/* FPop1 and FPop2 are not instructions. Don't accept them. */
|
|
|
|
|
|
2014-10-09 20:16:53 +08:00
|
|
|
|
{ "fdtoi", F3F(2, 0x34, 0x0d2), F3F(~2, ~0x34, ~0x0d2)|RS1_G0, "B,g", F_FLOAT, 0, 0, v6 },
|
|
|
|
|
{ "fstoi", F3F(2, 0x34, 0x0d1), F3F(~2, ~0x34, ~0x0d1)|RS1_G0, "f,g", F_FLOAT, 0, 0, v6 },
|
|
|
|
|
{ "fqtoi", F3F(2, 0x34, 0x0d3), F3F(~2, ~0x34, ~0x0d3)|RS1_G0, "R,g", F_FLOAT, 0, 0, v8 },
|
|
|
|
|
|
|
|
|
|
{ "fdtox", F3F(2, 0x34, 0x082), F3F(~2, ~0x34, ~0x082)|RS1_G0, "B,H", F_FLOAT, 0, 0, v9 },
|
|
|
|
|
{ "fstox", F3F(2, 0x34, 0x081), F3F(~2, ~0x34, ~0x081)|RS1_G0, "f,H", F_FLOAT, 0, 0, v9 },
|
|
|
|
|
{ "fqtox", F3F(2, 0x34, 0x083), F3F(~2, ~0x34, ~0x083)|RS1_G0, "R,H", F_FLOAT, 0, 0, v9 },
|
|
|
|
|
|
|
|
|
|
{ "fitod", F3F(2, 0x34, 0x0c8), F3F(~2, ~0x34, ~0x0c8)|RS1_G0, "f,H", F_FLOAT, 0, 0, v6 },
|
|
|
|
|
{ "fitos", F3F(2, 0x34, 0x0c4), F3F(~2, ~0x34, ~0x0c4)|RS1_G0, "f,g", F_FLOAT, 0, 0, v6 },
|
|
|
|
|
{ "fitoq", F3F(2, 0x34, 0x0cc), F3F(~2, ~0x34, ~0x0cc)|RS1_G0, "f,J", F_FLOAT, 0, 0, v8 },
|
|
|
|
|
|
|
|
|
|
{ "fxtod", F3F(2, 0x34, 0x088), F3F(~2, ~0x34, ~0x088)|RS1_G0, "B,H", F_FLOAT, 0, 0, v9 },
|
|
|
|
|
{ "fxtos", F3F(2, 0x34, 0x084), F3F(~2, ~0x34, ~0x084)|RS1_G0, "B,g", F_FLOAT, 0, 0, v9 },
|
|
|
|
|
{ "fxtoq", F3F(2, 0x34, 0x08c), F3F(~2, ~0x34, ~0x08c)|RS1_G0, "B,J", F_FLOAT, 0, 0, v9 },
|
|
|
|
|
|
|
|
|
|
{ "fdtoq", F3F(2, 0x34, 0x0ce), F3F(~2, ~0x34, ~0x0ce)|RS1_G0, "B,J", F_FLOAT, 0, 0, v8 },
|
|
|
|
|
{ "fdtos", F3F(2, 0x34, 0x0c6), F3F(~2, ~0x34, ~0x0c6)|RS1_G0, "B,g", F_FLOAT, 0, 0, v6 },
|
|
|
|
|
{ "fqtod", F3F(2, 0x34, 0x0cb), F3F(~2, ~0x34, ~0x0cb)|RS1_G0, "R,H", F_FLOAT, 0, 0, v8 },
|
|
|
|
|
{ "fqtos", F3F(2, 0x34, 0x0c7), F3F(~2, ~0x34, ~0x0c7)|RS1_G0, "R,g", F_FLOAT, 0, 0, v8 },
|
|
|
|
|
{ "fstod", F3F(2, 0x34, 0x0c9), F3F(~2, ~0x34, ~0x0c9)|RS1_G0, "f,H", F_FLOAT, 0, 0, v6 },
|
|
|
|
|
{ "fstoq", F3F(2, 0x34, 0x0cd), F3F(~2, ~0x34, ~0x0cd)|RS1_G0, "f,J", F_FLOAT, 0, 0, v8 },
|
|
|
|
|
|
|
|
|
|
{ "fdivd", F3F(2, 0x34, 0x04e), F3F(~2, ~0x34, ~0x04e), "v,B,H", F_FLOAT, 0, 0, v6 },
|
|
|
|
|
{ "fdivq", F3F(2, 0x34, 0x04f), F3F(~2, ~0x34, ~0x04f), "V,R,J", F_FLOAT, 0, 0, v8 },
|
|
|
|
|
{ "fdivx", F3F(2, 0x34, 0x04f), F3F(~2, ~0x34, ~0x04f), "V,R,J", F_FLOAT|F_ALIAS, 0, 0, v8 },
|
|
|
|
|
{ "fdivs", F3F(2, 0x34, 0x04d), F3F(~2, ~0x34, ~0x04d), "e,f,g", F_FLOAT, 0, 0, v6 },
|
|
|
|
|
{ "fmuld", F3F(2, 0x34, 0x04a), F3F(~2, ~0x34, ~0x04a), "v,B,H", F_FLOAT, 0, 0, v6 },
|
|
|
|
|
{ "fmulq", F3F(2, 0x34, 0x04b), F3F(~2, ~0x34, ~0x04b), "V,R,J", F_FLOAT, 0, 0, v8 },
|
|
|
|
|
{ "fmulx", F3F(2, 0x34, 0x04b), F3F(~2, ~0x34, ~0x04b), "V,R,J", F_FLOAT|F_ALIAS, 0, 0, v8 },
|
|
|
|
|
{ "fmuls", F3F(2, 0x34, 0x049), F3F(~2, ~0x34, ~0x049), "e,f,g", F_FLOAT, 0, 0, v6 },
|
|
|
|
|
|
|
|
|
|
{ "fdmulq", F3F(2, 0x34, 0x06e), F3F(~2, ~0x34, ~0x06e), "v,B,J", F_FLOAT, 0, 0, v8 },
|
|
|
|
|
{ "fdmulx", F3F(2, 0x34, 0x06e), F3F(~2, ~0x34, ~0x06e), "v,B,J", F_FLOAT|F_ALIAS, 0, 0, v8 },
|
|
|
|
|
{ "fsmuld", F3F(2, 0x34, 0x069), F3F(~2, ~0x34, ~0x069), "e,f,H", F_FLOAT, HWCAP_FSMULD, 0, v8 },
|
|
|
|
|
|
|
|
|
|
{ "fsqrtd", F3F(2, 0x34, 0x02a), F3F(~2, ~0x34, ~0x02a)|RS1_G0, "B,H", F_FLOAT, 0, 0, v7 },
|
|
|
|
|
{ "fsqrtq", F3F(2, 0x34, 0x02b), F3F(~2, ~0x34, ~0x02b)|RS1_G0, "R,J", F_FLOAT, 0, 0, v8 },
|
|
|
|
|
{ "fsqrtx", F3F(2, 0x34, 0x02b), F3F(~2, ~0x34, ~0x02b)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, 0, 0, v8 },
|
|
|
|
|
{ "fsqrts", F3F(2, 0x34, 0x029), F3F(~2, ~0x34, ~0x029)|RS1_G0, "f,g", F_FLOAT, 0, 0, v7 },
|
|
|
|
|
|
|
|
|
|
{ "fabsd", F3F(2, 0x34, 0x00a), F3F(~2, ~0x34, ~0x00a)|RS1_G0, "B,H", F_FLOAT, 0, 0, v9 },
|
|
|
|
|
{ "fabsq", F3F(2, 0x34, 0x00b), F3F(~2, ~0x34, ~0x00b)|RS1_G0, "R,J", F_FLOAT, 0, 0, v9 },
|
|
|
|
|
{ "fabsx", F3F(2, 0x34, 0x00b), F3F(~2, ~0x34, ~0x00b)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, 0, 0, v9 },
|
|
|
|
|
{ "fabss", F3F(2, 0x34, 0x009), F3F(~2, ~0x34, ~0x009)|RS1_G0, "f,g", F_FLOAT, 0, 0, v6 },
|
|
|
|
|
{ "fmovd", F3F(2, 0x34, 0x002), F3F(~2, ~0x34, ~0x002)|RS1_G0, "B,H", F_FLOAT, 0, 0, v9 },
|
|
|
|
|
{ "fmovq", F3F(2, 0x34, 0x003), F3F(~2, ~0x34, ~0x003)|RS1_G0, "R,J", F_FLOAT, 0, 0, v9 },
|
|
|
|
|
{ "fmovx", F3F(2, 0x34, 0x003), F3F(~2, ~0x34, ~0x003)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, 0, 0, v9 },
|
|
|
|
|
{ "fmovs", F3F(2, 0x34, 0x001), F3F(~2, ~0x34, ~0x001)|RS1_G0, "f,g", F_FLOAT, 0, 0, v6 },
|
|
|
|
|
{ "fnegd", F3F(2, 0x34, 0x006), F3F(~2, ~0x34, ~0x006)|RS1_G0, "B,H", F_FLOAT, 0, 0, v9 },
|
|
|
|
|
{ "fnegq", F3F(2, 0x34, 0x007), F3F(~2, ~0x34, ~0x007)|RS1_G0, "R,J", F_FLOAT, 0, 0, v9 },
|
|
|
|
|
{ "fnegx", F3F(2, 0x34, 0x007), F3F(~2, ~0x34, ~0x007)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, 0, 0, v9 },
|
|
|
|
|
{ "fnegs", F3F(2, 0x34, 0x005), F3F(~2, ~0x34, ~0x005)|RS1_G0, "f,g", F_FLOAT, 0, 0, v6 },
|
|
|
|
|
|
|
|
|
|
{ "faddd", F3F(2, 0x34, 0x042), F3F(~2, ~0x34, ~0x042), "v,B,H", F_FLOAT, 0, 0, v6 },
|
|
|
|
|
{ "faddq", F3F(2, 0x34, 0x043), F3F(~2, ~0x34, ~0x043), "V,R,J", F_FLOAT, 0, 0, v8 },
|
|
|
|
|
{ "faddx", F3F(2, 0x34, 0x043), F3F(~2, ~0x34, ~0x043), "V,R,J", F_FLOAT|F_ALIAS, 0, 0, v8 },
|
|
|
|
|
{ "fadds", F3F(2, 0x34, 0x041), F3F(~2, ~0x34, ~0x041), "e,f,g", F_FLOAT, 0, 0, v6 },
|
|
|
|
|
{ "fsubd", F3F(2, 0x34, 0x046), F3F(~2, ~0x34, ~0x046), "v,B,H", F_FLOAT, 0, 0, v6 },
|
|
|
|
|
{ "fsubq", F3F(2, 0x34, 0x047), F3F(~2, ~0x34, ~0x047), "V,R,J", F_FLOAT, 0, 0, v8 },
|
|
|
|
|
{ "fsubx", F3F(2, 0x34, 0x047), F3F(~2, ~0x34, ~0x047), "V,R,J", F_FLOAT|F_ALIAS, 0, 0, v8 },
|
|
|
|
|
{ "fsubs", F3F(2, 0x34, 0x045), F3F(~2, ~0x34, ~0x045), "e,f,g", F_FLOAT, 0, 0, v6 },
|
1999-05-03 15:29:11 +08:00
|
|
|
|
|
|
|
|
|
#define CMPFCC(x) (((x)&0x3)<<25)
|
|
|
|
|
|
2014-10-09 20:16:53 +08:00
|
|
|
|
{ "fcmpd", F3F(2, 0x35, 0x052), F3F(~2, ~0x35, ~0x052)|RD_G0, "v,B", F_FLOAT, 0, 0, v6 },
|
|
|
|
|
{ "fcmpd", CMPFCC(0)|F3F(2, 0x35, 0x052), CMPFCC(~0)|F3F(~2, ~0x35, ~0x052), "6,v,B", F_FLOAT, 0, 0, v9 },
|
|
|
|
|
{ "fcmpd", CMPFCC(1)|F3F(2, 0x35, 0x052), CMPFCC(~1)|F3F(~2, ~0x35, ~0x052), "7,v,B", F_FLOAT, 0, 0, v9 },
|
|
|
|
|
{ "fcmpd", CMPFCC(2)|F3F(2, 0x35, 0x052), CMPFCC(~2)|F3F(~2, ~0x35, ~0x052), "8,v,B", F_FLOAT, 0, 0, v9 },
|
|
|
|
|
{ "fcmpd", CMPFCC(3)|F3F(2, 0x35, 0x052), CMPFCC(~3)|F3F(~2, ~0x35, ~0x052), "9,v,B", F_FLOAT, 0, 0, v9 },
|
|
|
|
|
{ "fcmped", F3F(2, 0x35, 0x056), F3F(~2, ~0x35, ~0x056)|RD_G0, "v,B", F_FLOAT, 0, 0, v6 },
|
|
|
|
|
{ "fcmped", CMPFCC(0)|F3F(2, 0x35, 0x056), CMPFCC(~0)|F3F(~2, ~0x35, ~0x056), "6,v,B", F_FLOAT, 0, 0, v9 },
|
|
|
|
|
{ "fcmped", CMPFCC(1)|F3F(2, 0x35, 0x056), CMPFCC(~1)|F3F(~2, ~0x35, ~0x056), "7,v,B", F_FLOAT, 0, 0, v9 },
|
|
|
|
|
{ "fcmped", CMPFCC(2)|F3F(2, 0x35, 0x056), CMPFCC(~2)|F3F(~2, ~0x35, ~0x056), "8,v,B", F_FLOAT, 0, 0, v9 },
|
|
|
|
|
{ "fcmped", CMPFCC(3)|F3F(2, 0x35, 0x056), CMPFCC(~3)|F3F(~2, ~0x35, ~0x056), "9,v,B", F_FLOAT, 0, 0, v9 },
|
|
|
|
|
{ "fcmpq", F3F(2, 0x35, 0x053), F3F(~2, ~0x35, ~0x053)|RD_G0, "V,R", F_FLOAT, 0, 0, v8 },
|
|
|
|
|
{ "fcmpq", CMPFCC(0)|F3F(2, 0x35, 0x053), CMPFCC(~0)|F3F(~2, ~0x35, ~0x053), "6,V,R", F_FLOAT, 0, 0, v9 },
|
|
|
|
|
{ "fcmpq", CMPFCC(1)|F3F(2, 0x35, 0x053), CMPFCC(~1)|F3F(~2, ~0x35, ~0x053), "7,V,R", F_FLOAT, 0, 0, v9 },
|
|
|
|
|
{ "fcmpq", CMPFCC(2)|F3F(2, 0x35, 0x053), CMPFCC(~2)|F3F(~2, ~0x35, ~0x053), "8,V,R", F_FLOAT, 0, 0, v9 },
|
|
|
|
|
{ "fcmpq", CMPFCC(3)|F3F(2, 0x35, 0x053), CMPFCC(~3)|F3F(~2, ~0x35, ~0x053), "9,V,R", F_FLOAT, 0, 0, v9 },
|
|
|
|
|
{ "fcmpeq", F3F(2, 0x35, 0x057), F3F(~2, ~0x35, ~0x057)|RD_G0, "V,R", F_FLOAT, 0, 0, v8 },
|
|
|
|
|
{ "fcmpeq", CMPFCC(0)|F3F(2, 0x35, 0x057), CMPFCC(~0)|F3F(~2, ~0x35, ~0x057), "6,V,R", F_FLOAT, 0, 0, v9 },
|
|
|
|
|
{ "fcmpeq", CMPFCC(1)|F3F(2, 0x35, 0x057), CMPFCC(~1)|F3F(~2, ~0x35, ~0x057), "7,V,R", F_FLOAT, 0, 0, v9 },
|
|
|
|
|
{ "fcmpeq", CMPFCC(2)|F3F(2, 0x35, 0x057), CMPFCC(~2)|F3F(~2, ~0x35, ~0x057), "8,V,R", F_FLOAT, 0, 0, v9 },
|
|
|
|
|
{ "fcmpeq", CMPFCC(3)|F3F(2, 0x35, 0x057), CMPFCC(~3)|F3F(~2, ~0x35, ~0x057), "9,V,R", F_FLOAT, 0, 0, v9 },
|
|
|
|
|
{ "fcmpx", F3F(2, 0x35, 0x053), F3F(~2, ~0x35, ~0x053)|RD_G0, "V,R", F_FLOAT|F_ALIAS, 0, 0, v8 },
|
|
|
|
|
{ "fcmpx", CMPFCC(0)|F3F(2, 0x35, 0x053), CMPFCC(~0)|F3F(~2, ~0x35, ~0x053), "6,V,R", F_FLOAT|F_ALIAS, 0, 0, v9 },
|
|
|
|
|
{ "fcmpx", CMPFCC(1)|F3F(2, 0x35, 0x053), CMPFCC(~1)|F3F(~2, ~0x35, ~0x053), "7,V,R", F_FLOAT|F_ALIAS, 0, 0, v9 },
|
|
|
|
|
{ "fcmpx", CMPFCC(2)|F3F(2, 0x35, 0x053), CMPFCC(~2)|F3F(~2, ~0x35, ~0x053), "8,V,R", F_FLOAT|F_ALIAS, 0, 0, v9 },
|
|
|
|
|
{ "fcmpx", CMPFCC(3)|F3F(2, 0x35, 0x053), CMPFCC(~3)|F3F(~2, ~0x35, ~0x053), "9,V,R", F_FLOAT|F_ALIAS, 0, 0, v9 },
|
|
|
|
|
{ "fcmpex", F3F(2, 0x35, 0x057), F3F(~2, ~0x35, ~0x057)|RD_G0, "V,R", F_FLOAT|F_ALIAS, 0, 0, v8 },
|
|
|
|
|
{ "fcmpex", CMPFCC(0)|F3F(2, 0x35, 0x057), CMPFCC(~0)|F3F(~2, ~0x35, ~0x057), "6,V,R", F_FLOAT|F_ALIAS, 0, 0, v9 },
|
|
|
|
|
{ "fcmpex", CMPFCC(1)|F3F(2, 0x35, 0x057), CMPFCC(~1)|F3F(~2, ~0x35, ~0x057), "7,V,R", F_FLOAT|F_ALIAS, 0, 0, v9 },
|
|
|
|
|
{ "fcmpex", CMPFCC(2)|F3F(2, 0x35, 0x057), CMPFCC(~2)|F3F(~2, ~0x35, ~0x057), "8,V,R", F_FLOAT|F_ALIAS, 0, 0, v9 },
|
|
|
|
|
{ "fcmpex", CMPFCC(3)|F3F(2, 0x35, 0x057), CMPFCC(~3)|F3F(~2, ~0x35, ~0x057), "9,V,R", F_FLOAT|F_ALIAS, 0, 0, v9 },
|
|
|
|
|
{ "fcmps", F3F(2, 0x35, 0x051), F3F(~2, ~0x35, ~0x051)|RD_G0, "e,f", F_FLOAT, 0, 0, v6 },
|
|
|
|
|
{ "fcmps", CMPFCC(0)|F3F(2, 0x35, 0x051), CMPFCC(~0)|F3F(~2, ~0x35, ~0x051), "6,e,f", F_FLOAT, 0, 0, v9 },
|
|
|
|
|
{ "fcmps", CMPFCC(1)|F3F(2, 0x35, 0x051), CMPFCC(~1)|F3F(~2, ~0x35, ~0x051), "7,e,f", F_FLOAT, 0, 0, v9 },
|
|
|
|
|
{ "fcmps", CMPFCC(2)|F3F(2, 0x35, 0x051), CMPFCC(~2)|F3F(~2, ~0x35, ~0x051), "8,e,f", F_FLOAT, 0, 0, v9 },
|
|
|
|
|
{ "fcmps", CMPFCC(3)|F3F(2, 0x35, 0x051), CMPFCC(~3)|F3F(~2, ~0x35, ~0x051), "9,e,f", F_FLOAT, 0, 0, v9 },
|
|
|
|
|
{ "fcmpes", F3F(2, 0x35, 0x055), F3F(~2, ~0x35, ~0x055)|RD_G0, "e,f", F_FLOAT, 0, 0, v6 },
|
|
|
|
|
{ "fcmpes", CMPFCC(0)|F3F(2, 0x35, 0x055), CMPFCC(~0)|F3F(~2, ~0x35, ~0x055), "6,e,f", F_FLOAT, 0, 0, v9 },
|
|
|
|
|
{ "fcmpes", CMPFCC(1)|F3F(2, 0x35, 0x055), CMPFCC(~1)|F3F(~2, ~0x35, ~0x055), "7,e,f", F_FLOAT, 0, 0, v9 },
|
|
|
|
|
{ "fcmpes", CMPFCC(2)|F3F(2, 0x35, 0x055), CMPFCC(~2)|F3F(~2, ~0x35, ~0x055), "8,e,f", F_FLOAT, 0, 0, v9 },
|
|
|
|
|
{ "fcmpes", CMPFCC(3)|F3F(2, 0x35, 0x055), CMPFCC(~3)|F3F(~2, ~0x35, ~0x055), "9,e,f", F_FLOAT, 0, 0, v9 },
|
1999-05-03 15:29:11 +08:00
|
|
|
|
|
|
|
|
|
/* These Extended FPop (FIFO) instructions are new in the Fujitsu
|
|
|
|
|
MB86934, replacing the CPop instructions from v6 and later
|
|
|
|
|
processors. */
|
|
|
|
|
|
2014-10-09 20:16:53 +08:00
|
|
|
|
#define EFPOP1_2(name, op, args) { name, F3F(2, 0x36, op), F3F(~2, ~0x36, ~op)|RS1_G0, args, 0, 0, 0, sparclite }
|
|
|
|
|
#define EFPOP1_3(name, op, args) { name, F3F(2, 0x36, op), F3F(~2, ~0x36, ~op), args, 0, 0, 0, sparclite }
|
|
|
|
|
#define EFPOP2_2(name, op, args) { name, F3F(2, 0x37, op), F3F(~2, ~0x37, ~op)|RD_G0, args, 0, 0, 0, sparclite }
|
1999-05-03 15:29:11 +08:00
|
|
|
|
|
|
|
|
|
EFPOP1_2 ("efitod", 0x0c8, "f,H"),
|
|
|
|
|
EFPOP1_2 ("efitos", 0x0c4, "f,g"),
|
|
|
|
|
EFPOP1_2 ("efdtoi", 0x0d2, "B,g"),
|
|
|
|
|
EFPOP1_2 ("efstoi", 0x0d1, "f,g"),
|
|
|
|
|
EFPOP1_2 ("efstod", 0x0c9, "f,H"),
|
|
|
|
|
EFPOP1_2 ("efdtos", 0x0c6, "B,g"),
|
|
|
|
|
EFPOP1_2 ("efmovs", 0x001, "f,g"),
|
|
|
|
|
EFPOP1_2 ("efnegs", 0x005, "f,g"),
|
|
|
|
|
EFPOP1_2 ("efabss", 0x009, "f,g"),
|
|
|
|
|
EFPOP1_2 ("efsqrtd", 0x02a, "B,H"),
|
|
|
|
|
EFPOP1_2 ("efsqrts", 0x029, "f,g"),
|
|
|
|
|
EFPOP1_3 ("efaddd", 0x042, "v,B,H"),
|
|
|
|
|
EFPOP1_3 ("efadds", 0x041, "e,f,g"),
|
|
|
|
|
EFPOP1_3 ("efsubd", 0x046, "v,B,H"),
|
|
|
|
|
EFPOP1_3 ("efsubs", 0x045, "e,f,g"),
|
|
|
|
|
EFPOP1_3 ("efdivd", 0x04e, "v,B,H"),
|
|
|
|
|
EFPOP1_3 ("efdivs", 0x04d, "e,f,g"),
|
|
|
|
|
EFPOP1_3 ("efmuld", 0x04a, "v,B,H"),
|
|
|
|
|
EFPOP1_3 ("efmuls", 0x049, "e,f,g"),
|
|
|
|
|
EFPOP1_3 ("efsmuld", 0x069, "e,f,H"),
|
|
|
|
|
EFPOP2_2 ("efcmpd", 0x052, "v,B"),
|
|
|
|
|
EFPOP2_2 ("efcmped", 0x056, "v,B"),
|
|
|
|
|
EFPOP2_2 ("efcmps", 0x051, "e,f"),
|
|
|
|
|
EFPOP2_2 ("efcmpes", 0x055, "e,f"),
|
|
|
|
|
|
|
|
|
|
#undef EFPOP1_2
|
|
|
|
|
#undef EFPOP1_3
|
|
|
|
|
#undef EFPOP2_2
|
|
|
|
|
|
|
|
|
|
/* These are marked F_ALIAS, so that they won't conflict with sparclite insns
|
|
|
|
|
present. Otherwise, the F_ALIAS flag is ignored. */
|
2014-10-09 20:16:53 +08:00
|
|
|
|
{ "cpop1", F3(2, 0x36, 0), F3(~2, ~0x36, ~1), "[1+2],d", F_ALIAS, 0, 0, v6notv9 },
|
|
|
|
|
{ "cpop2", F3(2, 0x37, 0), F3(~2, ~0x37, ~1), "[1+2],d", F_ALIAS, 0, 0, v6notv9 },
|
1999-05-03 15:29:11 +08:00
|
|
|
|
|
|
|
|
|
/* sparclet specific insns */
|
|
|
|
|
|
2013-08-06 00:11:07 +08:00
|
|
|
|
COMMUTEOP ("umac", 0x3e, letandleon),
|
|
|
|
|
COMMUTEOP ("smac", 0x3f, letandleon),
|
|
|
|
|
|
1999-05-03 15:29:11 +08:00
|
|
|
|
COMMUTEOP ("umacd", 0x2e, sparclet),
|
|
|
|
|
COMMUTEOP ("smacd", 0x2f, sparclet),
|
|
|
|
|
COMMUTEOP ("umuld", 0x09, sparclet),
|
|
|
|
|
COMMUTEOP ("smuld", 0x0d, sparclet),
|
|
|
|
|
|
2014-10-09 20:16:53 +08:00
|
|
|
|
{ "shuffle", F3(2, 0x2d, 0), F3(~2, ~0x2d, ~0)|ASI(~0), "1,2,d", 0, 0, 0, sparclet },
|
|
|
|
|
{ "shuffle", F3(2, 0x2d, 1), F3(~2, ~0x2d, ~1), "1,i,d", 0, 0, 0, sparclet },
|
1999-05-03 15:29:11 +08:00
|
|
|
|
|
|
|
|
|
/* The manual isn't completely accurate on these insns. The `rs2' field is
|
|
|
|
|
treated as being 6 bits to account for 6 bit immediates to cpush. It is
|
|
|
|
|
assumed that it is intended that bit 5 is 0 when rs2 contains a reg. */
|
|
|
|
|
#define BIT5 (1<<5)
|
2014-10-09 20:16:53 +08:00
|
|
|
|
{ "crdcxt", F3(2, 0x36, 0)|SLCPOP(4), F3(~2, ~0x36, ~0)|SLCPOP(~4)|BIT5|RS2(~0), "U,d", 0, 0, 0, sparclet },
|
|
|
|
|
{ "cwrcxt", F3(2, 0x36, 0)|SLCPOP(3), F3(~2, ~0x36, ~0)|SLCPOP(~3)|BIT5|RS2(~0), "1,u", 0, 0, 0, sparclet },
|
|
|
|
|
{ "cpush", F3(2, 0x36, 0)|SLCPOP(0), F3(~2, ~0x36, ~0)|SLCPOP(~0)|BIT5|RD(~0), "1,2", 0, 0, 0, sparclet },
|
|
|
|
|
{ "cpush", F3(2, 0x36, 1)|SLCPOP(0), F3(~2, ~0x36, ~1)|SLCPOP(~0)|RD(~0), "1,Y", 0, 0, 0, sparclet },
|
|
|
|
|
{ "cpusha", F3(2, 0x36, 0)|SLCPOP(1), F3(~2, ~0x36, ~0)|SLCPOP(~1)|BIT5|RD(~0), "1,2", 0, 0, 0, sparclet },
|
|
|
|
|
{ "cpusha", F3(2, 0x36, 1)|SLCPOP(1), F3(~2, ~0x36, ~1)|SLCPOP(~1)|RD(~0), "1,Y", 0, 0, 0, sparclet },
|
|
|
|
|
{ "cpull", F3(2, 0x36, 0)|SLCPOP(2), F3(~2, ~0x36, ~0)|SLCPOP(~2)|BIT5|RS1(~0)|RS2(~0), "d", 0, 0, 0, sparclet },
|
1999-05-03 15:29:11 +08:00
|
|
|
|
#undef BIT5
|
|
|
|
|
|
|
|
|
|
/* sparclet coprocessor branch insns */
|
|
|
|
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#define SLCBCC2(opcode, mask, lose) \
|
2014-10-09 20:16:53 +08:00
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{ opcode, (mask), ANNUL|(lose), "l", F_DELAYED|F_CONDBR, 0, 0, sparclet }, \
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{ opcode, (mask)|ANNUL, (lose), ",a l", F_DELAYED|F_CONDBR, 0, 0, sparclet }
|
1999-05-03 15:29:11 +08:00
|
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|
#define SLCBCC(opcode, mask) \
|
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SLCBCC2(opcode, F2(0, 7)|COND(mask), F2(~0, ~7)|COND(~(mask)))
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/* cbn,cba can't be defined here because they're defined elsewhere and GAS
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requires all mnemonics of the same name to be consecutive. */
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/*SLCBCC("cbn", 0), - already defined */
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SLCBCC("cbe", 1),
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SLCBCC("cbf", 2),
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SLCBCC("cbef", 3),
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SLCBCC("cbr", 4),
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SLCBCC("cber", 5),
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SLCBCC("cbfr", 6),
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SLCBCC("cbefr", 7),
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/*SLCBCC("cba", 8), - already defined */
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SLCBCC("cbne", 9),
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SLCBCC("cbnf", 10),
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SLCBCC("cbnef", 11),
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SLCBCC("cbnr", 12),
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SLCBCC("cbner", 13),
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SLCBCC("cbnfr", 14),
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SLCBCC("cbnefr", 15),
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#undef SLCBCC2
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#undef SLCBCC
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|
2014-10-09 20:16:53 +08:00
|
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|
{ "casa", F3(3, 0x3c, 0), F3(~3, ~0x3c, ~0), "[1]A,2,d", 0, 0, 0, v9andleon },
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{ "casa", F3(3, 0x3c, 1), F3(~3, ~0x3c, ~1), "[1]o,2,d", 0, 0, 0, v9andleon },
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|
{ "casxa", F3(3, 0x3e, 0), F3(~3, ~0x3e, ~0), "[1]A,2,d", 0, 0, 0, v9 },
|
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|
{ "casxa", F3(3, 0x3e, 1), F3(~3, ~0x3e, ~1), "[1]o,2,d", 0, 0, 0, v9 },
|
1999-05-03 15:29:11 +08:00
|
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|
|
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|
/* v9 synthetic insns */
|
2014-10-09 20:16:53 +08:00
|
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{ "iprefetch", F2(0, 1)|(2<<20)|BPRED, F2(~0, ~1)|(1<<20)|ANNUL|COND(~0), "G", 0, 0, 0, v9 }, /* bn,a,pt %xcc,label */
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|
{ "signx", F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|ASI(~0)|RS2_G0, "1,d", F_ALIAS, 0, 0, v9 }, /* sra rs1,%g0,rd */
|
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|
{ "signx", F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|ASI(~0)|RS2_G0, "r", F_ALIAS, 0, 0, v9 }, /* sra rd,%g0,rd */
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|
{ "clruw", F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|ASI(~0)|RS2_G0, "1,d", F_ALIAS, 0, 0, v9 }, /* srl rs1,%g0,rd */
|
|
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|
|
{ "clruw", F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|ASI(~0)|RS2_G0, "r", F_ALIAS, 0, 0, v9 }, /* srl rd,%g0,rd */
|
|
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|
{ "cas", F3(3, 0x3c, 0)|ASI(0x80), F3(~3, ~0x3c, ~0)|ASI(~0x80), "[1],2,d", F_ALIAS, 0, 0, v9 }, /* casa [rs1]ASI_P,rs2,rd */
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|
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|
{ "casl", F3(3, 0x3c, 0)|ASI(0x88), F3(~3, ~0x3c, ~0)|ASI(~0x88), "[1],2,d", F_ALIAS, 0, 0, v9 }, /* casa [rs1]ASI_P_L,rs2,rd */
|
|
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|
|
{ "casx", F3(3, 0x3e, 0)|ASI(0x80), F3(~3, ~0x3e, ~0)|ASI(~0x80), "[1],2,d", F_ALIAS, 0, 0, v9 }, /* casxa [rs1]ASI_P,rs2,rd */
|
|
|
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|
{ "casxl", F3(3, 0x3e, 0)|ASI(0x88), F3(~3, ~0x3e, ~0)|ASI(~0x88), "[1],2,d", F_ALIAS, 0, 0, v9 }, /* casxa [rs1]ASI_P_L,rs2,rd */
|
1999-05-03 15:29:11 +08:00
|
|
|
|
|
|
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|
|
/* Ultrasparc extensions */
|
2014-10-09 20:16:53 +08:00
|
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|
|
{ "shutdown", F3F(2, 0x36, 0x080), F3F(~2, ~0x36, ~0x080)|RD_G0|RS1_G0|RS2_G0, "", 0, HWCAP_VIS, 0, v9a },
|
1999-05-03 15:29:11 +08:00
|
|
|
|
|
|
|
|
|
/* FIXME: Do we want to mark these as F_FLOAT, or something similar? */
|
2014-10-09 20:16:53 +08:00
|
|
|
|
{ "fpadd16", F3F(2, 0x36, 0x050), F3F(~2, ~0x36, ~0x050), "v,B,H", 0, HWCAP_VIS, 0, v9a },
|
|
|
|
|
{ "fpadd16s", F3F(2, 0x36, 0x051), F3F(~2, ~0x36, ~0x051), "e,f,g", 0, HWCAP_VIS, 0, v9a },
|
|
|
|
|
{ "fpadd32", F3F(2, 0x36, 0x052), F3F(~2, ~0x36, ~0x052), "v,B,H", 0, HWCAP_VIS, 0, v9a },
|
|
|
|
|
{ "fpadd32s", F3F(2, 0x36, 0x053), F3F(~2, ~0x36, ~0x053), "e,f,g", 0, HWCAP_VIS, 0, v9a },
|
|
|
|
|
{ "fpsub16", F3F(2, 0x36, 0x054), F3F(~2, ~0x36, ~0x054), "v,B,H", 0, HWCAP_VIS, 0, v9a },
|
|
|
|
|
{ "fpsub16s", F3F(2, 0x36, 0x055), F3F(~2, ~0x36, ~0x055), "e,f,g", 0, HWCAP_VIS, 0, v9a },
|
|
|
|
|
{ "fpsub32", F3F(2, 0x36, 0x056), F3F(~2, ~0x36, ~0x056), "v,B,H", 0, HWCAP_VIS, 0, v9a },
|
|
|
|
|
{ "fpsub32s", F3F(2, 0x36, 0x057), F3F(~2, ~0x36, ~0x057), "e,f,g", 0, HWCAP_VIS, 0, v9a },
|
|
|
|
|
|
|
|
|
|
{ "fpack32", F3F(2, 0x36, 0x03a), F3F(~2, ~0x36, ~0x03a), "v,B,H", 0, HWCAP_VIS, 0, v9a },
|
|
|
|
|
{ "fpack16", F3F(2, 0x36, 0x03b), F3F(~2, ~0x36, ~0x03b)|RS1_G0, "B,g", 0, HWCAP_VIS, 0, v9a },
|
|
|
|
|
{ "fpackfix", F3F(2, 0x36, 0x03d), F3F(~2, ~0x36, ~0x03d)|RS1_G0, "B,g", 0, HWCAP_VIS, 0, v9a },
|
|
|
|
|
{ "fexpand", F3F(2, 0x36, 0x04d), F3F(~2, ~0x36, ~0x04d)|RS1_G0, "f,H", 0, HWCAP_VIS, 0, v9a },
|
|
|
|
|
{ "fpmerge", F3F(2, 0x36, 0x04b), F3F(~2, ~0x36, ~0x04b), "e,f,H", 0, HWCAP_VIS, 0, v9a },
|
1999-05-03 15:29:11 +08:00
|
|
|
|
|
|
|
|
|
/* Note that the mixing of 32/64 bit regs is intentional. */
|
2014-10-09 20:16:53 +08:00
|
|
|
|
{ "fmul8x16", F3F(2, 0x36, 0x031), F3F(~2, ~0x36, ~0x031), "e,B,H", 0, HWCAP_VIS, 0, v9a },
|
|
|
|
|
{ "fmul8x16au", F3F(2, 0x36, 0x033), F3F(~2, ~0x36, ~0x033), "e,f,H", 0, HWCAP_VIS, 0, v9a },
|
|
|
|
|
{ "fmul8x16al", F3F(2, 0x36, 0x035), F3F(~2, ~0x36, ~0x035), "e,f,H", 0, HWCAP_VIS, 0, v9a },
|
|
|
|
|
{ "fmul8sux16", F3F(2, 0x36, 0x036), F3F(~2, ~0x36, ~0x036), "v,B,H", 0, HWCAP_VIS, 0, v9a },
|
|
|
|
|
{ "fmul8ulx16", F3F(2, 0x36, 0x037), F3F(~2, ~0x36, ~0x037), "v,B,H", 0, HWCAP_VIS, 0, v9a },
|
|
|
|
|
{ "fmuld8sux16", F3F(2, 0x36, 0x038), F3F(~2, ~0x36, ~0x038), "e,f,H", 0, HWCAP_VIS, 0, v9a },
|
|
|
|
|
{ "fmuld8ulx16", F3F(2, 0x36, 0x039), F3F(~2, ~0x36, ~0x039), "e,f,H", 0, HWCAP_VIS, 0, v9a },
|
|
|
|
|
|
|
|
|
|
{ "alignaddr", F3F(2, 0x36, 0x018), F3F(~2, ~0x36, ~0x018), "1,2,d", 0, HWCAP_VIS, 0, v9a },
|
|
|
|
|
{ "alignaddrl", F3F(2, 0x36, 0x01a), F3F(~2, ~0x36, ~0x01a), "1,2,d", 0, HWCAP_VIS, 0, v9a },
|
2016-05-09 19:09:53 +08:00
|
|
|
|
{ "faligndata", F3F(2, 0x36, 0x048), F3F(~2, ~0x36, ~0x048), "v,B,H", 0, HWCAP_VIS, 0, v9a }, /* faligndatag */
|
opcodes,gas: adjust sparc insns and make GAS aware of it
This patch marks the SPARC instructions in the opcodes table with their
proper opcode architectures, and makes the assembler aware of them.
This allows the assembler to properly realize when a new instruction
needs a higher architecture (after v9b) and to react accordingly
emitting an error message or bumping the architecture.
It also expands architecture mismatch tests to cover architectures
higher than v9b, and fixes a couple of minor bugs in the GAS testsuite.
opcodes/ChangeLog:
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* sparc-opc.c (sparc_opcodes): Adjust instructions opcode
architecture according to the hardware capabilities they require.
(sparc_priv_regs): New table.
(sparc_hpriv_regs): Likewise.
(sparc_asr_regs): Likewise.
(v9anotv9m): Define.
gas/ChangeLog:
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-sparc.c (sparc_arch_table): adjust the GAS
architectures to use the right opcode architecture.
(sparc_md_end): Handle v9{c,d,e,v,m}.
(sparc_ip): Fix some comments.
* testsuite/gas/sparc/ldx_efsr.d: Fix the architecture of this
instruction, which is v9d.
* testsuite/gas/sparc/mwait.s: Remove the `rd %mwait,%g1'
instruction from the test, as %mwait is not readable.
* testsuite/gas/sparc/mwait.d: Likewise.
* testsuite/gas/sparc/mism-1.s: Expand to check v9b and v9e
mismatch architecture errors.
* testsuite/gas/sparc/mism-2.s: New file.
2016-06-17 17:14:18 +08:00
|
|
|
|
{ "faligndata", F3F(2, 0x36, 0x049), F3F(~2, ~0x36, ~0x049), "v,B,5,}", 0, 0, HWCAP2_SPARC5, v9m }, /* faligndatai */
|
2014-10-09 20:16:53 +08:00
|
|
|
|
|
|
|
|
|
{ "fzerod", F3F(2, 0x36, 0x060), F3F(~2, ~0x36, ~0x060), "H", 0, HWCAP_VIS, 0, v9a },
|
|
|
|
|
{ "fzero", F3F(2, 0x36, 0x060), F3F(~2, ~0x36, ~0x060), "H", F_ALIAS, HWCAP_VIS, 0, v9a },
|
|
|
|
|
{ "fzeros", F3F(2, 0x36, 0x061), F3F(~2, ~0x36, ~0x061), "g", 0, HWCAP_VIS, 0, v9a },
|
|
|
|
|
{ "foned", F3F(2, 0x36, 0x07e), F3F(~2, ~0x36, ~0x07e), "H", 0, HWCAP_VIS, 0, v9a },
|
|
|
|
|
{ "fone", F3F(2, 0x36, 0x07e), F3F(~2, ~0x36, ~0x07e), "H", F_ALIAS, HWCAP_VIS, 0, v9a },
|
|
|
|
|
{ "fones", F3F(2, 0x36, 0x07f), F3F(~2, ~0x36, ~0x07f), "g", 0, HWCAP_VIS, 0, v9a },
|
|
|
|
|
{ "fsrc1d", F3F(2, 0x36, 0x074), F3F(~2, ~0x36, ~0x074), "v,H", 0, HWCAP_VIS, 0, v9a },
|
|
|
|
|
{ "fsrc1", F3F(2, 0x36, 0x074), F3F(~2, ~0x36, ~0x074), "v,H", F_ALIAS, HWCAP_VIS, 0, v9a },
|
|
|
|
|
{ "fsrc1s", F3F(2, 0x36, 0x075), F3F(~2, ~0x36, ~0x075), "e,g", 0, HWCAP_VIS, 0, v9a },
|
|
|
|
|
{ "fsrc2d", F3F(2, 0x36, 0x078), F3F(~2, ~0x36, ~0x078), "B,H", 0, HWCAP_VIS, 0, v9a },
|
|
|
|
|
{ "fsrc2", F3F(2, 0x36, 0x078), F3F(~2, ~0x36, ~0x078), "B,H", F_ALIAS, HWCAP_VIS, 0, v9a },
|
|
|
|
|
{ "fsrc2s", F3F(2, 0x36, 0x079), F3F(~2, ~0x36, ~0x079), "f,g", 0, HWCAP_VIS, 0, v9a },
|
|
|
|
|
{ "fnot1d", F3F(2, 0x36, 0x06a), F3F(~2, ~0x36, ~0x06a), "v,H", 0, HWCAP_VIS, 0, v9a },
|
|
|
|
|
{ "fnot1", F3F(2, 0x36, 0x06a), F3F(~2, ~0x36, ~0x06a), "v,H", F_ALIAS, HWCAP_VIS, 0, v9a },
|
|
|
|
|
{ "fnot1s", F3F(2, 0x36, 0x06b), F3F(~2, ~0x36, ~0x06b), "e,g", 0, HWCAP_VIS, 0, v9a },
|
|
|
|
|
{ "fnot2d", F3F(2, 0x36, 0x066), F3F(~2, ~0x36, ~0x066), "B,H", 0, HWCAP_VIS, 0, v9a },
|
|
|
|
|
{ "fnot2", F3F(2, 0x36, 0x066), F3F(~2, ~0x36, ~0x066), "B,H", F_ALIAS, HWCAP_VIS, 0, v9a },
|
|
|
|
|
{ "fnot2s", F3F(2, 0x36, 0x067), F3F(~2, ~0x36, ~0x067), "f,g", 0, HWCAP_VIS, 0, v9a },
|
|
|
|
|
{ "ford", F3F(2, 0x36, 0x07c), F3F(~2, ~0x36, ~0x07c), "v,B,H", 0, HWCAP_VIS, 0, v9a },
|
|
|
|
|
{ "for", F3F(2, 0x36, 0x07c), F3F(~2, ~0x36, ~0x07c), "v,B,H", F_ALIAS, HWCAP_VIS, 0, v9a },
|
|
|
|
|
{ "fors", F3F(2, 0x36, 0x07d), F3F(~2, ~0x36, ~0x07d), "e,f,g", 0, HWCAP_VIS, 0, v9a },
|
|
|
|
|
{ "fnord", F3F(2, 0x36, 0x062), F3F(~2, ~0x36, ~0x062), "v,B,H", 0, HWCAP_VIS, 0, v9a },
|
|
|
|
|
{ "fnor", F3F(2, 0x36, 0x062), F3F(~2, ~0x36, ~0x062), "v,B,H", F_ALIAS, HWCAP_VIS, 0, v9a },
|
|
|
|
|
{ "fnors", F3F(2, 0x36, 0x063), F3F(~2, ~0x36, ~0x063), "e,f,g", 0, HWCAP_VIS, 0, v9a },
|
|
|
|
|
{ "fandd", F3F(2, 0x36, 0x070), F3F(~2, ~0x36, ~0x070), "v,B,H", 0, HWCAP_VIS, 0, v9a },
|
|
|
|
|
{ "fand", F3F(2, 0x36, 0x070), F3F(~2, ~0x36, ~0x070), "v,B,H", F_ALIAS, HWCAP_VIS, 0, v9a },
|
|
|
|
|
{ "fands", F3F(2, 0x36, 0x071), F3F(~2, ~0x36, ~0x071), "e,f,g", 0, HWCAP_VIS, 0, v9a },
|
|
|
|
|
{ "fnandd", F3F(2, 0x36, 0x06e), F3F(~2, ~0x36, ~0x06e), "v,B,H", 0, HWCAP_VIS, 0, v9a },
|
|
|
|
|
{ "fnand", F3F(2, 0x36, 0x06e), F3F(~2, ~0x36, ~0x06e), "v,B,H", F_ALIAS, HWCAP_VIS, 0, v9a },
|
|
|
|
|
{ "fnands", F3F(2, 0x36, 0x06f), F3F(~2, ~0x36, ~0x06f), "e,f,g", 0, HWCAP_VIS, 0, v9a },
|
|
|
|
|
{ "fxord", F3F(2, 0x36, 0x06c), F3F(~2, ~0x36, ~0x06c), "v,B,H", 0, HWCAP_VIS, 0, v9a },
|
|
|
|
|
{ "fxor", F3F(2, 0x36, 0x06c), F3F(~2, ~0x36, ~0x06c), "v,B,H", F_ALIAS, HWCAP_VIS, 0, v9a },
|
|
|
|
|
{ "fxors", F3F(2, 0x36, 0x06d), F3F(~2, ~0x36, ~0x06d), "e,f,g", 0, HWCAP_VIS, 0, v9a },
|
|
|
|
|
{ "fxnord", F3F(2, 0x36, 0x072), F3F(~2, ~0x36, ~0x072), "v,B,H", 0, HWCAP_VIS, 0, v9a },
|
|
|
|
|
{ "fxnor", F3F(2, 0x36, 0x072), F3F(~2, ~0x36, ~0x072), "v,B,H", F_ALIAS, HWCAP_VIS, 0, v9a },
|
|
|
|
|
{ "fxnors", F3F(2, 0x36, 0x073), F3F(~2, ~0x36, ~0x073), "e,f,g", 0, HWCAP_VIS, 0, v9a },
|
|
|
|
|
{ "fornot1d", F3F(2, 0x36, 0x07a), F3F(~2, ~0x36, ~0x07a), "v,B,H", 0, HWCAP_VIS, 0, v9a },
|
|
|
|
|
{ "fornot1", F3F(2, 0x36, 0x07a), F3F(~2, ~0x36, ~0x07a), "v,B,H", F_ALIAS, HWCAP_VIS, 0, v9a },
|
|
|
|
|
{ "fornot1s", F3F(2, 0x36, 0x07b), F3F(~2, ~0x36, ~0x07b), "e,f,g", 0, HWCAP_VIS, 0, v9a },
|
|
|
|
|
{ "fornot2d", F3F(2, 0x36, 0x076), F3F(~2, ~0x36, ~0x076), "v,B,H", 0, HWCAP_VIS, 0, v9a },
|
|
|
|
|
{ "fornot2", F3F(2, 0x36, 0x076), F3F(~2, ~0x36, ~0x076), "v,B,H", F_ALIAS, HWCAP_VIS, 0, v9a },
|
|
|
|
|
{ "fornot2s", F3F(2, 0x36, 0x077), F3F(~2, ~0x36, ~0x077), "e,f,g", 0, HWCAP_VIS, 0, v9a },
|
|
|
|
|
{ "fandnot1d", F3F(2, 0x36, 0x068), F3F(~2, ~0x36, ~0x068), "v,B,H", 0, HWCAP_VIS, 0, v9a },
|
|
|
|
|
{ "fandnot1", F3F(2, 0x36, 0x068), F3F(~2, ~0x36, ~0x068), "v,B,H", F_ALIAS, HWCAP_VIS, 0, v9a },
|
|
|
|
|
{ "fandnot1s", F3F(2, 0x36, 0x069), F3F(~2, ~0x36, ~0x069), "e,f,g", 0, HWCAP_VIS, 0, v9a },
|
|
|
|
|
{ "fandnot2d", F3F(2, 0x36, 0x064), F3F(~2, ~0x36, ~0x064), "v,B,H", 0, HWCAP_VIS, 0, v9a },
|
|
|
|
|
{ "fandnot2", F3F(2, 0x36, 0x064), F3F(~2, ~0x36, ~0x064), "v,B,H", F_ALIAS, HWCAP_VIS, 0, v9a },
|
|
|
|
|
{ "fandnot2s", F3F(2, 0x36, 0x065), F3F(~2, ~0x36, ~0x065), "e,f,g", 0, HWCAP_VIS, 0, v9a },
|
|
|
|
|
|
|
|
|
|
{ "fpcmpgt16", F3F(2, 0x36, 0x028), F3F(~2, ~0x36, ~0x028), "v,B,d", 0, HWCAP_VIS, 0, v9a },
|
|
|
|
|
{ "fcmpgt16", F3F(2, 0x36, 0x028), F3F(~2, ~0x36, ~0x028), "v,B,d", F_ALIAS, HWCAP_VIS, 0, v9a },
|
|
|
|
|
{ "fpcmpgt32", F3F(2, 0x36, 0x02c), F3F(~2, ~0x36, ~0x02c), "v,B,d", 0, HWCAP_VIS, 0, v9a },
|
|
|
|
|
{ "fcmpgt32", F3F(2, 0x36, 0x02c), F3F(~2, ~0x36, ~0x02c), "v,B,d", F_ALIAS, HWCAP_VIS, 0, v9a },
|
|
|
|
|
{ "fpcmple16", F3F(2, 0x36, 0x020), F3F(~2, ~0x36, ~0x020), "v,B,d", 0, HWCAP_VIS, 0, v9a },
|
|
|
|
|
{ "fcmple16", F3F(2, 0x36, 0x020), F3F(~2, ~0x36, ~0x020), "v,B,d", F_ALIAS, HWCAP_VIS, 0, v9a },
|
|
|
|
|
{ "fpcmple32", F3F(2, 0x36, 0x024), F3F(~2, ~0x36, ~0x024), "v,B,d", 0, HWCAP_VIS, 0, v9a },
|
|
|
|
|
{ "fcmple32", F3F(2, 0x36, 0x024), F3F(~2, ~0x36, ~0x024), "v,B,d", F_ALIAS, HWCAP_VIS, 0, v9a },
|
|
|
|
|
{ "fpcmpne16", F3F(2, 0x36, 0x022), F3F(~2, ~0x36, ~0x022), "v,B,d", 0, HWCAP_VIS, 0, v9a },
|
|
|
|
|
{ "fpcmpune16", F3F(2, 0x36, 0x022), F3F(~2, ~0x36, ~0x022), "v,B,d", F_ALIAS, HWCAP_VIS, 0, v9a },
|
|
|
|
|
{ "fcmpne16", F3F(2, 0x36, 0x022), F3F(~2, ~0x36, ~0x022), "v,B,d", F_ALIAS, HWCAP_VIS, 0, v9a },
|
|
|
|
|
{ "fpcmpne32", F3F(2, 0x36, 0x026), F3F(~2, ~0x36, ~0x026), "v,B,d", 0, HWCAP_VIS, 0, v9a },
|
|
|
|
|
{ "fpcmpune32", F3F(2, 0x36, 0x026), F3F(~2, ~0x36, ~0x026), "v,B,d", F_ALIAS, HWCAP_VIS, 0, v9a },
|
|
|
|
|
{ "fcmpne32", F3F(2, 0x36, 0x026), F3F(~2, ~0x36, ~0x026), "v,B,d", F_ALIAS, HWCAP_VIS, 0, v9a },
|
|
|
|
|
{ "fpcmpeq16", F3F(2, 0x36, 0x02a), F3F(~2, ~0x36, ~0x02a), "v,B,d", 0, HWCAP_VIS, 0, v9a },
|
|
|
|
|
{ "fpcmpueq16", F3F(2, 0x36, 0x02a), F3F(~2, ~0x36, ~0x02a), "v,B,d", F_ALIAS, HWCAP_VIS, 0, v9a },
|
|
|
|
|
{ "fcmpeq16", F3F(2, 0x36, 0x02a), F3F(~2, ~0x36, ~0x02a), "v,B,d", F_ALIAS, HWCAP_VIS, 0, v9a },
|
|
|
|
|
{ "fpcmpeq32", F3F(2, 0x36, 0x02e), F3F(~2, ~0x36, ~0x02e), "v,B,d", 0, HWCAP_VIS, 0, v9a },
|
|
|
|
|
{ "fpcmpueq32", F3F(2, 0x36, 0x02e), F3F(~2, ~0x36, ~0x02e), "v,B,d", F_ALIAS, HWCAP_VIS, 0, v9a },
|
|
|
|
|
{ "fcmpeq32", F3F(2, 0x36, 0x02e), F3F(~2, ~0x36, ~0x02e), "v,B,d", F_ALIAS, HWCAP_VIS, 0, v9a },
|
|
|
|
|
|
|
|
|
|
{ "edge8cc", F3F(2, 0x36, 0x000), F3F(~2, ~0x36, ~0x000), "1,2,d", 0, HWCAP_VIS, 0, v9a },
|
|
|
|
|
{ "edge8lcc", F3F(2, 0x36, 0x002), F3F(~2, ~0x36, ~0x002), "1,2,d", 0, HWCAP_VIS, 0, v9a },
|
|
|
|
|
{ "edge16cc", F3F(2, 0x36, 0x004), F3F(~2, ~0x36, ~0x004), "1,2,d", 0, HWCAP_VIS, 0, v9a },
|
|
|
|
|
{ "edge16lcc", F3F(2, 0x36, 0x006), F3F(~2, ~0x36, ~0x006), "1,2,d", 0, HWCAP_VIS, 0, v9a },
|
|
|
|
|
{ "edge32cc", F3F(2, 0x36, 0x008), F3F(~2, ~0x36, ~0x008), "1,2,d", 0, HWCAP_VIS, 0, v9a },
|
|
|
|
|
{ "edge32lcc", F3F(2, 0x36, 0x00a), F3F(~2, ~0x36, ~0x00a), "1,2,d", 0, HWCAP_VIS, 0, v9a },
|
|
|
|
|
|
|
|
|
|
{ "edge8", F3F(2, 0x36, 0x000), F3F(~2, ~0x36, ~0x000), "1,2,d", F_ALIAS, HWCAP_VIS, 0, v9a },
|
|
|
|
|
{ "edge8l", F3F(2, 0x36, 0x002), F3F(~2, ~0x36, ~0x002), "1,2,d", F_ALIAS, HWCAP_VIS, 0, v9a },
|
|
|
|
|
{ "edge16", F3F(2, 0x36, 0x004), F3F(~2, ~0x36, ~0x004), "1,2,d", F_ALIAS, HWCAP_VIS, 0, v9a },
|
|
|
|
|
{ "edge16l", F3F(2, 0x36, 0x006), F3F(~2, ~0x36, ~0x006), "1,2,d", F_ALIAS, HWCAP_VIS, 0, v9a },
|
|
|
|
|
{ "edge32", F3F(2, 0x36, 0x008), F3F(~2, ~0x36, ~0x008), "1,2,d", F_ALIAS, HWCAP_VIS, 0, v9a },
|
|
|
|
|
{ "edge32l", F3F(2, 0x36, 0x00a), F3F(~2, ~0x36, ~0x00a), "1,2,d", F_ALIAS, HWCAP_VIS, 0, v9a },
|
|
|
|
|
|
|
|
|
|
{ "pdist", F3F(2, 0x36, 0x03e), F3F(~2, ~0x36, ~0x03e), "v,B,H", 0, HWCAP_VIS, 0, v9a },
|
|
|
|
|
|
|
|
|
|
{ "array8", F3F(2, 0x36, 0x010), F3F(~2, ~0x36, ~0x010), "1,2,d", 0, HWCAP_VIS, 0, v9a },
|
|
|
|
|
{ "array16", F3F(2, 0x36, 0x012), F3F(~2, ~0x36, ~0x012), "1,2,d", 0, HWCAP_VIS, 0, v9a },
|
|
|
|
|
{ "array32", F3F(2, 0x36, 0x014), F3F(~2, ~0x36, ~0x014), "1,2,d", 0, HWCAP_VIS, 0, v9a },
|
1999-05-03 15:29:11 +08:00
|
|
|
|
|
2000-10-20 18:38:47 +08:00
|
|
|
|
/* Cheetah instructions */
|
2014-10-18 03:56:41 +08:00
|
|
|
|
{ "edge8n", F3F(2, 0x36, 0x001), F3F(~2, ~0x36, ~0x001), "1,2,d", 0, HWCAP_VIS2, 0, v9b },
|
|
|
|
|
{ "edge8ln", F3F(2, 0x36, 0x003), F3F(~2, ~0x36, ~0x003), "1,2,d", 0, HWCAP_VIS2, 0, v9b },
|
|
|
|
|
{ "edge16n", F3F(2, 0x36, 0x005), F3F(~2, ~0x36, ~0x005), "1,2,d", 0, HWCAP_VIS2, 0, v9b },
|
|
|
|
|
{ "edge16ln", F3F(2, 0x36, 0x007), F3F(~2, ~0x36, ~0x007), "1,2,d", 0, HWCAP_VIS2, 0, v9b },
|
|
|
|
|
{ "edge32n", F3F(2, 0x36, 0x009), F3F(~2, ~0x36, ~0x009), "1,2,d", 0, HWCAP_VIS2, 0, v9b },
|
|
|
|
|
{ "edge32ln", F3F(2, 0x36, 0x00b), F3F(~2, ~0x36, ~0x00b), "1,2,d", 0, HWCAP_VIS2, 0, v9b },
|
2014-10-09 20:16:53 +08:00
|
|
|
|
|
2014-10-18 03:56:41 +08:00
|
|
|
|
{ "bmask", F3F(2, 0x36, 0x019), F3F(~2, ~0x36, ~0x019), "1,2,d", 0, HWCAP_VIS2, 0, v9b },
|
|
|
|
|
{ "bshuffle", F3F(2, 0x36, 0x04c), F3F(~2, ~0x36, ~0x04c), "v,B,H", 0, HWCAP_VIS2, 0, v9b },
|
2014-10-09 20:16:53 +08:00
|
|
|
|
|
2014-10-18 03:56:41 +08:00
|
|
|
|
{ "siam", F3F(2, 0x36, 0x081), F3F(~2, ~0x36, ~0x081)|RD_G0|RS1_G0|RS2(~7), "3", 0, HWCAP_VIS2, 0, v9b },
|
2014-10-09 20:16:53 +08:00
|
|
|
|
|
opcodes,gas: adjust sparc insns and make GAS aware of it
This patch marks the SPARC instructions in the opcodes table with their
proper opcode architectures, and makes the assembler aware of them.
This allows the assembler to properly realize when a new instruction
needs a higher architecture (after v9b) and to react accordingly
emitting an error message or bumping the architecture.
It also expands architecture mismatch tests to cover architectures
higher than v9b, and fixes a couple of minor bugs in the GAS testsuite.
opcodes/ChangeLog:
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* sparc-opc.c (sparc_opcodes): Adjust instructions opcode
architecture according to the hardware capabilities they require.
(sparc_priv_regs): New table.
(sparc_hpriv_regs): Likewise.
(sparc_asr_regs): Likewise.
(v9anotv9m): Define.
gas/ChangeLog:
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-sparc.c (sparc_arch_table): adjust the GAS
architectures to use the right opcode architecture.
(sparc_md_end): Handle v9{c,d,e,v,m}.
(sparc_ip): Fix some comments.
* testsuite/gas/sparc/ldx_efsr.d: Fix the architecture of this
instruction, which is v9d.
* testsuite/gas/sparc/mwait.s: Remove the `rd %mwait,%g1'
instruction from the test, as %mwait is not readable.
* testsuite/gas/sparc/mwait.d: Likewise.
* testsuite/gas/sparc/mism-1.s: Expand to check v9b and v9e
mismatch architecture errors.
* testsuite/gas/sparc/mism-2.s: New file.
2016-06-17 17:14:18 +08:00
|
|
|
|
{ "fnadds", F3F(2, 0x34, 0x051), F3F(~2, ~0x34, ~0x051), "e,f,g", F_FLOAT, HWCAP_HPC, 0, v9d },
|
|
|
|
|
{ "fnaddd", F3F(2, 0x34, 0x052), F3F(~2, ~0x34, ~0x052), "v,B,H", F_FLOAT, HWCAP_HPC, 0, v9d },
|
|
|
|
|
{ "fnmuls", F3F(2, 0x34, 0x059), F3F(~2, ~0x34, ~0x059), "e,f,g", F_FLOAT, HWCAP_HPC, 0, v9d },
|
|
|
|
|
{ "fnmuld", F3F(2, 0x34, 0x05a), F3F(~2, ~0x34, ~0x05a), "v,B,H", F_FLOAT, HWCAP_HPC, 0, v9d },
|
|
|
|
|
{ "fhadds", F3F(2, 0x34, 0x061), F3F(~2, ~0x34, ~0x061), "e,f,g", F_FLOAT, HWCAP_HPC, 0, v9d },
|
|
|
|
|
{ "fhaddd", F3F(2, 0x34, 0x062), F3F(~2, ~0x34, ~0x062), "v,B,H", F_FLOAT, HWCAP_HPC, 0, v9d },
|
|
|
|
|
{ "fhsubs", F3F(2, 0x34, 0x065), F3F(~2, ~0x34, ~0x065), "e,f,g", F_FLOAT, HWCAP_HPC, 0, v9d },
|
|
|
|
|
{ "fhsubd", F3F(2, 0x34, 0x066), F3F(~2, ~0x34, ~0x066), "v,B,H", F_FLOAT, HWCAP_HPC, 0, v9d },
|
|
|
|
|
{ "fnhadds", F3F(2, 0x34, 0x071), F3F(~2, ~0x34, ~0x071), "e,f,g", F_FLOAT, HWCAP_HPC, 0, v9d },
|
|
|
|
|
{ "fnhaddd", F3F(2, 0x34, 0x072), F3F(~2, ~0x34, ~0x072), "v,B,H", F_FLOAT, HWCAP_HPC, 0, v9d },
|
|
|
|
|
{ "fnsmuld", F3F(2, 0x34, 0x079), F3F(~2, ~0x34, ~0x079), "e,f,H", F_FLOAT, HWCAP_HPC, 0, v9d },
|
|
|
|
|
{ "fpmaddx", F3(2, 0x37, 0)|OPF_LOW4(0), F3(~2, ~0x37, 0)|OPF_LOW4(~0), "v,B,5,H", F_FLOAT, HWCAP_IMA, 0, v9v },
|
|
|
|
|
{ "fmadds", F3(2, 0x37, 0)|OPF_LOW4(1), F3(~2, ~0x37, 0)|OPF_LOW4(~1), "e,f,4,g", F_FLOAT, HWCAP_FMAF, 0, v9d },
|
|
|
|
|
{ "fmaddd", F3(2, 0x37, 0)|OPF_LOW4(2), F3(~2, ~0x37, 0)|OPF_LOW4(~2), "v,B,5,H", F_FLOAT, HWCAP_FMAF, 0, v9d },
|
|
|
|
|
{ "fpmaddxhi", F3(2, 0x37, 0)|OPF_LOW4(4), F3(~2, ~0x37, 0)|OPF_LOW4(~4), "v,B,5,H", F_FLOAT, HWCAP_IMA, 0, v9v },
|
|
|
|
|
{ "fmsubs", F3(2, 0x37, 0)|OPF_LOW4(5), F3(~2, ~0x37, 0)|OPF_LOW4(~5), "e,f,4,g", F_FLOAT, HWCAP_FMAF, 0, v9d },
|
|
|
|
|
{ "fmsubd", F3(2, 0x37, 0)|OPF_LOW4(6), F3(~2, ~0x37, 0)|OPF_LOW4(~6), "v,B,5,H", F_FLOAT, HWCAP_FMAF, 0, v9d },
|
|
|
|
|
{ "fnmsubs", F3(2, 0x37, 0)|OPF_LOW4(9), F3(~2, ~0x37, 0)|OPF_LOW4(~9), "e,f,4,g", F_FLOAT, HWCAP_FMAF, 0, v9d },
|
|
|
|
|
{ "fnmsubd", F3(2, 0x37, 0)|OPF_LOW4(10), F3(~2, ~0x37, 0)|OPF_LOW4(~10), "v,B,5,H", F_FLOAT, HWCAP_FMAF, 0, v9d },
|
|
|
|
|
{ "fnmadds", F3(2, 0x37, 0)|OPF_LOW4(13), F3(~2, ~0x37, 0)|OPF_LOW4(~13), "e,f,4,g", F_FLOAT, HWCAP_FMAF, 0, v9d },
|
|
|
|
|
{ "fnmaddd", F3(2, 0x37, 0)|OPF_LOW4(14), F3(~2, ~0x37, 0)|OPF_LOW4(~14), "v,B,5,H", F_FLOAT, HWCAP_FMAF, 0, v9d },
|
|
|
|
|
{ "fumadds", F3(2, 0x3f, 0)|OPF_LOW4(1), F3(~2, ~0x3f, 0)|OPF_LOW4(~1), "e,f,4,g", F_FLOAT, HWCAP_FJFMAU, 0, v9v },
|
|
|
|
|
{ "fumaddd", F3(2, 0x3f, 0)|OPF_LOW4(2), F3(~2, ~0x3f, 0)|OPF_LOW4(~2), "v,B,5,H", F_FLOAT, HWCAP_FJFMAU, 0, v9v },
|
|
|
|
|
{ "fumsubs", F3(2, 0x3f, 0)|OPF_LOW4(5), F3(~2, ~0x3f, 0)|OPF_LOW4(~5), "e,f,4,g", F_FLOAT, HWCAP_FJFMAU, 0, v9v },
|
|
|
|
|
{ "fumsubd", F3(2, 0x3f, 0)|OPF_LOW4(6), F3(~2, ~0x3f, 0)|OPF_LOW4(~6), "v,B,5,H", F_FLOAT, HWCAP_FJFMAU, 0, v9v },
|
|
|
|
|
{ "fnumsubs", F3(2, 0x3f, 0)|OPF_LOW4(9), F3(~2, ~0x3f, 0)|OPF_LOW4(~9), "e,f,4,g", F_FLOAT, HWCAP_FJFMAU, 0, v9v },
|
|
|
|
|
{ "fnumsubd", F3(2, 0x3f, 0)|OPF_LOW4(10), F3(~2, ~0x3f, 0)|OPF_LOW4(~10), "v,B,5,H", F_FLOAT, HWCAP_FJFMAU, 0, v9v },
|
|
|
|
|
{ "fnumadds", F3(2, 0x3f, 0)|OPF_LOW4(13), F3(~2, ~0x3f, 0)|OPF_LOW4(~13), "e,f,4,g", F_FLOAT, HWCAP_FJFMAU, 0, v9v },
|
|
|
|
|
{ "fnumaddd", F3(2, 0x3f, 0)|OPF_LOW4(14), F3(~2, ~0x3f, 0)|OPF_LOW4(~14), "v,B,5,H", F_FLOAT, HWCAP_FJFMAU, 0, v9v },
|
|
|
|
|
{ "addxc", F3F(2, 0x36, 0x011), F3F(~2, ~0x36, ~0x011), "1,2,d", 0, HWCAP_VIS3, 0, v9d },
|
|
|
|
|
{ "addxccc", F3F(2, 0x36, 0x013), F3F(~2, ~0x36, ~0x013), "1,2,d", 0, HWCAP_VIS3, 0, v9d },
|
|
|
|
|
{ "umulxhi", F3F(2, 0x36, 0x016), F3F(~2, ~0x36, ~0x016), "1,2,d", 0, HWCAP_VIS3, 0, v9d },
|
|
|
|
|
{ "lzcnt", F3F(2, 0x36, 0x017), F3F(~2, ~0x36, ~0x017), "2,d", 0, HWCAP_VIS3, 0, v9d },
|
|
|
|
|
{ "lzd", F3F(2, 0x36, 0x017), F3F(~2, ~0x36, ~0x017), "2,d", F_ALIAS, HWCAP_VIS3, 0, v9d },
|
|
|
|
|
{ "cmask8", F3F(2, 0x36, 0x01b), F3F(~2, ~0x36, ~0x01b), "2", 0, HWCAP_VIS3, 0, v9d },
|
|
|
|
|
{ "cmask16", F3F(2, 0x36, 0x01d), F3F(~2, ~0x36, ~0x01d), "2", 0, HWCAP_VIS3, 0, v9d },
|
|
|
|
|
{ "cmask32", F3F(2, 0x36, 0x01f), F3F(~2, ~0x36, ~0x01f), "2", 0, HWCAP_VIS3, 0, v9d },
|
|
|
|
|
{ "fsll16", F3F(2, 0x36, 0x021), F3F(~2, ~0x36, ~0x021), "v,B,H", 0, HWCAP_VIS3, 0, v9d },
|
|
|
|
|
{ "fsrl16", F3F(2, 0x36, 0x023), F3F(~2, ~0x36, ~0x023), "v,B,H", 0, HWCAP_VIS3, 0, v9d },
|
|
|
|
|
{ "fsll32", F3F(2, 0x36, 0x025), F3F(~2, ~0x36, ~0x025), "v,B,H", 0, HWCAP_VIS3, 0, v9d },
|
|
|
|
|
{ "fsrl32", F3F(2, 0x36, 0x027), F3F(~2, ~0x36, ~0x027), "v,B,H", 0, HWCAP_VIS3, 0, v9d },
|
|
|
|
|
{ "fslas16", F3F(2, 0x36, 0x029), F3F(~2, ~0x36, ~0x029), "v,B,H", 0, HWCAP_VIS3, 0, v9d },
|
|
|
|
|
{ "fsra16", F3F(2, 0x36, 0x02b), F3F(~2, ~0x36, ~0x02b), "v,B,H", 0, HWCAP_VIS3, 0, v9d },
|
|
|
|
|
{ "fslas32", F3F(2, 0x36, 0x02d), F3F(~2, ~0x36, ~0x02d), "v,B,H", 0, HWCAP_VIS3, 0, v9d },
|
|
|
|
|
{ "fsra32", F3F(2, 0x36, 0x02f), F3F(~2, ~0x36, ~0x02f), "v,B,H", 0, HWCAP_VIS3, 0, v9d },
|
|
|
|
|
{ "pdistn", F3F(2, 0x36, 0x03f), F3F(~2, ~0x36, ~0x03f), "v,B,d", 0, HWCAP_VIS3, 0, v9d },
|
|
|
|
|
{ "fmean16", F3F(2, 0x36, 0x040), F3F(~2, ~0x36, ~0x040), "v,B,H", 0, HWCAP_VIS3, 0, v9d },
|
|
|
|
|
{ "fpadd64", F3F(2, 0x36, 0x042), F3F(~2, ~0x36, ~0x042), "v,B,H", 0, HWCAP_VIS3, HWCAP2_VIS3B, v9d },
|
|
|
|
|
{ "fchksm16", F3F(2, 0x36, 0x044), F3F(~2, ~0x36, ~0x044), "v,B,H", 0, HWCAP_VIS3, 0, v9d },
|
|
|
|
|
{ "fpsub64", F3F(2, 0x36, 0x046), F3F(~2, ~0x36, ~0x046), "v,B,H", 0, HWCAP_VIS3, HWCAP2_VIS3B, v9d },
|
|
|
|
|
{ "fpadds16", F3F(2, 0x36, 0x058), F3F(~2, ~0x36, ~0x058), "v,B,H", 0, HWCAP_VIS3, 0, v9d },
|
|
|
|
|
{ "fpadds16s", F3F(2, 0x36, 0x059), F3F(~2, ~0x36, ~0x059), "e,f,g", 0, HWCAP_VIS3, 0, v9d },
|
|
|
|
|
{ "fpadds32", F3F(2, 0x36, 0x05a), F3F(~2, ~0x36, ~0x05a), "v,B,H", 0, HWCAP_VIS3, 0, v9d },
|
|
|
|
|
{ "fpadds32s", F3F(2, 0x36, 0x05b), F3F(~2, ~0x36, ~0x05b), "e,f,g", 0, HWCAP_VIS3, 0, v9d },
|
|
|
|
|
{ "fpsubs16", F3F(2, 0x36, 0x05c), F3F(~2, ~0x36, ~0x05c), "v,B,H", 0, HWCAP_VIS3, 0, v9d },
|
|
|
|
|
{ "fpsubs16s", F3F(2, 0x36, 0x05d), F3F(~2, ~0x36, ~0x05d), "e,f,g", 0, HWCAP_VIS3, 0, v9d },
|
|
|
|
|
{ "fpsubs32", F3F(2, 0x36, 0x05e), F3F(~2, ~0x36, ~0x05e), "v,B,H", 0, HWCAP_VIS3, 0, v9d },
|
|
|
|
|
{ "fpsubs32s", F3F(2, 0x36, 0x05f), F3F(~2, ~0x36, ~0x05f), "e,f,g", 0, HWCAP_VIS3, 0, v9d },
|
|
|
|
|
{ "movdtox", F3F(2, 0x36, 0x110), F3F(~2, ~0x36, ~0x110), "B,d", F_FLOAT, HWCAP_VIS3, 0, v9d },
|
|
|
|
|
{ "movstouw", F3F(2, 0x36, 0x111), F3F(~2, ~0x36, ~0x111), "f,d", F_FLOAT, HWCAP_VIS3, 0, v9d },
|
|
|
|
|
{ "movstosw", F3F(2, 0x36, 0x113), F3F(~2, ~0x36, ~0x113), "f,d", F_FLOAT, HWCAP_VIS3, 0, v9d },
|
|
|
|
|
{ "movxtod", F3F(2, 0x36, 0x118), F3F(~2, ~0x36, ~0x118), "2,H", F_FLOAT, HWCAP_VIS3, 0, v9d },
|
|
|
|
|
{ "movwtos", F3F(2, 0x36, 0x119), F3F(~2, ~0x36, ~0x119), "2,g", F_FLOAT, HWCAP_VIS3, 0, v9d },
|
|
|
|
|
{ "xmulx", F3F(2, 0x36, 0x115), F3F(~2, ~0x36, ~0x115), "1,2,d", 0, HWCAP_VIS3, 0, v9d },
|
|
|
|
|
{ "xmulxhi", F3F(2, 0x36, 0x116), F3F(~2, ~0x36, ~0x116), "1,2,d", 0, HWCAP_VIS3, 0, v9d },
|
|
|
|
|
{ "fpcmpule8", F3F(2, 0x36, 0x120), F3F(~2, ~0x36, ~0x120), "v,B,d", 0, HWCAP_VIS3, HWCAP2_VIS3B, v9d },
|
|
|
|
|
{ "fucmple8", F3F(2, 0x36, 0x120), F3F(~2, ~0x36, ~0x120), "v,B,d", F_ALIAS, HWCAP_VIS3, 0, v9d },
|
|
|
|
|
{ "fpcmpune8", F3F(2, 0x36, 0x122), F3F(~2, ~0x36, ~0x122), "v,B,d", 0, HWCAP_VIS3, HWCAP2_VIS3B, v9d },
|
|
|
|
|
{ "fpcmpne8", F3F(2, 0x36, 0x122), F3F(~2, ~0x36, ~0x122), "v,B,d", F_PREF_ALIAS, HWCAP_VIS3, 0, v9d },
|
|
|
|
|
{ "fucmpne8", F3F(2, 0x36, 0x122), F3F(~2, ~0x36, ~0x122), "v,B,d", F_ALIAS, HWCAP_VIS3, 0, v9d },
|
|
|
|
|
{ "fpcmpugt8", F3F(2, 0x36, 0x128), F3F(~2, ~0x36, ~0x128), "v,B,d", 0, HWCAP_VIS3, HWCAP2_VIS3B, v9d },
|
|
|
|
|
{ "fucmpgt8", F3F(2, 0x36, 0x128), F3F(~2, ~0x36, ~0x128), "v,B,d", F_ALIAS, HWCAP_VIS3, 0, v9d },
|
|
|
|
|
{ "fpcmpueq8", F3F(2, 0x36, 0x12a), F3F(~2, ~0x36, ~0x12a), "v,B,d", 0, HWCAP_VIS3, HWCAP2_VIS3B, v9d },
|
|
|
|
|
{ "fpcmpeq8", F3F(2, 0x36, 0x12a), F3F(~2, ~0x36, ~0x12a), "v,B,d", F_PREF_ALIAS, HWCAP_VIS3, 0, v9d },
|
|
|
|
|
{ "fucmpeq8", F3F(2, 0x36, 0x12a), F3F(~2, ~0x36, ~0x12a), "v,B,d", F_ALIAS, HWCAP_VIS3, 0, v9d },
|
|
|
|
|
{"aes_kexpand0",F3F(2, 0x36, 0x130), F3F(~2, ~0x36, ~0x130), "v,B,H", F_FLOAT, HWCAP_AES, 0, v9e },
|
|
|
|
|
{"aes_kexpand2",F3F(2, 0x36, 0x131), F3F(~2, ~0x36, ~0x131), "v,B,H", F_FLOAT, HWCAP_AES, 0, v9e },
|
|
|
|
|
{ "des_ip", F3F(2, 0x36, 0x134), F3F(~2, ~0x36, ~0x134), "v,H", F_FLOAT, HWCAP_DES, 0, v9e },
|
|
|
|
|
{ "des_iip", F3F(2, 0x36, 0x135), F3F(~2, ~0x36, ~0x135), "v,H", F_FLOAT, HWCAP_DES, 0, v9e },
|
|
|
|
|
{ "des_kexpand",F3F(2, 0x36, 0x136), F3F(~2, ~0x36, ~0x136), "v,X,H", F_FLOAT, HWCAP_DES, 0, v9e },
|
|
|
|
|
{"kasumi_fi_fi",F3F(2, 0x36, 0x138), F3F(~2, ~0x36, ~0x138), "v,B,H", F_FLOAT, HWCAP_KASUMI, 0, v9e },
|
2016-08-26 22:31:31 +08:00
|
|
|
|
{ "camellia_fl",F3F(2, 0x36, 0x13c), F3F(~2, ~0x36, ~0x13c), "v,B,H", F_FLOAT, HWCAP_CAMELLIA, 0, v9e },
|
opcodes,gas: adjust sparc insns and make GAS aware of it
This patch marks the SPARC instructions in the opcodes table with their
proper opcode architectures, and makes the assembler aware of them.
This allows the assembler to properly realize when a new instruction
needs a higher architecture (after v9b) and to react accordingly
emitting an error message or bumping the architecture.
It also expands architecture mismatch tests to cover architectures
higher than v9b, and fixes a couple of minor bugs in the GAS testsuite.
opcodes/ChangeLog:
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* sparc-opc.c (sparc_opcodes): Adjust instructions opcode
architecture according to the hardware capabilities they require.
(sparc_priv_regs): New table.
(sparc_hpriv_regs): Likewise.
(sparc_asr_regs): Likewise.
(v9anotv9m): Define.
gas/ChangeLog:
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-sparc.c (sparc_arch_table): adjust the GAS
architectures to use the right opcode architecture.
(sparc_md_end): Handle v9{c,d,e,v,m}.
(sparc_ip): Fix some comments.
* testsuite/gas/sparc/ldx_efsr.d: Fix the architecture of this
instruction, which is v9d.
* testsuite/gas/sparc/mwait.s: Remove the `rd %mwait,%g1'
instruction from the test, as %mwait is not readable.
* testsuite/gas/sparc/mwait.d: Likewise.
* testsuite/gas/sparc/mism-1.s: Expand to check v9b and v9e
mismatch architecture errors.
* testsuite/gas/sparc/mism-2.s: New file.
2016-06-17 17:14:18 +08:00
|
|
|
|
{"camellia_fli",F3F(2, 0x36, 0x13d), F3F(~2, ~0x36, ~0x13d), "v,B,H", F_FLOAT, HWCAP_CAMELLIA, 0, v9e },
|
|
|
|
|
{ "md5", F3F(2, 0x36, 0x140), F3F(~2, ~0x36, ~0x140), "", F_FLOAT, HWCAP_MD5, 0, v9e },
|
|
|
|
|
{ "sha1", F3F(2, 0x36, 0x141), F3F(~2, ~0x36, ~0x141), "", F_FLOAT, HWCAP_SHA1, 0, v9e },
|
|
|
|
|
{ "sha256", F3F(2, 0x36, 0x142), F3F(~2, ~0x36, ~0x142), "", F_FLOAT, HWCAP_SHA256, 0, v9e },
|
|
|
|
|
{ "sha512", F3F(2, 0x36, 0x143), F3F(~2, ~0x36, ~0x143), "", F_FLOAT, HWCAP_SHA512, 0, v9e },
|
|
|
|
|
{ "crc32c", F3F(2, 0x36, 0x147), F3F(~2, ~0x36, ~0x147), "v,B,H", F_FLOAT, HWCAP_CRC32C, 0, v9e },
|
|
|
|
|
{ "xmpmul", F3F(2, 0x36, 0x148)|RD(1), F3F(~2, ~0x36, ~0x148)|RD(~1), "X", F_FLOAT, 0, HWCAP2_XMPMUL, v9m },
|
|
|
|
|
{ "mpmul", F3F(2, 0x36, 0x148), F3F(~2, ~0x36, ~0x148), "X", F_FLOAT, HWCAP_MPMUL, 0, v9e },
|
|
|
|
|
{ "xmontmul", F3F(2, 0x36, 0x149)|RD(1), F3F(~2, ~0x36, ~0x149)|RD(~1), "X", F_FLOAT, 0, HWCAP2_XMONT, v9m },
|
|
|
|
|
{ "montmul", F3F(2, 0x36, 0x149), F3F(~2, ~0x36, ~0x149), "X", F_FLOAT, HWCAP_MONT, 0, v9e },
|
|
|
|
|
{ "xmontsqr", F3F(2, 0x36, 0x14a)|RD(1), F3F(~2, ~0x36, ~0x14a)|RD(~1), "X", F_FLOAT, 0, HWCAP2_XMONT, v9m },
|
|
|
|
|
{ "montsqr", F3F(2, 0x36, 0x14a), F3F(~2, ~0x36, ~0x14a), "X", F_FLOAT, HWCAP_MONT, 0, v9e },
|
|
|
|
|
{"aes_eround01", F3F4(2, 0x19, 0), F3F4(~2, ~0x19, ~0), "v,B,5,H", F_FLOAT, HWCAP_AES, 0, v9e },
|
|
|
|
|
{"aes_eround23", F3F4(2, 0x19, 1), F3F4(~2, ~0x19, ~1), "v,B,5,H", F_FLOAT, HWCAP_AES, 0, v9e },
|
|
|
|
|
{"aes_dround01", F3F4(2, 0x19, 2), F3F4(~2, ~0x19, ~2), "v,B,5,H", F_FLOAT, HWCAP_AES, 0, v9e },
|
|
|
|
|
{"aes_dround23", F3F4(2, 0x19, 3), F3F4(~2, ~0x19, ~3), "v,B,5,H", F_FLOAT, HWCAP_AES, 0, v9e },
|
|
|
|
|
{"aes_eround01_l",F3F4(2, 0x19, 4), F3F4(~2, ~0x19, ~4), "v,B,5,H", F_FLOAT, HWCAP_AES, 0, v9e },
|
|
|
|
|
{"aes_eround23_l",F3F4(2, 0x19, 5), F3F4(~2, ~0x19, ~5), "v,B,5,H", F_FLOAT, HWCAP_AES, 0, v9e },
|
|
|
|
|
{"aes_dround01_l",F3F4(2, 0x19, 6), F3F4(~2, ~0x19, ~6), "v,B,5,H", F_FLOAT, HWCAP_AES, 0, v9e },
|
|
|
|
|
{"aes_dround23_l",F3F4(2, 0x19, 7), F3F4(~2, ~0x19, ~7), "v,B,5,H", F_FLOAT, HWCAP_AES, 0, v9e },
|
|
|
|
|
{"aes_kexpand1", F3F4(2, 0x19, 8), F3F4(~2, ~0x19, ~8), "v,B,),H", F_FLOAT, HWCAP_AES, 0, v9e },
|
|
|
|
|
{"des_round", F3F4(2, 0x19, 9), F3F4(~2, ~0x19, ~9), "v,B,5,H", F_FLOAT, HWCAP_DES, 0, v9e },
|
|
|
|
|
{"kasumi_fl_xor", F3F4(2, 0x19, 10), F3F4(~2, ~0x19, ~10), "v,B,5,H", F_FLOAT, HWCAP_KASUMI, 0, v9e },
|
|
|
|
|
{"kasumi_fi_xor", F3F4(2, 0x19, 11), F3F4(~2, ~0x19, ~11), "v,B,5,H", F_FLOAT, HWCAP_KASUMI, 0, v9e },
|
|
|
|
|
{"camellia_f", F3F4(2, 0x19, 12), F3F4(~2, ~0x19, ~12), "v,B,5,H", F_FLOAT, HWCAP_CAMELLIA, 0, v9e },
|
|
|
|
|
{ "flcmps", CMPFCC(0)|F3F(2, 0x36, 0x151), CMPFCC(~0)|F3F(~2, ~0x36, ~0x151), "6,e,f", F_FLOAT, HWCAP_HPC, 0, v9d },
|
|
|
|
|
{ "flcmps", CMPFCC(1)|F3F(2, 0x36, 0x151), CMPFCC(~1)|F3F(~2, ~0x36, ~0x151), "7,e,f", F_FLOAT, HWCAP_HPC, 0, v9d },
|
|
|
|
|
{ "flcmps", CMPFCC(2)|F3F(2, 0x36, 0x151), CMPFCC(~2)|F3F(~2, ~0x36, ~0x151), "8,e,f", F_FLOAT, HWCAP_HPC, 0, v9d },
|
|
|
|
|
{ "flcmps", CMPFCC(3)|F3F(2, 0x36, 0x151), CMPFCC(~3)|F3F(~2, ~0x36, ~0x151), "9,e,f", F_FLOAT, HWCAP_HPC, 0, v9d },
|
|
|
|
|
{ "flcmpd", CMPFCC(0)|F3F(2, 0x36, 0x152), CMPFCC(~0)|F3F(~2, ~0x36, ~0x152), "6,v,B", F_FLOAT, HWCAP_HPC, 0, v9d },
|
|
|
|
|
{ "flcmpd", CMPFCC(1)|F3F(2, 0x36, 0x152), CMPFCC(~1)|F3F(~2, ~0x36, ~0x152), "7,v,B", F_FLOAT, HWCAP_HPC, 0, v9d },
|
|
|
|
|
{ "flcmpd", CMPFCC(2)|F3F(2, 0x36, 0x152), CMPFCC(~2)|F3F(~2, ~0x36, ~0x152), "8,v,B", F_FLOAT, HWCAP_HPC, 0, v9d },
|
|
|
|
|
{ "flcmpd", CMPFCC(3)|F3F(2, 0x36, 0x152), CMPFCC(~3)|F3F(~2, ~0x36, ~0x152), "9,v,B", F_FLOAT, HWCAP_HPC, 0, v9d },
|
|
|
|
|
|
|
|
|
|
{ "mwait", F3(2, 0x30, 0)|RD(28), F3(~2, ~0x30, ~0)|RD(~28)|RS1_G0|ASI(~0), "2", 0, 0, HWCAP2_MWAIT, v9m }, /* mwait r */
|
|
|
|
|
{ "mwait", F3(2, 0x30, 1)|RD(28), F3(~2, ~0x30, ~1)|RD(~28)|RS1_G0, "i", 0, 0, HWCAP2_MWAIT, v9m }, /* mwait imm */
|
2014-10-09 20:16:53 +08:00
|
|
|
|
|
2016-05-09 19:09:53 +08:00
|
|
|
|
/* Other SPARC5 and VIS4.0 instructions. */
|
2014-10-09 20:16:53 +08:00
|
|
|
|
|
opcodes,gas: adjust sparc insns and make GAS aware of it
This patch marks the SPARC instructions in the opcodes table with their
proper opcode architectures, and makes the assembler aware of them.
This allows the assembler to properly realize when a new instruction
needs a higher architecture (after v9b) and to react accordingly
emitting an error message or bumping the architecture.
It also expands architecture mismatch tests to cover architectures
higher than v9b, and fixes a couple of minor bugs in the GAS testsuite.
opcodes/ChangeLog:
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* sparc-opc.c (sparc_opcodes): Adjust instructions opcode
architecture according to the hardware capabilities they require.
(sparc_priv_regs): New table.
(sparc_hpriv_regs): Likewise.
(sparc_asr_regs): Likewise.
(v9anotv9m): Define.
gas/ChangeLog:
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-sparc.c (sparc_arch_table): adjust the GAS
architectures to use the right opcode architecture.
(sparc_md_end): Handle v9{c,d,e,v,m}.
(sparc_ip): Fix some comments.
* testsuite/gas/sparc/ldx_efsr.d: Fix the architecture of this
instruction, which is v9d.
* testsuite/gas/sparc/mwait.s: Remove the `rd %mwait,%g1'
instruction from the test, as %mwait is not readable.
* testsuite/gas/sparc/mwait.d: Likewise.
* testsuite/gas/sparc/mism-1.s: Expand to check v9b and v9e
mismatch architecture errors.
* testsuite/gas/sparc/mism-2.s: New file.
2016-06-17 17:14:18 +08:00
|
|
|
|
{ "subxc", F3(2, 0x36, 0)|OPF(0x41), F3(~2, ~0x36, ~0)|OPF(~0x41), "1,2,d", 0, 0, HWCAP2_SPARC5, v9m },
|
|
|
|
|
{ "subxccc", F3(2, 0x36, 0)|OPF(0x43), F3(~2, ~0x36, ~0)|OPF(~0x43), "1,2,d", 0, 0, HWCAP2_SPARC5, v9m },
|
|
|
|
|
|
|
|
|
|
{ "fpadd8", F3F(2, 0x36, 0x124), F3F(~2, ~0x36, ~0x124), "v,B,H", 0, 0, HWCAP2_SPARC5, v9m },
|
|
|
|
|
{ "fpadds8", F3F(2, 0x36, 0x126), F3F(~2, ~0x36, ~0x126), "v,B,H", 0, 0, HWCAP2_SPARC5, v9m },
|
|
|
|
|
{ "fpaddus8", F3F(2, 0x36, 0x127), F3F(~2, ~0x36, ~0x127), "v,B,H", 0, 0, HWCAP2_SPARC5, v9m },
|
|
|
|
|
{ "fpaddus16", F3F(2, 0x36, 0x123), F3F(~2, ~0x36, ~0x123), "v,B,H", 0, 0, HWCAP2_SPARC5, v9m },
|
|
|
|
|
{ "fpcmple8", F3F(2, 0x36, 0x034), F3F(~2, ~0x36, ~0x034), "v,B,d", 0, 0, HWCAP2_SPARC5, v9m },
|
|
|
|
|
{ "fpcmpgt8", F3F(2, 0x36, 0x03c), F3F(~2, ~0x36, ~0x03c), "v,B,d", 0, 0, HWCAP2_SPARC5, v9m },
|
|
|
|
|
{ "fpcmpule16", F3F(2, 0x36, 0x12e), F3F(~2, ~0x36, ~0x12e), "v,B,d", 0, 0, HWCAP2_SPARC5, v9m },
|
|
|
|
|
{ "fpcmpugt16", F3F(2, 0x36, 0x12b), F3F(~2, ~0x36, ~0x12b), "v,B,d", 0, 0, HWCAP2_SPARC5, v9m },
|
|
|
|
|
{ "fpcmpule32", F3F(2, 0x36, 0x12f), F3F(~2, ~0x36, ~0x12f), "v,B,d", 0, 0, HWCAP2_SPARC5, v9m },
|
|
|
|
|
{ "fpcmpugt32", F3F(2, 0x36, 0x12c), F3F(~2, ~0x36, ~0x12c), "v,B,d", 0, 0, HWCAP2_SPARC5, v9m },
|
|
|
|
|
{ "fpmax8", F3F(2, 0x36, 0x11d), F3F(~2, ~0x36, ~0x11d), "v,B,H", 0, 0, HWCAP2_SPARC5, v9m },
|
|
|
|
|
{ "fpmax16", F3F(2, 0x36, 0x11e), F3F(~2, ~0x36, ~0x11e), "v,B,H", 0, 0, HWCAP2_SPARC5, v9m },
|
|
|
|
|
{ "fpmax32", F3F(2, 0x36, 0x11f), F3F(~2, ~0x36, ~0x11f), "v,B,H", 0, 0, HWCAP2_SPARC5, v9m },
|
|
|
|
|
{ "fpmaxu8", F3F(2, 0x36, 0x15d), F3F(~2, ~0x36, ~0x15d), "v,B,H", 0, 0, HWCAP2_SPARC5, v9m },
|
|
|
|
|
{ "fpmaxu16", F3F(2, 0x36, 0x15e), F3F(~2, ~0x36, ~0x15e), "v,B,H", 0, 0, HWCAP2_SPARC5, v9m },
|
|
|
|
|
{ "fpmaxu32", F3F(2, 0x36, 0x15f), F3F(~2, ~0x36, ~0x15f), "v,B,H", 0, 0, HWCAP2_SPARC5, v9m },
|
|
|
|
|
{ "fpmin8", F3F(2, 0x36, 0x11a), F3F(~2, ~0x36, ~0x11a), "v,B,H", 0, 0, HWCAP2_SPARC5, v9m },
|
|
|
|
|
{ "fpmin16", F3F(2, 0x36, 0x11b), F3F(~2, ~0x36, ~0x11b), "v,B,H", 0, 0, HWCAP2_SPARC5, v9m },
|
|
|
|
|
{ "fpmin32", F3F(2, 0x36, 0x11c), F3F(~2, ~0x36, ~0x11c), "v,B,H", 0, 0, HWCAP2_SPARC5, v9m },
|
|
|
|
|
{ "fpminu8", F3F(2, 0x36, 0x15a), F3F(~2, ~0x36, ~0x15a), "v,B,H", 0, 0, HWCAP2_SPARC5, v9m },
|
|
|
|
|
{ "fpminu16", F3F(2, 0x36, 0x15b), F3F(~2, ~0x36, ~0x15b), "v,B,H", 0, 0, HWCAP2_SPARC5, v9m },
|
|
|
|
|
{ "fpminu32", F3F(2, 0x36, 0x15c), F3F(~2, ~0x36, ~0x15c), "v,B,H", 0, 0, HWCAP2_SPARC5, v9m },
|
|
|
|
|
{ "fpsub8", F3F(2, 0x36, 0x154), F3F(~2, ~0x36, ~0x154), "v,B,H", 0, 0, HWCAP2_SPARC5, v9m },
|
|
|
|
|
{ "fpsubs8", F3F(2, 0x36, 0x156), F3F(~2, ~0x36, ~0x156), "v,B,H", 0, 0, HWCAP2_SPARC5, v9m },
|
|
|
|
|
{ "fpsubus8", F3F(2, 0x36, 0x157), F3F(~2, ~0x36, ~0x157), "v,B,H", 0, 0, HWCAP2_SPARC5, v9m },
|
|
|
|
|
{ "fpsubus16", F3F(2, 0x36, 0x153), F3F(~2, ~0x36, ~0x153), "v,B,H", 0, 0, HWCAP2_SPARC5, v9m },
|
2011-08-06 00:52:50 +08:00
|
|
|
|
|
1999-05-03 15:29:11 +08:00
|
|
|
|
/* More v9 specific insns, these need to come last so they do not clash
|
|
|
|
|
with v9a instructions such as "edge8" which looks like impdep1. */
|
|
|
|
|
|
|
|
|
|
#define IMPDEP(name, code) \
|
2014-10-09 20:16:53 +08:00
|
|
|
|
{ name, F3(2, code, 0), F3(~2, ~code, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v9notv9a }, \
|
|
|
|
|
{ name, F3(2, code, 1), F3(~2, ~code, ~1), "1,i,d", 0, 0, 0, v9notv9a }, \
|
|
|
|
|
{ name, F3(2, code, 0), F3(~2, ~code, ~0), "x,1,2,d", 0, 0, 0, v9notv9a }, \
|
|
|
|
|
{ name, F3(2, code, 0), F3(~2, ~code, ~0), "x,e,f,g", 0, 0, 0, v9notv9a }
|
1999-05-03 15:29:11 +08:00
|
|
|
|
|
|
|
|
|
IMPDEP ("impdep1", 0x36),
|
|
|
|
|
IMPDEP ("impdep2", 0x37),
|
|
|
|
|
|
|
|
|
|
#undef IMPDEP
|
|
|
|
|
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
const int sparc_num_opcodes = ((sizeof sparc_opcodes)/(sizeof sparc_opcodes[0]));
|
|
|
|
|
|
|
|
|
|
/* Utilities for argument parsing. */
|
|
|
|
|
|
|
|
|
|
typedef struct
|
|
|
|
|
{
|
|
|
|
|
int value;
|
|
|
|
|
const char *name;
|
|
|
|
|
} arg;
|
|
|
|
|
|
|
|
|
|
/* Look up NAME in TABLE. */
|
|
|
|
|
|
|
|
|
|
static int
|
2005-07-01 19:16:33 +08:00
|
|
|
|
lookup_name (const arg *table, const char *name)
|
1999-05-03 15:29:11 +08:00
|
|
|
|
{
|
|
|
|
|
const arg *p;
|
|
|
|
|
|
|
|
|
|
for (p = table; p->name; ++p)
|
|
|
|
|
if (strcmp (name, p->name) == 0)
|
|
|
|
|
return p->value;
|
|
|
|
|
|
|
|
|
|
return -1;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Look up VALUE in TABLE. */
|
|
|
|
|
|
|
|
|
|
static const char *
|
2005-07-01 19:16:33 +08:00
|
|
|
|
lookup_value (const arg *table, int value)
|
1999-05-03 15:29:11 +08:00
|
|
|
|
{
|
|
|
|
|
const arg *p;
|
|
|
|
|
|
|
|
|
|
for (p = table; p->name; ++p)
|
|
|
|
|
if (value == p->value)
|
|
|
|
|
return p->name;
|
|
|
|
|
|
2005-07-01 19:16:33 +08:00
|
|
|
|
return NULL;
|
1999-05-03 15:29:11 +08:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Handle ASI's. */
|
|
|
|
|
|
|
|
|
|
static arg asi_table[] =
|
|
|
|
|
{
|
|
|
|
|
/* These are in the v9 architecture manual. */
|
|
|
|
|
/* The shorter versions appear first, they're here because Sun's as has them.
|
|
|
|
|
Sun's as uses #ASI_P_L instead of #ASI_PL (which appears in the
|
|
|
|
|
UltraSPARC architecture manual). */
|
|
|
|
|
{ 0x04, "#ASI_N" },
|
|
|
|
|
{ 0x0c, "#ASI_N_L" },
|
|
|
|
|
{ 0x10, "#ASI_AIUP" },
|
|
|
|
|
{ 0x11, "#ASI_AIUS" },
|
|
|
|
|
{ 0x18, "#ASI_AIUP_L" },
|
|
|
|
|
{ 0x19, "#ASI_AIUS_L" },
|
|
|
|
|
{ 0x80, "#ASI_P" },
|
|
|
|
|
{ 0x81, "#ASI_S" },
|
|
|
|
|
{ 0x82, "#ASI_PNF" },
|
|
|
|
|
{ 0x83, "#ASI_SNF" },
|
|
|
|
|
{ 0x88, "#ASI_P_L" },
|
|
|
|
|
{ 0x89, "#ASI_S_L" },
|
|
|
|
|
{ 0x8a, "#ASI_PNF_L" },
|
|
|
|
|
{ 0x8b, "#ASI_SNF_L" },
|
|
|
|
|
{ 0x04, "#ASI_NUCLEUS" },
|
|
|
|
|
{ 0x0c, "#ASI_NUCLEUS_LITTLE" },
|
|
|
|
|
{ 0x10, "#ASI_AS_IF_USER_PRIMARY" },
|
|
|
|
|
{ 0x11, "#ASI_AS_IF_USER_SECONDARY" },
|
|
|
|
|
{ 0x18, "#ASI_AS_IF_USER_PRIMARY_LITTLE" },
|
|
|
|
|
{ 0x19, "#ASI_AS_IF_USER_SECONDARY_LITTLE" },
|
|
|
|
|
{ 0x80, "#ASI_PRIMARY" },
|
|
|
|
|
{ 0x81, "#ASI_SECONDARY" },
|
|
|
|
|
{ 0x82, "#ASI_PRIMARY_NOFAULT" },
|
|
|
|
|
{ 0x83, "#ASI_SECONDARY_NOFAULT" },
|
|
|
|
|
{ 0x88, "#ASI_PRIMARY_LITTLE" },
|
|
|
|
|
{ 0x89, "#ASI_SECONDARY_LITTLE" },
|
|
|
|
|
{ 0x8a, "#ASI_PRIMARY_NOFAULT_LITTLE" },
|
|
|
|
|
{ 0x8b, "#ASI_SECONDARY_NOFAULT_LITTLE" },
|
2008-04-23 15:49:33 +08:00
|
|
|
|
/* These are UltraSPARC and Niagara extensions. */
|
|
|
|
|
{ 0x14, "#ASI_PHYS_USE_EC" },
|
|
|
|
|
{ 0x15, "#ASI_PHYS_BYPASS_EC_E" },
|
|
|
|
|
{ 0x16, "#ASI_BLK_AIUP_4V" },
|
|
|
|
|
{ 0x17, "#ASI_BLK_AIUS_4V" },
|
|
|
|
|
{ 0x1c, "#ASI_PHYS_USE_EC_L" },
|
|
|
|
|
{ 0x1d, "#ASI_PHYS_BYPASS_EC_E_L" },
|
|
|
|
|
{ 0x1e, "#ASI_BLK_AIUP_L_4V" },
|
|
|
|
|
{ 0x1f, "#ASI_BLK_AIUS_L_4V" },
|
|
|
|
|
{ 0x20, "#ASI_SCRATCHPAD" },
|
|
|
|
|
{ 0x21, "#ASI_MMU" },
|
|
|
|
|
{ 0x23, "#ASI_BLK_INIT_QUAD_LDD_AIUS" },
|
|
|
|
|
{ 0x24, "#ASI_NUCLEUS_QUAD_LDD" },
|
|
|
|
|
{ 0x25, "#ASI_QUEUE" },
|
|
|
|
|
{ 0x26, "#ASI_QUAD_LDD_PHYS_4V" },
|
|
|
|
|
{ 0x2c, "#ASI_NUCLEUS_QUAD_LDD_L" },
|
|
|
|
|
{ 0x30, "#ASI_PCACHE_DATA_STATUS" },
|
|
|
|
|
{ 0x31, "#ASI_PCACHE_DATA" },
|
|
|
|
|
{ 0x32, "#ASI_PCACHE_TAG" },
|
|
|
|
|
{ 0x33, "#ASI_PCACHE_SNOOP_TAG" },
|
|
|
|
|
{ 0x34, "#ASI_QUAD_LDD_PHYS" },
|
|
|
|
|
{ 0x38, "#ASI_WCACHE_VALID_BITS" },
|
|
|
|
|
{ 0x39, "#ASI_WCACHE_DATA" },
|
|
|
|
|
{ 0x3a, "#ASI_WCACHE_TAG" },
|
|
|
|
|
{ 0x3b, "#ASI_WCACHE_SNOOP_TAG" },
|
|
|
|
|
{ 0x3c, "#ASI_QUAD_LDD_PHYS_L" },
|
|
|
|
|
{ 0x40, "#ASI_SRAM_FAST_INIT" },
|
|
|
|
|
{ 0x41, "#ASI_CORE_AVAILABLE" },
|
|
|
|
|
{ 0x41, "#ASI_CORE_ENABLE_STAT" },
|
|
|
|
|
{ 0x41, "#ASI_CORE_ENABLE" },
|
|
|
|
|
{ 0x41, "#ASI_XIR_STEERING" },
|
|
|
|
|
{ 0x41, "#ASI_CORE_RUNNING_RW" },
|
|
|
|
|
{ 0x41, "#ASI_CORE_RUNNING_W1S" },
|
|
|
|
|
{ 0x41, "#ASI_CORE_RUNNING_W1C" },
|
|
|
|
|
{ 0x41, "#ASI_CORE_RUNNING_STAT" },
|
|
|
|
|
{ 0x41, "#ASI_CMT_ERROR_STEERING" },
|
|
|
|
|
{ 0x41, "#ASI_DCACHE_INVALIDATE" },
|
|
|
|
|
{ 0x41, "#ASI_DCACHE_UTAG" },
|
|
|
|
|
{ 0x41, "#ASI_DCACHE_SNOOP_TAG" },
|
|
|
|
|
{ 0x42, "#ASI_DCACHE_INVALIDATE" },
|
|
|
|
|
{ 0x43, "#ASI_DCACHE_UTAG" },
|
|
|
|
|
{ 0x44, "#ASI_DCACHE_SNOOP_TAG" },
|
|
|
|
|
{ 0x45, "#ASI_LSU_CONTROL_REG" },
|
|
|
|
|
{ 0x45, "#ASI_DCU_CONTROL_REG" },
|
|
|
|
|
{ 0x46, "#ASI_DCACHE_DATA" },
|
|
|
|
|
{ 0x47, "#ASI_DCACHE_TAG" },
|
|
|
|
|
{ 0x48, "#ASI_INTR_DISPATCH_STAT" },
|
|
|
|
|
{ 0x49, "#ASI_INTR_RECEIVE" },
|
|
|
|
|
{ 0x4a, "#ASI_UPA_CONFIG" },
|
|
|
|
|
{ 0x4a, "#ASI_JBUS_CONFIG" },
|
|
|
|
|
{ 0x4a, "#ASI_SAFARI_CONFIG" },
|
|
|
|
|
{ 0x4a, "#ASI_SAFARI_ADDRESS" },
|
|
|
|
|
{ 0x4b, "#ASI_ESTATE_ERROR_EN" },
|
|
|
|
|
{ 0x4c, "#ASI_AFSR" },
|
|
|
|
|
{ 0x4d, "#ASI_AFAR" },
|
|
|
|
|
{ 0x4e, "#ASI_EC_TAG_DATA" },
|
|
|
|
|
{ 0x50, "#ASI_IMMU" },
|
|
|
|
|
{ 0x51, "#ASI_IMMU_TSB_8KB_PTR" },
|
|
|
|
|
{ 0x52, "#ASI_IMMU_TSB_16KB_PTR" },
|
|
|
|
|
{ 0x54, "#ASI_ITLB_DATA_IN" },
|
|
|
|
|
{ 0x55, "#ASI_ITLB_DATA_ACCESS" },
|
|
|
|
|
{ 0x56, "#ASI_ITLB_TAG_READ" },
|
|
|
|
|
{ 0x57, "#ASI_IMMU_DEMAP" },
|
|
|
|
|
{ 0x58, "#ASI_DMMU" },
|
|
|
|
|
{ 0x59, "#ASI_DMMU_TSB_8KB_PTR" },
|
|
|
|
|
{ 0x5a, "#ASI_DMMU_TSB_64KB_PTR" },
|
|
|
|
|
{ 0x5b, "#ASI_DMMU_TSB_DIRECT_PTR" },
|
|
|
|
|
{ 0x5c, "#ASI_DTLB_DATA_IN" },
|
|
|
|
|
{ 0x5d, "#ASI_DTLB_DATA_ACCESS" },
|
|
|
|
|
{ 0x5e, "#ASI_DTLB_TAG_READ" },
|
|
|
|
|
{ 0x5f, "#ASI_DMMU_DEMAP" },
|
|
|
|
|
{ 0x60, "#ASI_IIU_INST_TRAP" },
|
|
|
|
|
{ 0x63, "#ASI_INTR_ID" },
|
|
|
|
|
{ 0x63, "#ASI_CORE_ID" },
|
|
|
|
|
{ 0x63, "#ASI_CESR_ID" },
|
|
|
|
|
{ 0x66, "#ASI_IC_INSTR" },
|
|
|
|
|
{ 0x67, "#ASI_IC_TAG" },
|
|
|
|
|
{ 0x68, "#ASI_IC_STAG" },
|
|
|
|
|
{ 0x6e, "#ASI_IC_PRE_DECODE" },
|
|
|
|
|
{ 0x6f, "#ASI_IC_NEXT_FIELD" },
|
|
|
|
|
{ 0x6f, "#ASI_BRPRED_ARRAY" },
|
|
|
|
|
{ 0x70, "#ASI_BLK_AIUP" },
|
|
|
|
|
{ 0x71, "#ASI_BLK_AIUS" },
|
|
|
|
|
{ 0x72, "#ASI_MCU_CTRL_REG" },
|
|
|
|
|
{ 0x74, "#ASI_EC_DATA" },
|
|
|
|
|
{ 0x75, "#ASI_EC_CTRL" },
|
|
|
|
|
{ 0x76, "#ASI_EC_W" },
|
|
|
|
|
{ 0x77, "#ASI_UDB_ERROR_W" },
|
|
|
|
|
{ 0x77, "#ASI_UDB_CONTROL_W" },
|
|
|
|
|
{ 0x77, "#ASI_INTR_W" },
|
|
|
|
|
{ 0x77, "#ASI_INTR_DATAN_W" },
|
|
|
|
|
{ 0x77, "#ASI_INTR_DISPATCH_W" },
|
|
|
|
|
{ 0x78, "#ASI_BLK_AIUPL" },
|
|
|
|
|
{ 0x79, "#ASI_BLK_AIUSL" },
|
|
|
|
|
{ 0x7e, "#ASI_EC_R" },
|
|
|
|
|
{ 0x7f, "#ASI_UDBH_ERROR_R" },
|
|
|
|
|
{ 0x7f, "#ASI_UDBL_ERROR_R" },
|
|
|
|
|
{ 0x7f, "#ASI_UDBH_CONTROL_R" },
|
|
|
|
|
{ 0x7f, "#ASI_UDBL_CONTROL_R" },
|
|
|
|
|
{ 0x7f, "#ASI_INTR_R" },
|
|
|
|
|
{ 0x7f, "#ASI_INTR_DATAN_R" },
|
|
|
|
|
{ 0xc0, "#ASI_PST8_P" },
|
|
|
|
|
{ 0xc1, "#ASI_PST8_S" },
|
|
|
|
|
{ 0xc2, "#ASI_PST16_P" },
|
|
|
|
|
{ 0xc3, "#ASI_PST16_S" },
|
|
|
|
|
{ 0xc4, "#ASI_PST32_P" },
|
|
|
|
|
{ 0xc5, "#ASI_PST32_S" },
|
|
|
|
|
{ 0xc8, "#ASI_PST8_PL" },
|
|
|
|
|
{ 0xc9, "#ASI_PST8_SL" },
|
|
|
|
|
{ 0xca, "#ASI_PST16_PL" },
|
|
|
|
|
{ 0xcb, "#ASI_PST16_SL" },
|
|
|
|
|
{ 0xcc, "#ASI_PST32_PL" },
|
|
|
|
|
{ 0xcd, "#ASI_PST32_SL" },
|
|
|
|
|
{ 0xd0, "#ASI_FL8_P" },
|
|
|
|
|
{ 0xd1, "#ASI_FL8_S" },
|
|
|
|
|
{ 0xd2, "#ASI_FL16_P" },
|
|
|
|
|
{ 0xd3, "#ASI_FL16_S" },
|
|
|
|
|
{ 0xd8, "#ASI_FL8_PL" },
|
|
|
|
|
{ 0xd9, "#ASI_FL8_SL" },
|
|
|
|
|
{ 0xda, "#ASI_FL16_PL" },
|
|
|
|
|
{ 0xdb, "#ASI_FL16_SL" },
|
|
|
|
|
{ 0xe0, "#ASI_BLK_COMMIT_P", },
|
|
|
|
|
{ 0xe1, "#ASI_BLK_COMMIT_S", },
|
|
|
|
|
{ 0xe2, "#ASI_BLK_INIT_QUAD_LDD_P" },
|
|
|
|
|
{ 0xf0, "#ASI_BLK_P", },
|
|
|
|
|
{ 0xf1, "#ASI_BLK_S", },
|
|
|
|
|
{ 0xf8, "#ASI_BLK_PL", },
|
|
|
|
|
{ 0xf9, "#ASI_BLK_SL", },
|
2016-07-13 16:42:28 +08:00
|
|
|
|
{ 0x22, "#ASI_TWINX_AIUP", },
|
|
|
|
|
{ 0x23, "#ASI_TWINX_AIUS", },
|
|
|
|
|
{ 0x26, "#ASI_TWINX_REAL", },
|
|
|
|
|
{ 0x27, "#ASI_TWINX_N", },
|
|
|
|
|
{ 0x2A, "#ASI_TWINX_AIUP_L", },
|
|
|
|
|
{ 0x2B, "#ASI_TWINX_AIUS_L", },
|
|
|
|
|
{ 0x2E, "#ASI_TWINX_REAL_L", },
|
|
|
|
|
{ 0x2F, "#ASI_TWINX_NL", },
|
|
|
|
|
{ 0xE2, "#ASI_TWINX_P", },
|
|
|
|
|
{ 0xE3, "#ASI_TWINX_S", },
|
|
|
|
|
{ 0xEA, "#ASI_TWINX_PL", },
|
|
|
|
|
{ 0xEB, "#ASI_TWINX_SL", },
|
1999-05-03 15:29:11 +08:00
|
|
|
|
{ 0, 0 }
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
/* Return the value for ASI NAME, or -1 if not found. */
|
|
|
|
|
|
|
|
|
|
int
|
2005-07-01 19:16:33 +08:00
|
|
|
|
sparc_encode_asi (const char *name)
|
1999-05-03 15:29:11 +08:00
|
|
|
|
{
|
|
|
|
|
return lookup_name (asi_table, name);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Return the name for ASI value VALUE or NULL if not found. */
|
|
|
|
|
|
|
|
|
|
const char *
|
2005-07-01 19:16:33 +08:00
|
|
|
|
sparc_decode_asi (int value)
|
1999-05-03 15:29:11 +08:00
|
|
|
|
{
|
|
|
|
|
return lookup_value (asi_table, value);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Handle membar masks. */
|
|
|
|
|
|
|
|
|
|
static arg membar_table[] =
|
|
|
|
|
{
|
|
|
|
|
{ 0x40, "#Sync" },
|
|
|
|
|
{ 0x20, "#MemIssue" },
|
|
|
|
|
{ 0x10, "#Lookaside" },
|
|
|
|
|
{ 0x08, "#StoreStore" },
|
|
|
|
|
{ 0x04, "#LoadStore" },
|
|
|
|
|
{ 0x02, "#StoreLoad" },
|
|
|
|
|
{ 0x01, "#LoadLoad" },
|
|
|
|
|
{ 0, 0 }
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
/* Return the value for membar arg NAME, or -1 if not found. */
|
|
|
|
|
|
|
|
|
|
int
|
2005-07-01 19:16:33 +08:00
|
|
|
|
sparc_encode_membar (const char *name)
|
1999-05-03 15:29:11 +08:00
|
|
|
|
{
|
|
|
|
|
return lookup_name (membar_table, name);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Return the name for membar value VALUE or NULL if not found. */
|
|
|
|
|
|
|
|
|
|
const char *
|
2005-07-01 19:16:33 +08:00
|
|
|
|
sparc_decode_membar (int value)
|
1999-05-03 15:29:11 +08:00
|
|
|
|
{
|
|
|
|
|
return lookup_value (membar_table, value);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Handle prefetch args. */
|
|
|
|
|
|
|
|
|
|
static arg prefetch_table[] =
|
|
|
|
|
{
|
|
|
|
|
{ 0, "#n_reads" },
|
|
|
|
|
{ 1, "#one_read" },
|
|
|
|
|
{ 2, "#n_writes" },
|
|
|
|
|
{ 3, "#one_write" },
|
|
|
|
|
{ 4, "#page" },
|
2000-10-20 18:38:47 +08:00
|
|
|
|
{ 16, "#invalidate" },
|
2008-04-23 15:49:33 +08:00
|
|
|
|
{ 17, "#unified", },
|
|
|
|
|
{ 20, "#n_reads_strong", },
|
|
|
|
|
{ 21, "#one_read_strong", },
|
|
|
|
|
{ 22, "#n_writes_strong", },
|
|
|
|
|
{ 23, "#one_write_strong", },
|
1999-05-03 15:29:11 +08:00
|
|
|
|
{ 0, 0 }
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
/* Return the value for prefetch arg NAME, or -1 if not found. */
|
|
|
|
|
|
|
|
|
|
int
|
2005-07-01 19:16:33 +08:00
|
|
|
|
sparc_encode_prefetch (const char *name)
|
1999-05-03 15:29:11 +08:00
|
|
|
|
{
|
|
|
|
|
return lookup_name (prefetch_table, name);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Return the name for prefetch value VALUE or NULL if not found. */
|
|
|
|
|
|
|
|
|
|
const char *
|
2005-07-01 19:16:33 +08:00
|
|
|
|
sparc_decode_prefetch (int value)
|
1999-05-03 15:29:11 +08:00
|
|
|
|
{
|
|
|
|
|
return lookup_value (prefetch_table, value);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Handle sparclet coprocessor registers. */
|
|
|
|
|
|
|
|
|
|
static arg sparclet_cpreg_table[] =
|
|
|
|
|
{
|
|
|
|
|
{ 0, "%ccsr" },
|
|
|
|
|
{ 1, "%ccfr" },
|
|
|
|
|
{ 2, "%cccrcr" },
|
|
|
|
|
{ 3, "%ccpr" },
|
|
|
|
|
{ 4, "%ccsr2" },
|
|
|
|
|
{ 5, "%cccrr" },
|
|
|
|
|
{ 6, "%ccrstr" },
|
|
|
|
|
{ 0, 0 }
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
/* Return the value for sparclet cpreg arg NAME, or -1 if not found. */
|
|
|
|
|
|
|
|
|
|
int
|
2005-07-01 19:16:33 +08:00
|
|
|
|
sparc_encode_sparclet_cpreg (const char *name)
|
1999-05-03 15:29:11 +08:00
|
|
|
|
{
|
|
|
|
|
return lookup_name (sparclet_cpreg_table, name);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Return the name for sparclet cpreg value VALUE or NULL if not found. */
|
|
|
|
|
|
|
|
|
|
const char *
|
2005-07-01 19:16:33 +08:00
|
|
|
|
sparc_decode_sparclet_cpreg (int value)
|
1999-05-03 15:29:11 +08:00
|
|
|
|
{
|
|
|
|
|
return lookup_value (sparclet_cpreg_table, value);
|
|
|
|
|
}
|