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binutils-gdb/sim/d10v/interp.c

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sim: switch config.h usage to defs.h The defs.h header will take care of including the various config.h headers. For now, it's just config.h, but we'll add more when we integrate gnulib in. This header should be used instead of config.h, and should be the first include in every .c file. We won't rely on the old behavior where we expected files to include the port's sim-main.h which then includes the common sim-basics.h which then includes config.h. We have a ton of code that includes things before sim-main.h, and it sometimes needs to be that way. Creating a dedicated header avoids the ordering mess and implicit inclusion that shows up otherwise.
2021-05-02 06:05:23 +08:00
/* This must come before any other includes. */
#include "defs.h"
sim: d10v: clean up misc warnings
2015-03-30 13:38:59 +08:00
#include <inttypes.h>
Initial creation of sourceware repository
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#include <signal.h>
#include "bfd.h"
sim: create header namespace The gdb/callback.h & gdb/remote-sim.h headers have nothing to do with gdb and are really definitions for the libsim API under the sim/ tree. While gdb uses those headers as a client, it's not specific to it. So create a new sim/ namespace and move the headers there.
2021-05-12 12:35:54 +08:00
#include "sim/callback.h"
#include "sim/sim.h"
Initial creation of sourceware repository
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sim: d10v: convert to nrun A lot of cpu state is stored in global variables, as is memory handling. The sim_size support needs unwinding at some point. But at least this is an improvement on the status quo.
2015-03-30 14:05:33 +08:00
#include "sim-main.h"
#include "sim-options.h"
sim: split sim-signal.h include out The sim-basics.h is too big and includes too many things. This leads to some arch's sim-main.h having circular loop issues with defs, and makes it hard to separate out common objects from arch-specific defs. By splitting up sim-basics.h and killing off sim-main.h, it'll make it easier to separate out the two.
2021-06-14 11:16:32 +08:00
#include "sim-signal.h"
sim: d10v: convert to nrun A lot of cpu state is stored in global variables, as is memory handling. The sim_size support needs unwinding at some point. But at least this is an improvement on the status quo.
2015-03-30 14:05:33 +08:00
sim: move register headers into sim/ namespace [PR sim/29869] These headers define the register numbers for each port to implement the sim_fetch_register & sim_store_register interfaces. While gdb uses these, the APIs are part of the sim, not gdb. Move the headers out of the gdb/ include namespace and into sim/ instead.
2022-12-10 19:33:58 +08:00
#include "sim/sim-d10v.h"
* remote-sim.c (gdbsim_wait): Pass target signal numbers to sim_resume. Expect target signal numbers from sim_stop_reason. * wrapper.c (gdb/signals.h): Include it. (SIGTRAP): Don't define. (SIGBUS): Likewise. (sim_stop_reason): Use TARGET_SIGNAL_* instead of SIG*. * sim-reason.c (sim_stop_reason): Use sim_signal_to_target, not sim_signal_to_host. * sim-signal.c (sim_signal_to_host): Fix typo. (sim_signal_to_target): New function. * interp.c (gdb/signals.h): Include it. (sim_stop_reason): Use TARGET_SIGNAL_*. * interf.c: (gdb/signals.h): Include it. (sim_stop_reason): Use TARGET_SIGNAL_*. * sim_calls.c (gdb/signals.h): Include it. (sim_stop_reason): Use TARGET_SIGNAL_*. * psim.c (cntrl_c_simulation): Use TARGET_SIGNAL_*.
2005-11-29 02:33:03 +08:00
#include "gdb/signals.h"
Initial creation of sourceware repository
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include "config.h" instead of BFD's sysdep.h in d10v/interp.c The change of include file introduces some new warnings about functions being used without a prototype. So a few more system includes have been added to compensate for that. sim/d10v/ChangeLog: * interp.c: #include "config.h" instead of "sysdep.h". Add conditional include of string.h or strings.h, as well as conditional include of stdlib.h.
2012-06-20 06:46:57 +08:00
#include <string.h>
#include <stdlib.h>
Fix build failure in d10v sim While building all targets on Ubuntu 20.04/aarch64, I ran into the following build error: In file included from /usr/include/string.h:495, from ../../bfd/bfd.h:48, from ../../../../repos/binutils-gdb/sim/d10v/interp.c:4: In function memset, inlined from sim_create_inferior at ../../../../repos/binutils-gdb/sim/d10v/interp.c:1146:3: /usr/include/aarch64-linux-gnu/bits/string_fortified.h:71:10: error: __builtin_memset offset [33, 616] from the object at State is out of the bounds of referenced subobject regs with type reg_t[16] {aka short unsigned int[16]} at offset 0 [-Werror=array-bounds] 71 | return __builtin___memset_chk (__dest, __ch, __len, __bos0 (__dest)); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ cc1: all warnings being treated as errors make[3]: *** [Makefile:558: interp.o] Error 1 The following patch fixes this. sim/ChangeLog: 2021-05-12 Luis Machado <luis.machado@linaro.org> * d10v/interp.c (sim_create_inferior): Fix memset call.
2021-05-11 03:06:50 +08:00
#include <assert.h>
include "config.h" instead of BFD's sysdep.h in d10v/interp.c The change of include file introduces some new warnings about functions being used without a prototype. So a few more system includes have been added to compensate for that. sim/d10v/ChangeLog: * interp.c: #include "config.h" instead of "sysdep.h". Add conditional include of string.h or strings.h, as well as conditional include of stdlib.h.
2012-06-20 06:46:57 +08:00
sim: d10v: switch to new target-newlib-syscall Use the new target-newlib-syscall module. This is needed to merge all the architectures into a single build, and d10v has a custom syscall table for its newlib/libgloss port. This allows cleaning up the syscall ifdef logic. We know these will always exist now.
2021-11-28 13:20:31 +08:00
#include "target-newlib-syscall.h"
Initial creation of sourceware repository
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enum _leftright { LEFT_FIRST, RIGHT_FIRST };
sim: cr16/d10v: move storage out of header These ports declare their State variable in a header and then include multiple times. This causes linker errors with newer gcc due to the change in -fno-common behavior. Move the storage to a C file so we only have one instance of it in the final program.
2021-01-09 16:10:52 +08:00
struct _state State;
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int d10v_debug;
import gdb-1999-09-13 snapshot
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/* Set this to true to get the previous segment layout. */
int old_segment_mapping;
Initial creation of sourceware repository
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unsigned long ins_type_counters[ (int)INS_MAX ];
sim: d10v: migrate to standard uintXX_t types This old port setup its own uintXX types, but since we require C11 now, we can assume the standard uintXX_t types exist and use them. Also migrate off the sim-specific unsignedXX types.
2021-12-06 01:24:12 +08:00
uint16_t OP[4];
Initial creation of sourceware repository
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remove PARAMS from sim This removes the last uses of PARAMS from sim. 2014-01-06 Tom Tromey <tromey@redhat.com> * README-HACKING: Don't use PARAMS. * arm/wrapper.c: Don't use PARAMS. * bfin/sim-main.h: Don't use PARAMS. * common/callback.c: Don't use PARAMS. * common/cgen-trace.c: Don't use PARAMS. * common/run-sim.h: Don't use PARAMS. * common/run.c: Don't use PARAMS. * common/sim-base.h: Don't use PARAMS. * common/sim-load.c: Don't use PARAMS. * common/sim-options.h: Don't use PARAMS. * common/sim-trace.c: Don't use PARAMS. * common/sim-trace.h: Don't use PARAMS. * common/sim-utils.h: Don't use PARAMS. * cr16/cr16_sim.h: Don't use PARAMS. * cr16/gencode.c: Don't use PARAMS. * cr16/interp.c: Don't use PARAMS. * cr16/simops.c: Don't use PARAMS. * d10v/d10v_sim.h: Don't use PARAMS. * d10v/gencode.c: Don't use PARAMS. * d10v/interp.c: Don't use PARAMS. * d10v/simops.c: Don't use PARAMS. * erc32/erc32.c: Don't use PARAMS. * erc32/exec.c: Don't use PARAMS. * erc32/float.c: Don't use PARAMS. * erc32/func.c: Don't use PARAMS. * erc32/sis.c: Don't use PARAMS. * erc32/sis.h: Don't use PARAMS. * mips/interp.c: Don't use PARAMS. * mips/sim-main.h: Don't use PARAMS. * sh/interp.c: Don't use PARAMS. * v850/sim-main.h: Don't use PARAMS. * v850/v850_sim.h: Don't use PARAMS.
2014-01-05 12:43:21 +08:00
static long hash (long insn, int format);
sim: d10v: migrate to standard uintXX_t types This old port setup its own uintXX types, but since we require C11 now, we can assume the standard uintXX_t types exist and use them. Also migrate off the sim-specific unsignedXX types.
2021-12-06 01:24:12 +08:00
static struct hash_entry *lookup_hash (SIM_DESC, SIM_CPU *, uint32_t ins, int size);
static void get_operands (struct simops *s, uint32_t ins);
static void do_long (SIM_DESC, SIM_CPU *, uint32_t ins);
static void do_2_short (SIM_DESC, SIM_CPU *, uint16_t ins1, uint16_t ins2, enum _leftright leftright);
static void do_parallel (SIM_DESC, SIM_CPU *, uint16_t ins1, uint16_t ins2);
remove PARAMS from sim This removes the last uses of PARAMS from sim. 2014-01-06 Tom Tromey <tromey@redhat.com> * README-HACKING: Don't use PARAMS. * arm/wrapper.c: Don't use PARAMS. * bfin/sim-main.h: Don't use PARAMS. * common/callback.c: Don't use PARAMS. * common/cgen-trace.c: Don't use PARAMS. * common/run-sim.h: Don't use PARAMS. * common/run.c: Don't use PARAMS. * common/sim-base.h: Don't use PARAMS. * common/sim-load.c: Don't use PARAMS. * common/sim-options.h: Don't use PARAMS. * common/sim-trace.c: Don't use PARAMS. * common/sim-trace.h: Don't use PARAMS. * common/sim-utils.h: Don't use PARAMS. * cr16/cr16_sim.h: Don't use PARAMS. * cr16/gencode.c: Don't use PARAMS. * cr16/interp.c: Don't use PARAMS. * cr16/simops.c: Don't use PARAMS. * d10v/d10v_sim.h: Don't use PARAMS. * d10v/gencode.c: Don't use PARAMS. * d10v/interp.c: Don't use PARAMS. * d10v/simops.c: Don't use PARAMS. * erc32/erc32.c: Don't use PARAMS. * erc32/exec.c: Don't use PARAMS. * erc32/float.c: Don't use PARAMS. * erc32/func.c: Don't use PARAMS. * erc32/sis.c: Don't use PARAMS. * erc32/sis.h: Don't use PARAMS. * mips/interp.c: Don't use PARAMS. * mips/sim-main.h: Don't use PARAMS. * sh/interp.c: Don't use PARAMS. * v850/sim-main.h: Don't use PARAMS. * v850/v850_sim.h: Don't use PARAMS.
2014-01-05 12:43:21 +08:00
static char *add_commas (char *buf, int sizeof_buf, unsigned long value);
sim: d10v: migrate to standard uintXX_t types This old port setup its own uintXX types, but since we require C11 now, we can assume the standard uintXX_t types exist and use them. Also migrate off the sim-specific unsignedXX types.
2021-12-06 01:24:12 +08:00
static INLINE uint8_t *map_memory (SIM_DESC, SIM_CPU *, unsigned phys_addr);
Initial creation of sourceware repository
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#define MAX_HASH 63
struct hash_entry
{
struct hash_entry *next;
sim: d10v: migrate to standard uintXX_t types This old port setup its own uintXX types, but since we require C11 now, we can assume the standard uintXX_t types exist and use them. Also migrate off the sim-specific unsignedXX types.
2021-12-06 01:24:12 +08:00
uint32_t opcode;
uint32_t mask;
Initial creation of sourceware repository
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int size;
struct simops *ops;
};
struct hash_entry hash_table[MAX_HASH+1];
INLINE static long
sim: d10v: clean up misc warnings
2015-03-30 13:38:59 +08:00
hash (long insn, int format)
Initial creation of sourceware repository
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{
if (format & LONG_OPCODE)
return ((insn & 0x3F000000) >> 24);
else
return((insn & 0x7E00) >> 9);
}
INLINE static struct hash_entry *
sim: d10v: migrate to standard uintXX_t types This old port setup its own uintXX types, but since we require C11 now, we can assume the standard uintXX_t types exist and use them. Also migrate off the sim-specific unsignedXX types.
2021-12-06 01:24:12 +08:00
lookup_hash (SIM_DESC sd, SIM_CPU *cpu, uint32_t ins, int size)
Initial creation of sourceware repository
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{
struct hash_entry *h;
if (size)
h = &hash_table[(ins & 0x3F000000) >> 24];
else
h = &hash_table[(ins & 0x7E00) >> 9];
while ((ins & h->mask) != h->opcode || h->size != size)
{
if (h->next == NULL)
sim: d10v: convert to common sim engine logic Now that we have access to the sim state everywhere, we can convert to the common engine logic for overall processing. This frees us up from tracking exception state ourselves.
2015-11-15 19:07:06 +08:00
sim_engine_halt (sd, cpu, NULL, PC, sim_stopped, SIM_SIGILL);
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h = h->next;
}
return (h);
}
INLINE static void
sim: d10v: migrate to standard uintXX_t types This old port setup its own uintXX types, but since we require C11 now, we can assume the standard uintXX_t types exist and use them. Also migrate off the sim-specific unsignedXX types.
2021-12-06 01:24:12 +08:00
get_operands (struct simops *s, uint32_t ins)
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{
int i, shift, bits, flags;
sim: d10v: migrate to standard uintXX_t types This old port setup its own uintXX types, but since we require C11 now, we can assume the standard uintXX_t types exist and use them. Also migrate off the sim-specific unsignedXX types.
2021-12-06 01:24:12 +08:00
uint32_t mask;
Initial creation of sourceware repository
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for (i=0; i < s->numops; i++)
{
shift = s->operands[3*i];
bits = s->operands[3*i+1];
flags = s->operands[3*i+2];
mask = 0x7FFFFFFF >> (31 - bits);
OP[i] = (ins >> shift) & mask;
}
/* FIXME: for tracing, update values that need to be updated each
instruction decode cycle */
State.trace.psw = PSW;
}
static void
sim: d10v: migrate to standard uintXX_t types This old port setup its own uintXX types, but since we require C11 now, we can assume the standard uintXX_t types exist and use them. Also migrate off the sim-specific unsignedXX types.
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do_long (SIM_DESC sd, SIM_CPU *cpu, uint32_t ins)
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{
struct hash_entry *h;
#ifdef DEBUG
if ((d10v_debug & DEBUG_INSTRUCTION) != 0)
sim: d10v: drop global callback state Now that we have access to the sim state in all the right places, use existing sim helpers in place of d10v_callback directly.
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sim_io_printf (sd, "do_long 0x%x\n", ins);
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#endif
sim: d10v: push down sd/cpu vars By itself, this commit doesn't really change anything. It lays the groundwork for using the cpu state in follow up commits, both for engine state and for cpu state. Splitting things up this way so it is easier to see how things have changed.
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h = lookup_hash (sd, cpu, ins, 1);
import gdb-1999-11-16 snapshot
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if (h == NULL)
return;
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get_operands (h->ops, ins);
State.ins_type = INS_LONG;
ins_type_counters[ (int)State.ins_type ]++;
sim: d10v: push down sd/cpu vars By itself, this commit doesn't really change anything. It lays the groundwork for using the cpu state in follow up commits, both for engine state and for cpu state. Splitting things up this way so it is easier to see how things have changed.
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(h->ops->func) (sd, cpu);
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}
static void
sim: d10v: migrate to standard uintXX_t types This old port setup its own uintXX types, but since we require C11 now, we can assume the standard uintXX_t types exist and use them. Also migrate off the sim-specific unsignedXX types.
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do_2_short (SIM_DESC sd, SIM_CPU *cpu, uint16_t ins1, uint16_t ins2, enum _leftright leftright)
Initial creation of sourceware repository
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{
struct hash_entry *h;
enum _ins_type first, second;
#ifdef DEBUG
if ((d10v_debug & DEBUG_INSTRUCTION) != 0)
sim: d10v: drop global callback state Now that we have access to the sim state in all the right places, use existing sim helpers in place of d10v_callback directly.
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sim_io_printf (sd, "do_2_short 0x%x (%s) -> 0x%x\n", ins1,
leftright ? "left" : "right", ins2);
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#endif
if (leftright == LEFT_FIRST)
{
first = INS_LEFT;
second = INS_RIGHT;
ins_type_counters[ (int)INS_LEFTRIGHT ]++;
}
else
{
first = INS_RIGHT;
second = INS_LEFT;
ins_type_counters[ (int)INS_RIGHTLEFT ]++;
}
/* Issue the first instruction */
sim: d10v: push down sd/cpu vars By itself, this commit doesn't really change anything. It lays the groundwork for using the cpu state in follow up commits, both for engine state and for cpu state. Splitting things up this way so it is easier to see how things have changed.
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h = lookup_hash (sd, cpu, ins1, 0);
import gdb-1999-11-16 snapshot
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if (h == NULL)
return;
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get_operands (h->ops, ins1);
State.ins_type = first;
ins_type_counters[ (int)State.ins_type ]++;
sim: d10v: push down sd/cpu vars By itself, this commit doesn't really change anything. It lays the groundwork for using the cpu state in follow up commits, both for engine state and for cpu state. Splitting things up this way so it is easier to see how things have changed.
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(h->ops->func) (sd, cpu);
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/* Issue the second instruction (if the PC hasn't changed) */
sim: d10v: convert to common sim engine logic Now that we have access to the sim state everywhere, we can convert to the common engine logic for overall processing. This frees us up from tracking exception state ourselves.
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if (!State.pc_changed)
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{
/* finish any existing instructions */
SLOT_FLUSH ();
sim: d10v: push down sd/cpu vars By itself, this commit doesn't really change anything. It lays the groundwork for using the cpu state in follow up commits, both for engine state and for cpu state. Splitting things up this way so it is easier to see how things have changed.
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h = lookup_hash (sd, cpu, ins2, 0);
import gdb-1999-11-16 snapshot
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if (h == NULL)
return;
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get_operands (h->ops, ins2);
State.ins_type = second;
ins_type_counters[ (int)State.ins_type ]++;
ins_type_counters[ (int)INS_CYCLES ]++;
sim: d10v: push down sd/cpu vars By itself, this commit doesn't really change anything. It lays the groundwork for using the cpu state in follow up commits, both for engine state and for cpu state. Splitting things up this way so it is easier to see how things have changed.
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(h->ops->func) (sd, cpu);
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}
sim: d10v: convert to common sim engine logic Now that we have access to the sim state everywhere, we can convert to the common engine logic for overall processing. This frees us up from tracking exception state ourselves.
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else
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ins_type_counters[ (int)INS_COND_JUMP ]++;
}
static void
sim: d10v: migrate to standard uintXX_t types This old port setup its own uintXX types, but since we require C11 now, we can assume the standard uintXX_t types exist and use them. Also migrate off the sim-specific unsignedXX types.
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do_parallel (SIM_DESC sd, SIM_CPU *cpu, uint16_t ins1, uint16_t ins2)
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{
struct hash_entry *h1, *h2;
#ifdef DEBUG
if ((d10v_debug & DEBUG_INSTRUCTION) != 0)
sim: d10v: drop global callback state Now that we have access to the sim state in all the right places, use existing sim helpers in place of d10v_callback directly.
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sim_io_printf (sd, "do_parallel 0x%x || 0x%x\n", ins1, ins2);
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#endif
ins_type_counters[ (int)INS_PARALLEL ]++;
sim: d10v: push down sd/cpu vars By itself, this commit doesn't really change anything. It lays the groundwork for using the cpu state in follow up commits, both for engine state and for cpu state. Splitting things up this way so it is easier to see how things have changed.
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h1 = lookup_hash (sd, cpu, ins1, 0);
import gdb-1999-11-16 snapshot
1999-11-17 10:31:06 +08:00
if (h1 == NULL)
return;
sim: d10v: push down sd/cpu vars By itself, this commit doesn't really change anything. It lays the groundwork for using the cpu state in follow up commits, both for engine state and for cpu state. Splitting things up this way so it is easier to see how things have changed.
2015-11-15 18:57:42 +08:00
h2 = lookup_hash (sd, cpu, ins2, 0);
import gdb-1999-11-16 snapshot
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if (h2 == NULL)
return;
Initial creation of sourceware repository
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if (h1->ops->exec_type == PARONLY)
{
get_operands (h1->ops, ins1);
State.ins_type = INS_LEFT_COND_TEST;
ins_type_counters[ (int)State.ins_type ]++;
sim: d10v: push down sd/cpu vars By itself, this commit doesn't really change anything. It lays the groundwork for using the cpu state in follow up commits, both for engine state and for cpu state. Splitting things up this way so it is easier to see how things have changed.
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(h1->ops->func) (sd, cpu);
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if (State.exe)
{
ins_type_counters[ (int)INS_COND_TRUE ]++;
get_operands (h2->ops, ins2);
State.ins_type = INS_RIGHT_COND_EXE;
ins_type_counters[ (int)State.ins_type ]++;
sim: d10v: push down sd/cpu vars By itself, this commit doesn't really change anything. It lays the groundwork for using the cpu state in follow up commits, both for engine state and for cpu state. Splitting things up this way so it is easier to see how things have changed.
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(h2->ops->func) (sd, cpu);
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}
else
ins_type_counters[ (int)INS_COND_FALSE ]++;
}
else if (h2->ops->exec_type == PARONLY)
{
get_operands (h2->ops, ins2);
State.ins_type = INS_RIGHT_COND_TEST;
ins_type_counters[ (int)State.ins_type ]++;
sim: d10v: push down sd/cpu vars By itself, this commit doesn't really change anything. It lays the groundwork for using the cpu state in follow up commits, both for engine state and for cpu state. Splitting things up this way so it is easier to see how things have changed.
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(h2->ops->func) (sd, cpu);
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if (State.exe)
{
ins_type_counters[ (int)INS_COND_TRUE ]++;
get_operands (h1->ops, ins1);
State.ins_type = INS_LEFT_COND_EXE;
ins_type_counters[ (int)State.ins_type ]++;
sim: d10v: push down sd/cpu vars By itself, this commit doesn't really change anything. It lays the groundwork for using the cpu state in follow up commits, both for engine state and for cpu state. Splitting things up this way so it is easier to see how things have changed.
2015-11-15 18:57:42 +08:00
(h1->ops->func) (sd, cpu);
Initial creation of sourceware repository
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}
else
ins_type_counters[ (int)INS_COND_FALSE ]++;
}
else
{
get_operands (h1->ops, ins1);
State.ins_type = INS_LEFT_PARALLEL;
ins_type_counters[ (int)State.ins_type ]++;
sim: d10v: push down sd/cpu vars By itself, this commit doesn't really change anything. It lays the groundwork for using the cpu state in follow up commits, both for engine state and for cpu state. Splitting things up this way so it is easier to see how things have changed.
2015-11-15 18:57:42 +08:00
(h1->ops->func) (sd, cpu);
sim: d10v: convert to common sim engine logic Now that we have access to the sim state everywhere, we can convert to the common engine logic for overall processing. This frees us up from tracking exception state ourselves.
2015-11-15 19:07:06 +08:00
get_operands (h2->ops, ins2);
State.ins_type = INS_RIGHT_PARALLEL;
ins_type_counters[ (int)State.ins_type ]++;
(h2->ops->func) (sd, cpu);
Initial creation of sourceware repository
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}
}
static char *
sim: d10v: clean up misc warnings
2015-03-30 13:38:59 +08:00
add_commas (char *buf, int sizeof_buf, unsigned long value)
Initial creation of sourceware repository
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{
int comma = 3;
char *endbuf = buf + sizeof_buf - 1;
*--endbuf = '\0';
do {
if (comma-- == 0)
{
*--endbuf = ',';
comma = 2;
}
*--endbuf = (value % 10) + '0';
} while ((value /= 10) != 0);
return endbuf;
}
sim: d10v: convert to common sim engine logic Now that we have access to the sim state everywhere, we can convert to the common engine logic for overall processing. This frees us up from tracking exception state ourselves.
2015-11-15 19:07:06 +08:00
static void
sim: d10v: clean up misc warnings
2015-03-30 13:38:59 +08:00
sim_size (int power)
Initial creation of sourceware repository
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{
int i;
import gdb-1999-11-16 snapshot
1999-11-17 10:31:06 +08:00
for (i = 0; i < IMEM_SEGMENTS; i++)
Initial creation of sourceware repository
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{
import gdb-1999-11-16 snapshot
1999-11-17 10:31:06 +08:00
if (State.mem.insn[i])
free (State.mem.insn[i]);
Initial creation of sourceware repository
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}
import gdb-1999-11-16 snapshot
1999-11-17 10:31:06 +08:00
for (i = 0; i < DMEM_SEGMENTS; i++)
Initial creation of sourceware repository
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{
import gdb-1999-11-16 snapshot
1999-11-17 10:31:06 +08:00
if (State.mem.data[i])
free (State.mem.data[i]);
Initial creation of sourceware repository
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}
import gdb-1999-11-16 snapshot
1999-11-17 10:31:06 +08:00
for (i = 0; i < UMEM_SEGMENTS; i++)
{
if (State.mem.unif[i])
free (State.mem.unif[i]);
}
/* Always allocate dmem segment 0. This contains the IMAP and DMAP
registers. */
State.mem.data[0] = calloc (1, SEGMENT_SIZE);
}
/* For tracing - leave info on last access around. */
static char *last_segname = "invalid";
static char *last_from = "invalid";
static char *last_to = "invalid";
enum
{
IMAP0_OFFSET = 0xff00,
DMAP0_OFFSET = 0xff08,
DMAP2_SHADDOW = 0xff04,
DMAP2_OFFSET = 0xff0c
};
static void
sim: d10v: push down sd/cpu vars By itself, this commit doesn't really change anything. It lays the groundwork for using the cpu state in follow up commits, both for engine state and for cpu state. Splitting things up this way so it is easier to see how things have changed.
2015-11-15 18:57:42 +08:00
set_dmap_register (SIM_DESC sd, int reg_nr, unsigned long value)
import gdb-1999-11-16 snapshot
1999-11-17 10:31:06 +08:00
{
sim: d10v: migrate to standard uintXX_t types This old port setup its own uintXX types, but since we require C11 now, we can assume the standard uintXX_t types exist and use them. Also migrate off the sim-specific unsignedXX types.
2021-12-06 01:24:12 +08:00
uint8_t *raw = map_memory (sd, NULL, SIM_D10V_MEMORY_DATA
import gdb-1999-11-16 snapshot
1999-11-17 10:31:06 +08:00
+ DMAP0_OFFSET + 2 * reg_nr);
WRITE_16 (raw, value);
Initial creation of sourceware repository
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#ifdef DEBUG
import gdb-1999-11-16 snapshot
1999-11-17 10:31:06 +08:00
if ((d10v_debug & DEBUG_MEMORY))
Initial creation of sourceware repository
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{
sim: d10v: drop global callback state Now that we have access to the sim state in all the right places, use existing sim helpers in place of d10v_callback directly.
2015-11-15 19:41:26 +08:00
sim_io_printf (sd, "mem: dmap%d=0x%04lx\n", reg_nr, value);
import gdb-1999-11-16 snapshot
1999-11-17 10:31:06 +08:00
}
#endif
}
Initial creation of sourceware repository
1999-04-16 09:35:26 +08:00
import gdb-1999-11-16 snapshot
1999-11-17 10:31:06 +08:00
static unsigned long
sim: d10v: push down sd/cpu vars By itself, this commit doesn't really change anything. It lays the groundwork for using the cpu state in follow up commits, both for engine state and for cpu state. Splitting things up this way so it is easier to see how things have changed.
2015-11-15 18:57:42 +08:00
dmap_register (SIM_DESC sd, SIM_CPU *cpu, void *regcache, int reg_nr)
import gdb-1999-11-16 snapshot
1999-11-17 10:31:06 +08:00
{
sim: d10v: migrate to standard uintXX_t types This old port setup its own uintXX types, but since we require C11 now, we can assume the standard uintXX_t types exist and use them. Also migrate off the sim-specific unsignedXX types.
2021-12-06 01:24:12 +08:00
uint8_t *raw = map_memory (sd, cpu, SIM_D10V_MEMORY_DATA
import gdb-1999-11-16 snapshot
1999-11-17 10:31:06 +08:00
+ DMAP0_OFFSET + 2 * reg_nr);
return READ_16 (raw);
}
static void
sim: d10v: push down sd/cpu vars By itself, this commit doesn't really change anything. It lays the groundwork for using the cpu state in follow up commits, both for engine state and for cpu state. Splitting things up this way so it is easier to see how things have changed.
2015-11-15 18:57:42 +08:00
set_imap_register (SIM_DESC sd, int reg_nr, unsigned long value)
import gdb-1999-11-16 snapshot
1999-11-17 10:31:06 +08:00
{
sim: d10v: migrate to standard uintXX_t types This old port setup its own uintXX types, but since we require C11 now, we can assume the standard uintXX_t types exist and use them. Also migrate off the sim-specific unsignedXX types.
2021-12-06 01:24:12 +08:00
uint8_t *raw = map_memory (sd, NULL, SIM_D10V_MEMORY_DATA
import gdb-1999-11-16 snapshot
1999-11-17 10:31:06 +08:00
+ IMAP0_OFFSET + 2 * reg_nr);
WRITE_16 (raw, value);
#ifdef DEBUG
if ((d10v_debug & DEBUG_MEMORY))
{
sim: d10v: drop global callback state Now that we have access to the sim state in all the right places, use existing sim helpers in place of d10v_callback directly.
2015-11-15 19:41:26 +08:00
sim_io_printf (sd, "mem: imap%d=0x%04lx\n", reg_nr, value);
Initial creation of sourceware repository
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}
#endif
}
import gdb-1999-11-16 snapshot
1999-11-17 10:31:06 +08:00
static unsigned long
sim: d10v: push down sd/cpu vars By itself, this commit doesn't really change anything. It lays the groundwork for using the cpu state in follow up commits, both for engine state and for cpu state. Splitting things up this way so it is easier to see how things have changed.
2015-11-15 18:57:42 +08:00
imap_register (SIM_DESC sd, SIM_CPU *cpu, void *regcache, int reg_nr)
import gdb-1999-11-16 snapshot
1999-11-17 10:31:06 +08:00
{
sim: d10v: migrate to standard uintXX_t types This old port setup its own uintXX types, but since we require C11 now, we can assume the standard uintXX_t types exist and use them. Also migrate off the sim-specific unsignedXX types.
2021-12-06 01:24:12 +08:00
uint8_t *raw = map_memory (sd, cpu, SIM_D10V_MEMORY_DATA
import gdb-1999-11-16 snapshot
1999-11-17 10:31:06 +08:00
+ IMAP0_OFFSET + 2 * reg_nr);
return READ_16 (raw);
}
Initial creation of sourceware repository
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import gdb-1999-11-16 snapshot
1999-11-17 10:31:06 +08:00
enum
{
HELD_SPI_IDX = 0,
HELD_SPU_IDX = 1
};
static unsigned long
spu_register (void)
Initial creation of sourceware repository
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{
import gdb-1999-11-16 snapshot
1999-11-17 10:31:06 +08:00
if (PSW_SM)
return GPR (SP_IDX);
else
return HELD_SP (HELD_SPU_IDX);
}
Initial creation of sourceware repository
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import gdb-1999-11-16 snapshot
1999-11-17 10:31:06 +08:00
static unsigned long
spi_register (void)
{
if (!PSW_SM)
return GPR (SP_IDX);
else
return HELD_SP (HELD_SPI_IDX);
}
static void
set_spi_register (unsigned long value)
{
if (!PSW_SM)
SET_GPR (SP_IDX, value);
SET_HELD_SP (HELD_SPI_IDX, value);
}
static void
set_spu_register (unsigned long value)
{
if (PSW_SM)
SET_GPR (SP_IDX, value);
SET_HELD_SP (HELD_SPU_IDX, value);
}
/* Given a virtual address in the DMAP address space, translate it
into a physical address. */
sim: cr16/d10v: localize translation funcs These functions are only used in the interp module, so there's no point in exporting them and declaring them in the external sim interface.
2015-11-10 15:04:53 +08:00
static unsigned long
sim: d10v: push down sd/cpu vars By itself, this commit doesn't really change anything. It lays the groundwork for using the cpu state in follow up commits, both for engine state and for cpu state. Splitting things up this way so it is easier to see how things have changed.
2015-11-15 18:57:42 +08:00
sim_d10v_translate_dmap_addr (SIM_DESC sd,
SIM_CPU *cpu,
unsigned long offset,
import gdb-1999-11-16 snapshot
1999-11-17 10:31:06 +08:00
int nr_bytes,
unsigned long *phys,
Index: gdb/ChangeLog 2003-05-07 Andrew Cagney <cagney@redhat.com> * d10v-tdep.c (remote_d10v_translate_xfer_address): Add "regcache". (d10v_print_registers_info): Update. (d10v_dmap_register, d10v_imap_register): Delete functions. (struct gdbarch_tdep): Add "regcache" parameter to "dmap_register" and "imap_register". (d10v_ts2_dmap_register, d10v_ts2_imap_register): Add "regcache". (d10v_ts3_dmap_register, d10v_ts3_imap_register): Add "regcache". * arch-utils.c (generic_remote_translate_xfer_address): Add "regcache" and "gdbarch" parameters. * gdbarch.sh (REMOTE_TRANSLATE_XFER_ADDRESS): Add "regcache" parameter. Change class to multi-arch. * gdbarch.h, gdbarch.c: Re-generate. * remote.c (remote_xfer_memory): Use gdbarch_remote_translate_xfer_address. Index: include/gdb/ChangeLog 2003-05-07 Andrew Cagney <cagney@redhat.com> * sim-d10v.h (sim_d10v_translate_addr): Add regcache parameter. (sim_d10v_translate_imap_addr): Add regcache parameter. (sim_d10v_translate_dmap_addr): Ditto. Index: sim/d10v/ChangeLog 2003-05-07 Andrew Cagney <cagney@redhat.com> * interp.c (sim_d10v_translate_addr): Add "regcache" parameter. (sim_d10v_translate_imap_addr): Ditto. (sim_d10v_translate_dmap_addr): Ditto. (xfer_mem): Pass NULL regcache to sim_d10v_translate_addr. (dmem_addr): Pass NULL regcache to sim_d10v_translate_dmap_addr. (dmap_register, imap_register): Add "regcache" parameter. (imem_addr): Pass NULL regcache to sim_d10v_translate_imap_addr. (sim_fetch_register): Pass NULL regcache to imap_register and dmap_register.
2003-05-08 03:21:13 +08:00
void *regcache,
sim: d10v: push down sd/cpu vars By itself, this commit doesn't really change anything. It lays the groundwork for using the cpu state in follow up commits, both for engine state and for cpu state. Splitting things up this way so it is easier to see how things have changed.
2015-11-15 18:57:42 +08:00
unsigned long (*dmap_register) (SIM_DESC,
SIM_CPU *,
void *regcache,
Index: gdb/ChangeLog 2003-05-07 Andrew Cagney <cagney@redhat.com> * d10v-tdep.c (remote_d10v_translate_xfer_address): Add "regcache". (d10v_print_registers_info): Update. (d10v_dmap_register, d10v_imap_register): Delete functions. (struct gdbarch_tdep): Add "regcache" parameter to "dmap_register" and "imap_register". (d10v_ts2_dmap_register, d10v_ts2_imap_register): Add "regcache". (d10v_ts3_dmap_register, d10v_ts3_imap_register): Add "regcache". * arch-utils.c (generic_remote_translate_xfer_address): Add "regcache" and "gdbarch" parameters. * gdbarch.sh (REMOTE_TRANSLATE_XFER_ADDRESS): Add "regcache" parameter. Change class to multi-arch. * gdbarch.h, gdbarch.c: Re-generate. * remote.c (remote_xfer_memory): Use gdbarch_remote_translate_xfer_address. Index: include/gdb/ChangeLog 2003-05-07 Andrew Cagney <cagney@redhat.com> * sim-d10v.h (sim_d10v_translate_addr): Add regcache parameter. (sim_d10v_translate_imap_addr): Add regcache parameter. (sim_d10v_translate_dmap_addr): Ditto. Index: sim/d10v/ChangeLog 2003-05-07 Andrew Cagney <cagney@redhat.com> * interp.c (sim_d10v_translate_addr): Add "regcache" parameter. (sim_d10v_translate_imap_addr): Ditto. (sim_d10v_translate_dmap_addr): Ditto. (xfer_mem): Pass NULL regcache to sim_d10v_translate_addr. (dmem_addr): Pass NULL regcache to sim_d10v_translate_dmap_addr. (dmap_register, imap_register): Add "regcache" parameter. (imem_addr): Pass NULL regcache to sim_d10v_translate_imap_addr. (sim_fetch_register): Pass NULL regcache to imap_register and dmap_register.
2003-05-08 03:21:13 +08:00
int reg_nr))
import gdb-1999-11-16 snapshot
1999-11-17 10:31:06 +08:00
{
short map;
int regno;
last_from = "logical-data";
if (offset >= DMAP_BLOCK_SIZE * SIM_D10V_NR_DMAP_REGS)
Initial creation of sourceware repository
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{
import gdb-1999-11-16 snapshot
1999-11-17 10:31:06 +08:00
/* Logical address out side of data segments, not supported */
return 0;
}
regno = (offset / DMAP_BLOCK_SIZE);
offset = (offset % DMAP_BLOCK_SIZE);
if ((offset % DMAP_BLOCK_SIZE) + nr_bytes > DMAP_BLOCK_SIZE)
{
/* Don't cross a BLOCK boundary */
nr_bytes = DMAP_BLOCK_SIZE - (offset % DMAP_BLOCK_SIZE);
}
sim: d10v: push down sd/cpu vars By itself, this commit doesn't really change anything. It lays the groundwork for using the cpu state in follow up commits, both for engine state and for cpu state. Splitting things up this way so it is easier to see how things have changed.
2015-11-15 18:57:42 +08:00
map = dmap_register (sd, cpu, regcache, regno);
import gdb-1999-11-16 snapshot
1999-11-17 10:31:06 +08:00
if (regno == 3)
{
/* Always maps to data memory */
int iospi = (offset / 0x1000) % 4;
int iosp = (map >> (4 * (3 - iospi))) % 0x10;
last_to = "io-space";
*phys = (SIM_D10V_MEMORY_DATA + (iosp * 0x10000) + 0xc000 + offset);
}
else
{
int sp = ((map & 0x3000) >> 12);
int segno = (map & 0x3ff);
switch (sp)
Initial creation of sourceware repository
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{
import gdb-1999-11-16 snapshot
1999-11-17 10:31:06 +08:00
case 0: /* 00: Unified memory */
*phys = SIM_D10V_MEMORY_UNIFIED + (segno * DMAP_BLOCK_SIZE) + offset;
last_to = "unified";
break;
case 1: /* 01: Instruction Memory */
*phys = SIM_D10V_MEMORY_INSN + (segno * DMAP_BLOCK_SIZE) + offset;
last_to = "chip-insn";
break;
case 2: /* 10: Internal data memory */
*phys = SIM_D10V_MEMORY_DATA + (segno << 16) + (regno * DMAP_BLOCK_SIZE) + offset;
last_to = "chip-data";
break;
case 3: /* 11: Reserved */
return 0;
Initial creation of sourceware repository
1999-04-16 09:35:26 +08:00
}
}
import gdb-1999-11-16 snapshot
1999-11-17 10:31:06 +08:00
return nr_bytes;
}
Initial creation of sourceware repository
1999-04-16 09:35:26 +08:00
import gdb-1999-11-16 snapshot
1999-11-17 10:31:06 +08:00
/* Given a virtual address in the IMAP address space, translate it
into a physical address. */
import gdb-1999-09-13 snapshot
1999-09-14 05:40:00 +08:00
sim: cr16/d10v: localize translation funcs These functions are only used in the interp module, so there's no point in exporting them and declaring them in the external sim interface.
2015-11-10 15:04:53 +08:00
static unsigned long
sim: d10v: push down sd/cpu vars By itself, this commit doesn't really change anything. It lays the groundwork for using the cpu state in follow up commits, both for engine state and for cpu state. Splitting things up this way so it is easier to see how things have changed.
2015-11-15 18:57:42 +08:00
sim_d10v_translate_imap_addr (SIM_DESC sd,
SIM_CPU *cpu,
unsigned long offset,
import gdb-1999-11-16 snapshot
1999-11-17 10:31:06 +08:00
int nr_bytes,
unsigned long *phys,
Index: gdb/ChangeLog 2003-05-07 Andrew Cagney <cagney@redhat.com> * d10v-tdep.c (remote_d10v_translate_xfer_address): Add "regcache". (d10v_print_registers_info): Update. (d10v_dmap_register, d10v_imap_register): Delete functions. (struct gdbarch_tdep): Add "regcache" parameter to "dmap_register" and "imap_register". (d10v_ts2_dmap_register, d10v_ts2_imap_register): Add "regcache". (d10v_ts3_dmap_register, d10v_ts3_imap_register): Add "regcache". * arch-utils.c (generic_remote_translate_xfer_address): Add "regcache" and "gdbarch" parameters. * gdbarch.sh (REMOTE_TRANSLATE_XFER_ADDRESS): Add "regcache" parameter. Change class to multi-arch. * gdbarch.h, gdbarch.c: Re-generate. * remote.c (remote_xfer_memory): Use gdbarch_remote_translate_xfer_address. Index: include/gdb/ChangeLog 2003-05-07 Andrew Cagney <cagney@redhat.com> * sim-d10v.h (sim_d10v_translate_addr): Add regcache parameter. (sim_d10v_translate_imap_addr): Add regcache parameter. (sim_d10v_translate_dmap_addr): Ditto. Index: sim/d10v/ChangeLog 2003-05-07 Andrew Cagney <cagney@redhat.com> * interp.c (sim_d10v_translate_addr): Add "regcache" parameter. (sim_d10v_translate_imap_addr): Ditto. (sim_d10v_translate_dmap_addr): Ditto. (xfer_mem): Pass NULL regcache to sim_d10v_translate_addr. (dmem_addr): Pass NULL regcache to sim_d10v_translate_dmap_addr. (dmap_register, imap_register): Add "regcache" parameter. (imem_addr): Pass NULL regcache to sim_d10v_translate_imap_addr. (sim_fetch_register): Pass NULL regcache to imap_register and dmap_register.
2003-05-08 03:21:13 +08:00
void *regcache,
sim: d10v: push down sd/cpu vars By itself, this commit doesn't really change anything. It lays the groundwork for using the cpu state in follow up commits, both for engine state and for cpu state. Splitting things up this way so it is easier to see how things have changed.
2015-11-15 18:57:42 +08:00
unsigned long (*imap_register) (SIM_DESC,
SIM_CPU *,
void *regcache,
Index: gdb/ChangeLog 2003-05-07 Andrew Cagney <cagney@redhat.com> * d10v-tdep.c (remote_d10v_translate_xfer_address): Add "regcache". (d10v_print_registers_info): Update. (d10v_dmap_register, d10v_imap_register): Delete functions. (struct gdbarch_tdep): Add "regcache" parameter to "dmap_register" and "imap_register". (d10v_ts2_dmap_register, d10v_ts2_imap_register): Add "regcache". (d10v_ts3_dmap_register, d10v_ts3_imap_register): Add "regcache". * arch-utils.c (generic_remote_translate_xfer_address): Add "regcache" and "gdbarch" parameters. * gdbarch.sh (REMOTE_TRANSLATE_XFER_ADDRESS): Add "regcache" parameter. Change class to multi-arch. * gdbarch.h, gdbarch.c: Re-generate. * remote.c (remote_xfer_memory): Use gdbarch_remote_translate_xfer_address. Index: include/gdb/ChangeLog 2003-05-07 Andrew Cagney <cagney@redhat.com> * sim-d10v.h (sim_d10v_translate_addr): Add regcache parameter. (sim_d10v_translate_imap_addr): Add regcache parameter. (sim_d10v_translate_dmap_addr): Ditto. Index: sim/d10v/ChangeLog 2003-05-07 Andrew Cagney <cagney@redhat.com> * interp.c (sim_d10v_translate_addr): Add "regcache" parameter. (sim_d10v_translate_imap_addr): Ditto. (sim_d10v_translate_dmap_addr): Ditto. (xfer_mem): Pass NULL regcache to sim_d10v_translate_addr. (dmem_addr): Pass NULL regcache to sim_d10v_translate_dmap_addr. (dmap_register, imap_register): Add "regcache" parameter. (imem_addr): Pass NULL regcache to sim_d10v_translate_imap_addr. (sim_fetch_register): Pass NULL regcache to imap_register and dmap_register.
2003-05-08 03:21:13 +08:00
int reg_nr))
import gdb-1999-11-16 snapshot
1999-11-17 10:31:06 +08:00
{
short map;
int regno;
int sp;
int segno;
last_from = "logical-insn";
if (offset >= (IMAP_BLOCK_SIZE * SIM_D10V_NR_IMAP_REGS))
{
/* Logical address outside of IMAP segments, not supported */
return 0;
}
regno = (offset / IMAP_BLOCK_SIZE);
offset = (offset % IMAP_BLOCK_SIZE);
if (offset + nr_bytes > IMAP_BLOCK_SIZE)
{
/* Don't cross a BLOCK boundary */
nr_bytes = IMAP_BLOCK_SIZE - offset;
}
sim: d10v: push down sd/cpu vars By itself, this commit doesn't really change anything. It lays the groundwork for using the cpu state in follow up commits, both for engine state and for cpu state. Splitting things up this way so it is easier to see how things have changed.
2015-11-15 18:57:42 +08:00
map = imap_register (sd, cpu, regcache, regno);
import gdb-1999-11-16 snapshot
1999-11-17 10:31:06 +08:00
sp = (map & 0x3000) >> 12;
segno = (map & 0x007f);
switch (sp)
{
case 0: /* 00: unified memory */
*phys = SIM_D10V_MEMORY_UNIFIED + (segno << 17) + offset;
last_to = "unified";
break;
case 1: /* 01: instruction memory */
*phys = SIM_D10V_MEMORY_INSN + (IMAP_BLOCK_SIZE * regno) + offset;
last_to = "chip-insn";
break;
case 2: /*10*/
/* Reserved. */
return 0;
case 3: /* 11: for testing - instruction memory */
offset = (offset % 0x800);
*phys = SIM_D10V_MEMORY_INSN + offset;
if (offset + nr_bytes > 0x800)
/* don't cross VM boundary */
nr_bytes = 0x800 - offset;
last_to = "test-insn";
break;
}
return nr_bytes;
}
import gdb-1999-09-13 snapshot
1999-09-14 05:40:00 +08:00
sim: cr16/d10v: localize translation funcs These functions are only used in the interp module, so there's no point in exporting them and declaring them in the external sim interface.
2015-11-10 15:04:53 +08:00
static unsigned long
sim: d10v: push down sd/cpu vars By itself, this commit doesn't really change anything. It lays the groundwork for using the cpu state in follow up commits, both for engine state and for cpu state. Splitting things up this way so it is easier to see how things have changed.
2015-11-15 18:57:42 +08:00
sim_d10v_translate_addr (SIM_DESC sd,
SIM_CPU *cpu,
unsigned long memaddr,
import gdb-1999-11-16 snapshot
1999-11-17 10:31:06 +08:00
int nr_bytes,
unsigned long *targ_addr,
Index: gdb/ChangeLog 2003-05-07 Andrew Cagney <cagney@redhat.com> * d10v-tdep.c (remote_d10v_translate_xfer_address): Add "regcache". (d10v_print_registers_info): Update. (d10v_dmap_register, d10v_imap_register): Delete functions. (struct gdbarch_tdep): Add "regcache" parameter to "dmap_register" and "imap_register". (d10v_ts2_dmap_register, d10v_ts2_imap_register): Add "regcache". (d10v_ts3_dmap_register, d10v_ts3_imap_register): Add "regcache". * arch-utils.c (generic_remote_translate_xfer_address): Add "regcache" and "gdbarch" parameters. * gdbarch.sh (REMOTE_TRANSLATE_XFER_ADDRESS): Add "regcache" parameter. Change class to multi-arch. * gdbarch.h, gdbarch.c: Re-generate. * remote.c (remote_xfer_memory): Use gdbarch_remote_translate_xfer_address. Index: include/gdb/ChangeLog 2003-05-07 Andrew Cagney <cagney@redhat.com> * sim-d10v.h (sim_d10v_translate_addr): Add regcache parameter. (sim_d10v_translate_imap_addr): Add regcache parameter. (sim_d10v_translate_dmap_addr): Ditto. Index: sim/d10v/ChangeLog 2003-05-07 Andrew Cagney <cagney@redhat.com> * interp.c (sim_d10v_translate_addr): Add "regcache" parameter. (sim_d10v_translate_imap_addr): Ditto. (sim_d10v_translate_dmap_addr): Ditto. (xfer_mem): Pass NULL regcache to sim_d10v_translate_addr. (dmem_addr): Pass NULL regcache to sim_d10v_translate_dmap_addr. (dmap_register, imap_register): Add "regcache" parameter. (imem_addr): Pass NULL regcache to sim_d10v_translate_imap_addr. (sim_fetch_register): Pass NULL regcache to imap_register and dmap_register.
2003-05-08 03:21:13 +08:00
void *regcache,
sim: d10v: push down sd/cpu vars By itself, this commit doesn't really change anything. It lays the groundwork for using the cpu state in follow up commits, both for engine state and for cpu state. Splitting things up this way so it is easier to see how things have changed.
2015-11-15 18:57:42 +08:00
unsigned long (*dmap_register) (SIM_DESC,
SIM_CPU *,
void *regcache,
Index: gdb/ChangeLog 2003-05-07 Andrew Cagney <cagney@redhat.com> * d10v-tdep.c (remote_d10v_translate_xfer_address): Add "regcache". (d10v_print_registers_info): Update. (d10v_dmap_register, d10v_imap_register): Delete functions. (struct gdbarch_tdep): Add "regcache" parameter to "dmap_register" and "imap_register". (d10v_ts2_dmap_register, d10v_ts2_imap_register): Add "regcache". (d10v_ts3_dmap_register, d10v_ts3_imap_register): Add "regcache". * arch-utils.c (generic_remote_translate_xfer_address): Add "regcache" and "gdbarch" parameters. * gdbarch.sh (REMOTE_TRANSLATE_XFER_ADDRESS): Add "regcache" parameter. Change class to multi-arch. * gdbarch.h, gdbarch.c: Re-generate. * remote.c (remote_xfer_memory): Use gdbarch_remote_translate_xfer_address. Index: include/gdb/ChangeLog 2003-05-07 Andrew Cagney <cagney@redhat.com> * sim-d10v.h (sim_d10v_translate_addr): Add regcache parameter. (sim_d10v_translate_imap_addr): Add regcache parameter. (sim_d10v_translate_dmap_addr): Ditto. Index: sim/d10v/ChangeLog 2003-05-07 Andrew Cagney <cagney@redhat.com> * interp.c (sim_d10v_translate_addr): Add "regcache" parameter. (sim_d10v_translate_imap_addr): Ditto. (sim_d10v_translate_dmap_addr): Ditto. (xfer_mem): Pass NULL regcache to sim_d10v_translate_addr. (dmem_addr): Pass NULL regcache to sim_d10v_translate_dmap_addr. (dmap_register, imap_register): Add "regcache" parameter. (imem_addr): Pass NULL regcache to sim_d10v_translate_imap_addr. (sim_fetch_register): Pass NULL regcache to imap_register and dmap_register.
2003-05-08 03:21:13 +08:00
int reg_nr),
sim: d10v: push down sd/cpu vars By itself, this commit doesn't really change anything. It lays the groundwork for using the cpu state in follow up commits, both for engine state and for cpu state. Splitting things up this way so it is easier to see how things have changed.
2015-11-15 18:57:42 +08:00
unsigned long (*imap_register) (SIM_DESC,
SIM_CPU *,
void *regcache,
Index: gdb/ChangeLog 2003-05-07 Andrew Cagney <cagney@redhat.com> * d10v-tdep.c (remote_d10v_translate_xfer_address): Add "regcache". (d10v_print_registers_info): Update. (d10v_dmap_register, d10v_imap_register): Delete functions. (struct gdbarch_tdep): Add "regcache" parameter to "dmap_register" and "imap_register". (d10v_ts2_dmap_register, d10v_ts2_imap_register): Add "regcache". (d10v_ts3_dmap_register, d10v_ts3_imap_register): Add "regcache". * arch-utils.c (generic_remote_translate_xfer_address): Add "regcache" and "gdbarch" parameters. * gdbarch.sh (REMOTE_TRANSLATE_XFER_ADDRESS): Add "regcache" parameter. Change class to multi-arch. * gdbarch.h, gdbarch.c: Re-generate. * remote.c (remote_xfer_memory): Use gdbarch_remote_translate_xfer_address. Index: include/gdb/ChangeLog 2003-05-07 Andrew Cagney <cagney@redhat.com> * sim-d10v.h (sim_d10v_translate_addr): Add regcache parameter. (sim_d10v_translate_imap_addr): Add regcache parameter. (sim_d10v_translate_dmap_addr): Ditto. Index: sim/d10v/ChangeLog 2003-05-07 Andrew Cagney <cagney@redhat.com> * interp.c (sim_d10v_translate_addr): Add "regcache" parameter. (sim_d10v_translate_imap_addr): Ditto. (sim_d10v_translate_dmap_addr): Ditto. (xfer_mem): Pass NULL regcache to sim_d10v_translate_addr. (dmem_addr): Pass NULL regcache to sim_d10v_translate_dmap_addr. (dmap_register, imap_register): Add "regcache" parameter. (imem_addr): Pass NULL regcache to sim_d10v_translate_imap_addr. (sim_fetch_register): Pass NULL regcache to imap_register and dmap_register.
2003-05-08 03:21:13 +08:00
int reg_nr))
import gdb-1999-11-16 snapshot
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{
unsigned long phys;
unsigned long seg;
unsigned long off;
import gdb-1999-09-13 snapshot
1999-09-14 05:40:00 +08:00
import gdb-1999-11-16 snapshot
1999-11-17 10:31:06 +08:00
last_from = "unknown";
last_to = "unknown";
import gdb-1999-09-13 snapshot
1999-09-14 05:40:00 +08:00
import gdb-1999-11-16 snapshot
1999-11-17 10:31:06 +08:00
seg = (memaddr >> 24);
off = (memaddr & 0xffffffL);
Initial creation of sourceware repository
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import gdb-1999-09-13 snapshot
1999-09-14 05:40:00 +08:00
/* However, if we've asked to use the previous generation of segment
mapping, rearrange the segments as follows. */
if (old_segment_mapping)
{
import gdb-1999-11-16 snapshot
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switch (seg)
import gdb-1999-09-13 snapshot
1999-09-14 05:40:00 +08:00
{
case 0x00: /* DMAP translated memory */
import gdb-1999-11-16 snapshot
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seg = 0x10;
import gdb-1999-09-13 snapshot
1999-09-14 05:40:00 +08:00
break;
case 0x01: /* IMAP translated memory */
import gdb-1999-11-16 snapshot
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seg = 0x11;
import gdb-1999-09-13 snapshot
1999-09-14 05:40:00 +08:00
break;
case 0x10: /* On-chip data memory */
import gdb-1999-11-16 snapshot
1999-11-17 10:31:06 +08:00
seg = 0x02;
import gdb-1999-09-13 snapshot
1999-09-14 05:40:00 +08:00
break;
case 0x11: /* On-chip insn memory */
import gdb-1999-11-16 snapshot
1999-11-17 10:31:06 +08:00
seg = 0x01;
import gdb-1999-09-13 snapshot
1999-09-14 05:40:00 +08:00
break;
case 0x12: /* Unified memory */
import gdb-1999-11-16 snapshot
1999-11-17 10:31:06 +08:00
seg = 0x00;
import gdb-1999-09-13 snapshot
1999-09-14 05:40:00 +08:00
break;
}
}
import gdb-1999-11-16 snapshot
1999-11-17 10:31:06 +08:00
switch (seg)
Initial creation of sourceware repository
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{
import gdb-1999-11-16 snapshot
1999-11-17 10:31:06 +08:00
case 0x00: /* Physical unified memory */
last_from = "phys-unified";
last_to = "unified";
phys = SIM_D10V_MEMORY_UNIFIED + off;
if ((off % SEGMENT_SIZE) + nr_bytes > SEGMENT_SIZE)
nr_bytes = SEGMENT_SIZE - (off % SEGMENT_SIZE);
break;
Initial creation of sourceware repository
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import gdb-1999-11-16 snapshot
1999-11-17 10:31:06 +08:00
case 0x01: /* Physical instruction memory */
last_from = "phys-insn";
last_to = "chip-insn";
phys = SIM_D10V_MEMORY_INSN + off;
if ((off % SEGMENT_SIZE) + nr_bytes > SEGMENT_SIZE)
nr_bytes = SEGMENT_SIZE - (off % SEGMENT_SIZE);
break;
Initial creation of sourceware repository
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import gdb-1999-11-16 snapshot
1999-11-17 10:31:06 +08:00
case 0x02: /* Physical data memory segment */
last_from = "phys-data";
last_to = "chip-data";
phys = SIM_D10V_MEMORY_DATA + off;
if ((off % SEGMENT_SIZE) + nr_bytes > SEGMENT_SIZE)
nr_bytes = SEGMENT_SIZE - (off % SEGMENT_SIZE);
break;
case 0x10: /* in logical data address segment */
sim: d10v: push down sd/cpu vars By itself, this commit doesn't really change anything. It lays the groundwork for using the cpu state in follow up commits, both for engine state and for cpu state. Splitting things up this way so it is easier to see how things have changed.
2015-11-15 18:57:42 +08:00
nr_bytes = sim_d10v_translate_dmap_addr (sd, cpu, off, nr_bytes, &phys,
regcache, dmap_register);
import gdb-1999-11-16 snapshot
1999-11-17 10:31:06 +08:00
break;
case 0x11: /* in logical instruction address segment */
sim: d10v: push down sd/cpu vars By itself, this commit doesn't really change anything. It lays the groundwork for using the cpu state in follow up commits, both for engine state and for cpu state. Splitting things up this way so it is easier to see how things have changed.
2015-11-15 18:57:42 +08:00
nr_bytes = sim_d10v_translate_imap_addr (sd, cpu, off, nr_bytes, &phys,
regcache, imap_register);
import gdb-1999-11-16 snapshot
1999-11-17 10:31:06 +08:00
break;
default:
return 0;
}
*targ_addr = phys;
return nr_bytes;
}
/* Return a pointer into the raw buffer designated by phys_addr. It
is assumed that the client has already ensured that the access
isn't going to cross a segment boundary. */
sim: d10v: migrate to standard uintXX_t types This old port setup its own uintXX types, but since we require C11 now, we can assume the standard uintXX_t types exist and use them. Also migrate off the sim-specific unsignedXX types.
2021-12-06 01:24:12 +08:00
uint8_t *
sim: d10v: push down sd/cpu vars By itself, this commit doesn't really change anything. It lays the groundwork for using the cpu state in follow up commits, both for engine state and for cpu state. Splitting things up this way so it is easier to see how things have changed.
2015-11-15 18:57:42 +08:00
map_memory (SIM_DESC sd, SIM_CPU *cpu, unsigned phys_addr)
import gdb-1999-11-16 snapshot
1999-11-17 10:31:06 +08:00
{
sim: d10v: migrate to standard uintXX_t types This old port setup its own uintXX types, but since we require C11 now, we can assume the standard uintXX_t types exist and use them. Also migrate off the sim-specific unsignedXX types.
2021-12-06 01:24:12 +08:00
uint8_t **memory;
uint8_t *raw;
import gdb-1999-11-16 snapshot
1999-11-17 10:31:06 +08:00
unsigned offset;
int segment = ((phys_addr >> 24) & 0xff);
switch (segment)
{
case 0x00: /* Unified memory */
Initial creation of sourceware repository
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{
import gdb-1999-11-16 snapshot
1999-11-17 10:31:06 +08:00
memory = &State.mem.unif[(phys_addr / SEGMENT_SIZE) % UMEM_SEGMENTS];
last_segname = "umem";
Initial creation of sourceware repository
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break;
}
import gdb-1999-11-16 snapshot
1999-11-17 10:31:06 +08:00
import gdb-1999-09-13 snapshot
1999-09-14 05:40:00 +08:00
case 0x01: /* On-chip insn memory */
Initial creation of sourceware repository
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{
import gdb-1999-11-16 snapshot
1999-11-17 10:31:06 +08:00
memory = &State.mem.insn[(phys_addr / SEGMENT_SIZE) % IMEM_SEGMENTS];
last_segname = "imem";
Initial creation of sourceware repository
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break;
}
import gdb-1999-11-16 snapshot
1999-11-17 10:31:06 +08:00
case 0x02: /* On-chip data memory */
Initial creation of sourceware repository
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{
import gdb-1999-11-16 snapshot
1999-11-17 10:31:06 +08:00
if ((phys_addr & 0xff00) == 0xff00)
Initial creation of sourceware repository
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{
import gdb-1999-11-16 snapshot
1999-11-17 10:31:06 +08:00
phys_addr = (phys_addr & 0xffff);
if (phys_addr == DMAP2_SHADDOW)
Initial creation of sourceware repository
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{
import gdb-1999-11-16 snapshot
1999-11-17 10:31:06 +08:00
phys_addr = DMAP2_OFFSET;
last_segname = "dmap";
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}
import gdb-1999-11-16 snapshot
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else
last_segname = "reg";
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}
import gdb-1999-11-16 snapshot
1999-11-17 10:31:06 +08:00
else
last_segname = "dmem";
memory = &State.mem.data[(phys_addr / SEGMENT_SIZE) % DMEM_SEGMENTS];
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break;
}
import gdb-1999-11-16 snapshot
1999-11-17 10:31:06 +08:00
Initial creation of sourceware repository
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default:
import gdb-1999-11-16 snapshot
1999-11-17 10:31:06 +08:00
/* OOPS! */
last_segname = "scrap";
sim: d10v: convert to common sim engine logic Now that we have access to the sim state everywhere, we can convert to the common engine logic for overall processing. This frees us up from tracking exception state ourselves.
2015-11-15 19:07:06 +08:00
sim_engine_halt (sd, cpu, NULL, PC, sim_stopped, SIM_SIGBUS);
Initial creation of sourceware repository
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}
import gdb-1999-11-16 snapshot
1999-11-17 10:31:06 +08:00
if (*memory == NULL)
sim: d10v: convert to common sim engine logic Now that we have access to the sim state everywhere, we can convert to the common engine logic for overall processing. This frees us up from tracking exception state ourselves.
2015-11-15 19:07:06 +08:00
*memory = xcalloc (1, SEGMENT_SIZE);
import gdb-1999-11-16 snapshot
1999-11-17 10:31:06 +08:00
offset = (phys_addr % SEGMENT_SIZE);
raw = *memory + offset;
return raw;
}
/* Transfer data to/from simulated memory. Since a bug in either the
simulated program or in gdb or the simulator itself may cause a
bogus address to be passed in, we need to do some sanity checking
on addresses to make sure they are within bounds. When an address
fails the bounds check, treat it as a zero length read/write rather
than aborting the entire run. */
static int
sim: d10v: push down sd/cpu vars By itself, this commit doesn't really change anything. It lays the groundwork for using the cpu state in follow up commits, both for engine state and for cpu state. Splitting things up this way so it is easier to see how things have changed.
2015-11-15 18:57:42 +08:00
xfer_mem (SIM_DESC sd,
SIM_ADDR virt,
import gdb-1999-11-16 snapshot
1999-11-17 10:31:06 +08:00
unsigned char *buffer,
int size,
int write_p)
{
sim: d10v: migrate to standard uintXX_t types This old port setup its own uintXX types, but since we require C11 now, we can assume the standard uintXX_t types exist and use them. Also migrate off the sim-specific unsignedXX types.
2021-12-06 01:24:12 +08:00
uint8_t *memory;
2003-06-22 Andrew Cagney <cagney@redhat.com> * interp.c (xfer_mem): Simplify. Only do a single partial transfer. Problem reported by Tom Rix.
2003-06-22 21:38:28 +08:00
unsigned long phys;
int phys_size;
sim: d10v: push down sd/cpu vars By itself, this commit doesn't really change anything. It lays the groundwork for using the cpu state in follow up commits, both for engine state and for cpu state. Splitting things up this way so it is easier to see how things have changed.
2015-11-15 18:57:42 +08:00
phys_size = sim_d10v_translate_addr (sd, NULL, virt, size, &phys, NULL,
2003-06-22 Andrew Cagney <cagney@redhat.com> * interp.c (xfer_mem): Simplify. Only do a single partial transfer. Problem reported by Tom Rix.
2003-06-22 21:38:28 +08:00
dmap_register, imap_register);
if (phys_size == 0)
return 0;
import gdb-1999-11-16 snapshot
1999-11-17 10:31:06 +08:00
sim: d10v: push down sd/cpu vars By itself, this commit doesn't really change anything. It lays the groundwork for using the cpu state in follow up commits, both for engine state and for cpu state. Splitting things up this way so it is easier to see how things have changed.
2015-11-15 18:57:42 +08:00
memory = map_memory (sd, NULL, phys);
import gdb-1999-11-16 snapshot
1999-11-17 10:31:06 +08:00
#ifdef DEBUG
2003-06-22 Andrew Cagney <cagney@redhat.com> * interp.c (xfer_mem): Simplify. Only do a single partial transfer. Problem reported by Tom Rix.
2003-06-22 21:38:28 +08:00
if ((d10v_debug & DEBUG_INSTRUCTION) != 0)
{
sim: d10v: drop global callback state Now that we have access to the sim state in all the right places, use existing sim helpers in place of d10v_callback directly.
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sim_io_printf
(sd,
sim: d10v: clean up pointer casts Use %p to print pointers instead of trying to cast them to longs.
2021-11-01 12:05:15 +08:00
"sim_%s %d bytes: 0x%08" PRIxTA " (%s) -> 0x%08lx (%s) -> %p (%s)\n",
sim: d10v: drop global callback state Now that we have access to the sim state in all the right places, use existing sim helpers in place of d10v_callback directly.
2015-11-15 19:41:26 +08:00
write_p ? "write" : "read",
2003-06-22 Andrew Cagney <cagney@redhat.com> * interp.c (xfer_mem): Simplify. Only do a single partial transfer. Problem reported by Tom Rix.
2003-06-22 21:38:28 +08:00
phys_size, virt, last_from,
phys, last_to,
sim: d10v: clean up pointer casts Use %p to print pointers instead of trying to cast them to longs.
2021-11-01 12:05:15 +08:00
memory, last_segname);
2003-06-22 Andrew Cagney <cagney@redhat.com> * interp.c (xfer_mem): Simplify. Only do a single partial transfer. Problem reported by Tom Rix.
2003-06-22 21:38:28 +08:00
}
import gdb-1999-11-16 snapshot
1999-11-17 10:31:06 +08:00
#endif
2003-06-22 Andrew Cagney <cagney@redhat.com> * interp.c (xfer_mem): Simplify. Only do a single partial transfer. Problem reported by Tom Rix.
2003-06-22 21:38:28 +08:00
if (write_p)
{
memcpy (memory, buffer, phys_size);
Initial creation of sourceware repository
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}
2003-06-22 Andrew Cagney <cagney@redhat.com> * interp.c (xfer_mem): Simplify. Only do a single partial transfer. Problem reported by Tom Rix.
2003-06-22 21:38:28 +08:00
else
{
memcpy (buffer, memory, phys_size);
}
return phys_size;
Initial creation of sourceware repository
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}
int
sim: common: change sim_read & sim_write to use void* buffers When reading/writing arbitrary data to the system's memory, the unsigned char pointer type doesn't make that much sense. Switch it to void so we align a bit with standard C library read/write functions, and to avoid having to sprinkle casts everywhere.
2022-10-27 00:08:30 +08:00
sim_write (SIM_DESC sd, SIM_ADDR addr, const void *buffer, int size)
Initial creation of sourceware repository
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{
/* FIXME: this should be performing a virtual transfer */
sim: d10v: fix build warnings The printf fix uses our PRIxTA for our sim address type. Then cast away the const (since the underlying code safely treats it as such) even if it's ugly. Finally touch up the argv iterator pointer to match the new func arg. With this tidied up, we can delete the SIM_AC_OPTION_WARNINGS(no) call to get the default common behavior where -Werror is enabled.
2021-04-19 09:13:34 +08:00
/* FIXME: We cast the const away, but it's safe because xfer_mem only reads
when write_p==1. This is still ugly. */
return xfer_mem (sd, addr, (void *) buffer, size, 1);
Initial creation of sourceware repository
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}
int
sim: common: change sim_read & sim_write to use void* buffers When reading/writing arbitrary data to the system's memory, the unsigned char pointer type doesn't make that much sense. Switch it to void so we align a bit with standard C library read/write functions, and to avoid having to sprinkle casts everywhere.
2022-10-27 00:08:30 +08:00
sim_read (SIM_DESC sd, SIM_ADDR addr, void *buffer, int size)
Initial creation of sourceware repository
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{
/* FIXME: this should be performing a virtual transfer */
sim: d10v: push down sd/cpu vars By itself, this commit doesn't really change anything. It lays the groundwork for using the cpu state in follow up commits, both for engine state and for cpu state. Splitting things up this way so it is easier to see how things have changed.
2015-11-15 18:57:42 +08:00
return xfer_mem (sd, addr, buffer, size, 0);
Initial creation of sourceware repository
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}
sim: arm/cr16/d10v/h8300/microblaze/sh: fill out sim-cpu pc fetch/store helpers This makes the common sim-cpu logic work.
2015-04-17 14:16:10 +08:00
static sim_cia
d10v_pc_get (sim_cpu *cpu)
{
return PC;
}
static void
d10v_pc_set (sim_cpu *cpu, sim_cia pc)
{
sim: d10v: push down sd/cpu vars By itself, this commit doesn't really change anything. It lays the groundwork for using the cpu state in follow up commits, both for engine state and for cpu state. Splitting things up this way so it is easier to see how things have changed.
2015-11-15 18:57:42 +08:00
SIM_DESC sd = CPU_STATE (cpu);
sim: arm/cr16/d10v/h8300/microblaze/sh: fill out sim-cpu pc fetch/store helpers This makes the common sim-cpu logic work.
2015-04-17 14:16:10 +08:00
SET_PC (pc);
}
sim: d10v: convert to nrun A lot of cpu state is stored in global variables, as is memory handling. The sim_size support needs unwinding at some point. But at least this is an improvement on the status quo.
2015-03-30 14:05:33 +08:00
static void
free_state (SIM_DESC sd)
{
if (STATE_MODULES (sd) != NULL)
sim_module_uninstall (sd);
sim_cpu_free_all (sd);
sim_state_free (sd);
}
sim: common: change sim_{fetch,store}_register helpers to use void* buffers When reading/writing arbitrary data to the system's memory, the unsigned char pointer type doesn't make that much sense. Switch it to void so we align a bit with standard C library read/write functions, and to avoid having to sprinkle casts everywhere.
2022-10-31 23:58:10 +08:00
static int d10v_reg_fetch (SIM_CPU *, int, void *, int);
static int d10v_reg_store (SIM_CPU *, int, const void *, int);
sim: arm/d10v/h8300/m68hc11/microblaze/mips/mn10300/moxie/sh/v850: convert to common sim_{fetch,store}_register
2015-12-30 16:28:45 +08:00
Initial creation of sourceware repository
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SIM_DESC
sim: sim_{create_inferior,open,parse_args}: constify argv/env slightly 2016-01-03 Mike Frysinger <vapier@gentoo.org> * sim-options.c (sim_parse_args): Mark argv array const. * sim-options.h (sim_parse_args): Likewise.
2016-01-03 14:51:44 +08:00
sim_open (SIM_OPEN_KIND kind, host_callback *cb,
struct bfd *abfd, char * const *argv)
Initial creation of sourceware repository
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{
struct simops *s;
struct hash_entry *h;
static int init_p = 0;
sim: d10v: fix build warnings The printf fix uses our PRIxTA for our sim address type. Then cast away the const (since the underlying code safely treats it as such) even if it's ugly. Finally touch up the argv iterator pointer to match the new func arg. With this tidied up, we can delete the SIM_AC_OPTION_WARNINGS(no) call to get the default common behavior where -Werror is enabled.
2021-04-19 09:13:34 +08:00
char * const *p;
sim: arm/cr16/d10v/h8300/microblaze/sh: fill out sim-cpu pc fetch/store helpers This makes the common sim-cpu logic work.
2015-04-17 14:16:10 +08:00
int i;
sim: d10v: convert to nrun A lot of cpu state is stored in global variables, as is memory handling. The sim_size support needs unwinding at some point. But at least this is an improvement on the status quo.
2015-03-30 14:05:33 +08:00
SIM_DESC sd = sim_state_alloc (kind, cb);
SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
Initial creation of sourceware repository
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sim: overhaul alignment settings management Currently, the sim-config module will abort if alignment settings haven't been specified by the port's configure.ac. This is a bit weird when we've allowed SIM_AC_OPTION_ALIGNMENT to seem like it's optional to use. Thus everyone invokes it. There are 4 alignment settings, but really only 2 matters: strict and nonstrict. The "mixed" setting is just the default ("unset"), and "forced" isn't used directly by anyone (it's available as a runtime option for some ports). The m4 macro has 2 args: the "wire" settings (which represents the hardwired port behavior), and the default settings (which are used if nothing else is specified). If none are specified, then the build won't work (see above as if SIM_AC_OPTION_ALIGNMENT wasn't called). If default settings are provided, then that is used, but we allow the user to override at runtime. Otherwise, the "wire" settings are used and user runtime options to change are ignored. Most ports specify a default, or set the "wire" to nonstrict. A few set "wire" to strict, but it's not clear that's necessary as it doesn't make the code behavior, by default, any different. It might make things a little faster, but we should provide the user the choice of the compromises to make: force a specific mode at compile time for faster runtime, or allow the choice at runtime. More likely it seems like an oversight when these ports were initially created, and/or copied & pasted from existing ports. With all that backstory, let's get to what this commit does. First kill off the idea of a compile-time default alignment and set it to nonstrict in the common code. For any ports that want strict alignment by default, that code is moved to sim_open while initializing the sim. That means WITH_DEFAULT_ALIGNMENT can be completely removed. Moving the default alignment to the runtime also allows removal of setting the "wire" settings at configure time. Which allows removing of all arguments to SIM_AC_OPTION_ALIGNMENT and moving that call to common code. The macro logic can be reworked to not pass WITH_ALIGNMENT as -D CPPFLAG and instead move it to config.h. All of these taken together mean we can hoist the macro up to the top level and share it among all sims so behavior is consistent among all the ports.
2021-06-07 12:54:20 +08:00
/* Set default options before parsing user options. */
current_alignment = STRICT_ALIGNMENT;
sim: d10v: switch to new target-newlib-syscall Use the new target-newlib-syscall module. This is needed to merge all the architectures into a single build, and d10v has a custom syscall table for its newlib/libgloss port. This allows cleaning up the syscall ifdef logic. We know these will always exist now.
2021-11-28 13:20:31 +08:00
cb->syscall_map = cb_d10v_syscall_map;
sim: overhaul alignment settings management Currently, the sim-config module will abort if alignment settings haven't been specified by the port's configure.ac. This is a bit weird when we've allowed SIM_AC_OPTION_ALIGNMENT to seem like it's optional to use. Thus everyone invokes it. There are 4 alignment settings, but really only 2 matters: strict and nonstrict. The "mixed" setting is just the default ("unset"), and "forced" isn't used directly by anyone (it's available as a runtime option for some ports). The m4 macro has 2 args: the "wire" settings (which represents the hardwired port behavior), and the default settings (which are used if nothing else is specified). If none are specified, then the build won't work (see above as if SIM_AC_OPTION_ALIGNMENT wasn't called). If default settings are provided, then that is used, but we allow the user to override at runtime. Otherwise, the "wire" settings are used and user runtime options to change are ignored. Most ports specify a default, or set the "wire" to nonstrict. A few set "wire" to strict, but it's not clear that's necessary as it doesn't make the code behavior, by default, any different. It might make things a little faster, but we should provide the user the choice of the compromises to make: force a specific mode at compile time for faster runtime, or allow the choice at runtime. More likely it seems like an oversight when these ports were initially created, and/or copied & pasted from existing ports. With all that backstory, let's get to what this commit does. First kill off the idea of a compile-time default alignment and set it to nonstrict in the common code. For any ports that want strict alignment by default, that code is moved to sim_open while initializing the sim. That means WITH_DEFAULT_ALIGNMENT can be completely removed. Moving the default alignment to the runtime also allows removal of setting the "wire" settings at configure time. Which allows removing of all arguments to SIM_AC_OPTION_ALIGNMENT and moving that call to common code. The macro logic can be reworked to not pass WITH_ALIGNMENT as -D CPPFLAG and instead move it to config.h. All of these taken together mean we can hoist the macro up to the top level and share it among all sims so behavior is consistent among all the ports.
2021-06-07 12:54:20 +08:00
sim: d10v: convert to nrun A lot of cpu state is stored in global variables, as is memory handling. The sim_size support needs unwinding at some point. But at least this is an improvement on the status quo.
2015-03-30 14:05:33 +08:00
/* The cpu data is kept in a separately allocated chunk of memory. */
sim: cgen: move cgen_cpu_max_extra_bytes logic into the common code Every arch handles this the same way, so move it to the common code. This will also make unifying the sim_cpu structure easier.
2016-08-12 22:12:41 +08:00
if (sim_cpu_alloc_all (sd, 1) != SIM_RC_OK)
sim: d10v: convert to nrun A lot of cpu state is stored in global variables, as is memory handling. The sim_size support needs unwinding at some point. But at least this is an improvement on the status quo.
2015-03-30 14:05:33 +08:00
{
free_state (sd);
return 0;
}
if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
{
free_state (sd);
return 0;
}
sim: parse_args: display getopt error ourselves Fix a long standing todo where we let getopt write directly to stderr when an invalid option is passed. Use the sim io funcs instead as they go through the filtered callbacks that gdb wants.
2016-01-04 10:40:34 +08:00
/* The parser will print an error message for us, so we silently return. */
sim: d10v: convert to nrun A lot of cpu state is stored in global variables, as is memory handling. The sim_size support needs unwinding at some point. But at least this is an improvement on the status quo.
2015-03-30 14:05:33 +08:00
if (sim_parse_args (sd, argv) != SIM_RC_OK)
{
free_state (sd);
return 0;
}
/* Check for/establish the a reference program image. */
sim: split program path out of argv vector We use the program argv to both find the program to run (argv[0]) and to hold the arguments to the program. Most of the time this is fine, but if we want to let programs specify argv[0] independently (which is possible in standard *NIX programs), this double duty doesn't work. So let's split the path to the program to run out into a separate field by itself. This simplifies the various sim_open funcs too. By itself, this code is more of a logical cleanup than something that is super useful. But it will open up customization of argv[0] in a follow up commit. Split the changes to make it easier to review.
2021-11-15 15:32:06 +08:00
if (sim_analyze_program (sd, STATE_PROG_FILE (sd), abfd) != SIM_RC_OK)
sim: d10v: convert to nrun A lot of cpu state is stored in global variables, as is memory handling. The sim_size support needs unwinding at some point. But at least this is an improvement on the status quo.
2015-03-30 14:05:33 +08:00
{
free_state (sd);
return 0;
}
/* Configure/verify the target byte order and other runtime
configuration options. */
if (sim_config (sd) != SIM_RC_OK)
{
sim_module_uninstall (sd);
return 0;
}
if (sim_post_argv_init (sd) != SIM_RC_OK)
{
/* Uninstall the modules to avoid memory leaks,
file descriptor leaks, etc. */
sim_module_uninstall (sd);
return 0;
}
sim: arm/cr16/d10v/h8300/microblaze/sh: fill out sim-cpu pc fetch/store helpers This makes the common sim-cpu logic work.
2015-04-17 14:16:10 +08:00
/* CPU specific initialization. */
for (i = 0; i < MAX_NR_PROCESSORS; ++i)
{
SIM_CPU *cpu = STATE_CPU (sd, i);
sim: arm/d10v/h8300/m68hc11/microblaze/mips/mn10300/moxie/sh/v850: convert to common sim_{fetch,store}_register
2015-12-30 16:28:45 +08:00
CPU_REG_FETCH (cpu) = d10v_reg_fetch;
CPU_REG_STORE (cpu) = d10v_reg_store;
sim: arm/cr16/d10v/h8300/microblaze/sh: fill out sim-cpu pc fetch/store helpers This makes the common sim-cpu logic work.
2015-04-17 14:16:10 +08:00
CPU_PC_FETCH (cpu) = d10v_pc_get;
CPU_PC_STORE (cpu) = d10v_pc_set;
}
import gdb-1999-09-13 snapshot
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old_segment_mapping = 0;
Initial creation of sourceware repository
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import gdb-1999-11-16 snapshot
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/* NOTE: This argument parsing is only effective when this function
is called by GDB. Standalone argument parsing is handled by
sim/common/run.c. */
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for (p = argv + 1; *p; ++p)
{
import gdb-1999-09-13 snapshot
1999-09-14 05:40:00 +08:00
if (strcmp (*p, "-oldseg") == 0)
old_segment_mapping = 1;
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#ifdef DEBUG
import gdb-1999-09-13 snapshot
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else if (strcmp (*p, "-t") == 0)
Initial creation of sourceware repository
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d10v_debug = DEBUG;
import gdb-1999-11-16 snapshot
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else if (strncmp (*p, "-t", 2) == 0)
d10v_debug = atoi (*p + 2);
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#endif
}
/* put all the opcodes in the hash table */
if (!init_p++)
{
for (s = Simops; s->func; s++)
{
h = &hash_table[hash(s->opcode,s->format)];
/* go to the last entry in the chain */
while (h->next)
h = h->next;
if (h->ops)
{
h->next = (struct hash_entry *) calloc(1,sizeof(struct hash_entry));
if (!h->next)
perror ("malloc failure");
h = h->next;
}
h->ops = s;
h->mask = s->mask;
h->opcode = s->opcode;
h->size = s->is_long;
}
}
/* reset the processor state */
import gdb-1999-11-16 snapshot
1999-11-17 10:31:06 +08:00
if (!State.mem.data[0])
sim_size (1);
Initial creation of sourceware repository
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sim: d10v: convert to nrun A lot of cpu state is stored in global variables, as is memory handling. The sim_size support needs unwinding at some point. But at least this is an improvement on the status quo.
2015-03-30 14:05:33 +08:00
return sd;
Initial creation of sourceware repository
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}
sim: d10v: migrate to standard uintXX_t types This old port setup its own uintXX types, but since we require C11 now, we can assume the standard uintXX_t types exist and use them. Also migrate off the sim-specific unsignedXX types.
2021-12-06 01:24:12 +08:00
uint8_t *
dmem_addr (SIM_DESC sd, SIM_CPU *cpu, uint16_t offset)
Initial creation of sourceware repository
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{
import gdb-1999-11-16 snapshot
1999-11-17 10:31:06 +08:00
unsigned long phys;
sim: d10v: migrate to standard uintXX_t types This old port setup its own uintXX types, but since we require C11 now, we can assume the standard uintXX_t types exist and use them. Also migrate off the sim-specific unsignedXX types.
2021-12-06 01:24:12 +08:00
uint8_t *mem;
import gdb-1999-11-16 snapshot
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int phys_size;
Initial creation of sourceware repository
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import gdb-1999-11-16 snapshot
1999-11-17 10:31:06 +08:00
/* Note: DMEM address range is 0..0x10000. Calling code can compute
things like ``0xfffe + 0x0e60 == 0x10e5d''. Since offset's type
sim: d10v: migrate to standard uintXX_t types This old port setup its own uintXX types, but since we require C11 now, we can assume the standard uintXX_t types exist and use them. Also migrate off the sim-specific unsignedXX types.
2021-12-06 01:24:12 +08:00
is uint16_t this is modulo'ed onto 0x0e5d. */
Initial creation of sourceware repository
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sim: d10v: push down sd/cpu vars By itself, this commit doesn't really change anything. It lays the groundwork for using the cpu state in follow up commits, both for engine state and for cpu state. Splitting things up this way so it is easier to see how things have changed.
2015-11-15 18:57:42 +08:00
phys_size = sim_d10v_translate_dmap_addr (sd, cpu, offset, 1, &phys, NULL,
import gdb-1999-11-16 snapshot
1999-11-17 10:31:06 +08:00
dmap_register);
if (phys_size == 0)
sim: d10v: convert to common sim engine logic Now that we have access to the sim state everywhere, we can convert to the common engine logic for overall processing. This frees us up from tracking exception state ourselves.
2015-11-15 19:07:06 +08:00
sim_engine_halt (sd, cpu, NULL, PC, sim_stopped, SIM_SIGBUS);
mem = map_memory (sd, cpu, phys);
Initial creation of sourceware repository
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#ifdef DEBUG
import gdb-1999-11-16 snapshot
1999-11-17 10:31:06 +08:00
if ((d10v_debug & DEBUG_MEMORY))
{
sim: d10v: drop global callback state Now that we have access to the sim state in all the right places, use existing sim helpers in place of d10v_callback directly.
2015-11-15 19:41:26 +08:00
sim_io_printf
(sd,
sim: d10v: clean up pointer casts Use %p to print pointers instead of trying to cast them to longs.
2021-11-01 12:05:15 +08:00
"mem: 0x%08x (%s) -> 0x%08lx %d (%s) -> %p (%s)\n",
import gdb-1999-11-16 snapshot
1999-11-17 10:31:06 +08:00
offset, last_from,
phys, phys_size, last_to,
sim: d10v: clean up pointer casts Use %p to print pointers instead of trying to cast them to longs.
2021-11-01 12:05:15 +08:00
mem, last_segname);
Initial creation of sourceware repository
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}
import gdb-1999-11-16 snapshot
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#endif
return mem;
Initial creation of sourceware repository
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}
sim: d10v: migrate to standard uintXX_t types This old port setup its own uintXX types, but since we require C11 now, we can assume the standard uintXX_t types exist and use them. Also migrate off the sim-specific unsignedXX types.
2021-12-06 01:24:12 +08:00
uint8_t *
imem_addr (SIM_DESC sd, SIM_CPU *cpu, uint32_t offset)
Initial creation of sourceware repository
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{
import gdb-1999-11-16 snapshot
1999-11-17 10:31:06 +08:00
unsigned long phys;
sim: d10v: migrate to standard uintXX_t types This old port setup its own uintXX types, but since we require C11 now, we can assume the standard uintXX_t types exist and use them. Also migrate off the sim-specific unsignedXX types.
2021-12-06 01:24:12 +08:00
uint8_t *mem;
sim: d10v: push down sd/cpu vars By itself, this commit doesn't really change anything. It lays the groundwork for using the cpu state in follow up commits, both for engine state and for cpu state. Splitting things up this way so it is easier to see how things have changed.
2015-11-15 18:57:42 +08:00
int phys_size = sim_d10v_translate_imap_addr (sd, cpu, offset, 1, &phys, NULL,
Index: gdb/ChangeLog 2003-05-07 Andrew Cagney <cagney@redhat.com> * d10v-tdep.c (remote_d10v_translate_xfer_address): Add "regcache". (d10v_print_registers_info): Update. (d10v_dmap_register, d10v_imap_register): Delete functions. (struct gdbarch_tdep): Add "regcache" parameter to "dmap_register" and "imap_register". (d10v_ts2_dmap_register, d10v_ts2_imap_register): Add "regcache". (d10v_ts3_dmap_register, d10v_ts3_imap_register): Add "regcache". * arch-utils.c (generic_remote_translate_xfer_address): Add "regcache" and "gdbarch" parameters. * gdbarch.sh (REMOTE_TRANSLATE_XFER_ADDRESS): Add "regcache" parameter. Change class to multi-arch. * gdbarch.h, gdbarch.c: Re-generate. * remote.c (remote_xfer_memory): Use gdbarch_remote_translate_xfer_address. Index: include/gdb/ChangeLog 2003-05-07 Andrew Cagney <cagney@redhat.com> * sim-d10v.h (sim_d10v_translate_addr): Add regcache parameter. (sim_d10v_translate_imap_addr): Add regcache parameter. (sim_d10v_translate_dmap_addr): Ditto. Index: sim/d10v/ChangeLog 2003-05-07 Andrew Cagney <cagney@redhat.com> * interp.c (sim_d10v_translate_addr): Add "regcache" parameter. (sim_d10v_translate_imap_addr): Ditto. (sim_d10v_translate_dmap_addr): Ditto. (xfer_mem): Pass NULL regcache to sim_d10v_translate_addr. (dmem_addr): Pass NULL regcache to sim_d10v_translate_dmap_addr. (dmap_register, imap_register): Add "regcache" parameter. (imem_addr): Pass NULL regcache to sim_d10v_translate_imap_addr. (sim_fetch_register): Pass NULL regcache to imap_register and dmap_register.
2003-05-08 03:21:13 +08:00
imap_register);
import gdb-1999-11-16 snapshot
1999-11-17 10:31:06 +08:00
if (phys_size == 0)
sim: d10v: convert to common sim engine logic Now that we have access to the sim state everywhere, we can convert to the common engine logic for overall processing. This frees us up from tracking exception state ourselves.
2015-11-15 19:07:06 +08:00
sim_engine_halt (sd, cpu, NULL, PC, sim_stopped, SIM_SIGBUS);
sim: d10v: push down sd/cpu vars By itself, this commit doesn't really change anything. It lays the groundwork for using the cpu state in follow up commits, both for engine state and for cpu state. Splitting things up this way so it is easier to see how things have changed.
2015-11-15 18:57:42 +08:00
mem = map_memory (sd, cpu, phys);
import gdb-1999-11-16 snapshot
1999-11-17 10:31:06 +08:00
#ifdef DEBUG
if ((d10v_debug & DEBUG_MEMORY))
{
sim: d10v: drop global callback state Now that we have access to the sim state in all the right places, use existing sim helpers in place of d10v_callback directly.
2015-11-15 19:41:26 +08:00
sim_io_printf
(sd,
sim: d10v: clean up pointer casts Use %p to print pointers instead of trying to cast them to longs.
2021-11-01 12:05:15 +08:00
"mem: 0x%08x (%s) -> 0x%08lx %d (%s) -> %p (%s)\n",
import gdb-1999-11-16 snapshot
1999-11-17 10:31:06 +08:00
offset, last_from,
phys, phys_size, last_to,
sim: d10v: clean up pointer casts Use %p to print pointers instead of trying to cast them to longs.
2021-11-01 12:05:15 +08:00
mem, last_segname);
import gdb-1999-11-16 snapshot
1999-11-17 10:31:06 +08:00
}
#endif
return mem;
Initial creation of sourceware repository
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}
sim: d10v: convert to common sim engine logic Now that we have access to the sim state everywhere, we can convert to the common engine logic for overall processing. This frees us up from tracking exception state ourselves.
2015-11-15 19:07:06 +08:00
static void
step_once (SIM_DESC sd, SIM_CPU *cpu)
Initial creation of sourceware repository
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{
sim: d10v: migrate to standard uintXX_t types This old port setup its own uintXX types, but since we require C11 now, we can assume the standard uintXX_t types exist and use them. Also migrate off the sim-specific unsignedXX types.
2021-12-06 01:24:12 +08:00
uint32_t inst;
uint8_t *iaddr;
Initial creation of sourceware repository
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sim: d10v: convert to common sim engine logic Now that we have access to the sim state everywhere, we can convert to the common engine logic for overall processing. This frees us up from tracking exception state ourselves.
2015-11-15 19:07:06 +08:00
/* TODO: Unindent this block. */
Initial creation of sourceware repository
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{
sim: d10v: migrate to standard uintXX_t types This old port setup its own uintXX types, but since we require C11 now, we can assume the standard uintXX_t types exist and use them. Also migrate off the sim-specific unsignedXX types.
2021-12-06 01:24:12 +08:00
iaddr = imem_addr (sd, cpu, (uint32_t)PC << 2);
Initial creation of sourceware repository
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inst = get_longword( iaddr );
State.pc_changed = 0;
ins_type_counters[ (int)INS_CYCLES ]++;
switch (inst & 0xC0000000)
{
case 0xC0000000:
/* long instruction */
sim: d10v: push down sd/cpu vars By itself, this commit doesn't really change anything. It lays the groundwork for using the cpu state in follow up commits, both for engine state and for cpu state. Splitting things up this way so it is easier to see how things have changed.
2015-11-15 18:57:42 +08:00
do_long (sd, cpu, inst & 0x3FFFFFFF);
Initial creation of sourceware repository
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break;
case 0x80000000:
/* R -> L */
sim: d10v: push down sd/cpu vars By itself, this commit doesn't really change anything. It lays the groundwork for using the cpu state in follow up commits, both for engine state and for cpu state. Splitting things up this way so it is easier to see how things have changed.
2015-11-15 18:57:42 +08:00
do_2_short (sd, cpu, inst & 0x7FFF, (inst & 0x3FFF8000) >> 15, RIGHT_FIRST);
Initial creation of sourceware repository
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break;
case 0x40000000:
/* L -> R */
sim: d10v: push down sd/cpu vars By itself, this commit doesn't really change anything. It lays the groundwork for using the cpu state in follow up commits, both for engine state and for cpu state. Splitting things up this way so it is easier to see how things have changed.
2015-11-15 18:57:42 +08:00
do_2_short (sd, cpu, (inst & 0x3FFF8000) >> 15, inst & 0x7FFF, LEFT_FIRST);
Initial creation of sourceware repository
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break;
case 0:
sim: d10v: push down sd/cpu vars By itself, this commit doesn't really change anything. It lays the groundwork for using the cpu state in follow up commits, both for engine state and for cpu state. Splitting things up this way so it is easier to see how things have changed.
2015-11-15 18:57:42 +08:00
do_parallel (sd, cpu, (inst & 0x3FFF8000) >> 15, inst & 0x7FFF);
Initial creation of sourceware repository
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break;
}
/* If the PC of the current instruction matches RPT_E then
schedule a branch to the loop start. If one of those
instructions happens to be a branch, than that instruction
will be ignored */
if (!State.pc_changed)
{
if (PSW_RP && PC == RPT_E)
{
/* Note: The behavour of a branch instruction at RPT_E
is implementation dependant, this simulator takes the
branch. Branching to RPT_E is valid, the instruction
must be executed before the loop is taken. */
if (RPT_C == 1)
{
SET_PSW_RP (0);
SET_RPT_C (0);
SET_PC (PC + 1);
}
else
{
SET_RPT_C (RPT_C - 1);
SET_PC (RPT_S);
}
}
else
SET_PC (PC + 1);
}
/* Check for a breakpoint trap on this instruction. This
overrides any pending branches or loops */
if (PSW_DB && PC == IBA)
{
SET_BPC (PC);
SET_BPSW (PSW);
SET_PSW (PSW & PSW_SM_BIT);
SET_PC (SDBT_VECTOR_START);
}
/* Writeback all the DATA / PC changes */
SLOT_FLUSH ();
}
sim: d10v: convert to common sim engine logic Now that we have access to the sim state everywhere, we can convert to the common engine logic for overall processing. This frees us up from tracking exception state ourselves.
2015-11-15 19:07:06 +08:00
}
void
sim_engine_run (SIM_DESC sd,
int next_cpu_nr, /* ignore */
int nr_cpus, /* ignore */
int siggnal)
{
sim_cpu *cpu;
SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
cpu = STATE_CPU (sd, 0);
switch (siggnal)
{
case 0:
break;
case GDB_SIGNAL_BUS:
SET_BPC (PC);
SET_BPSW (PSW);
SET_HW_PSW ((PSW & (PSW_F0_BIT | PSW_F1_BIT | PSW_C_BIT)));
JMP (AE_VECTOR_START);
SLOT_FLUSH ();
break;
case GDB_SIGNAL_ILL:
SET_BPC (PC);
SET_BPSW (PSW);
SET_HW_PSW ((PSW & (PSW_F0_BIT | PSW_F1_BIT | PSW_C_BIT)));
JMP (RIE_VECTOR_START);
SLOT_FLUSH ();
break;
default:
/* just ignore it */
break;
}
while (1)
{
step_once (sd, cpu);
if (sim_events_tick (sd))
sim_events_process (sd);
}
Initial creation of sourceware repository
1999-04-16 09:35:26 +08:00
}
void
sim: d10v: clean up misc warnings
2015-03-30 13:38:59 +08:00
sim_info (SIM_DESC sd, int verbose)
Initial creation of sourceware repository
1999-04-16 09:35:26 +08:00
{
char buf1[40];
char buf2[40];
char buf3[40];
char buf4[40];
char buf5[40];
unsigned long left = ins_type_counters[ (int)INS_LEFT ] + ins_type_counters[ (int)INS_LEFT_COND_EXE ];
unsigned long left_nops = ins_type_counters[ (int)INS_LEFT_NOPS ];
unsigned long left_parallel = ins_type_counters[ (int)INS_LEFT_PARALLEL ];
unsigned long left_cond = ins_type_counters[ (int)INS_LEFT_COND_TEST ];
unsigned long left_total = left + left_parallel + left_cond + left_nops;
unsigned long right = ins_type_counters[ (int)INS_RIGHT ] + ins_type_counters[ (int)INS_RIGHT_COND_EXE ];
unsigned long right_nops = ins_type_counters[ (int)INS_RIGHT_NOPS ];
unsigned long right_parallel = ins_type_counters[ (int)INS_RIGHT_PARALLEL ];
unsigned long right_cond = ins_type_counters[ (int)INS_RIGHT_COND_TEST ];
unsigned long right_total = right + right_parallel + right_cond + right_nops;
unsigned long unknown = ins_type_counters[ (int)INS_UNKNOWN ];
unsigned long ins_long = ins_type_counters[ (int)INS_LONG ];
unsigned long parallel = ins_type_counters[ (int)INS_PARALLEL ];
unsigned long leftright = ins_type_counters[ (int)INS_LEFTRIGHT ];
unsigned long rightleft = ins_type_counters[ (int)INS_RIGHTLEFT ];
unsigned long cond_true = ins_type_counters[ (int)INS_COND_TRUE ];
unsigned long cond_false = ins_type_counters[ (int)INS_COND_FALSE ];
unsigned long cond_jump = ins_type_counters[ (int)INS_COND_JUMP ];
unsigned long cycles = ins_type_counters[ (int)INS_CYCLES ];
unsigned long total = (unknown + left_total + right_total + ins_long);
int size = strlen (add_commas (buf1, sizeof (buf1), total));
int parallel_size = strlen (add_commas (buf1, sizeof (buf1),
(left_parallel > right_parallel) ? left_parallel : right_parallel));
int cond_size = strlen (add_commas (buf1, sizeof (buf1), (left_cond > right_cond) ? left_cond : right_cond));
int nop_size = strlen (add_commas (buf1, sizeof (buf1), (left_nops > right_nops) ? left_nops : right_nops));
int normal_size = strlen (add_commas (buf1, sizeof (buf1), (left > right) ? left : right));
sim: d10v: drop global callback state Now that we have access to the sim state in all the right places, use existing sim helpers in place of d10v_callback directly.
2015-11-15 19:41:26 +08:00
sim_io_printf (sd,
"executed %*s left instruction(s), %*s normal, %*s parallel, %*s EXExxx, %*s nops\n",
size, add_commas (buf1, sizeof (buf1), left_total),
normal_size, add_commas (buf2, sizeof (buf2), left),
parallel_size, add_commas (buf3, sizeof (buf3), left_parallel),
cond_size, add_commas (buf4, sizeof (buf4), left_cond),
nop_size, add_commas (buf5, sizeof (buf5), left_nops));
sim_io_printf (sd,
"executed %*s right instruction(s), %*s normal, %*s parallel, %*s EXExxx, %*s nops\n",
size, add_commas (buf1, sizeof (buf1), right_total),
normal_size, add_commas (buf2, sizeof (buf2), right),
parallel_size, add_commas (buf3, sizeof (buf3), right_parallel),
cond_size, add_commas (buf4, sizeof (buf4), right_cond),
nop_size, add_commas (buf5, sizeof (buf5), right_nops));
Initial creation of sourceware repository
1999-04-16 09:35:26 +08:00
if (ins_long)
sim: d10v: drop global callback state Now that we have access to the sim state in all the right places, use existing sim helpers in place of d10v_callback directly.
2015-11-15 19:41:26 +08:00
sim_io_printf (sd,
"executed %*s long instruction(s)\n",
size, add_commas (buf1, sizeof (buf1), ins_long));
Initial creation of sourceware repository
1999-04-16 09:35:26 +08:00
if (parallel)
sim: d10v: drop global callback state Now that we have access to the sim state in all the right places, use existing sim helpers in place of d10v_callback directly.
2015-11-15 19:41:26 +08:00
sim_io_printf (sd,
"executed %*s parallel instruction(s)\n",
size, add_commas (buf1, sizeof (buf1), parallel));
Initial creation of sourceware repository
1999-04-16 09:35:26 +08:00
if (leftright)
sim: d10v: drop global callback state Now that we have access to the sim state in all the right places, use existing sim helpers in place of d10v_callback directly.
2015-11-15 19:41:26 +08:00
sim_io_printf (sd,
"executed %*s instruction(s) encoded L->R\n",
size, add_commas (buf1, sizeof (buf1), leftright));
Initial creation of sourceware repository
1999-04-16 09:35:26 +08:00
if (rightleft)
sim: d10v: drop global callback state Now that we have access to the sim state in all the right places, use existing sim helpers in place of d10v_callback directly.
2015-11-15 19:41:26 +08:00
sim_io_printf (sd,
"executed %*s instruction(s) encoded R->L\n",
size, add_commas (buf1, sizeof (buf1), rightleft));
Initial creation of sourceware repository
1999-04-16 09:35:26 +08:00
if (unknown)
sim: d10v: drop global callback state Now that we have access to the sim state in all the right places, use existing sim helpers in place of d10v_callback directly.
2015-11-15 19:41:26 +08:00
sim_io_printf (sd,
"executed %*s unknown instruction(s)\n",
size, add_commas (buf1, sizeof (buf1), unknown));
Initial creation of sourceware repository
1999-04-16 09:35:26 +08:00
if (cond_true)
sim: d10v: drop global callback state Now that we have access to the sim state in all the right places, use existing sim helpers in place of d10v_callback directly.
2015-11-15 19:41:26 +08:00
sim_io_printf (sd,
"executed %*s instruction(s) due to EXExxx condition being true\n",
size, add_commas (buf1, sizeof (buf1), cond_true));
Initial creation of sourceware repository
1999-04-16 09:35:26 +08:00
if (cond_false)
sim: d10v: drop global callback state Now that we have access to the sim state in all the right places, use existing sim helpers in place of d10v_callback directly.
2015-11-15 19:41:26 +08:00
sim_io_printf (sd,
"skipped %*s instruction(s) due to EXExxx condition being false\n",
size, add_commas (buf1, sizeof (buf1), cond_false));
Initial creation of sourceware repository
1999-04-16 09:35:26 +08:00
if (cond_jump)
sim: d10v: drop global callback state Now that we have access to the sim state in all the right places, use existing sim helpers in place of d10v_callback directly.
2015-11-15 19:41:26 +08:00
sim_io_printf (sd,
"skipped %*s instruction(s) due to conditional branch succeeding\n",
size, add_commas (buf1, sizeof (buf1), cond_jump));
Initial creation of sourceware repository
1999-04-16 09:35:26 +08:00
sim: d10v: drop global callback state Now that we have access to the sim state in all the right places, use existing sim helpers in place of d10v_callback directly.
2015-11-15 19:41:26 +08:00
sim_io_printf (sd,
"executed %*s cycle(s)\n",
size, add_commas (buf1, sizeof (buf1), cycles));
Initial creation of sourceware repository
1999-04-16 09:35:26 +08:00
sim: d10v: drop global callback state Now that we have access to the sim state in all the right places, use existing sim helpers in place of d10v_callback directly.
2015-11-15 19:41:26 +08:00
sim_io_printf (sd,
"executed %*s total instructions\n",
size, add_commas (buf1, sizeof (buf1), total));
Initial creation of sourceware repository
1999-04-16 09:35:26 +08:00
}
SIM_RC
sim: sim_{create_inferior,open,parse_args}: constify argv/env slightly 2016-01-03 Mike Frysinger <vapier@gentoo.org> * sim-options.c (sim_parse_args): Mark argv array const. * sim-options.h (sim_parse_args): Likewise.
2016-01-03 14:51:44 +08:00
sim_create_inferior (SIM_DESC sd, struct bfd *abfd,
char * const *argv, char * const *env)
Initial creation of sourceware repository
1999-04-16 09:35:26 +08:00
{
bfd_vma start_address;
Fix build failure in d10v sim While building all targets on Ubuntu 20.04/aarch64, I ran into the following build error: In file included from /usr/include/string.h:495, from ../../bfd/bfd.h:48, from ../../../../repos/binutils-gdb/sim/d10v/interp.c:4: In function memset, inlined from sim_create_inferior at ../../../../repos/binutils-gdb/sim/d10v/interp.c:1146:3: /usr/include/aarch64-linux-gnu/bits/string_fortified.h:71:10: error: __builtin_memset offset [33, 616] from the object at State is out of the bounds of referenced subobject regs with type reg_t[16] {aka short unsigned int[16]} at offset 0 [-Werror=array-bounds] 71 | return __builtin___memset_chk (__dest, __ch, __len, __bos0 (__dest)); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ cc1: all warnings being treated as errors make[3]: *** [Makefile:558: interp.o] Error 1 The following patch fixes this. sim/ChangeLog: 2021-05-12 Luis Machado <luis.machado@linaro.org> * d10v/interp.c (sim_create_inferior): Fix memset call.
2021-05-11 03:06:50 +08:00
/* Make sure we have the right structure for the following memset. */
sim/d10v: Use offsetof in a static assertion about structure layout. clang 11 fails to compile the static assertion as it cannot compute the pointer value at a compile time: gdb/sim/d10v/interp.c:1149:37: error: static_assert expression is not an integral constant expression static_assert ((uintptr_t) &State == (uintptr_t) &State.regs, ~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~ 1 error generated. Instead, assert that the offset of State.regs is 0. sim/d10v/ChangeLog: * interp.c (sim_create_inferior): Use offsetof in static assertion.
2021-05-22 08:26:24 +08:00
static_assert (offsetof (struct _state, regs) == 0,
"State.regs is not at offset 0");
Fix build failure in d10v sim While building all targets on Ubuntu 20.04/aarch64, I ran into the following build error: In file included from /usr/include/string.h:495, from ../../bfd/bfd.h:48, from ../../../../repos/binutils-gdb/sim/d10v/interp.c:4: In function memset, inlined from sim_create_inferior at ../../../../repos/binutils-gdb/sim/d10v/interp.c:1146:3: /usr/include/aarch64-linux-gnu/bits/string_fortified.h:71:10: error: __builtin_memset offset [33, 616] from the object at State is out of the bounds of referenced subobject regs with type reg_t[16] {aka short unsigned int[16]} at offset 0 [-Werror=array-bounds] 71 | return __builtin___memset_chk (__dest, __ch, __len, __bos0 (__dest)); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ cc1: all warnings being treated as errors make[3]: *** [Makefile:558: interp.o] Error 1 The following patch fixes this. sim/ChangeLog: 2021-05-12 Luis Machado <luis.machado@linaro.org> * d10v/interp.c (sim_create_inferior): Fix memset call.
2021-05-11 03:06:50 +08:00
/* Reset state from the regs field until the mem field. */
memset (&State, 0, (uintptr_t) &State.mem - (uintptr_t) &State.regs);
Initial creation of sourceware repository
1999-04-16 09:35:26 +08:00
2002-05-28 Elena Zannoni <ezannoni@redhat.com> * interp.c (sim_create_inferior): Add comment. From Alan Matsuoka <alanm@redhat.com>: From 2001-04-27 Jason Eckhardt <jle@cygnus.com>: * simops.c (OP_4400): Output "mvf0f" instead of "mf0f". (OP_4401): Output "mvf0t" instead of "mf0t". (OP_460B): Do not output a flag register. (OP_4609): Do not output a flag register.
2002-05-28 23:49:52 +08:00
/* There was a hack here to copy the values of argc and argv into r0
and r1. The values were also saved into some high memory that
won't be overwritten by the stack (0x7C00). The reason for doing
this was to allow the 'run' program to accept arguments. Without
the hack, this is not possible anymore. If the simulator is run
from the debugger, arguments cannot be passed in, so this makes
no difference. */
Initial creation of sourceware repository
1999-04-16 09:35:26 +08:00
/* set PC */
if (abfd != NULL)
start_address = bfd_get_start_address (abfd);
else
start_address = 0xffc0 << 2;
#ifdef DEBUG
if (d10v_debug)
Don't use BFD_VMA_FMT in gdb and sim Like commit b82817674f, this replaces BFD_VMA_FMT "x" in sim/ with PRIx64 and casts to promote bfd_vma to uint64_t. The one file using BFD_VMA_FMT in gdb/ instead now uses hex_string, and a typo in the warning message is fixed.
2022-08-04 11:18:05 +08:00
sim_io_printf (sd, "sim_create_inferior: PC=0x%" PRIx64 "\n",
(uint64_t) start_address);
Initial creation of sourceware repository
1999-04-16 09:35:26 +08:00
#endif
sim: d10v: push down sd/cpu vars By itself, this commit doesn't really change anything. It lays the groundwork for using the cpu state in follow up commits, both for engine state and for cpu state. Splitting things up this way so it is easier to see how things have changed.
2015-11-15 18:57:42 +08:00
{
SIM_CPU *cpu = STATE_CPU (sd, 0);
SET_CREG (PC_CR, start_address >> 2);
}
Initial creation of sourceware repository
1999-04-16 09:35:26 +08:00
import gdb-1999-11-16 snapshot
1999-11-17 10:31:06 +08:00
/* cpu resets imap0 to 0 and imap1 to 0x7f, but D10V-EVA board
initializes imap0 and imap1 to 0x1000 as part of its ROM
initialization. */
import gdb-1999-09-13 snapshot
1999-09-14 05:40:00 +08:00
if (old_segment_mapping)
Initial creation of sourceware repository
1999-04-16 09:35:26 +08:00
{
import gdb-1999-11-16 snapshot
1999-11-17 10:31:06 +08:00
/* External memory startup. This is the HARD reset state. */
sim: d10v: push down sd/cpu vars By itself, this commit doesn't really change anything. It lays the groundwork for using the cpu state in follow up commits, both for engine state and for cpu state. Splitting things up this way so it is easier to see how things have changed.
2015-11-15 18:57:42 +08:00
set_imap_register (sd, 0, 0x0000);
set_imap_register (sd, 1, 0x007f);
set_dmap_register (sd, 0, 0x2000);
set_dmap_register (sd, 1, 0x2000);
set_dmap_register (sd, 2, 0x0000); /* Old DMAP */
set_dmap_register (sd, 3, 0x0000);
Initial creation of sourceware repository
1999-04-16 09:35:26 +08:00
}
else
{
import gdb-1999-11-16 snapshot
1999-11-17 10:31:06 +08:00
/* Internal memory startup. This is the ROM intialized state. */
sim: d10v: push down sd/cpu vars By itself, this commit doesn't really change anything. It lays the groundwork for using the cpu state in follow up commits, both for engine state and for cpu state. Splitting things up this way so it is easier to see how things have changed.
2015-11-15 18:57:42 +08:00
set_imap_register (sd, 0, 0x1000);
set_imap_register (sd, 1, 0x1000);
set_dmap_register (sd, 0, 0x2000);
set_dmap_register (sd, 1, 0x2000);
set_dmap_register (sd, 2, 0x2000); /* DMAP2 initial internal value is
0x2000 on the new board. */
set_dmap_register (sd, 3, 0x0000);
Initial creation of sourceware repository
1999-04-16 09:35:26 +08:00
}
SLOT_FLUSH ();
return SIM_RC_OK;
}
sim: arm/d10v/h8300/m68hc11/microblaze/mips/mn10300/moxie/sh/v850: convert to common sim_{fetch,store}_register
2015-12-30 16:28:45 +08:00
static int
sim: common: change sim_{fetch,store}_register helpers to use void* buffers When reading/writing arbitrary data to the system's memory, the unsigned char pointer type doesn't make that much sense. Switch it to void so we align a bit with standard C library read/write functions, and to avoid having to sprinkle casts everywhere.
2022-10-31 23:58:10 +08:00
d10v_reg_fetch (SIM_CPU *cpu, int rn, void *memory, int length)
Initial creation of sourceware repository
1999-04-16 09:35:26 +08:00
{
sim: arm/d10v/h8300/m68hc11/microblaze/mips/mn10300/moxie/sh/v850: convert to common sim_{fetch,store}_register
2015-12-30 16:28:45 +08:00
SIM_DESC sd = CPU_STATE (cpu);
import gdb-1999-11-16 snapshot
1999-11-17 10:31:06 +08:00
int size;
Fix name of enum used in cast (sim_fetch_register, sim_store_register).
2002-06-09 06:19:56 +08:00
switch ((enum sim_d10v_regs) rn)
import gdb-1999-11-16 snapshot
1999-11-17 10:31:06 +08:00
{
Fill-out d10v enum so that there are no ``=''.
2002-06-02 02:15:43 +08:00
case SIM_D10V_R0_REGNUM:
case SIM_D10V_R1_REGNUM:
case SIM_D10V_R2_REGNUM:
case SIM_D10V_R3_REGNUM:
case SIM_D10V_R4_REGNUM:
case SIM_D10V_R5_REGNUM:
case SIM_D10V_R6_REGNUM:
case SIM_D10V_R7_REGNUM:
case SIM_D10V_R8_REGNUM:
case SIM_D10V_R9_REGNUM:
case SIM_D10V_R10_REGNUM:
case SIM_D10V_R11_REGNUM:
case SIM_D10V_R12_REGNUM:
case SIM_D10V_R13_REGNUM:
case SIM_D10V_R14_REGNUM:
case SIM_D10V_R15_REGNUM:
import gdb-1999-11-16 snapshot
1999-11-17 10:31:06 +08:00
WRITE_16 (memory, GPR (rn - SIM_D10V_R0_REGNUM));
size = 2;
Fill-out d10v enum so that there are no ``=''.
2002-06-02 02:15:43 +08:00
break;
case SIM_D10V_CR0_REGNUM:
case SIM_D10V_CR1_REGNUM:
case SIM_D10V_CR2_REGNUM:
case SIM_D10V_CR3_REGNUM:
case SIM_D10V_CR4_REGNUM:
case SIM_D10V_CR5_REGNUM:
case SIM_D10V_CR6_REGNUM:
case SIM_D10V_CR7_REGNUM:
case SIM_D10V_CR8_REGNUM:
case SIM_D10V_CR9_REGNUM:
case SIM_D10V_CR10_REGNUM:
case SIM_D10V_CR11_REGNUM:
case SIM_D10V_CR12_REGNUM:
case SIM_D10V_CR13_REGNUM:
case SIM_D10V_CR14_REGNUM:
case SIM_D10V_CR15_REGNUM:
import gdb-1999-11-16 snapshot
1999-11-17 10:31:06 +08:00
WRITE_16 (memory, CREG (rn - SIM_D10V_CR0_REGNUM));
size = 2;
Fill-out d10v enum so that there are no ``=''.
2002-06-02 02:15:43 +08:00
break;
case SIM_D10V_A0_REGNUM:
case SIM_D10V_A1_REGNUM:
import gdb-1999-11-16 snapshot
1999-11-17 10:31:06 +08:00
WRITE_64 (memory, ACC (rn - SIM_D10V_A0_REGNUM));
size = 8;
Fill-out d10v enum so that there are no ``=''.
2002-06-02 02:15:43 +08:00
break;
case SIM_D10V_SPI_REGNUM:
import gdb-1999-11-16 snapshot
1999-11-17 10:31:06 +08:00
/* PSW_SM indicates that the current SP is the USER
stack-pointer. */
WRITE_16 (memory, spi_register ());
size = 2;
Fill-out d10v enum so that there are no ``=''.
2002-06-02 02:15:43 +08:00
break;
case SIM_D10V_SPU_REGNUM:
import gdb-1999-11-16 snapshot
1999-11-17 10:31:06 +08:00
/* PSW_SM indicates that the current SP is the USER
stack-pointer. */
WRITE_16 (memory, spu_register ());
size = 2;
Fill-out d10v enum so that there are no ``=''.
2002-06-02 02:15:43 +08:00
break;
case SIM_D10V_IMAP0_REGNUM:
case SIM_D10V_IMAP1_REGNUM:
sim: d10v: push down sd/cpu vars By itself, this commit doesn't really change anything. It lays the groundwork for using the cpu state in follow up commits, both for engine state and for cpu state. Splitting things up this way so it is easier to see how things have changed.
2015-11-15 18:57:42 +08:00
WRITE_16 (memory, imap_register (sd, cpu, NULL, rn - SIM_D10V_IMAP0_REGNUM));
import gdb-1999-11-16 snapshot
1999-11-17 10:31:06 +08:00
size = 2;
Fill-out d10v enum so that there are no ``=''.
2002-06-02 02:15:43 +08:00
break;
case SIM_D10V_DMAP0_REGNUM:
case SIM_D10V_DMAP1_REGNUM:
case SIM_D10V_DMAP2_REGNUM:
case SIM_D10V_DMAP3_REGNUM:
sim: d10v: push down sd/cpu vars By itself, this commit doesn't really change anything. It lays the groundwork for using the cpu state in follow up commits, both for engine state and for cpu state. Splitting things up this way so it is easier to see how things have changed.
2015-11-15 18:57:42 +08:00
WRITE_16 (memory, dmap_register (sd, cpu, NULL, rn - SIM_D10V_DMAP0_REGNUM));
import gdb-1999-11-16 snapshot
1999-11-17 10:31:06 +08:00
size = 2;
Fill-out d10v enum so that there are no ``=''.
2002-06-02 02:15:43 +08:00
break;
case SIM_D10V_TS2_DMAP_REGNUM:
size = 0;
break;
default:
size = 0;
break;
import gdb-1999-11-16 snapshot
1999-11-17 10:31:06 +08:00
}
return size;
Initial creation of sourceware repository
1999-04-16 09:35:26 +08:00
}
sim: arm/d10v/h8300/m68hc11/microblaze/mips/mn10300/moxie/sh/v850: convert to common sim_{fetch,store}_register
2015-12-30 16:28:45 +08:00
static int
sim: common: change sim_{fetch,store}_register helpers to use void* buffers When reading/writing arbitrary data to the system's memory, the unsigned char pointer type doesn't make that much sense. Switch it to void so we align a bit with standard C library read/write functions, and to avoid having to sprinkle casts everywhere.
2022-10-31 23:58:10 +08:00
d10v_reg_store (SIM_CPU *cpu, int rn, const void *memory, int length)
Initial creation of sourceware repository
1999-04-16 09:35:26 +08:00
{
sim: arm/d10v/h8300/m68hc11/microblaze/mips/mn10300/moxie/sh/v850: convert to common sim_{fetch,store}_register
2015-12-30 16:28:45 +08:00
SIM_DESC sd = CPU_STATE (cpu);
import gdb-1999-11-16 snapshot
1999-11-17 10:31:06 +08:00
int size;
Fix name of enum used in cast (sim_fetch_register, sim_store_register).
2002-06-09 06:19:56 +08:00
switch ((enum sim_d10v_regs) rn)
import gdb-1999-11-16 snapshot
1999-11-17 10:31:06 +08:00
{
Fill-out d10v enum so that there are no ``=''.
2002-06-02 02:15:43 +08:00
case SIM_D10V_R0_REGNUM:
case SIM_D10V_R1_REGNUM:
case SIM_D10V_R2_REGNUM:
case SIM_D10V_R3_REGNUM:
case SIM_D10V_R4_REGNUM:
case SIM_D10V_R5_REGNUM:
case SIM_D10V_R6_REGNUM:
case SIM_D10V_R7_REGNUM:
case SIM_D10V_R8_REGNUM:
case SIM_D10V_R9_REGNUM:
case SIM_D10V_R10_REGNUM:
case SIM_D10V_R11_REGNUM:
case SIM_D10V_R12_REGNUM:
case SIM_D10V_R13_REGNUM:
case SIM_D10V_R14_REGNUM:
case SIM_D10V_R15_REGNUM:
import gdb-1999-11-16 snapshot
1999-11-17 10:31:06 +08:00
SET_GPR (rn - SIM_D10V_R0_REGNUM, READ_16 (memory));
size = 2;
Fill-out d10v enum so that there are no ``=''.
2002-06-02 02:15:43 +08:00
break;
case SIM_D10V_CR0_REGNUM:
case SIM_D10V_CR1_REGNUM:
case SIM_D10V_CR2_REGNUM:
case SIM_D10V_CR3_REGNUM:
case SIM_D10V_CR4_REGNUM:
case SIM_D10V_CR5_REGNUM:
case SIM_D10V_CR6_REGNUM:
case SIM_D10V_CR7_REGNUM:
case SIM_D10V_CR8_REGNUM:
case SIM_D10V_CR9_REGNUM:
case SIM_D10V_CR10_REGNUM:
case SIM_D10V_CR11_REGNUM:
case SIM_D10V_CR12_REGNUM:
case SIM_D10V_CR13_REGNUM:
case SIM_D10V_CR14_REGNUM:
case SIM_D10V_CR15_REGNUM:
import gdb-1999-11-16 snapshot
1999-11-17 10:31:06 +08:00
SET_CREG (rn - SIM_D10V_CR0_REGNUM, READ_16 (memory));
size = 2;
Fill-out d10v enum so that there are no ``=''.
2002-06-02 02:15:43 +08:00
break;
case SIM_D10V_A0_REGNUM:
case SIM_D10V_A1_REGNUM:
import gdb-1999-11-16 snapshot
1999-11-17 10:31:06 +08:00
SET_ACC (rn - SIM_D10V_A0_REGNUM, READ_64 (memory) & MASK40);
size = 8;
Fill-out d10v enum so that there are no ``=''.
2002-06-02 02:15:43 +08:00
break;
case SIM_D10V_SPI_REGNUM:
import gdb-1999-11-16 snapshot
1999-11-17 10:31:06 +08:00
/* PSW_SM indicates that the current SP is the USER
stack-pointer. */
set_spi_register (READ_16 (memory));
size = 2;
Fill-out d10v enum so that there are no ``=''.
2002-06-02 02:15:43 +08:00
break;
case SIM_D10V_SPU_REGNUM:
import gdb-1999-11-16 snapshot
1999-11-17 10:31:06 +08:00
set_spu_register (READ_16 (memory));
size = 2;
Fill-out d10v enum so that there are no ``=''.
2002-06-02 02:15:43 +08:00
break;
case SIM_D10V_IMAP0_REGNUM:
case SIM_D10V_IMAP1_REGNUM:
sim: d10v: push down sd/cpu vars By itself, this commit doesn't really change anything. It lays the groundwork for using the cpu state in follow up commits, both for engine state and for cpu state. Splitting things up this way so it is easier to see how things have changed.
2015-11-15 18:57:42 +08:00
set_imap_register (sd, rn - SIM_D10V_IMAP0_REGNUM, READ_16(memory));
import gdb-1999-11-16 snapshot
1999-11-17 10:31:06 +08:00
size = 2;
Fill-out d10v enum so that there are no ``=''.
2002-06-02 02:15:43 +08:00
break;
case SIM_D10V_DMAP0_REGNUM:
case SIM_D10V_DMAP1_REGNUM:
case SIM_D10V_DMAP2_REGNUM:
case SIM_D10V_DMAP3_REGNUM:
sim: d10v: push down sd/cpu vars By itself, this commit doesn't really change anything. It lays the groundwork for using the cpu state in follow up commits, both for engine state and for cpu state. Splitting things up this way so it is easier to see how things have changed.
2015-11-15 18:57:42 +08:00
set_dmap_register (sd, rn - SIM_D10V_DMAP0_REGNUM, READ_16(memory));
import gdb-1999-11-16 snapshot
1999-11-17 10:31:06 +08:00
size = 2;
Fill-out d10v enum so that there are no ``=''.
2002-06-02 02:15:43 +08:00
break;
case SIM_D10V_TS2_DMAP_REGNUM:
size = 0;
break;
default:
size = 0;
break;
import gdb-1999-11-16 snapshot
1999-11-17 10:31:06 +08:00
}
Initial creation of sourceware repository
1999-04-16 09:35:26 +08:00
SLOT_FLUSH ();
import gdb-1999-11-16 snapshot
1999-11-17 10:31:06 +08:00
return size;
Initial creation of sourceware repository
1999-04-16 09:35:26 +08:00
}
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