2010-10-26 02:09:10 +08:00
|
|
|
|
2010-10-25 Chao-ying Fu <fu@mips.com>
|
|
|
|
|
|
|
|
|
|
|
|
* mips-opc.c (madd, maddu, msub, msubu, mult, multu): Change D33 to D32.
|
|
|
|
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|
|
2010-10-25 23:33:54 +08:00
|
|
|
|
2010-10-25 Nathan Sidwell <nathan@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* tic6x-dis.c: Add attribution.
|
|
|
|
|
|
|
2010-10-22 07:50:57 +08:00
|
|
|
|
2010-10-22 Alan Modra <amodra@gmail.com>
|
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|
|
|
|
|
|
|
|
|
* Makefile.am (CLEANFILES): Add stamp-lm32. Sort.
|
|
|
|
|
|
* Makefile.in: Regenerate.
|
|
|
|
|
|
|
2010-10-18 08:15:35 +08:00
|
|
|
|
2010-10-18 Maciej W. Rozycki <macro@linux-mips.org>
|
|
|
|
|
|
|
|
|
|
|
|
* mips-opc.c (mips_builtin_opcodes): Move M_LD_OB and M_SD_OB
|
|
|
|
|
|
macros before their corresponding MIPS III hardware instructions.
|
|
|
|
|
|
|
2010-10-17 05:53:16 +08:00
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|
|
|
2010-10-16 H.J. Lu <hongjiu.lu@intel.com>
|
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|
|
|
|
|
|
|
|
|
|
* i386-gen.c (cpu_flag_init): Add CpuNop to CPU_GENERIC64_FLAGS.
|
|
|
|
|
|
|
|
|
|
|
|
* i386-init.h: Regenerated.
|
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|
|
2010-10-16 04:44:46 +08:00
|
|
|
|
2010-10-15 Mike Frysinger <vapier@gentoo.org>
|
|
|
|
|
|
|
|
|
|
|
|
* bfin-dis.c (decode_dsp32alu_0): Call imm5d() for BYTEOP2M.
|
|
|
|
|
|
|
2010-10-15 07:16:19 +08:00
|
|
|
|
2010-10-14 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl: Remove CheckRegSize from movq.
|
|
|
|
|
|
* i386-tbl.h: Regenerated.
|
|
|
|
|
|
|
2010-10-15 05:37:30 +08:00
|
|
|
|
2010-10-14 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl: Remove CheckRegSize from instructions with
|
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|
|
|
|
0, 1 or fixed operands.
|
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|
|
|
|
* i386-tbl.h: Regenerated.
|
|
|
|
|
|
|
2010-10-15 02:45:10 +08:00
|
|
|
|
2010-10-14 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-gen.c (opcode_modifiers): Add CheckRegSize.
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.h (CheckRegSize): New.
|
|
|
|
|
|
(i386_opcode_modifier): Add checkregsize.
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl: Add CheckRegSize to instructions which
|
|
|
|
|
|
require register size check.
|
|
|
|
|
|
* i386-tbl.h: Regenerated.
|
|
|
|
|
|
|
2010-10-12 06:18:42 +08:00
|
|
|
|
2010-10-12 Andreas Schwab <schwab@linux-m68k.org>
|
|
|
|
|
|
|
|
|
|
|
|
* m68k-opc.c (m68k_opcodes): Move fnop before fbf.
|
|
|
|
|
|
|
2010-10-11 19:56:53 +08:00
|
|
|
|
2010-10-11 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* s390-opc.c: Make the instruction masks for the load/store on
|
|
|
|
|
|
condition instructions to cover the condition code mask as well.
|
|
|
|
|
|
* s390-opc.txt: lgoc -> locg and stgoc -> stocg.
|
|
|
|
|
|
|
2010-10-11 14:10:35 +08:00
|
|
|
|
2010-10-11 Jan Kratochvil <jan.kratochvil@redhat.com>
|
|
|
|
|
|
Jiang Jilin <freephp@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* Makefile.am (libopcodes_a_SOURCES): New as empty.
|
|
|
|
|
|
* Makefile.in: Regenerate.
|
|
|
|
|
|
|
2010-10-09 14:50:23 +08:00
|
|
|
|
2010-10-09 Matt Rice <ratmice@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* fr30-desc.h: Regenerate.
|
|
|
|
|
|
* frv-desc.h: Regenerate.
|
|
|
|
|
|
* ip2k-desc.h: Regenerate.
|
|
|
|
|
|
* iq2000-desc.h: Regenerate.
|
|
|
|
|
|
* lm32-desc.h: Regenerate.
|
|
|
|
|
|
* m32c-desc.h: Regenerate.
|
|
|
|
|
|
* m32r-desc.h: Regenerate.
|
|
|
|
|
|
* mep-desc.h: Regenerate.
|
|
|
|
|
|
* mep-opc.c: Regenerate.
|
|
|
|
|
|
* mt-desc.h: Regenerate.
|
|
|
|
|
|
* openrisc-desc.h: Regenerate.
|
|
|
|
|
|
* xc16x-desc.h: Regenerate.
|
|
|
|
|
|
* xstormy16-desc.h: Regenerate.
|
|
|
|
|
|
|
2010-10-08 22:00:50 +08:00
|
|
|
|
2010-10-08 Pierre Muller <muller@ics.u-strasbg.fr>
|
|
|
|
|
|
|
|
|
|
|
|
Fix build with -DDEBUG=7
|
|
|
|
|
|
* frv-opc.c: Regenerate.
|
|
|
|
|
|
* or32-dis.c (DEBUG): Don't redefine.
|
|
|
|
|
|
(find_bytes_big, or32_extract, or32_opcode_match, or32_print_register):
|
|
|
|
|
|
Adapt DEBUG code to some type changes throughout.
|
|
|
|
|
|
* or32-opc.c (or32_extract): Likewise.
|
|
|
|
|
|
|
2010-10-07 19:28:49 +08:00
|
|
|
|
2010-10-07 Bernd Schmidt <bernds@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* tic6x-dis.c (print_insn_tic6x): Correct decoding of fstg field
|
|
|
|
|
|
in SPKERNEL instructions.
|
|
|
|
|
|
|
2010-10-02 15:04:07 +08:00
|
|
|
|
2010-10-02 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR binutils/12076
|
|
|
|
|
|
* i386-dis.c (RMAL): Remove duplicate.
|
|
|
|
|
|
|
2010-10-01 00:02:35 +08:00
|
|
|
|
2010-09-30 Pierre Muller <muller@ics.u-strasbg.fr>
|
|
|
|
|
|
|
|
|
|
|
|
* s390-mkopc.c (main): Exit with error 1 if sscanf fails
|
|
|
|
|
|
to parse all 6 parameters.
|
|
|
|
|
|
|
2010-09-30 19:32:15 +08:00
|
|
|
|
2010-09-28 Pierre Muller <muller@ics.u-strasbg.fr>
|
|
|
|
|
|
|
|
|
|
|
|
* s390-mkopc.c (main): Change description array size to 80.
|
|
|
|
|
|
Add maximum length of 79 to description parsing.
|
|
|
|
|
|
|
2010-09-28 04:23:01 +08:00
|
|
|
|
2010-09-27 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
|
|
|
|
|
|
|
|
|
|
|
|
* configure: Regenerate.
|
|
|
|
|
|
|
2010-09-27 21:36:48 +08:00
|
|
|
|
2010-09-27 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* s390-mkopc.c (enum s390_opcde_cpu_val): Add S390_OPCODE_Z196.
|
|
|
|
|
|
(main): Recognize the new CPU string.
|
|
|
|
|
|
* s390-opc.c: Add new instruction formats and masks.
|
|
|
|
|
|
* s390-opc.txt: Add new z196 instructions.
|
|
|
|
|
|
|
2010-09-27 21:33:00 +08:00
|
|
|
|
2010-09-27 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* s390-dis.c (print_insn_s390): Pick instruction with most
|
|
|
|
|
|
specific mask.
|
|
|
|
|
|
* s390-opc.c: Add unused bits to the insn mask.
|
|
|
|
|
|
* s390-opc.txt: Reorder some instructions to prefer more recent
|
|
|
|
|
|
versions.
|
|
|
|
|
|
|
2010-09-27 17:47:05 +08:00
|
|
|
|
2010-09-27 Tejas Belagod <tejas.belagod@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm_dis.c (print_insn_coprocessor): Apply off-by-alignment
|
|
|
|
|
|
correction to unaligned PCs while printing comment.
|
|
|
|
|
|
|
2010-09-23 23:52:19 +08:00
|
|
|
|
2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c (arm_opcodes): Add Virtualiztion Extensions support.
|
|
|
|
|
|
(thumb32_opcodes): Likewise.
|
|
|
|
|
|
(banked_regname): New function.
|
|
|
|
|
|
(print_insn_arm): Add Virtualization Extensions support.
|
|
|
|
|
|
(print_insn_thumb32): Likewise.
|
|
|
|
|
|
|
2010-09-23 23:37:45 +08:00
|
|
|
|
2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c (arm_opcodes): Support disassembly of UDIV and SDIV in
|
|
|
|
|
|
ARM state.
|
|
|
|
|
|
|
2010-09-23 23:26:24 +08:00
|
|
|
|
2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c (arm_opcodes): SMC implies Security Extensions.
|
|
|
|
|
|
(thumb32_opcodes): Likewise.
|
|
|
|
|
|
|
2010-09-23 23:18:19 +08:00
|
|
|
|
2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c (arm_opcodes): Add support for pldw.
|
|
|
|
|
|
(thumb32_opcodes): Likewise.
|
|
|
|
|
|
|
2010-09-23 05:55:17 +08:00
|
|
|
|
2010-09-22 Robin Getz <robin.getz@analog.com>
|
|
|
|
|
|
|
|
|
|
|
|
* bfin-dis.c (fmtconst): Cast address to 32bits.
|
|
|
|
|
|
|
2010-09-23 05:54:33 +08:00
|
|
|
|
2010-09-22 Mike Frysinger <vapier@gentoo.org>
|
|
|
|
|
|
|
|
|
|
|
|
* bfin-dis.c (decode_REGMV_0): Rewrite valid combo checks.
|
|
|
|
|
|
|
2010-09-23 05:53:46 +08:00
|
|
|
|
2010-09-22 Robin Getz <robin.getz@analog.com>
|
|
|
|
|
|
|
|
|
|
|
|
* bfin-dis.c (decode_ProgCtrl_0): Check for parallel insns.
|
|
|
|
|
|
Reject P6/P7 to TESTSET.
|
|
|
|
|
|
(decode_PushPopReg_0): Check for parallel insns. Reject pushing
|
|
|
|
|
|
SP onto the stack.
|
|
|
|
|
|
(decode_PushPopMultiple_0): Check for parallel insns. Make sure
|
|
|
|
|
|
P/D fields match all the time.
|
|
|
|
|
|
(decode_CCflag_0): Check for parallel insns. Verify x/y fields
|
|
|
|
|
|
are 0 for accumulator compares.
|
|
|
|
|
|
(decode_CC2stat_0): Check for parallel insns. Reject CC<op>CC.
|
|
|
|
|
|
(decode_CaCTRL_0, decode_ccMV_0, decode_CC2dreg_0, decode_BRCC_0,
|
|
|
|
|
|
decode_UJUMP_0, decode_LOGI2op_0, decode_COMPI2opD_0,
|
|
|
|
|
|
decode_COMPI2opP_0, decode_LoopSetup_0, decode_LDIMMhalf_0,
|
|
|
|
|
|
decode_CALLa_0, decode_linkage_0, decode_pseudoDEBUG_0,
|
|
|
|
|
|
decode_pseudoOChar_0, decode_pseudodbg_assert_0): Check for parallel
|
|
|
|
|
|
insns.
|
|
|
|
|
|
(decode_dagMODim_0): Verify br field for IREG ops.
|
|
|
|
|
|
(decode_LDST_0): Reject preg load into same preg.
|
|
|
|
|
|
(_print_insn_bfin): Handle returns for ILLEGAL decodes.
|
|
|
|
|
|
(print_insn_bfin): Likewise.
|
|
|
|
|
|
|
2010-09-23 05:53:14 +08:00
|
|
|
|
2010-09-22 Mike Frysinger <vapier@gentoo.org>
|
|
|
|
|
|
|
|
|
|
|
|
* bfin-dis.c (decode_PushPopMultiple_0): Return 0 when pr > 5.
|
|
|
|
|
|
|
2010-09-23 05:41:39 +08:00
|
|
|
|
2010-09-22 Robin Getz <robin.getz@analog.com>
|
|
|
|
|
|
|
|
|
|
|
|
* bfin-dis.c (decode_dsp32shiftimm_0): Add missing "S" flag.
|
|
|
|
|
|
|
2010-09-23 05:39:08 +08:00
|
|
|
|
2010-09-22 Mike Frysinger <vapier@gentoo.org>
|
|
|
|
|
|
|
|
|
|
|
|
* bfin-dis.c (decode_CC2stat_0): Decode all ASTAT bits.
|
|
|
|
|
|
|
2010-09-23 05:38:20 +08:00
|
|
|
|
2010-09-22 Robin Getz <robin.getz@analog.com>
|
|
|
|
|
|
|
|
|
|
|
|
* bfin-dis.c (IS_DREG, IS_PREG, IS_GENREG, IS_DAGREG): Reject
|
|
|
|
|
|
register values greater than 8.
|
|
|
|
|
|
(IS_RESERVEDREG, allreg, mostreg): New helpers.
|
|
|
|
|
|
(decode_ProgCtrl_0): Call IS_DREG/IS_PREG as appropriate.
|
|
|
|
|
|
(decode_PushPopReg_0): Call mostreg/allreg as appropriate.
|
|
|
|
|
|
(decode_CC2dreg_0): Check valid CC register number.
|
|
|
|
|
|
|
2010-09-23 05:26:13 +08:00
|
|
|
|
2010-09-22 Robin Getz <robin.getz@analog.com>
|
|
|
|
|
|
|
|
|
|
|
|
* bfin-dis.c (decode_pseudoDEBUG_0): Add space after DBG.
|
|
|
|
|
|
|
2010-09-23 05:05:03 +08:00
|
|
|
|
2010-09-22 Robin Getz <robin.getz@analog.com>
|
|
|
|
|
|
|
|
|
|
|
|
* bfin-dis.c (machine_registers): Add AC0_COPY, V_COPY, and RND_MOD.
|
|
|
|
|
|
(reg_names): Likewise.
|
|
|
|
|
|
(decode_statbits): Likewise; while reformatting to make manageable.
|
|
|
|
|
|
|
2010-09-23 04:59:00 +08:00
|
|
|
|
2010-09-22 Mike Frysinger <vapier@gentoo.org>
|
|
|
|
|
|
|
|
|
|
|
|
* bfin-dis.c (decode_pseudoDEBUG_0): Add space after OUTC.
|
|
|
|
|
|
(decode_pseudoOChar_0): New function.
|
|
|
|
|
|
(_print_insn_bfin): Remove #if 0 and call new decode_pseudoOChar_0.
|
|
|
|
|
|
|
2010-09-23 04:37:25 +08:00
|
|
|
|
2010-09-22 Robin Getz <robin.getz@analog.com>
|
|
|
|
|
|
|
|
|
|
|
|
* bfin-dis.c (decode_dsp32shift_0): Decode sub opcodes 2/2 as
|
|
|
|
|
|
LSHIFT instead of SHIFT.
|
|
|
|
|
|
|
2010-09-23 04:32:40 +08:00
|
|
|
|
2010-09-22 Mike Frysinger <vapier@gentoo.org>
|
|
|
|
|
|
|
|
|
|
|
|
* bfin-dis.c (constant_formats): Constify the whole structure.
|
|
|
|
|
|
(fmtconst): Add const to return value.
|
|
|
|
|
|
(reg_names): Mark const.
|
|
|
|
|
|
(decode_multfunc): Mark s0/s1 as const.
|
|
|
|
|
|
(decode_macfunc): Mark a/sop as const.
|
|
|
|
|
|
|
2010-09-17 18:13:41 +08:00
|
|
|
|
2010-09-17 Tejas Belagod <tejas.belagod@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm_dis.c (coprocessor_opcodes): Add MRC entry for APSR_nzcv.
|
|
|
|
|
|
|
2010-09-15 07:49:04 +08:00
|
|
|
|
2010-09-14 Maciej W. Rozycki <macro@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* mips-opc.c (mips_builtin_opcodes): Add "sync_acquire",
|
|
|
|
|
|
"sync_mb", "sync_release", "sync_rmb" and "sync_wmb".
|
|
|
|
|
|
|
2010-09-10 21:00:54 +08:00
|
|
|
|
2010-09-10 Pierre Muller <muller@ics.u-strasbg.fr>
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* src/opcodes/dlx-dis.c (print_insn_dlx): Use dlx_insn type for
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|
dlx_insn_type array.
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|
2010-09-01 05:56:57 +08:00
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2010-08-31 H.J. Lu <hongjiu.lu@intel.com>
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|
PR binutils/11960
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* i386-dis.c (sIv): New.
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|
(dis386): Replace Iq with sIv on "pushT".
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(reg_table): Replace T with {T|} on callT, JcallT, jmpT and JjmpT.
|
2010-10-09 14:50:23 +08:00
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|
(x86_64_table): Replace {T|}/{P|} with P.
|
2010-09-01 05:56:57 +08:00
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|
(putop): Add 'w' to 'T'/'P' if needed for Intel syntax.
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(OP_sI): Update v_mode. Remove w_mode.
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|
2010-08-27 21:59:55 +08:00
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2010-08-27 Nathan Froyd <froydnj@codesourcery.com>
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|
* ppc-opc.c (powerpc_opcodes) [lswx,lswi,stswx,stswi]: Deprecate
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|
on E500 and E500MC.
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|
2010-08-18 04:37:26 +08:00
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2010-08-17 H.J. Lu <hongjiu.lu@intel.com>
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* i386-dis.c (reg_table): Replace Eb with Mb on prefetch and
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|
prefetchw.
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|
2010-08-07 02:22:50 +08:00
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2010-08-06 Quentin Neill <quentin.neill@amd.com>
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* i386-gen.c (cpu_flag_init): Define CpuNop extension flag, add
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|
to processor flags for PENTIUMPRO processors and later.
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* i386-opc.h (enum): Add CpuNop.
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|
(i386_cpu_flags): Add cpunop bit.
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* i386-opc.tbl: Change nop cpu_flags.
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* i386-init.h: Regenerated.
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* i386-tbl.h: Likewise.
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2010-08-07 00:33:43 +08:00
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2010-08-06 Quentin Neill <quentin.neill@amd.com>
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* i386-opc.h (enum): Fix typos in comments.
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|
2010-08-06 11:59:49 +08:00
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2010-08-06 Alan Modra <amodra@gmail.com>
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* disassemble.c: Formatting.
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(disassemble_init_for_target <ARCH_m32c>): Comment on endian.
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2010-08-06 09:03:17 +08:00
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2010-08-05 H.J. Lu <hongjiu.lu@intel.com>
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* i386-opc.tbl: Add Cpu186 to ud1/ud2/ud2a/ud2b.
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* i386-tbl.h: Regenerated.
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2010-08-06 08:52:57 +08:00
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|
2010-08-05 H.J. Lu <hongjiu.lu@intel.com>
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* i386-dis.c (dis386_twobyte): Replace ud2a/ud2b with ud2/ud1.
|
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|
* i386-opc.tbl: Add ud1. Remove Cpu686 from ud2/ud2a/ud2b.
|
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|
* i386-tbl.h: Regenerated.
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|
[include/opcode]
* rx.h (RX_Operand_Type): Add TwoReg.
(RX_Opcode_ID): Remove ediv and ediv2.
[opcodes]
* rx-decode.opc (SRR): New.
(rx_decode_opcode): Use it for movbi and movbir. Decode NOP2 (mov
r0,r0) and NOP3 (max r0,r0) special cases.
* rx-decode.c: Regenerate.
[sim/rx]
* rx.c (decode_cache_base): New.
(id_names): Remove ediv and edivu.
(optype_names): Add TwoReg.
(maybe_get_mem_page): New.
(rx_get_byte): Call it.
(get_op): Add TwoReg support.
(put_op): Likewise.
(PD, PS, PS2, GD, GS, GS2, DSZ, SSZ, S2SZ, US1, US2, OM): "opcode"
is a pointer now.
(DO_RETURN): New. We use longjmp to return an exception result.
(decode_opcode): Make opcode a pointer to the decode cache. Save
decoded opcode information and re-use. Call DO_RETURN instead of
return throughout. Remove ediv and edivu.
* mem.c (ptdc): New. Adds decode cache.
(rx_mem_ptr): Support it.
(rx_mem_decode_cache): New.
* mem.h (enum mem_ptr_action): add MPA_DECODE_CACHE.
(rx_mem_decode_cache): Declare.
* gdb-if.c (sim_resume): Add decode_opcode's setjmp logic here...
* main.c (main): ...and here. Use a fast loop if neither trace
nor disassemble is given.
* cpu.h (RX_MAKE_STEPPED, RX_MAKE_HIT_BREAK, RX_MAKE_EXITED,
RX_MAKE_STOPPED, RX_EXITED, RX_STOPPED): Adjust so that 0 is not a
valid code for anything.
2010-07-30 02:41:28 +08:00
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|
2010-07-29 DJ Delorie <dj@redhat.com>
|
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|
|
* rx-decode.opc (SRR): New.
|
|
|
|
|
|
(rx_decode_opcode): Use it for movbi and movbir. Decode NOP2 (mov
|
|
|
|
|
|
r0,r0) and NOP3 (max r0,r0) special cases.
|
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|
|
* rx-decode.c: Regenerate.
|
2010-08-06 11:59:49 +08:00
|
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|
2010-07-29 05:54:34 +08:00
|
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|
2010-07-28 H.J. Lu <hongjiu.lu@intel.com>
|
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|
* i386-dis.c: Add 0F to VEX opcode enums.
|
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|
2010-07-28 08:36:46 +08:00
|
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|
2010-07-27 DJ Delorie <dj@redhat.com>
|
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|
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|
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|
|
* rx-decode.opc (store_flags): Remove, replace with F_* macros.
|
|
|
|
|
|
(rx_decode_opcode): Likewise.
|
|
|
|
|
|
* rx-decode.c: Regenerate.
|
|
|
|
|
|
|
2010-07-23 22:52:54 +08:00
|
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|
|
2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
|
|
|
|
|
|
Ina Pandit <ina.pandit@kpitcummins.com>
|
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|
|
|
* v850-dis.c (v850_sreg_names): Updated structure for system
|
|
|
|
|
|
registers.
|
|
|
|
|
|
(float_cc_names): new structure for condition codes.
|
|
|
|
|
|
(print_value): Update the function that prints value.
|
|
|
|
|
|
(get_operand_value): New function to get the operand value.
|
|
|
|
|
|
(disassemble): Updated to handle the disassembly of instructions.
|
|
|
|
|
|
(print_insn_v850): Updated function to print instruction for different
|
|
|
|
|
|
families.
|
|
|
|
|
|
* opcodes/v850-opc.c (v850_msg_is_out_of_range, insert_i5div1,
|
|
|
|
|
|
extract_i5div1, insert_i5div2, extract_i5div2, insert_i5div3,
|
|
|
|
|
|
extract_i5div3, insert_d5_4, extract_d5_4, extract_d8_6,
|
|
|
|
|
|
insert_d8_7, extract_d8_7, insert_v8, extract_v8, insert_u16_loop,
|
|
|
|
|
|
extract_u16_loop, insert_d16_15, extract_d16_15, insert_d16_16,
|
|
|
|
|
|
extract_d16_16, nsert_d17_16, extract_d17_16, insert_d22,
|
|
|
|
|
|
extract_d22, insert_d23, extract_d23, insert_i9, extract_i9,
|
|
|
|
|
|
insert_u9, extract_u9, extract_spe, insert_r4, extract_r4): New.
|
|
|
|
|
|
(insert_d8_7, insert_d5_4, insert_i5div): Remove.
|
|
|
|
|
|
(v850_operands): Update with the relocation name. Also update
|
|
|
|
|
|
the instructions with specific set of processors.
|
|
|
|
|
|
|
2010-07-09 06:40:28 +08:00
|
|
|
|
2010-07-08 Tejas Belagod <tejas.belagod@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c (print_insn_arm): Add cases for printing more
|
|
|
|
|
|
symbolic operands.
|
|
|
|
|
|
(print_insn_thumb32): Likewise.
|
|
|
|
|
|
|
2010-07-06 08:06:04 +08:00
|
|
|
|
2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* mips-dis.c (print_insn_mips): Correct branch instruction type
|
|
|
|
|
|
determination.
|
|
|
|
|
|
|
2010-07-06 08:02:46 +08:00
|
|
|
|
2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* mips-dis.c (print_mips16_insn_arg): Remove branch instruction
|
|
|
|
|
|
type and delay slot determination.
|
|
|
|
|
|
(print_insn_mips16): Extend branch instruction type and delay
|
|
|
|
|
|
slot determination to cover all instructions.
|
|
|
|
|
|
* mips16-opc.c (BR): Remove macro.
|
|
|
|
|
|
(UBR, CBR): New macros.
|
|
|
|
|
|
(mips16_opcodes): Update branch annotation for "b", "beqz",
|
|
|
|
|
|
"bnez", "bteqz" and "btnez". Add branch annotation for "jalrc"
|
|
|
|
|
|
and "jrc".
|
|
|
|
|
|
|
2010-07-06 01:14:22 +08:00
|
|
|
|
2010-07-05 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
AVX Programming Reference (June, 2010)
|
|
|
|
|
|
* i386-dis.c (mod_table): Replace rdrnd with rdrand.
|
|
|
|
|
|
* i386-opc.tbl: Likewise.
|
|
|
|
|
|
* i386-tbl.h: Regenerated.
|
|
|
|
|
|
|
2010-07-06 00:40:32 +08:00
|
|
|
|
2010-07-05 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.h (CpuFSGSBase): Fix a typo in comments.
|
|
|
|
|
|
|
2010-07-03 16:27:23 +08:00
|
|
|
|
2010-07-03 Andreas Schwab <schwab@linux-m68k.org>
|
|
|
|
|
|
|
|
|
|
|
|
* ppc-dis.c (powerpc_init_dialect): Cast PPC_OPCODE_xxx to
|
|
|
|
|
|
ppc_cpu_t before inverting.
|
2010-07-03 16:29:51 +08:00
|
|
|
|
(ppc_parse_cpu): Likewise.
|
|
|
|
|
|
(print_insn_powerpc): Likewise.
|
2010-07-03 16:27:23 +08:00
|
|
|
|
|
2010-07-03 14:51:56 +08:00
|
|
|
|
2010-07-03 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* ppc-dis.c (ppc_opts, powerpc_init_dialect): Remove old opcode flags.
|
|
|
|
|
|
* ppc-opc.c (PPC32, POWER32, COM32, CLASSIC): Delete.
|
|
|
|
|
|
(PPC64, MFDEC2): Update.
|
|
|
|
|
|
(NON32, NO371): Define.
|
|
|
|
|
|
(powerpc_opcode): Update to not use old opcode flags, and avoid
|
|
|
|
|
|
-m601 duplicates.
|
|
|
|
|
|
|
2010-07-03 12:09:56 +08:00
|
|
|
|
2010-07-03 DJ Delorie <dj@delorie.com>
|
|
|
|
|
|
|
|
|
|
|
|
* m32c-ibld.c: Regenerate.
|
|
|
|
|
|
|
2010-07-03 11:33:17 +08:00
|
|
|
|
2010-07-03 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* ppc-opc.c (PWR2COM): Define.
|
|
|
|
|
|
(PPCPWR2): Add PPC_OPCODE_COMMON.
|
|
|
|
|
|
(powerpc_opcodes): Add "subc", "subco", "subco.", "fcir", "fcir.",
|
|
|
|
|
|
"fcirz", "fcirz." to -mcom opcodes. Remove "mfsri", "dclst",
|
|
|
|
|
|
"rac" from -mcom.
|
|
|
|
|
|
|
Support AVX Programming Reference (June, 2010)
gas/
2010-07-01 H.J. Lu <hongjiu.lu@intel.com>
AVX Programming Reference (June, 2010)
* config/tc-i386.c (cpu_arch): Add .xsaveopt, .fsgsbase, .rdrnd
and .f16c.
* doc/c-i386.texi: Document xsaveopt, fsgsbase, rdrnd and f16c.
gas/testsuite/
2010-07-01 H.J. Lu <hongjiu.lu@intel.com>
AVX Programming Reference (June, 2010)
* gas/i386/arch-10.s: Add xsaveopt.
* gas/i386/x86-64-arch-2.s: Likwise.
* gas/i386/arch-10.d: Updated.
* gas/i386/arch-10-1.l: Likewise.
* gas/i386/arch-10-2.l: Likewise.
* gas/i386/arch-10-3.l: Likewise.
* gas/i386/arch-10-4.l: Likewise.
* gas/i386/x86-64-arch-2.d: Likewise.
* gas/i386/f16c-intel.d: New.
* gas/i386/f16c.d: Likewise.
* gas/i386/f16c.s: Likewise.
* gas/i386/fsgs-intel.d: Likewise.
* gas/i386/fsgs.d: Likewise.
* gas/i386/fsgs.s: Likewise.
* gas/i386/rdrnd-intel.d: Likewise.
* gas/i386/rdrnd.d: Likewise.
* gas/i386/rdrnd.s: Likewise.
* gas/i386/x86-64-f16c-intel.d: Likewise.
* gas/i386/x86-64-f16c.d: Likewise.
* gas/i386/x86-64-f16c.s: Likewise.
* gas/i386/x86-64-fsgs-intel.d: Likewise.
* gas/i386/x86-64-fsgs.d: Likewise.
* gas/i386/x86-64-fsgs.s: Likewise.
* gas/i386/x86-64-rdrnd-intel.d: Likewise.
* gas/i386/x86-64-rdrnd.d: Likewise.
* gas/i386/x86-64-rdrnd.s: Likewise.
* gas/i386/i386.exp: Run f16c, f16c-intel, fsgs, fsgs-intel,
rdrnd, rdrnd-intel, x86-64-f16c, x86-64-f16c-intel, x86-64-fsgs,
x86-64-fsgs-intel, x86-64-rdrnd, x86-64-rdrnd-intel.
* gas/i386/x86-64-xsave.s: Add tests for xsaveopt64.
* gas/i386/x86-64-xsave-intel.d: Updated.
* gas/i386/x86-64-xsave.d: Likewise.
opcodes/
2010-07-01 H.J. Lu <hongjiu.lu@intel.com>
AVX Programming Reference (June, 2010)
* i386-dis.c (PREFIX_0FAE_REG_0): New.
(PREFIX_0FAE_REG_1): Likewise.
(PREFIX_0FAE_REG_2): Likewise.
(PREFIX_0FAE_REG_3): Likewise.
(PREFIX_VEX_3813): Likewise.
(PREFIX_VEX_3A1D): Likewise.
(prefix_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1,
PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3, PREFIX_VEX_3813 and
PREFIX_VEX_3A1D.
(vex_table): Add PREFIX_VEX_3813 and PREFIX_VEX_3A1D.
(mod_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1,
PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3 xsaveopt and rdrnd.
* i386-gen.c (cpu_flag_init): Add CPU_XSAVEOPT_FLAGS,
CPU_FSGSBASE_FLAGS, CPU_RDRND_FLAGS and CPU_F16C_FLAGS.
(cpu_flags): Add CpuXsaveopt, CpuFSGSBase, CpuRdRnd and CpuF16C.
* i386-opc.h (CpuXsaveopt): New.
(CpuFSGSBase):Likewise.
(CpuRdRnd): Likewise.
(CpuF16C): Likewise.
(i386_cpu_flags): Add cpuxsaveopt, cpufsgsbase, cpurdrnd and
cpuf16c.
* i386-opc.tbl: Add xsaveopt, rdfsbase, rdgsbase, rdrnd,
wrfsbase, wrgsbase, vcvtph2ps and vcvtps2ph.
2010-07-02 05:55:02 +08:00
|
|
|
|
2010-07-01 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
AVX Programming Reference (June, 2010)
|
|
|
|
|
|
* i386-dis.c (PREFIX_0FAE_REG_0): New.
|
|
|
|
|
|
(PREFIX_0FAE_REG_1): Likewise.
|
|
|
|
|
|
(PREFIX_0FAE_REG_2): Likewise.
|
|
|
|
|
|
(PREFIX_0FAE_REG_3): Likewise.
|
|
|
|
|
|
(PREFIX_VEX_3813): Likewise.
|
|
|
|
|
|
(PREFIX_VEX_3A1D): Likewise.
|
|
|
|
|
|
(prefix_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1,
|
|
|
|
|
|
PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3, PREFIX_VEX_3813 and
|
|
|
|
|
|
PREFIX_VEX_3A1D.
|
|
|
|
|
|
(vex_table): Add PREFIX_VEX_3813 and PREFIX_VEX_3A1D.
|
|
|
|
|
|
(mod_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1,
|
|
|
|
|
|
PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3 xsaveopt and rdrnd.
|
|
|
|
|
|
|
|
|
|
|
|
* i386-gen.c (cpu_flag_init): Add CPU_XSAVEOPT_FLAGS,
|
|
|
|
|
|
CPU_FSGSBASE_FLAGS, CPU_RDRND_FLAGS and CPU_F16C_FLAGS.
|
|
|
|
|
|
(cpu_flags): Add CpuXsaveopt, CpuFSGSBase, CpuRdRnd and CpuF16C.
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.h (CpuXsaveopt): New.
|
2010-07-06 00:40:32 +08:00
|
|
|
|
(CpuFSGSBase): Likewise.
|
Support AVX Programming Reference (June, 2010)
gas/
2010-07-01 H.J. Lu <hongjiu.lu@intel.com>
AVX Programming Reference (June, 2010)
* config/tc-i386.c (cpu_arch): Add .xsaveopt, .fsgsbase, .rdrnd
and .f16c.
* doc/c-i386.texi: Document xsaveopt, fsgsbase, rdrnd and f16c.
gas/testsuite/
2010-07-01 H.J. Lu <hongjiu.lu@intel.com>
AVX Programming Reference (June, 2010)
* gas/i386/arch-10.s: Add xsaveopt.
* gas/i386/x86-64-arch-2.s: Likwise.
* gas/i386/arch-10.d: Updated.
* gas/i386/arch-10-1.l: Likewise.
* gas/i386/arch-10-2.l: Likewise.
* gas/i386/arch-10-3.l: Likewise.
* gas/i386/arch-10-4.l: Likewise.
* gas/i386/x86-64-arch-2.d: Likewise.
* gas/i386/f16c-intel.d: New.
* gas/i386/f16c.d: Likewise.
* gas/i386/f16c.s: Likewise.
* gas/i386/fsgs-intel.d: Likewise.
* gas/i386/fsgs.d: Likewise.
* gas/i386/fsgs.s: Likewise.
* gas/i386/rdrnd-intel.d: Likewise.
* gas/i386/rdrnd.d: Likewise.
* gas/i386/rdrnd.s: Likewise.
* gas/i386/x86-64-f16c-intel.d: Likewise.
* gas/i386/x86-64-f16c.d: Likewise.
* gas/i386/x86-64-f16c.s: Likewise.
* gas/i386/x86-64-fsgs-intel.d: Likewise.
* gas/i386/x86-64-fsgs.d: Likewise.
* gas/i386/x86-64-fsgs.s: Likewise.
* gas/i386/x86-64-rdrnd-intel.d: Likewise.
* gas/i386/x86-64-rdrnd.d: Likewise.
* gas/i386/x86-64-rdrnd.s: Likewise.
* gas/i386/i386.exp: Run f16c, f16c-intel, fsgs, fsgs-intel,
rdrnd, rdrnd-intel, x86-64-f16c, x86-64-f16c-intel, x86-64-fsgs,
x86-64-fsgs-intel, x86-64-rdrnd, x86-64-rdrnd-intel.
* gas/i386/x86-64-xsave.s: Add tests for xsaveopt64.
* gas/i386/x86-64-xsave-intel.d: Updated.
* gas/i386/x86-64-xsave.d: Likewise.
opcodes/
2010-07-01 H.J. Lu <hongjiu.lu@intel.com>
AVX Programming Reference (June, 2010)
* i386-dis.c (PREFIX_0FAE_REG_0): New.
(PREFIX_0FAE_REG_1): Likewise.
(PREFIX_0FAE_REG_2): Likewise.
(PREFIX_0FAE_REG_3): Likewise.
(PREFIX_VEX_3813): Likewise.
(PREFIX_VEX_3A1D): Likewise.
(prefix_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1,
PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3, PREFIX_VEX_3813 and
PREFIX_VEX_3A1D.
(vex_table): Add PREFIX_VEX_3813 and PREFIX_VEX_3A1D.
(mod_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1,
PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3 xsaveopt and rdrnd.
* i386-gen.c (cpu_flag_init): Add CPU_XSAVEOPT_FLAGS,
CPU_FSGSBASE_FLAGS, CPU_RDRND_FLAGS and CPU_F16C_FLAGS.
(cpu_flags): Add CpuXsaveopt, CpuFSGSBase, CpuRdRnd and CpuF16C.
* i386-opc.h (CpuXsaveopt): New.
(CpuFSGSBase):Likewise.
(CpuRdRnd): Likewise.
(CpuF16C): Likewise.
(i386_cpu_flags): Add cpuxsaveopt, cpufsgsbase, cpurdrnd and
cpuf16c.
* i386-opc.tbl: Add xsaveopt, rdfsbase, rdgsbase, rdrnd,
wrfsbase, wrgsbase, vcvtph2ps and vcvtps2ph.
2010-07-02 05:55:02 +08:00
|
|
|
|
(CpuRdRnd): Likewise.
|
|
|
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|
(CpuF16C): Likewise.
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|
|
|
(i386_cpu_flags): Add cpuxsaveopt, cpufsgsbase, cpurdrnd and
|
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|
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|
cpuf16c.
|
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* i386-opc.tbl: Add xsaveopt, rdfsbase, rdgsbase, rdrnd,
|
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|
|
wrfsbase, wrgsbase, vcvtph2ps and vcvtps2ph.
|
2010-07-02 05:57:04 +08:00
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|
* i386-init.h: Regenerated.
|
|
|
|
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|
* i386-tbl.h: Likewise.
|
Support AVX Programming Reference (June, 2010)
gas/
2010-07-01 H.J. Lu <hongjiu.lu@intel.com>
AVX Programming Reference (June, 2010)
* config/tc-i386.c (cpu_arch): Add .xsaveopt, .fsgsbase, .rdrnd
and .f16c.
* doc/c-i386.texi: Document xsaveopt, fsgsbase, rdrnd and f16c.
gas/testsuite/
2010-07-01 H.J. Lu <hongjiu.lu@intel.com>
AVX Programming Reference (June, 2010)
* gas/i386/arch-10.s: Add xsaveopt.
* gas/i386/x86-64-arch-2.s: Likwise.
* gas/i386/arch-10.d: Updated.
* gas/i386/arch-10-1.l: Likewise.
* gas/i386/arch-10-2.l: Likewise.
* gas/i386/arch-10-3.l: Likewise.
* gas/i386/arch-10-4.l: Likewise.
* gas/i386/x86-64-arch-2.d: Likewise.
* gas/i386/f16c-intel.d: New.
* gas/i386/f16c.d: Likewise.
* gas/i386/f16c.s: Likewise.
* gas/i386/fsgs-intel.d: Likewise.
* gas/i386/fsgs.d: Likewise.
* gas/i386/fsgs.s: Likewise.
* gas/i386/rdrnd-intel.d: Likewise.
* gas/i386/rdrnd.d: Likewise.
* gas/i386/rdrnd.s: Likewise.
* gas/i386/x86-64-f16c-intel.d: Likewise.
* gas/i386/x86-64-f16c.d: Likewise.
* gas/i386/x86-64-f16c.s: Likewise.
* gas/i386/x86-64-fsgs-intel.d: Likewise.
* gas/i386/x86-64-fsgs.d: Likewise.
* gas/i386/x86-64-fsgs.s: Likewise.
* gas/i386/x86-64-rdrnd-intel.d: Likewise.
* gas/i386/x86-64-rdrnd.d: Likewise.
* gas/i386/x86-64-rdrnd.s: Likewise.
* gas/i386/i386.exp: Run f16c, f16c-intel, fsgs, fsgs-intel,
rdrnd, rdrnd-intel, x86-64-f16c, x86-64-f16c-intel, x86-64-fsgs,
x86-64-fsgs-intel, x86-64-rdrnd, x86-64-rdrnd-intel.
* gas/i386/x86-64-xsave.s: Add tests for xsaveopt64.
* gas/i386/x86-64-xsave-intel.d: Updated.
* gas/i386/x86-64-xsave.d: Likewise.
opcodes/
2010-07-01 H.J. Lu <hongjiu.lu@intel.com>
AVX Programming Reference (June, 2010)
* i386-dis.c (PREFIX_0FAE_REG_0): New.
(PREFIX_0FAE_REG_1): Likewise.
(PREFIX_0FAE_REG_2): Likewise.
(PREFIX_0FAE_REG_3): Likewise.
(PREFIX_VEX_3813): Likewise.
(PREFIX_VEX_3A1D): Likewise.
(prefix_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1,
PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3, PREFIX_VEX_3813 and
PREFIX_VEX_3A1D.
(vex_table): Add PREFIX_VEX_3813 and PREFIX_VEX_3A1D.
(mod_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1,
PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3 xsaveopt and rdrnd.
* i386-gen.c (cpu_flag_init): Add CPU_XSAVEOPT_FLAGS,
CPU_FSGSBASE_FLAGS, CPU_RDRND_FLAGS and CPU_F16C_FLAGS.
(cpu_flags): Add CpuXsaveopt, CpuFSGSBase, CpuRdRnd and CpuF16C.
* i386-opc.h (CpuXsaveopt): New.
(CpuFSGSBase):Likewise.
(CpuRdRnd): Likewise.
(CpuF16C): Likewise.
(i386_cpu_flags): Add cpuxsaveopt, cpufsgsbase, cpurdrnd and
cpuf16c.
* i386-opc.tbl: Add xsaveopt, rdfsbase, rdgsbase, rdrnd,
wrfsbase, wrgsbase, vcvtph2ps and vcvtps2ph.
2010-07-02 05:55:02 +08:00
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2010-07-01 10:29:12 +08:00
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2010-07-01 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
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* ppc-opc.c (powerpc_opcodes): Revert deprecation of mfocrf, mtcrf
|
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and mtocrf on EFS.
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2010-06-29 12:17:34 +08:00
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2010-06-29 Alan Modra <amodra@gmail.com>
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* maxq-dis.c: Delete file.
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* Makefile.am: Remove references to maxq.
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* configure.in: Likewise.
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* disassemble.c: Likewise.
|
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* Makefile.in: Regenerate.
|
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|
* configure: Regenerate.
|
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* po/POTFILES.in: Regenerate.
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2010-06-28 22:41:59 +08:00
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2010-06-29 Alan Modra <amodra@gmail.com>
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* mep-dis.c: Regenerate.
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2010-06-28 17:10:25 +08:00
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2010-06-28 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
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* arm-disc.c (parse_insn_neon): Fix Neon alignment syntax.
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2010-06-27 12:07:55 +08:00
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2010-06-27 Alan Modra <amodra@gmail.com>
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* arc-dis.c (arc_sprintf): Delete set but unused variables.
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(decodeInstr): Likewise.
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* dlx-dis.c (print_insn_dlx): Likewise.
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* h8300-dis.c (bfd_h8_disassemble_init): Likewise.
|
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* maxq-dis.c (check_move, print_insn): Likewise.
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* mep-dis.c (mep_examine_ivc2_insns): Likewise.
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* msp430-dis.c (msp430_branchinstr): Likewise.
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* bfin-dis.c (_print_insn_bfin): Avoid set but unused warning.
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* cgen-asm.in (parse_insn_normal, _cgen_assemble_insn): Likewise.
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* sparc-dis.c (print_insn_sparc): Likewise.
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* fr30-asm.c: Regenerate.
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* frv-asm.c: Regenerate.
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* ip2k-asm.c: Regenerate.
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* iq2000-asm.c: Regenerate.
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* lm32-asm.c: Regenerate.
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* m32c-asm.c: Regenerate.
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* m32r-asm.c: Regenerate.
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* mep-asm.c: Regenerate.
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* mt-asm.c: Regenerate.
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* openrisc-asm.c: Regenerate.
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* xc16x-asm.c: Regenerate.
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* xstormy16-asm.c: Regenerate.
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2010-06-17 00:27:37 +08:00
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2010-06-16 Vincent Rivière <vincent.riviere@freesbee.fr>
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PR gas/11673
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* m68k-opc.c (m68k_opcodes): Remove move.l for isab and later.
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2010-06-16 23:12:51 +08:00
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2010-06-16 Vincent Rivière <vincent.riviere@freesbee.fr>
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PR binutils/11676
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* m68k-dis.c (print_insn_arg): Prefix float constants with #0e.
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2010-06-14 22:48:05 +08:00
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2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
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* ppc-dis.c (ppc_opts): Remove PPC_OPCODE_E500MC from e500 and
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e500x2. Add PPC_OPCODE_E500 to e500 and e500x2
|
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* ppc-opc.c (powerpc_opcodes): Deprecate all opcodes on EFS which
|
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touch floating point regs and are enabled by COM, PPC or PPCCOM.
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Treat sync as msync on e500. Treat eieio as mbar 1 on e500.
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Treat lwsync as msync on e500.
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2010-06-07 18:43:52 +08:00
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2010-06-07 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
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* arm-dis.c (thumb-opcodes): Add disassembly for movs.
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2010-05-29 00:04:21 +08:00
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2010-05-28 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
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2010-06-14 22:48:05 +08:00
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* arm-dis.c (print_insn_neon): Ensure disassembly of Neon
|
2010-05-29 00:04:21 +08:00
|
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constants is the same on 32-bit and 64-bit hosts.
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2010-05-27 18:45:52 +08:00
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2010-05-27 Jason Duerstock <jason.duerstock+binutils@gmail.com>
|
2010-05-27 18:43:27 +08:00
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* m68k-dis.c (print_insn_m68k): Emit undefined instructions as
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.short directives so that they can be reassembled.
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2010-05-27 05:49:30 +08:00
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2010-05-26 Catherine Moore <clm@codesourcery.com>
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David Ung <davidu@mips.com>
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* mips-opc.c: Change membership to I1 for instructions ssnop and
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ehb.
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2010-05-27 00:08:23 +08:00
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2010-05-26 H.J. Lu <hongjiu.lu@intel.com>
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* i386-dis.c (sib): New.
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(get_sib): Likewise.
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(print_insn): Call get_sib.
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OP_E_memory): Use sib.
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2010-05-26 20:59:56 +08:00
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2010-05-26 Catherine Moore <clm@codesoourcery.com>
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* mips-dis.c (mips_arch): Remove INSN_MIPS16.
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* mips-opc.c (I16): Remove.
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(mips_builtin_op): Reclassify jalx.
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2010-05-19 11:44:36 +08:00
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2010-05-19 Alan Modra <amodra@gmail.com>
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* ppc-opc.c (powerpc_opcodes): Enable divdeu, devweu, divde,
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|
divwe, divdeuo, divweuo, divdeo, divweo for A2. Add icswepx.
|
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2010-05-13 14:30:09 +08:00
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2010-05-13 Alan Modra <amodra@gmail.com>
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* ppc-opc.c (powerpc_opcodes): Correct wclr encoding.
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2010-05-12 01:36:33 +08:00
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2010-05-11 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
|
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* arm-dis.c (thumb_opcodes): Update ldmia entry to use new %W
|
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format.
|
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(print_insn_thumb16): Add support for new %W format.
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|
2010-05-07 20:28:50 +08:00
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|
2010-05-07 Tristan Gingold <gingold@adacore.com>
|
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* Makefile.in: Regenerate with automake 1.11.1.
|
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* aclocal.m4: Ditto.
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2010-05-05 23:28:26 +08:00
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2010-05-05 Nick Clifton <nickc@redhat.com>
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* po/es.po: Updated Spanish translation.
|
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|
2010-04-22 22:37:16 +08:00
|
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|
2010-04-22 Nick Clifton <nickc@redhat.com>
|
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* po/opcodes.pot: Updated by the Translation project.
|
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|
* po/vi.po: Updated Vietnamese translation.
|
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|
2010-04-17 05:35:24 +08:00
|
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|
2010-04-16 H.J. Lu <hongjiu.lu@intel.com>
|
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|
|
|
|
|
|
|
* i386-dis.c (get_valid_dis386): Return bad_opcode on unknown
|
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|
|
|
bits in opcode.
|
|
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|
|
|
|
2010-04-09 22:40:18 +08:00
|
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|
|
2010-04-09 Nick Clifton <nickc@redhat.com>
|
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|
|
|
|
|
|
|
|
* i386-dis.c (print_insn): Remove unused variable op.
|
|
|
|
|
|
(OP_sI): Remove unused variable mask.
|
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|
2010-04-07 15:20:51 +08:00
|
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|
|
2010-04-07 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* configure: Regenerate.
|
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|
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|
2010-04-07 00:04:34 +08:00
|
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|
|
2010-04-06 Peter Bergner <bergner@vnet.ibm.com>
|
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|
|
|
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|
|
* ppc-opc.c (RBOPT): New define.
|
|
|
|
|
|
("dccci"): Enable for PPCA2. Make operands optional.
|
|
|
|
|
|
("iccci"): Likewise. Do not deprecate for PPC476.
|
|
|
|
|
|
|
2010-04-06 23:41:43 +08:00
|
|
|
|
2010-04-02 Masaki Muranaka <monaka@monami-software.com>
|
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|
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|
|
|
|
|
|
* cr16-opc.c (cr16_instruction): Fix typo in comment.
|
|
|
|
|
|
|
bfd:
* Makefile.am (ALL_MACHINES): Add cpu-tic6x.lo.
(ALL_MACHINES_CFILES): Add cpu-tic6x.c.
(BFD32_BACKENDS): Add elf32-tic6x.lo.
(BFD32_BACKENDS_CFILES): Add elf32-tic6x.c.
* Makefile.in: Regenerate.
* archures.c (bfd_arch_tic6x, bfd_tic6x_arch): New.
(bfd_archures_list): Update.
* config.bfd (tic6x-*-elf): New.
* configure.in (bfd_elf32_tic6x_be_vec, bfd_elf32_tic6x_le_vec):
New.
* configure: Regenerate.
* cpu-tic6x.c, elf32-tic6x.c: New.
* reloc.c (BFD_RELOC_C6000_PCR_S21, BFD_RELOC_C6000_PCR_S12,
BFD_RELOC_C6000_PCR_S10, BFD_RELOC_C6000_PCR_S7,
BFD_RELOC_C6000_ABS_S16, BFD_RELOC_C6000_ABS_L16,
BFD_RELOC_C6000_ABS_H16, BFD_RELOC_C6000_SBR_U15_B,
BFD_RELOC_C6000_SBR_U15_H, BFD_RELOC_C6000_SBR_U15_W,
BFD_RELOC_C6000_SBR_S16, BFD_RELOC_C6000_SBR_L16_B,
BFD_RELOC_C6000_SBR_L16_H, BFD_RELOC_C6000_SBR_L16_W,
BFD_RELOC_C6000_SBR_H16_B, BFD_RELOC_C6000_SBR_H16_H,
BFD_RELOC_C6000_SBR_H16_W, BFD_RELOC_C6000_SBR_GOT_U15_W,
BFD_RELOC_C6000_SBR_GOT_L16_W, BFD_RELOC_C6000_SBR_GOT_H16_W,
BFD_RELOC_C6000_DSBT_INDEX, BFD_RELOC_C6000_PREL31,
BFD_RELOC_C6000_COPY, BFD_RELOC_C6000_ALIGN,
BFD_RELOC_C6000_FPHEAD, BFD_RELOC_C6000_NOCMP): New.
* targets.c (bfd_elf32_tic6x_be_vec, bfd_elf32_tic6x_le_vec): New.
(_bfd_target_vector): Update.
* bfd-in2.h, libbfd.h: Regenerate.
binutils:
* MAINTAINERS: Add self as TI C6X maintainer.
* NEWS: Add news entry for TI C6X support.
* readelf.c: Include elf/tic6x.h.
(guess_is_rela): Handle EM_TI_C6000.
(dump_relocations): Likewise.
(get_tic6x_dynamic_type): New.
(get_dynamic_type): Call it.
(get_machine_flags): Handle EF_C6000_REL.
(get_osabi_name): Handle machine-specific values only for relevant
machines. Handle C6X values.
(get_tic6x_segment_type): New.
(get_segment_type): Call it.
(get_tic6x_section_type_name): New.
(get_section_type_name): Call it.
(is_32bit_abs_reloc, is_16bit_abs_reloc, is_none_reloc): Handle
EM_TI_C6000.
gas:
* Makefile.am (TARGET_CPU_CFILES): Add config/tc-tic6x.c.
(TARGET_CPU_HFILES): Add config/tc-tic6x.h.
* Makefile.in: Regenerate.
* NEWS: Add news entry for TI C6X support.
* app.c (do_scrub_chars): Handle "||^" for TI C6X. Handle
TC_PREDICATE_START_CHAR and TC_PREDICATE_END_CHAR. Keep spaces in
operands if TC_KEEP_OPERAND_SPACES.
* configure.tgt (tic6x-*-*): New.
* config/tc-ia64.h (TC_PREDICATE_START_CHAR,
TC_PREDICATE_END_CHAR): Define.
* config/tc-tic6x.c, config/tc-tic6x.h: New.
* doc/Makefile.am (CPU_DOCS): Add c-tic6x.texi.
* doc/Makefile.in: Regenerate.
* doc/all.texi (TIC6X): Define.
* doc/as.texinfo: Add TI C6X documentation. Include c-tic6x.texi.
* doc/c-tic6x.texi: New.
gas/testsuite:
* gas/tic6x: New directory and testcases.
include:
* dis-asm.h (print_insn_tic6x): Declare.
include/elf:
* common.h (ELFOSABI_C6000_ELFABI, ELFOSABI_C6000_LINUX): Define.
* tic6x.h: New.
include/opcode:
* tic6x-control-registers.h, tic6x-insn-formats.h,
tic6x-opcode-table.h, tic6x.h: New.
ld:
* Makefile.am (ALL_EMULATIONS): Add eelf32_tic6x_be.o and
eelf32_tic6x_le.o.
(eelf32_tic6x_be.c, eelf32_tic6x_le.c): New.
* NEWS: Add news entry for TI C6X support.
* configure.tgt (tic6x-*-*): New.
* emulparams/elf32_tic6x_be.sh, emulparams/elf32_tic6x_le.sh: New.
ld/testsuite:
* ld-elf/flags1.d, ld-elf/merge.d: XFAIL for tic6x-*-*.
* ld-elf/sec-to-seg.exp: Set B_test_same_seg to 0 for tic6x-*-*.
* ld-tic6x: New directory and testcases.
opcodes:
* Makefile.am (TARGET_LIBOPCODES_CFILES): Add tic6x-dis.c.
* Makefile.in: Regenerate.
* configure.in (bfd_tic6x_arch): New.
* configure: Regenerate.
* disassemble.c (ARCH_tic6x): Define if ARCH_all.
(disassembler): Handle TI C6X.
* tic6x-dis.c: New.
2010-03-26 05:12:36 +08:00
|
|
|
|
2010-03-25 Joseph Myers <joseph@codesourcery.com>
|
|
|
|
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|
|
|
|
|
* Makefile.am (TARGET_LIBOPCODES_CFILES): Add tic6x-dis.c.
|
|
|
|
|
|
* Makefile.in: Regenerate.
|
|
|
|
|
|
* configure.in (bfd_tic6x_arch): New.
|
|
|
|
|
|
* configure: Regenerate.
|
|
|
|
|
|
* disassemble.c (ARCH_tic6x): Define if ARCH_all.
|
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|
|
|
(disassembler): Handle TI C6X.
|
|
|
|
|
|
* tic6x-dis.c: New.
|
|
|
|
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|
|
2010-03-24 13:16:29 +08:00
|
|
|
|
2010-03-24 Mike Frysinger <vapier@gentoo.org>
|
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|
|
|
|
|
|
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|
|
* bfin-dis.c (decode_regs_hi): Change REG_LH2 typo to REG_MH2.
|
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|
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|
|
2010-03-23 23:59:45 +08:00
|
|
|
|
2010-03-23 Joseph Myers <joseph@codesourcery.com>
|
|
|
|
|
|
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|
|
|
|
|
* dis-buf.c (buffer_read_memory): Give error for reading just
|
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|
before the start of memory.
|
|
|
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|
|
2010-03-23 10:56:24 +08:00
|
|
|
|
2010-03-22 Sebastian Pop <sebastian.pop@amd.com>
|
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|
|
|
|
Quentin Neill <quentin.neill@amd.com>
|
|
|
|
|
|
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|
|
|
|
* i386-dis.c (OP_LWP_I): Removed.
|
|
|
|
|
|
(reg_table): Do not use OP_LWP_I, use Iq.
|
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|
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|
|
(OP_LWPCB_E): Remove use of names16.
|
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|
|
(OP_LWP_E): Same.
|
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|
|
* i386-opc.tbl: Removed 16bit LWP insns. 32bit LWP insns
|
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|
|
|
|
should not set the Vex.length bit.
|
|
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|
* i386-tbl.h: Regenerated.
|
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|
2010-02-25 09:00:13 +08:00
|
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|
2010-02-25 Edmar Wienskoski <edmar@freescale.com>
|
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|
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|
|
* ppc-dis.c (ppc_opts): Add PPC_OPCODE_E500MC for "e500mc64".
|
|
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|
|
2010-02-24 23:11:44 +08:00
|
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|
|
2010-02-24 Nick Clifton <nickc@redhat.com>
|
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|
|
|
|
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|
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|
|
PR binutils/6773
|
|
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|
|
* arm-dis.c (arm_opcodes): Replace <prefix>addsubx with
|
|
|
|
|
|
<prefix>asx. Replace <prefix>subaddx with <prefix>sax.
|
|
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|
|
(thumb32_opcodes): Likewise.
|
|
|
|
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|
|
2010-02-15 18:09:39 +08:00
|
|
|
|
2010-02-15 Nick Clifton <nickc@redhat.com>
|
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|
|
|
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|
|
* po/vi.po: Updated Vietnamese translation.
|
|
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|
|
2010-02-13 12:38:57 +08:00
|
|
|
|
2010-02-12 Doug Evans <dje@sebabeach.org>
|
|
|
|
|
|
|
|
|
|
|
|
* lm32-opinst.c: Regenerate.
|
|
|
|
|
|
|
* fr30-desc.c, * fr30-desc.h, * fr30-opc.c,
* frv-desc.c, * frv-desc.h, * frv-opc.c,
* ip2k-desc.c, * ip2k-desc.h, * ip2k-opc.c,
* iq2000-desc.c, * iq2000-desc.h, * iq2000-opc.c,
* lm32-desc.c, * lm32-desc.h, * lm32-opc.c, * lm32-opinst.c,
* m32c-desc.c, * m32c-desc.h, * m32c-opc.c,
* m32r-desc.c, * m32r-desc.h, * m32r-opc.c, * m32r-opinst.c,
* mep-desc.c, * mep-desc.h, * mep-opc.c,
* mt-desc.c, * mt-desc.h, * mt-opc.c,
* openrisc-desc.c, * openrisc-desc.h, * openrisc-opc.c,
* xc16x-desc.c, * xc16x-desc.h, * xc16x-opc.c,
* xstormy16-desc.c, * xstormy16-desc.h, * xstormy16-opc.c: Regenerate.
2010-02-12 11:25:49 +08:00
|
|
|
|
2010-02-11 Doug Evans <dje@sebabeach.org>
|
|
|
|
|
|
|
* cgen-dis.in (print_normal): Delete CGEN_PRINT_NORMAL.
(print_address): Delete CGEN_PRINT_ADDRESS.
* fr30-dis.c, * frv-dis.c, * ip2k-dis.c, * iq2000-dis.c,
* lm32-dis.c, * m32c-dis.c, * m32r-desc.c, * m32r-desc.h,
* m32r-dis.c, * mep-dis.c, * mt-dis.c, * openrisc-dis.c,
* xc16x-dis.c, * xstormy16-dis.c: Regenerate.
2010-02-12 12:42:28 +08:00
|
|
|
|
* cgen-dis.in (print_normal): Delete CGEN_PRINT_NORMAL.
|
|
|
|
|
|
(print_address): Delete CGEN_PRINT_ADDRESS.
|
|
|
|
|
|
* fr30-dis.c, * frv-dis.c, * ip2k-dis.c, * iq2000-dis.c,
|
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|
|
|
* lm32-dis.c, * m32c-dis.c, * m32r-desc.c, * m32r-desc.h,
|
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|
|
* m32r-dis.c, * mep-dis.c, * mt-dis.c, * openrisc-dis.c,
|
|
|
|
|
|
* xc16x-dis.c, * xstormy16-dis.c: Regenerate.
|
|
|
|
|
|
|
* fr30-desc.c, * fr30-desc.h, * fr30-opc.c,
* frv-desc.c, * frv-desc.h, * frv-opc.c,
* ip2k-desc.c, * ip2k-desc.h, * ip2k-opc.c,
* iq2000-desc.c, * iq2000-desc.h, * iq2000-opc.c,
* lm32-desc.c, * lm32-desc.h, * lm32-opc.c, * lm32-opinst.c,
* m32c-desc.c, * m32c-desc.h, * m32c-opc.c,
* m32r-desc.c, * m32r-desc.h, * m32r-opc.c, * m32r-opinst.c,
* mep-desc.c, * mep-desc.h, * mep-opc.c,
* mt-desc.c, * mt-desc.h, * mt-opc.c,
* openrisc-desc.c, * openrisc-desc.h, * openrisc-opc.c,
* xc16x-desc.c, * xc16x-desc.h, * xc16x-opc.c,
* xstormy16-desc.c, * xstormy16-desc.h, * xstormy16-opc.c: Regenerate.
2010-02-12 11:25:49 +08:00
|
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|
* fr30-desc.c, * fr30-desc.h, * fr30-opc.c,
|
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|
* frv-desc.c, * frv-desc.h, * frv-opc.c,
|
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|
* ip2k-desc.c, * ip2k-desc.h, * ip2k-opc.c,
|
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|
* iq2000-desc.c, * iq2000-desc.h, * iq2000-opc.c,
|
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|
* lm32-desc.c, * lm32-desc.h, * lm32-opc.c, * lm32-opinst.c,
|
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|
|
* m32c-desc.c, * m32c-desc.h, * m32c-opc.c,
|
|
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|
* m32r-desc.c, * m32r-desc.h, * m32r-opc.c, * m32r-opinst.c,
|
|
|
|
|
|
* mep-desc.c, * mep-desc.h, * mep-opc.c,
|
|
|
|
|
|
* mt-desc.c, * mt-desc.h, * mt-opc.c,
|
|
|
|
|
|
* openrisc-desc.c, * openrisc-desc.h, * openrisc-opc.c,
|
|
|
|
|
|
* xc16x-desc.c, * xc16x-desc.h, * xc16x-opc.c,
|
|
|
|
|
|
* xstormy16-desc.c, * xstormy16-desc.h, * xstormy16-opc.c: Regenerate.
|
|
|
|
|
|
|
2010-02-11 21:41:19 +08:00
|
|
|
|
2010-02-11 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c: Update copyright.
|
|
|
|
|
|
* i386-gen.c: Likewise.
|
|
|
|
|
|
* i386-opc.h: Likewise.
|
|
|
|
|
|
* i386-opc.tbl: Likewise.
|
|
|
|
|
|
|
2010-02-11 13:06:14 +08:00
|
|
|
|
2010-02-10 Quentin Neill <quentin.neill@amd.com>
|
|
|
|
|
|
Sebastian Pop <sebastian.pop@amd.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (OP_EX_VexImmW): Reintroduced
|
|
|
|
|
|
function to handle 5th imm8 operand.
|
|
|
|
|
|
(PREFIX_VEX_3A48): Added.
|
|
|
|
|
|
(PREFIX_VEX_3A49): Added.
|
|
|
|
|
|
(VEX_W_3A48_P_2): Added.
|
|
|
|
|
|
(VEX_W_3A49_P_2): Added.
|
|
|
|
|
|
(prefix table): Added entries for PREFIX_VEX_3A48
|
|
|
|
|
|
and PREFIX_VEX_3A49.
|
|
|
|
|
|
(vex table): Added entries for VEX_W_3A48_P_2 and
|
|
|
|
|
|
and VEX_W_3A49_P_2.
|
|
|
|
|
|
* i386-gen.c (operand_type_init): Added OPERAND_TYPE_VEC_IMM4
|
|
|
|
|
|
for Vec_Imm4 operands.
|
|
|
|
|
|
* i386-opc.h (enum): Added Vec_Imm4.
|
|
|
|
|
|
(i386_operand_type): Added vec_imm4.
|
|
|
|
|
|
* i386-opc.tbl: Add entries for vpermilp[ds].
|
|
|
|
|
|
* i386-init.h: Regenerated.
|
|
|
|
|
|
* i386-tbl.h: Regenerated.
|
|
|
|
|
|
|
2010-02-11 03:59:07 +08:00
|
|
|
|
2010-02-10 Richard Sandiford <r.sandiford@uk.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* ppc-dis.c (ppc_opts): Add "pwr4", "pwr5", "pwr5x", "pwr6"
|
|
|
|
|
|
and "pwr7". Move "a2" into alphabetical order.
|
|
|
|
|
|
|
2010-02-08 09:59:38 +08:00
|
|
|
|
2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
|
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|
|
|
|
|
|
|
|
|
|
* ppc-dis.c (ppc_opts): Add titan entry.
|
|
|
|
|
|
* ppc-opc.c (TITAN, MULHW): Define.
|
|
|
|
|
|
(powerpc_opcodes): Support AppliedMicro Titan core (APM83xxx).
|
|
|
|
|
|
|
2010-02-04 04:36:14 +08:00
|
|
|
|
2010-02-03 Quentin Neill <quentin.neill@amd.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-gen.c (cpu_flag_init): Rename CPU_AMDFAM15_FLAGS
|
|
|
|
|
|
to CPU_BDVER1_FLAGS
|
|
|
|
|
|
* i386-init.h: Regenerated.
|
|
|
|
|
|
|
2010-02-03 20:47:06 +08:00
|
|
|
|
2010-02-03 Anthony Green <green@moxielogic.com>
|
|
|
|
|
|
|
|
|
|
|
|
* moxie-opc.c (moxie_form1_opc_info): Move "nop" from 0x00 to
|
|
|
|
|
|
0x0f, and make 0x00 an illegal instruction.
|
|
|
|
|
|
|
2010-01-30 00:47:55 +08:00
|
|
|
|
2010-01-29 Daniel Jacobowitz <dan@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* opcodes/arm-dis.c (struct arm_private_data): New.
|
|
|
|
|
|
(print_insn_coprocessor, print_insn_arm): Update to use struct
|
|
|
|
|
|
arm_private_data.
|
|
|
|
|
|
(is_mapping_symbol, get_map_sym_type): New functions.
|
|
|
|
|
|
(get_sym_code_type): Check the symbol's section. Do not check
|
|
|
|
|
|
mapping symbols.
|
|
|
|
|
|
(print_insn): Default to disassembling ARM mode code. Check
|
|
|
|
|
|
for mapping symbols separately from other symbols. Use
|
|
|
|
|
|
struct arm_private_data.
|
|
|
|
|
|
|
Allow VL=1 on scalar FMA instructions.
gas/testsuite/
2010-01-28 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/fma-scalar-intel.d: New.
* gas/i386/fma-scalar.d: Likewise.
* gas/i386/fma-scalar.s: Likewise.
* gas/i386/x86-64-fma-scalar-intel.d: Likewise.
* gas/i386/x86-64-fma-scalar.d: Likewise.
* gas/i386/x86-64-fma-scalar.s: Likewise.
* gas/i386/i386.exp: Run fma-scalar, fma-scalar-intel,
x86-64-fma-scalar and x86-64-fma-scalar-intel.
opcodes/
2010-01-28 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (EXVexWdqScalar): New.
(vex_scalar_w_dq_mode): Likewise.
(prefix_table): Update entries for PREFIX_VEX_3899,
PREFIX_VEX_389B, PREFIX_VEX_389D, PREFIX_VEX_389F,
PREFIX_VEX_38A9, PREFIX_VEX_38AB, PREFIX_VEX_38AD,
PREFIX_VEX_38AF, PREFIX_VEX_38B9, PREFIX_VEX_38BB,
PREFIX_VEX_38BD and PREFIX_VEX_38BF.
(intel_operand_size): Handle vex_scalar_w_dq_mode.
(OP_EX): Likewise.
2010-01-28 23:33:23 +08:00
|
|
|
|
2010-01-28 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (EXVexWdqScalar): New.
|
|
|
|
|
|
(vex_scalar_w_dq_mode): Likewise.
|
|
|
|
|
|
(prefix_table): Update entries for PREFIX_VEX_3899,
|
|
|
|
|
|
PREFIX_VEX_389B, PREFIX_VEX_389D, PREFIX_VEX_389F,
|
|
|
|
|
|
PREFIX_VEX_38A9, PREFIX_VEX_38AB, PREFIX_VEX_38AD,
|
|
|
|
|
|
PREFIX_VEX_38AF, PREFIX_VEX_38B9, PREFIX_VEX_38BB,
|
|
|
|
|
|
PREFIX_VEX_38BD and PREFIX_VEX_38BF.
|
|
|
|
|
|
(intel_operand_size): Handle vex_scalar_w_dq_mode.
|
|
|
|
|
|
(OP_EX): Likewise.
|
|
|
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|
|
Allow VL=1 on AVX scalar instructions.
gas/
2010-01-27 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (avxscalar): New.
(OPTION_MAVXSCALAR): Likewise.
(build_vex_prefix): Select vector_length for scalar instructions
based on avxscalar.
(md_longopts): Add OPTION_MAVXSCALAR.
(md_parse_option): Handle OPTION_MAVXSCALAR.
(md_show_usage): Add -mavxscalar=.
* doc/c-i386.texi: Document -mavxscalar=.
gas/testsuite/
2010-01-27 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/avx-scalar-intel.d: New.
* gas/i386/avx-scalar.d: Likewise.
* gas/i386/avx-scalar.s: Likewise.
* gas/i386/x86-64-avx-scalar-intel.d: Likewise.
* gas/i386/x86-64-avx-scalar.d: Likewise.
* gas/i386/x86-64-avx-scalar.s: Likewise.
* gas/i386/i386.exp: Run avx-scalar, avx-scalar-intel,
x86-64-avx-scalar and x86-64-avx-scalar-intel.
opcodes/
2010-01-27 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (XMScalar): New.
(EXdScalar): Likewise.
(EXqScalar): Likewise.
(EXqScalarS): Likewise.
(VexScalar): Likewise.
(EXdVexScalarS): Likewise.
(EXqVexScalarS): Likewise.
(XMVexScalar): Likewise.
(scalar_mode): Likewise.
(d_scalar_mode): Likewise.
(d_scalar_swap_mode): Likewise.
(q_scalar_mode): Likewise.
(q_scalar_swap_mode): Likewise.
(vex_scalar_mode): Likewise.
(vex_len_table): Duplcate entries for VEX_LEN_10_P_1,
VEX_LEN_10_P_3, VEX_LEN_11_P_1, VEX_LEN_11_P_3, VEX_LEN_2A_P_1,
VEX_LEN_2A_P_3, VEX_LEN_2C_P_3, VEX_LEN_2D_P_1, VEX_LEN_2E_P_0,
VEX_LEN_2E_P_2, VEX_LEN_2F_P_2, VEX_LEN_51_P_1, VEX_LEN_51_P_3,
VEX_LEN_52_P_1, VEX_LEN_53_P_1, VEX_LEN_58_P_1, VEX_LEN_58_P_3,
VEX_LEN_59_P_1, VEX_LEN_5A_P_1, VEX_LEN_5A_P_3, VEX_LEN_5C_P_1,
VEX_LEN_5C_P_3, VEX_LEN_5D_P_1, VEX_LEN_5D_P_3, VEX_LEN_5E_P_1,
VEX_LEN_5E_P_3, VEX_LEN_5F_P_1, VEX_LEN_5F_P_3, VEX_LEN_6E_P_2,
VEX_LEN_7E_P_1, VEX_LEN_7E_P_2, VEX_LEN_D6_P_2, VEX_LEN_C2_P_1,
VEX_LEN_C2_P_3, VEX_LEN_3A0A_P_2 and VEX_LEN_3A0B_P_2.
(vex_w_table): Update entries for VEX_W_10_P_1, VEX_W_10_P_3,
VEX_W_11_P_1, VEX_W_11_P_3, VEX_W_2E_P_0, VEX_W_2E_P_2,
VEX_W_2F_P_0, VEX_W_2F_P_2, VEX_W_51_P_1, VEX_W_51_P_3,
VEX_W_52_P_1, VEX_W_53_P_1, VEX_W_58_P_1, VEX_W_58_P_3,
VEX_W_59_P_1, VEX_W_59_P_3, VEX_W_5A_P_1, VEX_W_5A_P_3,
VEX_W_5C_P_1, VEX_W_5C_P_3, VEX_W_5D_P_1, VEX_W_5D_P_3,
VEX_W_5E_P_1, VEX_W_5E_P_3, VEX_W_5F_P_1, VEX_W_5F_P_3,
VEX_W_7E_P_1, VEX_W_D6_P_2 VEX_W_C2_P_1, VEX_W_C2_P_3,
VEX_W_3A0A_P_2 and VEX_W_3A0B_P_2.
(intel_operand_size): Handle d_scalar_mode, d_scalar_swap_mode,
q_scalar_mode, q_scalar_swap_mode.
(OP_XMM): Handle scalar_mode.
(OP_EX): Handle d_scalar_mode, d_scalar_swap_mode, q_scalar_mode
and q_scalar_swap_mode.
(OP_VEX): Handle vex_scalar_mode.
2010-01-27 22:34:40 +08:00
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2010-01-27 H.J. Lu <hongjiu.lu@intel.com>
|
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* i386-dis.c (XMScalar): New.
|
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(EXdScalar): Likewise.
|
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(EXqScalar): Likewise.
|
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(EXqScalarS): Likewise.
|
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(VexScalar): Likewise.
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(EXdVexScalarS): Likewise.
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(EXqVexScalarS): Likewise.
|
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(XMVexScalar): Likewise.
|
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(scalar_mode): Likewise.
|
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(d_scalar_mode): Likewise.
|
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(d_scalar_swap_mode): Likewise.
|
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(q_scalar_mode): Likewise.
|
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(q_scalar_swap_mode): Likewise.
|
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(vex_scalar_mode): Likewise.
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(vex_len_table): Duplcate entries for VEX_LEN_10_P_1,
|
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VEX_LEN_10_P_3, VEX_LEN_11_P_1, VEX_LEN_11_P_3, VEX_LEN_2A_P_1,
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VEX_LEN_2A_P_3, VEX_LEN_2C_P_3, VEX_LEN_2D_P_1, VEX_LEN_2E_P_0,
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VEX_LEN_2E_P_2, VEX_LEN_2F_P_2, VEX_LEN_51_P_1, VEX_LEN_51_P_3,
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VEX_LEN_52_P_1, VEX_LEN_53_P_1, VEX_LEN_58_P_1, VEX_LEN_58_P_3,
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VEX_LEN_59_P_1, VEX_LEN_5A_P_1, VEX_LEN_5A_P_3, VEX_LEN_5C_P_1,
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VEX_LEN_5C_P_3, VEX_LEN_5D_P_1, VEX_LEN_5D_P_3, VEX_LEN_5E_P_1,
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VEX_LEN_5E_P_3, VEX_LEN_5F_P_1, VEX_LEN_5F_P_3, VEX_LEN_6E_P_2,
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VEX_LEN_7E_P_1, VEX_LEN_7E_P_2, VEX_LEN_D6_P_2, VEX_LEN_C2_P_1,
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VEX_LEN_C2_P_3, VEX_LEN_3A0A_P_2 and VEX_LEN_3A0B_P_2.
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(vex_w_table): Update entries for VEX_W_10_P_1, VEX_W_10_P_3,
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VEX_W_11_P_1, VEX_W_11_P_3, VEX_W_2E_P_0, VEX_W_2E_P_2,
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VEX_W_2F_P_0, VEX_W_2F_P_2, VEX_W_51_P_1, VEX_W_51_P_3,
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VEX_W_52_P_1, VEX_W_53_P_1, VEX_W_58_P_1, VEX_W_58_P_3,
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VEX_W_59_P_1, VEX_W_59_P_3, VEX_W_5A_P_1, VEX_W_5A_P_3,
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VEX_W_5C_P_1, VEX_W_5C_P_3, VEX_W_5D_P_1, VEX_W_5D_P_3,
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VEX_W_5E_P_1, VEX_W_5E_P_3, VEX_W_5F_P_1, VEX_W_5F_P_3,
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VEX_W_7E_P_1, VEX_W_D6_P_2 VEX_W_C2_P_1, VEX_W_C2_P_3,
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VEX_W_3A0A_P_2 and VEX_W_3A0B_P_2.
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(intel_operand_size): Handle d_scalar_mode, d_scalar_swap_mode,
|
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q_scalar_mode, q_scalar_swap_mode.
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(OP_XMM): Handle scalar_mode.
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(OP_EX): Handle d_scalar_mode, d_scalar_swap_mode, q_scalar_mode
|
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and q_scalar_swap_mode.
|
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(OP_VEX): Handle vex_scalar_mode.
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2010-01-25 07:22:43 +08:00
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2010-01-24 H.J. Lu <hongjiu.lu@intel.com>
|
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* i386-dis.c (prefix_table): Remove trailing { Bad_Opcode }.
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2010-01-25 05:35:13 +08:00
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2010-01-24 H.J. Lu <hongjiu.lu@intel.com>
|
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* i386-dis.c (vex_len_table): Remove trailing { Bad_Opcode }.
|
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2010-01-25 04:39:40 +08:00
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2010-01-24 H.J. Lu <hongjiu.lu@intel.com>
|
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* i386-dis.c (prefix_table): Remove trailing { Bad_Opcode }.
|
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2010-01-25 02:24:23 +08:00
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2010-01-24 H.J. Lu <hongjiu.lu@intel.com>
|
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|
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* i386-dis.c (Bad_Opcode): New.
|
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(bad_opcode): Likewise.
|
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(dis386): Replace { "(bad)", { XX } } with { Bad_Opcode }.
|
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(dis386_twobyte): Likewise.
|
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(reg_table): Likewise.
|
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(prefix_table): Likewise.
|
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(x86_64_table): Likewise.
|
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(vex_len_table): Likewise.
|
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(vex_w_table): Likewise.
|
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(mod_table): Likewise.
|
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(rm_table): Likewise.
|
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(float_reg): Likewise.
|
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(reg_table): Remove trailing "(bad)" entries.
|
|
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(prefix_table): Likewise.
|
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(x86_64_table): Likewise.
|
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(vex_len_table): Likewise.
|
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(vex_w_table): Likewise.
|
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(mod_table): Likewise.
|
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(rm_table): Likewise.
|
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(get_valid_dis386): Handle bytemode 0.
|
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2010-01-24 08:59:13 +08:00
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2010-01-23 H.J. Lu <hongjiu.lu@intel.com>
|
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* i386-opc.h (VEXScalar): New.
|
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* i386-opc.tbl: Replace "Vex" with "Vex=3" on AVX scalar
|
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|
instructions.
|
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* i386-tbl.h: Regenerated.
|
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2010-01-22 01:32:32 +08:00
|
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|
2010-01-21 H.J. Lu <hongjiu.lu@intel.com>
|
2010-01-22 01:30:14 +08:00
|
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* i386-dis.c (mod_table): Use FXSAVE on xsave and xrstor.
|
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* i386-opc.tbl: Add xsave64 and xrstor64.
|
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|
* i386-tbl.h: Regenerated.
|
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|
2010-01-20 18:54:03 +08:00
|
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|
2010-01-20 Nick Clifton <nickc@redhat.com>
|
|
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|
PR 11170
|
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* arm-dis.c (print_arm_address): Do not ignore negative bit in PC
|
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|
based post-indexed addressing.
|
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2010-01-16 05:24:13 +08:00
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|
2010-01-15 Sebastian Pop <sebastian.pop@amd.com>
|
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|
* i386-opc.tbl: Support all the possible aliases for VPCOM* insns.
|
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|
* i386-tbl.h: Regenerated.
|
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|
2010-01-15 03:35:36 +08:00
|
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|
2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
|
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|
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* i386-opc.h (VexVVVV): Replace VEX.DNS with VEX.NDS in
|
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|
comments.
|
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|
2010-01-15 01:29:18 +08:00
|
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|
2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
|
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|
|
|
|
|
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|
|
* i386-dis.c (names_mm): New.
|
|
|
|
|
|
(intel_names_mm): Likewise.
|
|
|
|
|
|
(att_names_mm): Likewise.
|
|
|
|
|
|
(names_xmm): Likewise.
|
|
|
|
|
|
(intel_names_xmm): Likewise.
|
|
|
|
|
|
(att_names_xmm): Likewise.
|
|
|
|
|
|
(names_ymm): Likewise.
|
|
|
|
|
|
(intel_names_ymm): Likewise.
|
|
|
|
|
|
(att_names_ymm): Likewise.
|
|
|
|
|
|
(print_insn): Set names_mm, names_xmm and names_ymm.
|
|
|
|
|
|
(OP_MMX): Use names_mm, names_xmm and names_ymm.
|
|
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|
|
|
(OP_XMM): Likewise.
|
|
|
|
|
|
(OP_EM): Likewise.
|
|
|
|
|
|
(OP_EMC): Likewise.
|
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|
|
(OP_MXC): Likewise.
|
|
|
|
|
|
(OP_EX): Likewise.
|
|
|
|
|
|
(XMM_Fixup): Likewise.
|
|
|
|
|
|
(OP_VEX): Likewise.
|
|
|
|
|
|
(OP_EX_VexReg): Likewise.
|
|
|
|
|
|
(OP_Vex_2src): Likewise.
|
|
|
|
|
|
(OP_Vex_2src_1): Likewise.
|
|
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|
|
|
(OP_Vex_2src_2): Likewise.
|
|
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|
|
(OP_REG_VexI4): Likewise.
|
|
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|
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|
|
2010-01-14 00:06:12 +08:00
|
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|
2010-01-13 H.J. Lu <hongjiu.lu@intel.com>
|
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|
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* i386-dis.c (print_insn): Update comments.
|
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|
2010-01-13 12:03:20 +08:00
|
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|
2010-01-12 H.J. Lu <hongjiu.lu@intel.com>
|
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|
|
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|
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|
|
* i386-dis.c (rex_original): Removed.
|
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|
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|
(ckprefix): Remove rex_original.
|
|
|
|
|
|
(print_insn): Update comments.
|
|
|
|
|
|
|
2010-01-10 05:11:44 +08:00
|
|
|
|
2010-01-09 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
|
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|
|
|
|
|
|
|
|
|
|
* Makefile.in: Regenerate.
|
|
|
|
|
|
* configure: Regenerate.
|
|
|
|
|
|
|
* cgen-ibld.in (insert_normal, extract_normal): Minor cleanup.
* fr30-ibld.c, * frv-ibld.c, * ip2k-ibld.c, * iq2000-ibld.c,
* lm32-ibld.c, * m32c-ibld.c, * m32r-ibld.c, * mep-ibld.c,
* mt-ibld.c, * openrisc-ibld.c, * xc16x-ibld.c,
* xstormy16-ibld.c: Regenerate.
2010-01-08 02:05:45 +08:00
|
|
|
|
2010-01-07 Doug Evans <dje@sebabeach.org>
|
|
|
|
|
|
|
|
|
|
|
|
* cgen-ibld.in (insert_normal, extract_normal): Minor cleanup.
|
|
|
|
|
|
* fr30-ibld.c, * frv-ibld.c, * ip2k-ibld.c, * iq2000-ibld.c,
|
|
|
|
|
|
* lm32-ibld.c, * m32c-ibld.c, * m32r-ibld.c, * mep-ibld.c,
|
|
|
|
|
|
* mt-ibld.c, * openrisc-ibld.c, * xc16x-ibld.c,
|
|
|
|
|
|
* xstormy16-ibld.c: Regenerate.
|
|
|
|
|
|
|
2010-01-07 06:52:47 +08:00
|
|
|
|
2010-01-06 Quentin Neill <quentin.neill@amd.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-gen.c (cpu_flag_init): Add new CPU_AMDFAM15_FLAGS.
|
|
|
|
|
|
* i386-init.h: Regenerated.
|
|
|
|
|
|
|
2010-01-06 23:02:45 +08:00
|
|
|
|
2010-01-06 Daniel Gutson <dgutson@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c (print_insn): Fixed search for next symbol and data
|
|
|
|
|
|
dumping condition, and the initial mapping symbol state.
|
|
|
|
|
|
|
cpu/
* m32c.cpu (f-dsp-32-u24): Fix mode of extract handler.
(f-dsp-40-u20, f-dsp-40-u24): Ditto.
opcodes/
* cgen-ibld.in: #include "cgen/basic-modes.h".
* fr30-ibld.c, * frv-ibld.c, * ip2k-ibld.c, * iq2000-ibld.c,
* lm32-ibld.c, * m32c-ibld.c, * m32r-ibld.c, * mep-ibld.c,
* mt-ibld.c, * openrisc-ibld.c, * xc16x-ibld.c,
* xstormy16-ibld.c: Regenerate.
2010-01-06 13:30:19 +08:00
|
|
|
|
2010-01-05 Doug Evans <dje@sebabeach.org>
|
|
|
|
|
|
|
|
|
|
|
|
* cgen-ibld.in: #include "cgen/basic-modes.h".
|
|
|
|
|
|
* fr30-ibld.c, * frv-ibld.c, * ip2k-ibld.c, * iq2000-ibld.c,
|
|
|
|
|
|
* lm32-ibld.c, * m32c-ibld.c, * m32r-ibld.c, * mep-ibld.c,
|
|
|
|
|
|
* mt-ibld.c, * openrisc-ibld.c, * xc16x-ibld.c,
|
|
|
|
|
|
* xstormy16-ibld.c: Regenerate.
|
|
|
|
|
|
|
2010-01-04 18:18:32 +08:00
|
|
|
|
2010-01-04 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
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PR 11123
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* arm-dis.c (print_insn_coprocessor): Initialise value.
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2010-01-04 10:32:56 +08:00
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2010-01-04 Edmar Wienskoski <edmar@freescale.com>
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* ppc-dis.c (ppc_opts): Add entry for "e500mc64".
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* cgen-asm.in: Update copyright year.
* cgen-dis.in: Update copyright year.
* cgen-ibld.in: Update copyright year.
* fr30-asm.c, * fr30-desc.c, * fr30-desc.h, * fr30-dis.c,
* fr30-ibld.c, * fr30-opc.c, * fr30-opc.h, * frv-asm.c, * frv-desc.c,
* frv-desc.h, * frv-dis.c, * frv-ibld.c, * frv-opc.c, * frv-opc.h,
* ip2k-asm.c, * ip2k-desc.c, * ip2k-desc.h, * ip2k-dis.c,
* ip2k-ibld.c, * ip2k-opc.c, * ip2k-opc.h, * iq2000-asm.c,
* iq2000-desc.c, * iq2000-desc.h, * iq2000-dis.c, * iq2000-ibld.c,
* iq2000-opc.c, * iq2000-opc.h, * lm32-asm.c, * lm32-desc.c,
* lm32-desc.h, * lm32-dis.c, * lm32-ibld.c, * lm32-opc.c, * lm32-opc.h,
* lm32-opinst.c, * m32c-asm.c, * m32c-desc.c, * m32c-desc.h,
* m32c-dis.c, * m32c-ibld.c, * m32c-opc.c, * m32c-opc.h, * m32r-asm.c,
* m32r-desc.c, * m32r-desc.h, * m32r-dis.c, * m32r-ibld.c,
* m32r-opc.c, * m32r-opc.h, * m32r-opinst.c, * mep-asm.c, * mep-desc.c,
* mep-desc.h, * mep-dis.c, * mep-ibld.c, * mep-opc.c, * mep-opc.h,
* mt-asm.c, * mt-desc.c, * mt-desc.h, * mt-dis.c, * mt-ibld.c,
* mt-opc.c, * mt-opc.h, * openrisc-asm.c, * openrisc-desc.c,
* openrisc-desc.h, * openrisc-dis.c, * openrisc-ibld.c,
* openrisc-opc.c, * openrisc-opc.h, * xc16x-asm.c, * xc16x-desc.c,
* xc16x-desc.h, * xc16x-dis.c, * xc16x-ibld.c, * xc16x-opc.c,
* xc16x-opc.h, * xstormy16-asm.c, * xstormy16-desc.c,
* xstormy16-desc.h, * xstormy16-dis.c, * xstormy16-ibld.c,
* xstormy16-opc.c, * xstormy16-opc.h: Regenerate.
2010-01-03 02:50:59 +08:00
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2010-01-02 Doug Evans <dje@sebabeach.org>
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* cgen-asm.in: Update copyright year.
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* cgen-dis.in: Update copyright year.
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* cgen-ibld.in: Update copyright year.
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* fr30-asm.c, * fr30-desc.c, * fr30-desc.h, * fr30-dis.c,
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* fr30-ibld.c, * fr30-opc.c, * fr30-opc.h, * frv-asm.c, * frv-desc.c,
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* frv-desc.h, * frv-dis.c, * frv-ibld.c, * frv-opc.c, * frv-opc.h,
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* ip2k-asm.c, * ip2k-desc.c, * ip2k-desc.h, * ip2k-dis.c,
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* ip2k-ibld.c, * ip2k-opc.c, * ip2k-opc.h, * iq2000-asm.c,
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* iq2000-desc.c, * iq2000-desc.h, * iq2000-dis.c, * iq2000-ibld.c,
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* iq2000-opc.c, * iq2000-opc.h, * lm32-asm.c, * lm32-desc.c,
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* lm32-desc.h, * lm32-dis.c, * lm32-ibld.c, * lm32-opc.c, * lm32-opc.h,
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* lm32-opinst.c, * m32c-asm.c, * m32c-desc.c, * m32c-desc.h,
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* m32c-dis.c, * m32c-ibld.c, * m32c-opc.c, * m32c-opc.h, * m32r-asm.c,
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* m32r-desc.c, * m32r-desc.h, * m32r-dis.c, * m32r-ibld.c,
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* m32r-opc.c, * m32r-opc.h, * m32r-opinst.c, * mep-asm.c, * mep-desc.c,
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* mep-desc.h, * mep-dis.c, * mep-ibld.c, * mep-opc.c, * mep-opc.h,
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* mt-asm.c, * mt-desc.c, * mt-desc.h, * mt-dis.c, * mt-ibld.c,
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* mt-opc.c, * mt-opc.h, * openrisc-asm.c, * openrisc-desc.c,
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* openrisc-desc.h, * openrisc-dis.c, * openrisc-ibld.c,
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* openrisc-opc.c, * openrisc-opc.h, * xc16x-asm.c, * xc16x-desc.c,
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* xc16x-desc.h, * xc16x-dis.c, * xc16x-ibld.c, * xc16x-opc.c,
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* xc16x-opc.h, * xstormy16-asm.c, * xstormy16-desc.c,
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* xstormy16-desc.h, * xstormy16-dis.c, * xstormy16-ibld.c,
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* xstormy16-opc.c, * xstormy16-opc.h: Regenerate.
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2009-12-20 02:36:27 +08:00
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2010-01-02 02:06:10 +08:00
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For older changes see ChangeLog-2009
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1999-05-03 15:29:11 +08:00
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Local Variables:
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2001-01-12 03:01:42 +08:00
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mode: change-log
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left-margin: 8
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fill-column: 74
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1999-05-03 15:29:11 +08:00
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version-control: never
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End:
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