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binutils-gdb/opcodes/ChangeLog

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Updated translations for some subdirectories
2021-01-12 21:18:50 +08:00
2021-01-12 Nick Clifton <nickc@redhat.com>
* po/sr.po: Updated Serbian translation.
Binutils: Check if AR works with --plugin and rc Check if AR works with --plugin and rc before passing --plugin to AR and RANLIB. bfd/ PR ld/27173 binutils/ PR ld/27173 * configure: Regenerated. gas/ PR ld/27173 * configure: Regenerated. gprof/ PR ld/27173 * configure: Regenerated. ld/ PR ld/27173 * configure: Regenerated. libctf/ PR ld/27173 * configure: Regenerated. opcodes/ PR ld/27173 * configure: Regenerated.
2021-01-12 08:29:31 +08:00
2021-01-11 H.J. Lu <hongjiu.lu@intel.com>
PR ld/27173
* configure: Regenerated.
aarch64: Remove support for CSRE This patch removes support for the CSRE extension from aarch64 gas/objdump. CSRE (FEAT_CSRE) is part of the Future Architecture Technologies program and at this time Arm is withdrawing this particular feature. The patch removes the system registers and the CSR PDEC instruction. gas/ChangeLog * NEWS: Remove CSRE. * config/tc-aarch64.c (parse_csr_operand): Delete. (parse_operands): Delete handling of AARCH64_OPND_CSRE_CSR. (aarch64_features): Remove csre. * doc/c-aarch64.texi: Remove CSRE. * testsuite/gas/aarch64/csre.d: Delete. * testsuite/gas/aarch64/csre-invalid.s: Likewise. * testsuite/gas/aarch64/csre-invalid.d: Likewise. * testsuite/gas/aarch64/csre_csr.s: Likewise. * testsuite/gas/aarch64/csre_csr.d: Likewise. * testsuite/gas/aarch64/csre_csr-invalid.s: Likewise. * testsuite/gas/aarch64/csre_csr-invalid.l: Likewise. * testsuite/gas/aarch64/csre_csr-invalid.d: Likewise. include/ChangeLog * opcode/aarch64.h (AARCH64_FEATURE_CSRE): Delete. (aarch64_opnd): Delete AARCH64_OPND_CSRE_CSR. opcodes/ChangeLog * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Likewise. * aarch64-opc-2.c: Likewise. * aarch64-opc.c (aarch64_print_operand): Delete handling of AARCH64_OPND_CSRE_CSR. * aarch64-tbl.h (aarch64_feature_csre): Delete. (CSRE): Likewise. (_CSRE_INSN): Likewise. (aarch64_opcode_table): Delete csr.
2021-01-06 01:39:04 +08:00
2021-01-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Likewise.
* aarch64-opc-2.c: Likewise.
* aarch64-opc.c (aarch64_print_operand):
Delete handling of AARCH64_OPND_CSRE_CSR.
* aarch64-tbl.h (aarch64_feature_csre): Delete.
(CSRE): Likewise.
(_CSRE_INSN): Likewise.
(aarch64_opcode_table): Delete csr.
Updated translations for multiple subdirectories
2021-01-11 20:55:33 +08:00
2021-01-11 Nick Clifton <nickc@redhat.com>
* po/de.po: Updated German translation.
* po/fr.po: Updated French translation.
* po/pt_BR.po: Updated Brazilian Portuguese translation.
* po/sv.po: Updated Swedish translation.
* po/uk.po: Updated Ukranian translation.
Binutils: Pass --plugin to AR and RANLIB Detect GCC LTO plugin. Pass --plugin to AR and RANLIB to support LTO build. bfd/ * configure: Regenerated. binutils/ * configure: Regenerated. gas/ * configure: Regenerated. gprof/ * configure: Regenerated. ld/ * configure: Regenerated. libctf/ * configure: Regenerated. opcodes/ * configure: Regenerated.
2021-01-09 22:47:58 +08:00
2021-01-09 H.J. Lu <hongjiu.lu@intel.com>
* configure: Regenerated.
Change version number to 2.36.50 and regenerate files
2021-01-09 19:01:01 +08:00
2021-01-09 Nick Clifton <nickc@redhat.com>
* configure: Regenerate.
* po/opcodes.pot: Regenerate.
Add Changelog entries and NEWS entries for 2.36 branch
2021-01-09 18:40:28 +08:00
2021-01-09 Nick Clifton <nickc@redhat.com>
* 2.36 release branch crated.
POWER10: Add Return-Oriented Programming instructions POWER10 adds some return-oriented programming (ROP) instructions and this patch adds support for them. You will notice that they are enabled for POWER8 and later, not just POWER10 and later. This is on purpose. This allows the instructions to be added to POWER8 binaries that can be run on POWER8, POWER9 and POWER10 cpus. On POWER8 and POWER9, these instructions just act as nop's. opcodes/ * ppc-opc.c (insert_dw, (extract_dw): New functions. (DW, (XRC_MASK): Define. (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics. gas/ * testsuite/gas/ppc/rop-checks.d, * testsuite/gas/ppc/rop-checks.l, * testsuite/gas/ppc/rop-checks.s, * testsuite/gas/ppc/rop.d, * testsuite/gas/ppc/rop.s: New tests. * testsuite/gas/ppc/ppc.exp: Run them.
2021-01-09 06:07:12 +08:00
2021-01-08 Peter Bergner <bergner@linux.ibm.com>
* ppc-opc.c (insert_dw, (extract_dw): New functions.
(DW, (XRC_MASK): Define.
(powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
configure regen commit f478212851 did the regen by hand, missed a change in ld/configure and didn't update line numbers. Fix that, and an old regen of ld/Makefile.in with the wrong automake. bfd/ * configure: Regenerate. binutils/ * configure: Regenerate. gas/ * configure: Regenerate. gprof/ * configure: Regenerate. ld/ * Makefile.in: Regenerate. * configure: Regenerate. libctf/ * configure: Regenerate. opcodes/ * configure: Regenerate. zlib/ * configure: Regenerate.
2021-01-09 08:33:29 +08:00
2021-01-09 Alan Modra <amodra@gmail.com>
* configure: Regenerate.
Updated Swedish translation for the opcodes/ subdirectory
2021-01-08 19:55:44 +08:00
2021-01-08 Nick Clifton <nickc@redhat.com>
* po/sv.po: Updated Swedish translation.
Treat the AArch64 register id_aa64mmfr2_el1 as a core system register. PR 27139 * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a core system register.
2021-01-08 19:29:43 +08:00
2021-01-08 Nick Clifton <nickc@redhat.com>
Fix places in the AArch64 opcodes library code where a call to assert() has side effects. PR 27129 * aarch64-dis.c (determine_disassembling_preference): Move call to aarch64_match_operands_constraint outside of the assertion. * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert. Replace with a return of FALSE.
2021-01-08 19:51:50 +08:00
PR 27129
* aarch64-dis.c (determine_disassembling_preference): Move call to
aarch64_match_operands_constraint outside of the assertion.
* aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
Replace with a return of FALSE.
Treat the AArch64 register id_aa64mmfr2_el1 as a core system register. PR 27139 * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a core system register.
2021-01-08 19:29:43 +08:00
PR 27139
* aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
core system register.
libtool.m4: update GNU/Hurd test from upstream. In upstream libtool, 47a889a4ca20 ("Improve GNU/Hurd support.") fixed detection of shlibpath_overrides_runpath, thus avoiding unnecessary relink. This backports it. . * libtool.m4: Match gnu* along other GNU systems. */ChangeLog: * configure: Re-generate.
2021-01-08 00:47:36 +08:00
2021-01-07 Samuel Thibault <samuel.thibault@gnu.org>
* configure: Regenerate.
Updated French translation for the opcodes/ subdirectory.
2021-01-07 22:47:20 +08:00
2021-01-07 Nick Clifton <nickc@redhat.com>
* po/fr.po: Updated French translation.
m68k: Require m68020up rather than m68000up for CHK.L instruction. * m68k-opc.c (chkl): Change minimum architecture requirement to m68020.
2021-01-07 22:44:27 +08:00
2021-01-07 Fredrik Noring <noring@nocrew.org>
* m68k-opc.c (chkl): Change minimum architecture requirement to
m68020.
RISC-V: Add pause hint instruction. Add support for the pause hint instruction, as specified in the Zihintpause extension. The pause instruction is encoded as a special form of a memory fence (which is available as part of the base instruction set). The chosen encoding does not mandate any particular memory ordering and therefore is a true hint. bfd/ * elfxx-riscv.c (riscv_std_z_ext_strtab): Added zihintpause. gas/ * config/tc-riscv.c (riscv_multi_subset_supports): Added INSN_CLASS_ZIHINTPAUSE. * testsuite/gas/riscv/pause.d: New testcase. Adding coverage for the pause hint instruction. * testsuite/gas/riscv/pause.s: Likewise. include/ * opcode/riscv-opc.h: Added MATCH_PAUSE, MASK_PAUSE and DECLARE_INSN for pause hint instruction. * opcode/riscv.h (enum riscv_insn_class): Added INSN_CLASS_ZIHINTPAUSE. opcodes/ * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
2021-01-07 15:53:25 +08:00
2021-01-07 Philipp Tomsich <prt@gnu.org>
* riscv-opc.c (riscv_opcodes): Add pause hint instruction.
RISC-V: Support riscv bitmanip frozen ZBA/ZBB/ZBC instructions (v0.93). In fact rev8/orc.b/zext.h are the aliases of grevi/gorci/pack[w], so we should update them to INSN_ALIAS when we have supported their true instruction in the future. Though we still use the [MATCH|MAKS]_[GREVI|GORCI|PACK|PACKW] to encode them. Besides, the orc.b has the same encoding both in rv32 and rv64, so we just keep one of them in the opcode table. This patch is implemented according to the following link, https://github.com/riscv/riscv-bitmanip/pull/101 2021-01-07 Claire Xenia Wolf <claire@symbioticeda.com> Jim Wilson <jimw@sifive.com> Andrew Waterman <andrew@sifive.com> Maxim Blinov <maxim.blinov@embecosm.com> Kito Cheng <kito.cheng@sifive.com> Nelson Chu <nelson.chu@sifive.com> bfd/ * elfxx-riscv.c (riscv_std_z_ext_strtab): Added zba, zbb and zbc. gas/ * config/tc-riscv.c (riscv_multi_subset_supports): Handle INSN_CLASS_ZB*. (riscv_get_default_ext_version): Do not check the default_isa_spec when the version defined in the riscv_opcodes table is ISA_SPEC_CLASS_DRAFT. * testsuite/gas/riscv/bitmanip-insns-32.d: New testcase. * testsuite/gas/riscv/bitmanip-insns-64.d: Likewise. * testsuite/gas/riscv/bitmanip-insns.s: Likewise. include/ * opcode/riscv-opc.h: Added MASK/MATCH/DECLARE_INSN for ZBA/ZBB/ZBC. * opcode/riscv.h (riscv_insn_class): Added INSN_CLASS_ZB*. (enum riscv_isa_spec_class): Added ISA_SPEC_CLASS_DRAFT for the frozen extensions. opcodes/ * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions. (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
2020-12-15 23:11:03 +08:00
2021-01-07 Claire Xenia Wolf <claire@symbioticeda.com>
Jim Wilson <jimw@sifive.com>
Andrew Waterman <andrew@sifive.com>
Maxim Blinov <maxim.blinov@embecosm.com>
Kito Cheng <kito.cheng@sifive.com>
Nelson Chu <nelson.chu@sifive.com>
* riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
(MASK_RVB_IMM): Used for rev8 and orc.b encoding.
Update year range in copyright notice of binutils files
2021-01-01 06:58:58 +08:00
2021-01-01 Alan Modra <amodra@gmail.com>
Update year range in copyright notice of all files.
ChangeLog rotation
2021-01-01 06:47:13 +08:00
For older changes see ChangeLog-2020
New 2016 binutils ChangeLog files Note that this does not create bfd/doc/ChangeLog, */testsuite/ChangeLog and include/*/ChangeLog files.
2016-01-01 18:44:31 +08:00
ChangeLog rotation
2021-01-01 06:47:13 +08:00
Copyright (C) 2021 Free Software Foundation, Inc.
New 2016 binutils ChangeLog files Note that this does not create bfd/doc/ChangeLog, */testsuite/ChangeLog and include/*/ChangeLog files.
2016-01-01 18:44:31 +08:00
Copying and distribution of this file, with or without modification,
are permitted in any medium without royalty provided the copyright
notice and this notice are preserved.
Local Variables:
mode: change-log
left-margin: 8
fill-column: 74
version-control: never
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