2024-07-20 19:43:19 +08:00
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2024-07-20 Nick Clifton <nickc@redhat.com>
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* 2.43 branch point.
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2024-01-15 22:42:15 +08:00
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2024-01-15 Nick Clifton <nickc@redhat.com>
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* 2.42 branch point.
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2023-07-03 18:12:15 +08:00
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2023-07-03 Nick Clifton <nickc@redhat.com>
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2024-07-20 19:43:19 +08:00
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* 2.41 Branch Point.
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2023-07-03 18:12:15 +08:00
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2023-03-15 21:06:23 +08:00
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2023-03-15 Nick Clifton <nickc@redhat.com>
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PR 30231
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* mep.opc (mep_print_insn): Check for an out of range index.
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2022-12-31 20:05:28 +08:00
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2022-12-31 Nick Clifton <nickc@redhat.com>
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* 2.40 branch created.
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2022-07-08 17:41:07 +08:00
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2022-07-08 Nick Clifton <nickc@redhat.com>
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* 2.39 branch created.
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2022-01-22 20:08:55 +08:00
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2022-01-22 Nick Clifton <nickc@redhat.com>
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* 2.38 release branch created.
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2021-07-03 10:09:24 +08:00
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2021-07-05 Alan Modra <amodra@gmail.com>
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* mep.opc (macros): Make static and const.
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(lookup_macro): Return and use const pointer.
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(expand_macro): Make mac param const.
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(expand_string): Make pmacro const.
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2021-07-03 21:50:57 +08:00
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2021-07-03 Nick Clifton <nickc@redhat.com>
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* 2.37 release branch created.
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2021-05-06 19:51:24 +08:00
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2021-05-06 Stafford Horne <shorne@gmail.com>
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PR 21464
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* or1k.opc (or1k_imm16_relocs, parse_reloc): Define parse logic
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for gotha() relocation.
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Use bool in opcodes
cpu/
* frv.opc: Replace bfd_boolean with bool, FALSE with false, and
TRUE with true throughout.
opcodes/
* sysdep.h (POISON_BFD_BOOLEAN): Define.
* aarch64-asm-2.c, * aarch64-asm.c, * aarch64-asm.h,
* aarch64-dis-2.c, * aarch64-dis.c, * aarch64-dis.h,
* aarch64-gen.c, * aarch64-opc.c, * aarch64-opc.h, * arc-dis.c,
* arc-dis.h, * arc-fxi.h, * arc-opc.c, * arm-dis.c, * bfin-dis.c,
* cris-dis.c, * csky-dis.c, * csky-opc.h, * dis-buf.c,
* disassemble.c, * frv-opc.c, * frv-opc.h, * h8300-dis.c,
* i386-dis.c, * m68k-dis.c, * metag-dis.c, * microblaze-dis.c,
* microblaze-dis.h, * micromips-opc.c, * mips-dis.c,
* mips-formats.h, * mips-opc.c, * mips16-opc.c, * mmix-dis.c,
* msp430-dis.c, * nds32-dis.c, * nfp-dis.c, * nios2-dis.c,
* ppc-dis.c, * riscv-dis.c, * score-dis.c, * score7-dis.c,
* tic6x-dis.c, * v850-dis.c, * vax-dis.c, * wasm32-dis.c,
* xtensa-dis.c: Replace bfd_boolean with bool, FALSE with false,
and TRUE with true throughout.
2021-03-31 08:06:19 +08:00
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2021-03-31 Alan Modra <amodra@gmail.com>
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* frv.opc: Replace bfd_boolean with bool, FALSE with false, and
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TRUE with true throughout.
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2021-03-29 07:14:48 +08:00
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2021-03-29 Alan Modra <amodra@gmail.com>
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* frv.opc (frv_is_branch_major, frv_is_float_major),
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(frv_is_media_major, frv_is_branch_insn, frv_is_float_insn),
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(frv_is_media_insn, spr_valid): Correct prototypes.
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2021-01-09 18:40:28 +08:00
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2021-01-09 Nick Clifton <nickc@redhat.com>
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* 2.36 release branch crated.
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2020-10-05 21:20:15 +08:00
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2020-10-05 Samanta Navarro <ferivoz@riseup.net>
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* m32r.cpu: Fix spelling mistakes.
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2020-09-19 00:56:43 +08:00
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2020-09-18 David Faust <david.faust@oracle.com>
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* bpf.cpu (insn-op-code-alu): Add SDIV and SMOD.
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(define-alu-insn-bin, daib): Take ISAs as an argument.
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(define-alu-instructions): Update calls to daib pmacro with
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ISAs; add sdiv and smod.
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2020-09-09 02:39:07 +08:00
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2020-09-08 David Faust <david.faust@oracle.com>
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* bpf.cpu (define-alu-instructions): Correct semantic operators
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for div, mod to unsigned versions.
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2020-09-01 06:18:02 +08:00
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2020-09-01 Alan Modra <amodra@gmail.com>
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* mep-core.cpu (f-8s8a2, f-12s4a2, f-17s16a2): Multiply signed
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value by two rather than shifting left.
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(f-24s5a2n): Similarly multiply signed f-24s5a2n-hi to extract.
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bpf: add xBPF ISA
This patch adds support for xBPF, another ISA targetting the BPF
virtual architecture. For now, the primary difference between eBPF
and xBPF is that xBPF supports indirect calls through the
'call %reg' form of the call instruction.
bfd/
* archures.c (bfd_mach_xbpf): Define.
* bfd-in2.h: Regenerate.
* cpu-bpf.c (bfd_xbpf_arch) New.
(bfd_bpf_arch) Update next in list field to point to xbpf arch.
cpu/
* bpf.cpu (arch bpf): Add xbpf mach and isas.
(define-xbpf-isa) New pmacro.
(all-isas) Add xbpfle,xbpfbe.
(endian-isas): New pmacro.
(mach xbpf): New.
(model xbpf-def): Likewise.
(h-gpr): Add xbpf mach.
(f-dstle, f-srcle, dstle, srcle): Add xbpfle isa.
(f-dstbe, f-srcbe, dstbe, srcbe): Add xbpfbe isa.
(define-alu-insn-un): Use new endian-isas pmacro.
(define-alu-insn-bin, define-alu-insn-mov): Likewise.
(define-endian-insn, define-lddw): Likewise.
(dlind, dxli, dxsi, dsti): Likewise.
(define-cond-jump-insn, define-call-insn): Likewise.
(define-atomic-insns): Likewise.
gas/
* config/tc-bpf.c: Add option -mxbpf to select xbpf isa.
* testsuite/gas/bpf/indcall-1.d: New file.
* testsuite/gas/bpf/indcall-1.s: Likewise.
* testsuite/gas/bpf/indcall-bad-1.l: Likewise.
* testsuite/gas/bpf/indcall-bad-1.s: Likewise.
* testsuite/gas/bpf/bpf.exp: Run new tests.
opcodes/
* bpf-desc.c: Regenerate.
* bpf-desc.h: Likewise.
* bpf-opc.c: Likewise.
* bpf-opc.h: Likewise.
* disassemble.c (disassemble_init_for_target): Set bits for xBPF
ISA when appropriate.
2020-08-26 21:39:00 +08:00
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2020-08-26 David Faust <david.faust@oracle.com>
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* bpf.cpu (arch bpf): Add xbpf mach and isas.
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(define-xbpf-isa) New pmacro.
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(all-isas) Add xbpfle,xbpfbe.
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(endian-isas): New pmacro.
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(mach xbpf): New.
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(model xbpf-def): Likewise.
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(h-gpr): Add xbpf mach.
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(f-dstle, f-srcle, dstle, srcle): Add xbpfle isa.
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(f-dstbe, f-srcbe, dstbe, srcbe): Add xbpfbe isa.
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(define-alu-insn-un): Use new endian-isas pmacro.
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(define-alu-insn-bin, define-alu-insn-mov): Likewise.
|
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(define-endian-insn, define-lddw): Likewise.
|
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(dlind, dxli, dxsi, dsti): Likewise.
|
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(define-cond-jump-insn, define-call-insn): Likewise.
|
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(define-atomic-insns): Likewise.
|
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2020-07-04 17:16:22 +08:00
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|
2020-07-04 Nick Clifton <nickc@redhat.com>
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Binutils 2.35 branch created.
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2020-06-26 02:34:29 +08:00
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2020-06-25 David Faust <david.faust@oracle.com>
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* bpf.cpu (f-offset16): Change type from INT to HI.
|
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(dxli): Simplify memory access.
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(dxsi): Likewise.
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(define-endian-insn): Update c-call in semantics.
|
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(dlabs) Likewise.
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(dlind) Likewise.
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2020-06-04 22:17:07 +08:00
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2020-06-02 Jose E. Marchesi <jose.marchesi@oracle.com>
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* bpf.cpu (define-bpf-isa): Set base-insn-bitsize to 64.
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* bpf.opc (bpf_print_insn): Do not set endian_code here.
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|
opcodes: discriminate endianness and insn-endianness in CGEN ports
The CGEN support code in opcodes accesses instruction contents using a
couple of functions defined in cgen-opc.c: cgen_get_insn_value and
cgen_put_insn_value. These functions use the "instruction endianness"
in the CPU description to order the read/written bytes.
The process of writing an instruction to the object file is:
a) cgen_put_insn_value ;; Writes out the opcodes.
b) ARCH_cgen_insert_operand
insert_normal
insert_1
cgen_put_insn_value ;; Writes out the bytes of the
;; operand.
Likewise, the process of reading an instruction from the object file
is:
a) cgen_get_insn_value ;; Reads the opcodes.
b) ARCH_cgen_extract_operand
extract_normal
extract_1
cgen_get_insn_value ;; Reads in the bytes of the
;; operand.
As can be seen above, cgen_{get,put}_insn_value are used to both
process the instruction opcodes (the constant fields conforming the
base instruction) and also the values of the instruction operands,
such as immediates.
This is problematic for architectures in which the endianness of
instructions is different to the endianness of data. An example is
BPF, where instructions are always encoded big-endian but the data may
be either big or little.
This patch changes the cgen_{get,put}_insn_value functions in order to
get an extra argument with the endianness to use, and adapts the
existin callers to these functions in order to provide cd->endian or
cd->insn_endian, whatever appropriate. Callers like extract_1 and
insert_1 pass cd->endian (since they are reading/writing operand
values) while callers reading/writing the base instruction pass
cd->insn_endian instead.
A few little adjustments have been needed in some existing CGEN based
ports:
* The BPF assembler uses cgen_put_insn_value. It has been adapted to
pass the new endian argument.
* The mep port has code in mep.opc that uses cgen_{get,put}_insn_value.
It has been adapted to pass the new endianargument. Ditto for a
call in the assembler.
Tested with --enable-targets=all.
Regested in all supported targets.
No regressions.
include/ChangeLog:
2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com>
* opcode/cgen.h: Get an `endian' argument in both
cgen_get_insn_value and cgen_put_insn_value.
opcodes/ChangeLog:
2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com>
* cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
(cgen_put_insn_value): Likewise.
(cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
* cgen-dis.in (print_insn): Likewise.
* cgen-ibld.in (insert_1): Likewise.
(insert_1): Likewise.
(insert_insn_normal): Likewise.
(extract_1): Likewise.
* bpf-dis.c: Regenerate.
* bpf-ibld.c: Likewise.
* bpf-ibld.c: Likewise.
* cgen-dis.in: Likewise.
* cgen-ibld.in: Likewise.
* cgen-opc.c: Likewise.
* epiphany-dis.c: Likewise.
* epiphany-ibld.c: Likewise.
* fr30-dis.c: Likewise.
* fr30-ibld.c: Likewise.
* frv-dis.c: Likewise.
* frv-ibld.c: Likewise.
* ip2k-dis.c: Likewise.
* ip2k-ibld.c: Likewise.
* iq2000-dis.c: Likewise.
* iq2000-ibld.c: Likewise.
* lm32-dis.c: Likewise.
* lm32-ibld.c: Likewise.
* m32c-dis.c: Likewise.
* m32c-ibld.c: Likewise.
* m32r-dis.c: Likewise.
* m32r-ibld.c: Likewise.
* mep-dis.c: Likewise.
* mep-ibld.c: Likewise.
* mt-dis.c: Likewise.
* mt-ibld.c: Likewise.
* or1k-dis.c: Likewise.
* or1k-ibld.c: Likewise.
* xc16x-dis.c: Likewise.
* xc16x-ibld.c: Likewise.
* xstormy16-dis.c: Likewise.
* xstormy16-ibld.c: Likewise.
gas/ChangeLog:
2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com>
* cgen.c (gas_cgen_finish_insn): Pass the endianness to
cgen_put_insn_value.
(gas_cgen_md_apply_fix): Likewise.
(gas_cgen_md_apply_fix): Likewise.
* config/tc-bpf.c (md_apply_fix): Pass data endianness to
cgen_put_insn_value.
* config/tc-mep.c (mep_check_ivc2_scheduling): Pass endianness to
cgen_put_insn_value.
cpu/ChangeLog:
2020-06-02 Jose E. Marchesi <jose.marchesi@oracle.com>
* mep.opc (print_slot_insn): Pass the insn endianness to
cgen_get_insn_value.
2020-06-04 22:15:53 +08:00
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2020-06-02 Jose E. Marchesi <jose.marchesi@oracle.com>
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* mep.opc (print_slot_insn): Pass the insn endianness to
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cgen_get_insn_value.
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2020-05-28 22:53:54 +08:00
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2020-05-28 Jose E. Marchesi <jose.marchesi@oracle.com>
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David Faust <david.faust@oracle.com>
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* bpf.cpu (define-alu-insn-un): Add definitions of semantics.
|
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(define-alu-insn-mov): Likewise.
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(daib): Likewise.
|
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(define-alu-instructions): Likewise.
|
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(define-endian-insn): Likewise.
|
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(define-lddw): Likewise.
|
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(dlabs): Likewise.
|
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(dlind): Likewise.
|
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(dxli): Likewise.
|
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(dxsi): Likewise.
|
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(dsti): Likewise.
|
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(define-ldstx-insns): Likewise.
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(define-st-insns): Likewise.
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(define-cond-jump-insn): Likewise.
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(dcji): Likewise.
|
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(define-condjump-insns): Likewise.
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(define-call-insn): Likewise.
|
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(ja): Likewise.
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("exit"): Likewise.
|
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(define-atomic-insns): Likewise.
|
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(sem-exchange-and-add): New macro.
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* bpf.cpu ("brkpt"): New instruction.
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(bpfbf): Set word-bitsize to 32 and insn-endian big.
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(h-gpr): Prefer r0 to `a' and r6 to `ctx'.
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(h-pc): Expand definition.
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* bpf.opc (bpf_print_insn): Set endian_code to BIG.
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2020-05-20 21:17:29 +08:00
|
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|
2020-05-21 Alan Modra <amodra@gmail.com>
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* mep.opc (mep_cgen_expand_macros_and_parse_operand): Replace
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"if (x) free (x)" with "free (x)".
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or1k: Remove 64-bit support, it's not used and it breaks 32-bit hosts
Reported by Rich Felker when building on 32-bit hosts. Backwards jump
negative offsets were not calculated correctly due to improper 32-bit
to 64-bit zero-extension. The 64-bit fields are present because we
are mixing 32-bit and 64-bit architectures in our cpu descriptions.
Removing 64-bit fixes the issue. We don't use 64-bit, there is an architecture
spec for 64-bit but no implementations or simulators. My thought is if
we need them in the future we should do the proper work to support both
32-bit and 64-bit implementations co-existing then.
cpu/ChangeLog:
yyyy-mm-dd Stafford Horne <shorne@gmail.com>
PR 25184
* or1k.cpu (arch or1k): Remove or64 and or64nd machs.
(ORBIS-MACHS, ORFPX32-MACHS): Remove pmacros.
(cpu or1k64bf, mach or64, mach or64nd): Remove definitions.
* or1kcommon.cpu (h-fdr): Remove hardware.
* or1korfpx.cpu (rDDF, rADF, rBDF): Remove operand definitions.
(float-regreg-insn): Remove lf- mnemonic -d instruction pattern.
(float-setflag-insn-base): Remove lf-sf mnemonic -d pattern.
(float-cust-insn): Remove "lf-cust" cust-num "-d" pattern.
(lf-rem-d, lf-itof-d, lf-ftoi-d, lf-madd-d): Remove.
2020-05-19 19:40:27 +08:00
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2020-05-19 Stafford Horne <shorne@gmail.com>
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PR 25184
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* or1k.cpu (arch or1k): Remove or64 and or64nd machs.
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|
(ORBIS-MACHS, ORFPX32-MACHS): Remove pmacros.
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(cpu or1k64bf, mach or64, mach or64nd): Remove definitions.
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* or1kcommon.cpu (h-fdr): Remove hardware.
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* or1korfpx.cpu (rDDF, rADF, rBDF): Remove operand definitions.
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(float-regreg-insn): Remove lf- mnemonic -d instruction pattern.
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(float-setflag-insn-base): Remove lf-sf mnemonic -d pattern.
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(float-cust-insn): Remove "lf-cust" cust-num "-d" pattern.
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(lf-rem-d, lf-itof-d, lf-ftoi-d, lf-madd-d): Remove.
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2020-04-16 15:52:57 +08:00
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2020-02-16 David Faust <david.faust@oracle.com>
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* bpf.cpu (define-cond-jump-insn): Renamed from djci.
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(dcji) New version with support for JMP32
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2020-02-03 08:56:30 +08:00
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2020-02-03 Alan Modra <amodra@gmail.com>
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* m32c.cpu (f-dsp-64-s16): Mask before shifting signed value.
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2020-02-01 10:38:43 +08:00
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2020-02-01 Alan Modra <amodra@gmail.com>
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* frv.cpu (f-u12): Multiply rather than left shift signed values.
|
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(f-label16, f-label24): Likewise.
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|
2020-01-30 19:29:20 +08:00
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|
2020-01-30 Alan Modra <amodra@gmail.com>
|
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* m32c.cpu (f-src32-rn-unprefixed-QI): Shift before inverting.
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(f-src32-rn-prefixed-QI, f-dst32-rn-unprefixed-QI): Likewise.
|
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(f-dst32-rn-prefixed-QI): Likewise.
|
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(f-dsp-32-s32): Mask before shifting left.
|
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(f-dsp-48-u32, f-dsp-48-s32): Likewise.
|
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(f-bitbase32-16-s11-unprefixed): Multiply signed field rather than
|
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shifting left.
|
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(f-bitbase32-24-s11-prefixed, f-bitbase32-24-s19-prefixed): Likewise.
|
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(h-gr-SI): Mask before shifting.
|
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2020-01-30 20:59:04 +08:00
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|
2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
|
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* bpf.cpu (define-alu-insn-un): The unary BPF instructions
|
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(neg and neg32) use OP_SRC_K even if they operate only in
|
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registers.
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|
2020-01-18 21:50:25 +08:00
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|
2020-01-18 Nick Clifton <nickc@redhat.com>
|
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Binutils 2.34 branch created.
|
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2020-01-11 10:02:11 +08:00
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|
2020-01-13 Alan Modra <amodra@gmail.com>
|
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* fr30.cpu (f-disp9, f-disp10, f-s10, f-rel9, f-rel12): Don't
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left shift signed values.
|
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|
2020-01-04 17:23:19 +08:00
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|
2020-01-06 Alan Modra <amodra@gmail.com>
|
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* m32c.cpu (f-dsp-8-u16, f-dsp-8-s16): Rearrange to mask any sign
|
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|
bits before shifting rather than masking after shifting.
|
|
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|
(f-dsp-16-u16, f-dsp-16-s16, f-dsp-32-u16, f-dsp-32-s16): Likewise.
|
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|
(f-dsp-40-u16, f-dsp-40-s16, f-dsp-48-u16, f-dsp-48-s16): Likewise.
|
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|
|
(f-dsp-64-u16, f-dsp-8-s24): Likewise.
|
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|
(f-bitbase32-16-s19-unprefixed): Avoid signed left shift.
|
|
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|
2020-01-04 Alan Modra <amodra@gmail.com>
|
2020-01-04 05:41:43 +08:00
|
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|
* m32r.cpu (f-disp8): Avoid left shift of negative values.
|
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|
(f-disp16, f-disp24): Likewise.
|
|
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|
|
2019-12-23 15:34:12 +08:00
|
|
|
|
2019-12-23 Alan Modra <amodra@gmail.com>
|
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|
* iq2000.cpu (f-offset): Avoid left shift of negative values.
|
|
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|
2019-12-20 12:07:44 +08:00
|
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|
|
2019-12-20 Alan Modra <amodra@gmail.com>
|
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|
* or1korbis.cpu (f-disp26, f-disp21): Don't left shift negative values.
|
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|
2019-12-17 11:56:39 +08:00
|
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|
2019-12-17 Alan Modra <amodra@gmail.com>
|
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|
* bpf.cpu (f-imm64): Avoid signed overflow.
|
|
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|
2019-12-16 07:30:07 +08:00
|
|
|
|
2019-12-16 Alan Modra <amodra@gmail.com>
|
|
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|
|
* xstormy16.cpu (f-rel12a): Avoid signed overflow.
|
|
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|
2019-12-11 14:15:14 +08:00
|
|
|
|
2019-12-11 Alan Modra <amodra@gmail.com>
|
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|
|
|
|
|
* epiphany.cpu (f-sdisp11): Don't sign extend with shifts.
|
|
|
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|
|
* lm32.cpu (f-branch, f-vall): Likewise.
|
|
|
|
|
|
* m32.cpu (f-lab-8-16): Likewise.
|
|
|
|
|
|
|
2019-12-10 15:36:09 +08:00
|
|
|
|
2019-12-11 Alan Modra <amodra@gmail.com>
|
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|
|
* epiphany.cpu (f-simm8, f-simm24): Use multiply rather than
|
|
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|
|
shift left to avoid UB on left shift of negative values.
|
|
|
|
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|
|
2019-11-20 17:16:24 +08:00
|
|
|
|
2019-11-20 Jose E. Marchesi <jose.marchesi@oracle.com>
|
|
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|
|
|
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|
|
* bpf.cpu: Fix comment describing the 128-bit instruction format.
|
|
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|
|
2019-09-09 17:27:03 +08:00
|
|
|
|
2019-09-09 Phil Blundell <pb@pbcl.net>
|
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|
|
binutils 2.33 branch created.
|
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|
|
2019-07-19 21:35:43 +08:00
|
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|
|
2019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com>
|
|
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|
|
* bpf.cpu (h-gpr): when disassembling, use %r0 and %r6 instead of
|
|
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|
|
%a and %ctx.
|
|
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|
|
2019-07-15 22:00:28 +08:00
|
|
|
|
2019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com>
|
|
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|
|
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|
|
* bpf.cpu (dlabs): New pmacro.
|
|
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|
|
(dlind): Likewise.
|
|
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|
|
|
|
cpu,opcodes,gas: fix arguments to ldabs and ldind eBPF instructions
The eBPF non-generic load instructions ldind{b,h,w,dw} and
ldabs{b,h,w,dw} do not take an explicit destination register as an
argument. Instead, they put the loaded value in %r0, implicitly.
This patch fixes the CPU BPF description to not expect a 'dst'
argument in these arguments, regenerates the corresponding files in
opcodes, and updates the impacted GAS tests.
Tested in a x86-64 host.
cpu/ChangeLog:
2019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com>
* bpf.cpu (dlsi): ldabs and ldind instructions do not take an
explicit 'dst' argument.
opcodes/ChangeLog:
2019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com>
* bpf-desc.c: Regenerate.
* bpf-opc.c: Likewise.
gas/ChangeLog:
2019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com>
* testsuite/gas/bpf/mem.s: Do not use explicit arguments for
ldabs and ldind instructions.
* testsuite/gas/bpf/mem.d: Updated accordingly.
* testsuite/gas/bpf/mem-be.d: Likewise.
2019-07-14 20:45:31 +08:00
|
|
|
|
2019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com>
|
|
|
|
|
|
|
|
|
|
|
|
* bpf.cpu (dlsi): ldabs and ldind instructions do not take an
|
|
|
|
|
|
explicit 'dst' argument.
|
|
|
|
|
|
|
2019-06-13 05:16:19 +08:00
|
|
|
|
2019-06-13 Stafford Horne <shorne@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* or1korfpx.cpu (float-setflag-insn-base): Add 'sf' to symbol.
|
|
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|
|
|
|
2019-06-13 05:16:19 +08:00
|
|
|
|
2019-06-13 Stafford Horne <shorne@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* or1k.cpu (or64nd, or32nd, or1200nd): Update comment.a
|
|
|
|
|
|
(l-adrp): Improve comment.
|
|
|
|
|
|
|
cpu/or1k: Define unordered comparisons
Add support for new floating point unordered comparisons. These have been
defined in OpenRISC architecture proposal 7[0] and are now included in the
architecture specification 1.3.
These new instructions provide the ability for floating point comparisons to
detect NaNs.
[0] https://openrisc.io/proposals/lfsf
cpu/ChangeLog:
yyyy-mm-dd Stafford Horne <shorne@gmail.com>
* or1korfpx.cpu (insn-opcode-float-regreg): Add SFUEQ_S, SFUNE_S,
SFUGT_S, SFUGE_S, SFULT_S, SFULE_S, SFUN_S, SFUEQ_D, SFUNE_D, SFUGT_D,
SFUGE_D, SFULT_D, SFULE_D, SFUN_D opcodes.
(float-setflag-insn-base): New pmacro based on float-setflag-insn.
(float-setflag-symantics, float-setflag-unordered-cmp-symantics,
float-setflag-unordered-symantics): New pmacro for instruction
symantics.
(float-setflag-insn): Update to use float-setflag-insn-base.
(float-setflag-unordered-insn): New pmacro for generating instructions.
2019-06-13 05:16:19 +08:00
|
|
|
|
2019-06-13 Stafford Horne <shorne@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* or1korfpx.cpu (insn-opcode-float-regreg): Add SFUEQ_S, SFUNE_S,
|
|
|
|
|
|
SFUGT_S, SFUGE_S, SFULT_S, SFULE_S, SFUN_S, SFUEQ_D, SFUNE_D, SFUGT_D,
|
|
|
|
|
|
SFUGE_D, SFULT_D, SFULE_D, SFUN_D opcodes.
|
|
|
|
|
|
(float-setflag-insn-base): New pmacro based on float-setflag-insn.
|
|
|
|
|
|
(float-setflag-symantics, float-setflag-unordered-cmp-symantics,
|
|
|
|
|
|
float-setflag-unordered-symantics): New pmacro for instruction
|
|
|
|
|
|
symantics.
|
|
|
|
|
|
(float-setflag-insn): Update to use float-setflag-insn-base.
|
|
|
|
|
|
(float-setflag-unordered-insn): New pmacro for generating instructions.
|
|
|
|
|
|
|
cpu/or1k: Add support for orfp64a32 spec
This patch adds support for OpenRISC 64-bit FPU operations on 32-bit cores by
using register pairs. The functionality has been added to OpenRISC architecture
specification version 1.3 as per architecture proposal 14[0].
For supporting assembly of both 64-bit and 32-bit precision instructions we have
defined CGEN_VALIDATE_INSN_SUPPORTED. This allows cgen to use 64-bit bit
architecture assembly parsing on 64-bit toolchains and 32-bit architecture
assembly parsing on 32-bit toolchains. Without this the assembler has issues
parsing register pairs.
This patch also contains a few fixes to the symantics for existing OpenRISC
single and double precision FPU operations.
[0] https://openrisc.io/proposals/orfpx64a32
cpu/ChangeLog:
yyyy-mm-dd Andrey Bacherov <avbacherov@opencores.org>
Stafford Horne <shorne@gmail.com>
* or1k.cpu (ORFPX64A32-MACHS): New pmacro.
(ORFPX-MACHS): Removed pmacro.
* or1k.opc (or1k_cgen_insn_supported): New function.
(CGEN_VALIDATE_INSN_SUPPORTED): Define macro.
(parse_regpair, print_regpair): New functions.
* or1kcommon.cpu (h-spr, spr-shift, spr-address, h-gpr): Reorder
and add comments.
(h-fdr): Update comment to indicate or64.
(reg-pair-reg-lo, reg-pair-reg-hi): New pmacros for register pairs.
(h-fd32r): New hardware for 64-bit fpu registers.
(h-i64r): New hardware for 64-bit int registers.
* or1korbis.cpu (f-resv-8-1): New field.
* or1korfpx.cpu (rDSF, rASF, rBSF): Update attribute to ORFPX32-MACHS.
(rDDF, rADF, rBDF): Update operand comment to indicate or64.
(f-rdoff-10-1, f-raoff-9-1, f-rboff-8-1): New fields.
(h-roff1): New hardware.
(double-field-and-ops mnemonic): New pmacro to generate operations
rDD32F, rAD32F, rBD32F, rDDI and rADI.
(float-regreg-insn): Update single precision generator to MACH
ORFPX32-MACHS. Add generator for or32 64-bit instructions.
(float-setflag-insn): Update single precision generator to MACH
ORFPX32-MACHS. Fix double instructions from single to double
precision. Add generator for or32 64-bit instructions.
(float-cust-insn cust-num): Update single precision generator to MACH
ORFPX32-MACHS. Add generator for or32 64-bit instructions.
(lf-rem-s, lf-itof-s, lf-ftoi-s, lf-madd-s): Update MACH to
ORFPX32-MACHS.
(lf-rem-d): Fix operation from mod to rem.
(lf-rem-d32, lf-itof-d32, lf-ftoi-d32, lf-madd-d32): New instruction.
(lf-itof-d): Fix operands from single to double.
(lf-ftoi-d): Update operand mode from DI to WI.
2019-06-13 05:16:18 +08:00
|
|
|
|
2019-06-13 Andrey Bacherov <avbacherov@opencores.org>
|
|
|
|
|
|
Stafford Horne <shorne@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* or1k.cpu (ORFPX64A32-MACHS): New pmacro.
|
|
|
|
|
|
(ORFPX-MACHS): Removed pmacro.
|
|
|
|
|
|
* or1k.opc (or1k_cgen_insn_supported): New function.
|
|
|
|
|
|
(CGEN_VALIDATE_INSN_SUPPORTED): Define macro.
|
|
|
|
|
|
(parse_regpair, print_regpair): New functions.
|
|
|
|
|
|
* or1kcommon.cpu (h-spr, spr-shift, spr-address, h-gpr): Reorder
|
|
|
|
|
|
and add comments.
|
|
|
|
|
|
(h-fdr): Update comment to indicate or64.
|
|
|
|
|
|
(reg-pair-reg-lo, reg-pair-reg-hi): New pmacros for register pairs.
|
|
|
|
|
|
(h-fd32r): New hardware for 64-bit fpu registers.
|
|
|
|
|
|
(h-i64r): New hardware for 64-bit int registers.
|
|
|
|
|
|
* or1korbis.cpu (f-resv-8-1): New field.
|
|
|
|
|
|
* or1korfpx.cpu (rDSF, rASF, rBSF): Update attribute to ORFPX32-MACHS.
|
|
|
|
|
|
(rDDF, rADF, rBDF): Update operand comment to indicate or64.
|
|
|
|
|
|
(f-rdoff-10-1, f-raoff-9-1, f-rboff-8-1): New fields.
|
|
|
|
|
|
(h-roff1): New hardware.
|
|
|
|
|
|
(double-field-and-ops mnemonic): New pmacro to generate operations
|
|
|
|
|
|
rDD32F, rAD32F, rBD32F, rDDI and rADI.
|
|
|
|
|
|
(float-regreg-insn): Update single precision generator to MACH
|
|
|
|
|
|
ORFPX32-MACHS. Add generator for or32 64-bit instructions.
|
|
|
|
|
|
(float-setflag-insn): Update single precision generator to MACH
|
|
|
|
|
|
ORFPX32-MACHS. Fix double instructions from single to double
|
|
|
|
|
|
precision. Add generator for or32 64-bit instructions.
|
|
|
|
|
|
(float-cust-insn cust-num): Update single precision generator to MACH
|
|
|
|
|
|
ORFPX32-MACHS. Add generator for or32 64-bit instructions.
|
|
|
|
|
|
(lf-rem-s, lf-itof-s, lf-ftoi-s, lf-madd-s): Update MACH to
|
|
|
|
|
|
ORFPX32-MACHS.
|
|
|
|
|
|
(lf-rem-d): Fix operation from mod to rem.
|
|
|
|
|
|
(lf-rem-d32, lf-itof-d32, lf-ftoi-d32, lf-madd-d32): New instruction.
|
|
|
|
|
|
(lf-itof-d): Fix operands from single to double.
|
|
|
|
|
|
(lf-ftoi-d): Update operand mode from DI to WI.
|
|
|
|
|
|
|
2019-05-24 01:03:59 +08:00
|
|
|
|
2019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
|
|
|
|
|
|
|
|
|
|
|
|
* bpf.cpu: New file.
|
|
|
|
|
|
* bpf.opc: Likewise.
|
|
|
|
|
|
|
2019-01-19 23:55:50 +08:00
|
|
|
|
2018-06-24 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
2.32 branch created.
|
|
|
|
|
|
|
or1k: Add the l.muld, l.muldu, l.macu, l.msbu insns
Also fix the incorrect definitions of multiply and divide carry and
overflow float.
Changes to the instructions are made in the .cpu file, then we
regenerate the binutils and sim files.
The changes also required a few fixups for tests and additional sim helpers.
cpu/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
Stafford Horne <shorne@gmail.com>
* or1korbis.cpu (insn-opcode-mac): Add opcodes for MACU and MSBU.
(insn-opcode-alu-regreg): Add opcodes for MULD and MULDU.
(l-mul): Fix overflow support and indentation.
(l-mulu): Fix overflow support and indentation.
(l-muld, l-muldu, l-msbu, l-macu): New instructions.
(l-div); Remove incorrect carry behavior.
(l-divu): Fix carry and overflow behavior.
(l-mac): Add overflow support.
(l-msb, l-msbu): Add carry and overflow support.
opcodes/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
Stafford Horne <shorne@gmail.com>
* or1k-desc.c: Regenerate.
* or1k-desc.h: Regenerate.
* or1k-opc.c: Regenerate.
* or1k-opc.h: Regenerate.
* or1k-opinst.c: Regenerate.
sim/common/ChangeLog:
yyyy-mm-dd Stafford Horne <shorne@gmail.com>
* cgen-ops.h (ADDCFDI): New function, add carry flag DI variant.
(ADDOFDI): New function, add overflow flag DI variant.
(SUBCFDI): New function, subtract carry flag DI variant.
(SUBOFDI): New function, subtract overflow flag DI variant.
sim/ChangeLog:
yyyy-mm-dd Stafford Horne <shorne@gmail.com>
* or1k/cpu.h: Regenerate.
* or1k/decode.c: Regenerate.
* or1k/decode.h: Regenerate.
* or1k/model.c: Regenerate.
* or1k/sem-switch.c: Regenerate.
* or1k/sem.c: Regenerate:
sim/testsuite/sim/or1k/ChangeLog:
yyyy-mm-dd Stafford Horne <shorne@gmail.com>
* div.S: Fix tests to match correct overflow/carry semantics.
* mul.S: Likewise.
gas/ChangeLog:
yyyy-mm-dd Stafford Horne <shorne@gmail.com>
* testsuite/gas/or1k/allinsn.s: Add instruction tests for
l.muld, l.muldu, l.macu, l.msb, l.msbu.
* testsuite/gas/or1k/allinsn.d: Add test results for new
instructions.
2018-10-05 10:41:41 +08:00
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2018-10-05 Richard Henderson <rth@twiddle.net>
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Stafford Horne <shorne@gmail.com>
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* or1korbis.cpu (insn-opcode-mac): Add opcodes for MACU and MSBU.
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(insn-opcode-alu-regreg): Add opcodes for MULD and MULDU.
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(l-mul): Fix overflow support and indentation.
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(l-mulu): Fix overflow support and indentation.
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(l-muld, l-muldu, l-msbu, l-macu): New instructions.
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(l-div); Remove incorrect carry behavior.
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(l-divu): Fix carry and overflow behavior.
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(l-mac): Add overflow support.
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(l-msb, l-msbu): Add carry and overflow support.
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or1k: Add the l.adrp insn and supporting relocations
This patch adds the new instruction and relocation as per proposal:
https://openrisc.io/proposals/ladrp
This is to be added to the spec in an upcoming revision. The new instruction
l.adrp loads the page offset of the current instruction offset by
a 21-bit immediate shifted left 13-bits. This is meant to be used with
a 13-bit lower bit page offset. This allows us to free up the got
register r16.
l.adrp r3, foo
l.ori r4, r3, po(foo)
l.lbz r5, po(foo)(r3)
l.sb po(foo)(r3), r6
The relocations we add are:
- BFD_RELOC_OR1K_PLTA26 For PLT jump relocation with PLT entry
asm: plta() implemented using l.ardp, meaning
no need for r16 (the GOT reg)
- BFD_RELOC_OR1K_GOT_PG21 Upper 21-bit Page offset got address
asm: got()
- BFD_RELOC_OR1K_TLS_GD_PG21 Upper 21-bit Page offset with TLS General
asm: tlsgd() Dynamic calculation
- BFD_RELOC_OR1K_TLS_LDM_PG21 Upper 21-bit Page offset with TLS local
asm: tlsldm() dynamic calculation
- BFD_RELOC_OR1K_TLS_IE_PG21 Upper 21-bit Page offset with TLS Initial
asm: gottp() Executable calculation
- BFD_RELOC_OR1K_PCREL_PG21 Default relocation for disp21 (l.adrp
instructions)
- BFD_RELOC_OR1K_LO13 low 13-bit page offset relocation
asm: po() i.e. mem loads, addi etc
- BFD_RELOC_OR1K_SLO13 low 13-bit page offset relocation
asm: po() i.e. mem stores, with split immediate
- BFD_RELOC_OR1K_GOT_LO13, low 13-bit page offset with GOT calcs
asm: gotpo()
- BFD_RELOC_OR1K_TLS_GD_LO13 Lower 13-bit offset with TLS GD calcs
asm: tlsgdpo()
- BFD_RELOC_OR1K_TLS_LDM_LO13 Lower 13-bit offset with TLS LD calcs
asm: tlsldmpo()
- BFD_RELOC_OR1K_TLS_IE_LO13 Lower 13-bit offset with TLS IE calcs
asm: gottppo()
bfd/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
* bfd-in2.h: Regenerated.
* elf32-or1k.c: (or1k_elf_howto_table): Fix formatting for
R_OR1K_PLT26, Add R_OR1K_PCREL_PG21, R_OR1K_GOT_PG21,
R_OR1K_TLS_GD_PG21, R_OR1K_TLS_LDM_PG21, R_OR1K_TLS_IE_PG21,
R_OR1K_LO13, R_OR1K_GOT_LO13, R_OR1K_TLS_GD_LO13, R_OR1K_TLS_LDM_LO13,
R_OR1K_TLS_IE_LO13, R_OR1K_SLO13, R_OR1K_PLTA26.
(or1k_reloc_map): Add BFD_RELOC_OR1K_PCREL_PG21,
BFD_RELOC_OR1K_GOT_PG21, BFD_RELOC_OR1K_TLS_GD_PG21,
BFD_RELOC_OR1K_TLS_LDM_PG21, BFD_RELOC_OR1K_TLS_IE_PG21,
BFD_RELOC_OR1K_LO13, BFD_RELOC_OR1K_GOT_LO13,
BFD_RELOC_OR1K_TLS_GD_LO13, BFD_RELOC_OR1K_TLS_GD_LO13,
BFD_RELOC_OR1K_TLS_LDM_LO13, BFD_RELOC_OR1K_TLS_IE_LO13,
BFD_RELOC_OR1K_SLO13, BFD_RELOC_OR1K_PLTA26.
(elf_or1k_link_hash_table): Add field saw_plta.
(or1k_final_link_relocate): Add value calculations for new relocations.
(or1k_elf_relocate_section): Add section relocations for new
relocations.
(or1k_write_plt_entry): New function.
(or1k_elf_finish_dynamic_sections): Add support for PLTA relocations
using new l.adrp instruction. Cleanup PLT relocation code generation.
* libbfd.h: Regenerated.
* reloc.c: Add BFD_RELOC_OR1K_PCREL_PG21, BFD_RELOC_OR1K_LO13,
BFD_RELOC_OR1K_SLO13, BFD_RELOC_OR1K_GOT_PG21, BFD_RELOC_OR1K_GOT_LO13,
BFD_RELOC_OR1K_PLTA26, BFD_RELOC_OR1K_TLS_GD_PG21,
BFD_RELOC_OR1K_TLS_GD_LO13, BFD_RELOC_OR1K_TLS_LDM_PG21,
BFD_RELOC_OR1K_TLS_LDM_LO13, BFD_RELOC_OR1K_TLS_IE_PG21,
BFD_RELOC_OR1K_TLS_IE_LO13.
cpu/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
* or1k.opc (parse_disp26): Add support for plta() relocations.
(parse_disp21): New function.
(or1k_rclass): New enum.
(or1k_rtype): New enum.
(or1k_imm16_relocs): Define new PO and SPO relocation mappings.
(parse_reloc): Add new po(), gotpo() and gottppo() for LO13 relocations.
(parse_imm16): Add support for the new 21bit and 13bit relocations.
* or1korbis.cpu (f-disp26): Don't assume SI.
(f-disp21): New pc-relative 21-bit 13 shifted to right.
(insn-opcode): Add ADRP.
(l-adrp): New instruction.
gas/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
* config/tc-or1k.c (or1k_apply_fix): Add BFD_RELOC_OR1K_TLS_GD_PG21,
BFD_RELOC_OR1K_TLS_GD_LO13, BFD_RELOC_OR1K_TLS_LDM_PG21,
BFD_RELOC_OR1K_TLS_LDM_LO13, BFD_RELOC_OR1K_TLS_IE_PG21,
BFD_RELOC_OR1K_TLS_IE_LO13.
* testsuite/gas/or1k/allinsn.s: Add test for l.adrp.
* testsuite/gas/or1k/allinsn.d: Add test results for new
instructions.
* testsuite/gas/or1k/reloc-1.s: Add tests to generate
R_OR1K_PLTA26, R_OR1K_GOT_PG21, R_OR1K_TLS_GD_PG21, R_OR1K_TLS_LDM_PG21,
R_OR1K_TLS_IE_PG21, R_OR1K_LO13, R_OR1K_GOT_LO13, R_OR1K_TLS_GD_LO13,
R_OR1K_TLD_LDM_LO13, R_OR1K_TLS_IE_LO13, R_OR1K_LO13, R_OR1K_SLO13
relocations.
* testsuite/gas/or1k/reloc-1.d: Add relocation results for
tests.
* testsuite/gas/or1k/reloc-2.s: Add negative tests for store to
gotpo().
* testsuite/gas/or1k/reloc-2.l: Add expected error test results.
ld/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
* testsuite/ld-or1k/or1k.exp: Add test cases for plt generation.
* testsuite/ld-or1k/plt1.dd: New file.
* testsuite/ld-or1k/plt1.s: New file.
* testsuite/ld-or1k/plt1.x.dd: New file.
* testsuite/ld-or1k/plta1.dd: New file.
* testsuite/ld-or1k/plta1.s: New file.
* testsuite/ld-or1k/pltlib.s: New file.
include/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
* elf/or1k.h (elf_or1k_reloc_type): Add R_OR1K_PCREL_PG21,
R_OR1K_GOT_PG21, R_OR1K_TLS_GD_PG21, R_OR1K_TLS_LDM_PG21,
R_OR1K_TLS_IE_PG21, R_OR1K_LO13, R_OR1K_GOT_LO13,
R_OR1K_TLS_GD_LO13, R_OR1K_TLS_LDM_LO13, R_OR1K_TLS_IE_LO13,
R_OR1K_SLO13, R_OR1K_PLTA26.
opcodes/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
* or1k-asm.c: Regenerated.
* or1k-desc.c: Regenerated.
* or1k-desc.h: Regenerated.
* or1k-dis.c: Regenerated.
* or1k-ibld.c: Regenerated.
* or1k-opc.c: Regenerated.
* or1k-opc.h: Regenerated.
* or1k-opinst.c: Regenerated.
2018-10-05 10:41:41 +08:00
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2018-10-05 Richard Henderson <rth@twiddle.net>
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* or1k.opc (parse_disp26): Add support for plta() relocations.
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(parse_disp21): New function.
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(or1k_rclass): New enum.
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(or1k_rtype): New enum.
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(or1k_imm16_relocs): Define new PO and SPO relocation mappings.
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(parse_reloc): Add new po(), gotpo() and gottppo() for LO13 relocations.
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(parse_imm16): Add support for the new 21bit and 13bit relocations.
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* or1korbis.cpu (f-disp26): Don't assume SI.
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(f-disp21): New pc-relative 21-bit 13 shifted to right.
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(insn-opcode): Add ADRP.
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(l-adrp): New instruction.
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or1k: Add relocations for high-signed and low-stores
This patch adds the following target relocations:
- BFD_RELOC_HI16_S High 16-bit relocation, for used with signed
asm: ha() lower.
- BFD_RELOC_HI16_S_GOTOFF High 16-bit GOT offset relocation for local
asm: gotoffha() symbols, for use with signed lower.
- BFD_RELOC_OR1K_TLS_IE_AHI16 High 16-bit TLS relocation with initial
asm: gottpoffha() executable calculation, for use with signed
lower.
- BFD_RELOC_OR1K_TLS_LE_AHI16 High 16-bit TLS relocation for local executable
asm: tpoffha() variables, for use with signed lower.
- BFD_RELOC_OR1K_SLO16 Split lower 16-bit relocation, used with
asm: lo() OpenRISC store instructions.
- BFD_RELOC_OR1K_GOTOFF_SLO16 Split lower 16-bit GOT offset relocation for
asm: gotofflo() local symbols, used with OpenRISC store
instructions.
- BFD_RELOC_OR1K_TLS_LE_SLO16 Split lower 16-bit relocation for TLS local
asm: tpofflo() executable variables, used with OpenRISC store
instructions.
bfd/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
Stafford Horne <shorne@gmail.com>
* bfd-in2.h: Regenerated.
* elf32-or1k.c (N_ONES): New macro.
(or1k_elf_howto_table): Fix R_OR1K_PLT26 to complain on overflow.
Add definitions for R_OR1K_TLS_TPOFF, R_OR1K_TLS_DTPOFF,
R_OR1K_TLS_DTPMOD, R_OR1K_AHI16, R_OR1K_GOTOFF_AHI16,
R_OR1K_TLS_IE_AHI16, R_OR1K_TLS_LE_AHI16, R_OR1K_SLO16,
R_OR1K_GOTOFF_SLO16, R_OR1K_TLS_LE_SLO16.
(or1k_reloc_map): Add entries for BFD_RELOC_HI16_S,
BFD_RELOC_LO16_GOTOFF, BFD_RELOC_HI16_GOTOFF, BFD_RELOC_HI16_S_GOTOFF,
BFD_RELOC_OR1K_TLS_IE_AHI16, BFD_RELOC_OR1K_TLS_LE_AHI16,
BFD_RELOC_OR1K_SLO16, BFD_RELOC_OR1K_GOTOFF_SLO16,
BFD_RELOC_OR1K_TLS_LE_SLO16.
(or1k_reloc_type_lookup): Change search loop to start ad index 0 and
also check results before returning.
(or1k_reloc_name_lookup): Simplify loop to use R_OR1K_max as index
limit.
(or1k_final_link_relocate): New function.
(or1k_elf_relocate_section): Add support for new AHI and SLO
relocations. Use or1k_final_link_relocate instead of generic
_bfd_final_link_relocate.
(or1k_elf_check_relocs): Add support for new AHI and SLO relocations.
* reloc.c: Add new enums for BFD_RELOC_OR1K_SLO16,
BFD_RELOC_OR1K_GOTOFF_SLO16, BFD_RELOC_OR1K_TLS_IE_AHI16,
BFD_RELOC_OR1K_TLS_IE_AHI16, BFD_RELOC_OR1K_TLS_LE_AHI16,
BFD_RELOC_OR1K_TLS_LE_SLO16. Remove unused BFD_RELOC_OR1K_GOTOFF_HI16
and BFD_RELOC_OR1K_GOTOFF_LO16.
* libbfd.h: Regenerated.
cpu/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
* or1k.opc: Add RTYPE_ enum.
(INVALID_STORE_RELOC): New string.
(or1k_imm16_relocs): New array array.
(parse_reloc): New static function that just does the parsing.
(parse_imm16): New static function for generic parsing.
(parse_simm16): Change to just call parse_imm16.
(parse_simm16_split): New function.
(parse_uimm16): Change to call parse_imm16.
(parse_uimm16_split): New function.
* or1korbis.cpu (simm16-split): Change to use new simm16_split.
(uimm16-split): Change to use new uimm16_split.
gas/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
* testsuite/gas/or1k/allinsn.d (l_ha): Add result for ha() relocation.
* testsuite/gas/or1k/allinsn.s (l_ha): Add test for ha() relocations.
* testsuite/gas/or1k/allinsn.exp: Renamed to or1k.exp.
* testsuite/gas/or1k/or1k.exp: Add reloc-2 list test.
* testsuite/gas/or1k/reloc-1.d: New file.
* testsuite/gas/or1k/reloc-1.s: New file.
* testsuite/gas/or1k/reloc-2.l: New file.
* testsuite/gas/or1k/reloc-2.s: New file.
include/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
* elf/or1k.h (elf_or1k_reloc_type): Add R_OR1K_AHI16,
R_OR1K_GOTOFF_AHI16, R_OR1K_TLS_IE_AHI16, R_OR1K_TLS_LE_AHI16,
R_OR1K_SLO16, R_OR1K_GOTOFF_SLO16, R_OR1K_TLS_LE_SLO16.
ld/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
* testsuite/ld-or1k/offsets1.d: New file.
* testsuite/ld-or1k/offsets1.s: New file.
* testsuite/ld-or1k/or1k.exp: New file.
opcodes/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
* or1k-asm.c: Regenerate.
2018-10-05 10:41:40 +08:00
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2018-10-05 Richard Henderson <rth@twiddle.net>
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* or1k.opc: Add RTYPE_ enum.
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(INVALID_STORE_RELOC): New string.
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(or1k_imm16_relocs): New array array.
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(parse_reloc): New static function that just does the parsing.
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(parse_imm16): New static function for generic parsing.
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(parse_simm16): Change to just call parse_imm16.
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(parse_simm16_split): New function.
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(parse_uimm16): Change to call parse_imm16.
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(parse_uimm16_split): New function.
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* or1korbis.cpu (simm16-split): Change to use new simm16_split.
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(uimm16-split): Change to use new uimm16_split.
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2018-07-24 15:05:52 +08:00
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2018-07-24 Alan Modra <amodra@gmail.com>
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PR 23430
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* or1kcommon.cpu (spr-reg-indices): Fix description typo.
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2018-05-09 14:20:29 +08:00
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2018-05-09 Sebastian Rasmussen <sebras@gmail.com>
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* or1kcommon.cpu (spr-reg-info): Typo fix.
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opcodes error messages
Another patch aimed at making binutils comply with the GNU coding
standard. The generated files require
https://sourceware.org/ml/cgen/2018-q1/msg00004.html
cpu/
* frv.opc: Include opintl.h.
(add_next_to_vliw): Use opcodes_error_handler to print error.
Standardize error message.
(fr500_check_insn_major_constraints, frv_vliw_add_insn): Likewise.
opcodes/
* sysdep.h (opcodes_error_handler): Define.
(_bfd_error_handler): Declare.
* Makefile.am: Remove stray #.
* opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
EDIT" comment.
* aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
* d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
* riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
opcodes_error_handler to print errors. Standardize error messages.
* msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
and include opintl.h.
* nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
* i386-gen.c: Standardize error messages.
* msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
* Makefile.in: Regenerate.
* epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
* epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
* fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
* frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
* iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
* lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
* m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
* m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
* mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
* mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
* or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
* xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
* xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
2018-03-02 05:53:50 +08:00
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2018-03-03 Alan Modra <amodra@gmail.com>
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* frv.opc: Include opintl.h.
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(add_next_to_vliw): Use opcodes_error_handler to print error.
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Standardize error message.
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(fr500_check_insn_major_constraints, frv_vliw_add_insn): Likewise.
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2018-01-13 21:26:38 +08:00
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2018-01-13 Nick Clifton <nickc@redhat.com>
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2.30 branch created.
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2017-03-20 23:33:51 +08:00
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2017-03-15 Stafford Horne <shorne@gmail.com>
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* or1kcommon.cpu: Add pc set semantics to also update ppc.
|
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|
2016-10-06 18:11:13 +08:00
|
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|
|
2016-10-06 Alan Modra <amodra@gmail.com>
|
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|
|
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|
|
|
* mep.opc (expand_string): Add fall through comment.
|
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|
2016-03-03 09:49:36 +08:00
|
|
|
|
2016-03-03 Alan Modra <amodra@gmail.com>
|
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|
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|
|
* fr30.cpu (f-m4): Replace bogus comment with a better guess
|
|
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|
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|
at what is really going on.
|
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|
|
2016-03-02 06:28:07 +08:00
|
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|
2016-03-02 Alan Modra <amodra@gmail.com>
|
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|
|
* fr30.cpu (f-m4): Replace -1 << 4 with -16.
|
|
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|
2016-02-02 02:21:37 +08:00
|
|
|
|
2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
|
|
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|
|
* epiphany.opc (epiphany_print_insn): Set info->bytes_per_line to
|
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|
|
|
a constant to better align disassembler output.
|
|
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|
|
2014-07-21 01:26:09 +08:00
|
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|
2014-07-20 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
|
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|
|
* or1korbis.cpu (l-msync, l-psync, l-csync): New instructions.
|
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|
2014-06-12 10:34:06 +08:00
|
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|
|
2014-06-12 Alan Modra <amodra@gmail.com>
|
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|
|
* or1k.opc: Whitespace fixes.
|
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|
2014-05-08 13:53:09 +08:00
|
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|
2014-05-08 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
|
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|
* or1korbis.cpu (h-atomic-reserve): New hardware.
|
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|
|
(h-atomic-address): Likewise.
|
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|
|
|
(insn-opcode): Add opcodes for LWA and SWA.
|
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|
|
(atomic-reserve): New operand.
|
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|
|
(atomic-address): Likewise.
|
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|
|
(l-lwa, l-swa): New instructions.
|
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|
|
(l-lbs): Fix typo in comment.
|
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|
(store-insn): Clear atomic reserve on store to atomic-address.
|
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|
|
Fix register names in fmt field.
|
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|
2014-04-22 22:57:47 +08:00
|
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|
2014-04-22 Christian Svensson <blue@cmd.nu>
|
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|
* openrisc.cpu: Delete.
|
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|
|
* openrisc.opc: Delete.
|
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|
|
* or1k.cpu: New file.
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|
* or1k.opc: New file.
|
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|
* or1kcommon.cpu: New file.
|
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|
* or1korbis.cpu: New file.
|
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|
* or1korfpx.cpu: New file.
|
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|
2013-12-04 08:40:24 +08:00
|
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|
|
2013-12-07 Mike Frysinger <vapier@gentoo.org>
|
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* epiphany.opc: Remove +x file mode.
|
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|
2013-03-09 01:25:12 +08:00
|
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|
2013-03-08 Yann Sionneau <yann.sionneau@gmail.com>
|
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|
|
PR binutils/15241
|
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|
|
* lm32.cpu (Control and status registers): Add CFG2, PSW,
|
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|
|
TLBVADDR, TLBPADDR and TLBBADVADDR.
|
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|
|
2012-11-30 Oleg Raikhman <oleg@adapteva.com>
Joern Rennecke <joern.rennecke@embecosm.com>
cpu:
* epiphany.cpu (keyword gr-names): Move sb/sl/ip after r9/r10/r12.
(load_insn): Add NO-DIS attribute to x, p, d, dpm, dl0, dl0.l.
(testset-insn): Add NO_DIS attribute to t.l.
(store-insn): Add NO-DIS attribute to x.l, p.l, d.l, dpm.l, dl0.l.
(move-insns): Add NO-DIS attribute to cmov.l.
(op-mmr-movts): Add NO-DIS attribute to movts.l.
(op-mmr-movfs): Add NO-DIS attribute to movfs.l.
(op-rrr): Add NO-DIS attribute to .l.
(shift-rrr): Add NO-DIS attribute to .l.
(op-shift-rri): Add NO-DIS attribute to i32.l.
(bitrl, movtl): Add NO-DIS attribute.
(op-iextrrr): Add NO-DIS attribute to .l
(op-two_operands-float, op-fabs-float): Add NO-DIS attribute to f32.l.
(op-fix2float-float, op-float2fix-float, op-fextop-float): Likewise.
opcodes:
* epiphany-desc.c, epiphany-desc.h, epiphany-opc.c: Regenerate.
2012-12-01 01:54:58 +08:00
|
|
|
|
2012-11-30 Oleg Raikhman <oleg@adapteva.com>
|
|
|
|
|
|
Joern Rennecke <joern.rennecke@embecosm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* epiphany.cpu (keyword gr-names): Move sb/sl/ip after r9/r10/r12.
|
|
|
|
|
|
(load_insn): Add NO-DIS attribute to x, p, d, dpm, dl0, dl0.l.
|
|
|
|
|
|
(testset-insn): Add NO_DIS attribute to t.l.
|
|
|
|
|
|
(store-insn): Add NO-DIS attribute to x.l, p.l, d.l, dpm.l, dl0.l.
|
|
|
|
|
|
(move-insns): Add NO-DIS attribute to cmov.l.
|
|
|
|
|
|
(op-mmr-movts): Add NO-DIS attribute to movts.l.
|
|
|
|
|
|
(op-mmr-movfs): Add NO-DIS attribute to movfs.l.
|
|
|
|
|
|
(op-rrr): Add NO-DIS attribute to .l.
|
|
|
|
|
|
(shift-rrr): Add NO-DIS attribute to .l.
|
|
|
|
|
|
(op-shift-rri): Add NO-DIS attribute to i32.l.
|
|
|
|
|
|
(bitrl, movtl): Add NO-DIS attribute.
|
|
|
|
|
|
(op-iextrrr): Add NO-DIS attribute to .l
|
|
|
|
|
|
(op-two_operands-float, op-fabs-float): Add NO-DIS attribute to f32.l.
|
|
|
|
|
|
(op-fix2float-float, op-float2fix-float, op-fextop-float): Likewise.
|
|
|
|
|
|
|
2012-02-27 14:57:57 +08:00
|
|
|
|
2012-02-27 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* mt.opc (print_dollarhex): Trim values to 32 bits.
|
|
|
|
|
|
|
2011-12-15 18:21:51 +08:00
|
|
|
|
2011-12-15 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* frv.opc (parse_uhi16): Fix handling of %hi operator on 64-bit
|
|
|
|
|
|
hosts.
|
|
|
|
|
|
|
2011-10-26 20:46:04 +08:00
|
|
|
|
2011-10-26 Joern Rennecke <joern.rennecke@embecosm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* epiphany.opc (parse_branch_addr): Fix type of valuep.
|
|
|
|
|
|
Cast value before printing it as a long.
|
|
|
|
|
|
(parse_postindex): Fix type of valuep.
|
|
|
|
|
|
|
bfd:
* Makefile.am (ALL_MACHINES): Add cpu-epiphany.lo .
(ALL_MACHINES_CFILES): Add cpu-epiphany.c .
(BFD32_BACKENDS): Add elf32-epiphany.lo .
(BFD32_BACKENDS_CFILES): Add elf32-epiphany.c .
* Makefile.in, bfd-in2.h, configure, libbfd.h: Regenerate.
* archures.c (bfd_arch_epiphany): Add.
(bfd_mach_epiphany16, bfd_mach_epiphany32): Define.
(bfd_epiphany_arch): Declare.
(bfd_archures_list): Add &bfd_epiphany_arch.
* config.bfd (epiphany-*-elf): New target case.
* configure.in (bfd_elf32_epiphany_vec): New target vector case.
* reloc.c (BFD_RELOC_EPIPHANY_SIMM8): New relocation.
(BFD_RELOC_EPIPHANY_SIMM24, BFD_RELOC_EPIPHANY_HIGH): Likewise.
(BFD_RELOC_EPIPHANY_LOW, BFD_RELOC_EPIPHANY_SIMM11): Likewise.
(BFD_RELOC_EPIPHANY_IMM11, BFD_RELOC_EPIPHANY_IMM8): Likewise.
* targets.c (bfd_elf32_epiphany_vec): Declare.
(_bfd_target_vector): Add bfd_elf32_epiphany_vec.
* po/SRC-POTFILES.in, po/bfd.pot: Regenerate.
* cpu-epiphany.c, elf32-epiphany.c: New files.
binutils:
* readelf.c (include "elf/epiphany.h")
(guess_is_rela, dump_relocation): Handle EM_ADAPTEVA_EPIPHANY.
(get_machine_name, is_32bit_abs_reloc, is_32bit_pcrel_reloc): Likewise.
(is_16bit_abs_reloc, is_none_reloc): Likewise.
* po/binutils.pot: Regenerate.
cpu:
* cpu/epiphany.cpu, cpu/epiphany.opc: New files.
gas:
* NEWS: Mention addition of Adapteva Epiphany support.
* config/tc-epiphany.c, config/tc-epiphany.h: New files.
* Makefile.am (TARGET_CPU_CFILES): Add config/tc-epiphany.c .
(TARGET_CPU_HFILES): Add config/tc-epiphany.h .
* Makefile.in, configure, doc/Makefile.in, po/POTFILES.in: Regenerate.
* configure.in: Also set using_cgen for epiphany.
* configure.tgt: Handle epiphany.
* doc/Makefile.am (CPU_DOCS): Add c-epiphany.texi .
* doc/all.texi: Set EPIPHANY.
* doc/as.texinfo: Add EPIPHANY-specific text.
* doc/c-epiphany.texi: New file.
* po/gas.pot: Regenerate.
gas/testsuite:
* gas/epiphany: New directory.
include:
* dis-asm.h (print_insn_epiphany): Declare.
* elf/epiphany.h: New file.
* elf/common.h (EM_ADAPTEVA_EPIPHANY): Define.
ld:
* NEWS: Mention addition of Adapteva Epiphany support.
* Makefile.am (ALL_EMULATION_SOURCES): Add eelf32epiphany.c .
(eelf32epiphany.c): New rule.
* Makefile.in: Regenerate.
* configure.tgt: Handle epiphany-*-elf.
* po/ld.pot: Regenerate.
* testsuite/ld-srec/srec.exp: xfail epiphany.
* emulparams/elf32epiphany.sh: New file.
opcodes:
* Makefile.am (HFILES): Add epiphany-desc.h and epiphany-opc.h .
(TARGET_LIBOPCODES_CFILES): Add epiphany-asm.c, epiphany-desc.c,
epiphany-dis.c, epiphany-ibld.c and epiphany-opc.c .
(CLEANFILES): Add stamp-epiphany.
(EPIPHANY_DEPS): Set. Make CGEN-generated Epiphany files depend on it.
(stamp-epiphany): New rule.
* Makefile.in, configure, po/POTFILES.in, po/opcodes.pot: Regenerate.
* configure.in: Handle bfd_epiphany_arch.
* disassemble.c (ARCH_epiphany): Define.
(disassembler): Handle bfd_arch_epiphany.
* epiphany-asm.c, epiphany-desc.c, epiphany-desc.h: New files.
* epiphany-dis.c, epiphany-ibld.c, epiphany-opc.c: Likewise.
* epiphany-opc.h: Likewise.
2011-10-25 19:18:16 +08:00
|
|
|
|
2011-10-25 Joern Rennecke <joern.rennecke@embecosm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* cpu/epiphany.cpu: New file.
|
|
|
|
|
|
* cpu/epiphany.opc: New file.
|
|
|
|
|
|
|
2011-08-22 23:25:07 +08:00
|
|
|
|
2011-08-22 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* fr30.cpu: Newly contributed file.
|
|
|
|
|
|
* fr30.opc: Likewise.
|
|
|
|
|
|
* ip2k.cpu: Likewise.
|
|
|
|
|
|
* ip2k.opc: Likewise.
|
|
|
|
|
|
* mep-avc.cpu: Likewise.
|
|
|
|
|
|
* mep-avc2.cpu: Likewise.
|
|
|
|
|
|
* mep-c5.cpu: Likewise.
|
|
|
|
|
|
* mep-core.cpu: Likewise.
|
|
|
|
|
|
* mep-default.cpu: Likewise.
|
|
|
|
|
|
* mep-ext-cop.cpu: Likewise.
|
|
|
|
|
|
* mep-fmax.cpu: Likewise.
|
|
|
|
|
|
* mep-h1.cpu: Likewise.
|
|
|
|
|
|
* mep-ivc2.cpu: Likewise.
|
|
|
|
|
|
* mep-rhcop.cpu: Likewise.
|
|
|
|
|
|
* mep-sample-ucidsp.cpu: Likewise.
|
|
|
|
|
|
* mep.cpu: Likewise.
|
|
|
|
|
|
* mep.opc: Likewise.
|
|
|
|
|
|
* openrisc.cpu: Likewise.
|
|
|
|
|
|
* openrisc.opc: Likewise.
|
|
|
|
|
|
* xstormy16.cpu: Likewise.
|
|
|
|
|
|
* xstormy16.opc: Likewise.
|
|
|
|
|
|
|
2010-10-08 22:00:50 +08:00
|
|
|
|
2010-10-08 Pierre Muller <muller@ics.u-strasbg.fr>
|
|
|
|
|
|
|
|
|
|
|
|
* frv.opc: #undef DEBUG.
|
|
|
|
|
|
|
2010-07-03 12:09:56 +08:00
|
|
|
|
2010-07-03 DJ Delorie <dj@delorie.com>
|
|
|
|
|
|
|
|
|
|
|
|
* m32c.cpu (f-dsp-8-s24): Mask high byte after shifting it.
|
|
|
|
|
|
|
* m32r.cpu (HASH-PREFIX): Delete.
(duhpo, dshpo): New pmacros.
(simm8, simm16): Delete HASH-PREFIX attribute, define with dshpo.
(uimm3, uimm4, uimm5, uimm8, uimm16, imm1): Delete HASH-PREFIX
attribute, define with dshpo.
(uimm24): Delete HASH-PREFIX attribute.
* m32r.opc (CGEN_PRINT_NORMAL): Delete.
(print_signed_with_hash_prefix): New function.
(print_unsigned_with_hash_prefix): New function.
* xc16x.cpu (dowh): New pmacro.
(upof16): Define with dowh, specify print handler.
(qbit, qlobit, qhibit): Ditto.
(upag16): Ditto.
* xc16x.opc (CGEN_PRINT_NORMAL): Delete.
(print_with_dot_prefix): New functions.
(print_with_pof_prefix, print_with_pag_prefix): New functions.
2010-02-12 12:38:21 +08:00
|
|
|
|
2010-02-11 Doug Evans <dje@sebabeach.org>
|
|
|
|
|
|
|
|
|
|
|
|
* m32r.cpu (HASH-PREFIX): Delete.
|
|
|
|
|
|
(duhpo, dshpo): New pmacros.
|
|
|
|
|
|
(simm8, simm16): Delete HASH-PREFIX attribute, define with dshpo.
|
|
|
|
|
|
(uimm3, uimm4, uimm5, uimm8, uimm16, imm1): Delete HASH-PREFIX
|
|
|
|
|
|
attribute, define with dshpo.
|
|
|
|
|
|
(uimm24): Delete HASH-PREFIX attribute.
|
|
|
|
|
|
* m32r.opc (CGEN_PRINT_NORMAL): Delete.
|
|
|
|
|
|
(print_signed_with_hash_prefix): New function.
|
|
|
|
|
|
(print_unsigned_with_hash_prefix): New function.
|
|
|
|
|
|
* xc16x.cpu (dowh): New pmacro.
|
|
|
|
|
|
(upof16): Define with dowh, specify print handler.
|
|
|
|
|
|
(qbit, qlobit, qhibit): Ditto.
|
|
|
|
|
|
(upag16): Ditto.
|
|
|
|
|
|
* xc16x.opc (CGEN_PRINT_NORMAL): Delete.
|
|
|
|
|
|
(print_with_dot_prefix): New functions.
|
|
|
|
|
|
(print_with_pof_prefix, print_with_pag_prefix): New functions.
|
|
|
|
|
|
|
* desc-cpu.scm (cgen-desc.h): Don't print virtual enums.
* sid-cpu.scm (cgen-desc.h): Ditto.
* enum.scm (enum-builtin!): New function.
* read.scm (reader-install-builtin!): Call it.
* rtl-c.scm (s-convop): Delete, replaced with ...
(s-int-convop, s-float-convop): ... new fns.
(ext, zext, trunc): Update.
(fext, ftrunc, float, ufloat, fix, ufix): Update.
* rtx-funcs.scm (fext, ftrunc, float, ufloat, fix, ufix): New parameter
`how'.
* cpu/mep-fmax.cpu (fcvtsw): Update.
* cpu/sh.cpu (h-fsd, h-fmov): Update.
* doc/rtl.texi (float-convop): Update.
* frv.cpu (floating-point-conversion): Update call to fp conv op.
(floating-point-dual-conversion, ne-floating-point-dual-conversion,
conditional-floating-point-conversion, ne-floating-point-conversion,
float-parallel-mul-add-double-semantics): Ditto.
2010-01-25 11:50:44 +08:00
|
|
|
|
2010-01-24 Doug Evans <dje@sebabeach.org>
|
|
|
|
|
|
|
|
|
|
|
|
* frv.cpu (floating-point-conversion): Update call to fp conv op.
|
|
|
|
|
|
(floating-point-dual-conversion, ne-floating-point-dual-conversion,
|
|
|
|
|
|
conditional-floating-point-conversion, ne-floating-point-conversion,
|
|
|
|
|
|
float-parallel-mul-add-double-semantics): Ditto.
|
|
|
|
|
|
|
cpu/
* m32c.cpu (f-dsp-32-u24): Fix mode of extract handler.
(f-dsp-40-u20, f-dsp-40-u24): Ditto.
opcodes/
* cgen-ibld.in: #include "cgen/basic-modes.h".
* fr30-ibld.c, * frv-ibld.c, * ip2k-ibld.c, * iq2000-ibld.c,
* lm32-ibld.c, * m32c-ibld.c, * m32r-ibld.c, * mep-ibld.c,
* mt-ibld.c, * openrisc-ibld.c, * xc16x-ibld.c,
* xstormy16-ibld.c: Regenerate.
2010-01-06 13:30:19 +08:00
|
|
|
|
2010-01-05 Doug Evans <dje@sebabeach.org>
|
|
|
|
|
|
|
|
|
|
|
|
* m32c.cpu (f-dsp-32-u24): Fix mode of extract handler.
|
|
|
|
|
|
(f-dsp-40-u20, f-dsp-40-u24): Ditto.
|
|
|
|
|
|
|
2010-01-03 02:37:59 +08:00
|
|
|
|
2010-01-02 Doug Evans <dje@sebabeach.org>
|
|
|
|
|
|
|
|
|
|
|
|
* m32c.opc (parse_signed16): Fix typo.
|
|
|
|
|
|
|
2009-12-11 21:42:17 +08:00
|
|
|
|
2009-12-11 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* frv.opc: Fix shadowed variable warnings.
|
|
|
|
|
|
* m32c.opc: Fix shadowed variable warnings.
|
|
|
|
|
|
|
Must use VOID expression in VOID context.
* xc16x.cpu (mov4): Fix mode of `sequence'.
(mov9, mov10): Ditto.
(movbsrr, moveb1, jmprel, jmpseg, jmps): Fix mode of `if'.
(callr, callseg, calls, trap, rets, reti): Ditto.
(jb, jbc, jnb, jnbs): Fix mode of `if'. Comment out no-op `sll'.
(atomic, extr, extp, extp1, extpg1, extpr, extpr1): Fix mode of `cond'.
(exts, exts1, extsr, extsr1, prior): Ditto.
2009-11-15 03:48:57 +08:00
|
|
|
|
2009-11-14 Doug Evans <dje@sebabeach.org>
|
|
|
|
|
|
|
|
|
|
|
|
Must use VOID expression in VOID context.
|
|
|
|
|
|
* xc16x.cpu (mov4): Fix mode of `sequence'.
|
|
|
|
|
|
(mov9, mov10): Ditto.
|
|
|
|
|
|
(movbsrr, moveb1, jmprel, jmpseg, jmps): Fix mode of `if'.
|
|
|
|
|
|
(callr, callseg, calls, trap, rets, reti): Ditto.
|
|
|
|
|
|
(jb, jbc, jnb, jnbs): Fix mode of `if'. Comment out no-op `sll'.
|
|
|
|
|
|
(atomic, extr, extp, extp1, extpg1, extpr, extpr1): Fix mode of `cond'.
|
|
|
|
|
|
(exts, exts1, extsr, extsr1, prior): Ditto.
|
|
|
|
|
|
|
2009-10-24 08:17:08 +08:00
|
|
|
|
2009-10-23 Doug Evans <dje@sebabeach.org>
|
|
|
|
|
|
|
|
|
|
|
|
* m32c.opc (opc.h): cgen-types.h -> cgen/basic-modes.h.
|
|
|
|
|
|
cgen-ops.h -> cgen/basic-ops.h.
|
|
|
|
|
|
|
2009-09-25 22:07:07 +08:00
|
|
|
|
2009-09-25 Alan Modra <amodra@bigpond.net.au>
|
|
|
|
|
|
|
|
|
|
|
|
* m32r.cpu (stb-plus): Typo fix.
|
|
|
|
|
|
|
* m32r.cpu (sth-plus): Fix address mode and calculation.
(stb-plus): Ditto.
(clrpsw): Fix mask calculation.
(bset, bclr, btst): Make mode in bit calculation match expression.
* xc16x.cpu (rtl-version): Set to 0.8.
(gr-names, ext-names,psw-names): Update, print-name -> enum-prefix,
make uppercase. Remove unnecessary name-prefix spec.
(grb-names, conditioncode-names, extconditioncode-names): Ditto.
(grb8-names, r8-names, regmem8-names, regdiv8-names): Ditto.
(reg0-name, reg0-name1, regbmem8-names, memgr8-names): Ditto.
(h-cr): New hardware.
(muls): Comment out parts that won't compile, add fixme.
(mulu, divl, divlu, jmpabs, jmpa-, jmprel, jbc, jnbs, callr): Ditto.
(scxti, scxtmg, scxtm, bclear, bclr18, bset19, bitset, bmov): Ditto.
(bmovn, band, bor, bxor, bcmp, bfldl, bfldh): Ditto.
2009-09-24 06:30:55 +08:00
|
|
|
|
2009-09-23 Doug Evans <dje@sebabeach.org>
|
|
|
|
|
|
|
|
|
|
|
|
* m32r.cpu (sth-plus): Fix address mode and calculation.
|
|
|
|
|
|
(stb-plus): Ditto.
|
|
|
|
|
|
(clrpsw): Fix mask calculation.
|
|
|
|
|
|
(bset, bclr, btst): Make mode in bit calculation match expression.
|
|
|
|
|
|
|
|
|
|
|
|
* xc16x.cpu (rtl-version): Set to 0.8.
|
|
|
|
|
|
(gr-names, ext-names,psw-names): Update, print-name -> enum-prefix,
|
|
|
|
|
|
make uppercase. Remove unnecessary name-prefix spec.
|
|
|
|
|
|
(grb-names, conditioncode-names, extconditioncode-names): Ditto.
|
|
|
|
|
|
(grb8-names, r8-names, regmem8-names, regdiv8-names): Ditto.
|
|
|
|
|
|
(reg0-name, reg0-name1, regbmem8-names, memgr8-names): Ditto.
|
|
|
|
|
|
(h-cr): New hardware.
|
|
|
|
|
|
(muls): Comment out parts that won't compile, add fixme.
|
|
|
|
|
|
(mulu, divl, divlu, jmpabs, jmpa-, jmprel, jbc, jnbs, callr): Ditto.
|
|
|
|
|
|
(scxti, scxtmg, scxtm, bclear, bclr18, bset19, bitset, bmov): Ditto.
|
|
|
|
|
|
(bmovn, band, bor, bxor, bcmp, bfldl, bfldh): Ditto.
|
|
|
|
|
|
|
2009-07-17 01:53:25 +08:00
|
|
|
|
2009-07-16 Doug Evans <dje@sebabeach.org>
|
|
|
|
|
|
|
|
|
|
|
|
* cpu/simplify.inc (*): One line doc strings don't need \n.
|
|
|
|
|
|
(df): Invoke define-full-ifield instead of claiming it's an alias.
|
|
|
|
|
|
(dno): Define.
|
|
|
|
|
|
(dnop): Mark as deprecated.
|
|
|
|
|
|
|
2009-06-22 08:53:25 +08:00
|
|
|
|
2009-06-22 Alan Modra <amodra@bigpond.net.au>
|
|
|
|
|
|
|
|
|
|
|
|
* m32c.opc (parse_lab_5_3): Use correct enum.
|
|
|
|
|
|
|
2009-01-07 09:09:24 +08:00
|
|
|
|
2009-01-07 Hans-Peter Nilsson <hp@axis.com>
|
|
|
|
|
|
|
|
|
|
|
|
* frv.cpu (mabshs): Explicitly sign-extend arguments of abs to DI.
|
|
|
|
|
|
(DI-ext-HI, DI-ext-UHI, DI-ext-DI): New pmacros.
|
|
|
|
|
|
(media-arith-sat-semantics): Explicitly sign- or zero-extend
|
|
|
|
|
|
arguments of "operation" to DI using "mode" and the new pmacros.
|
|
|
|
|
|
|
2009-01-04 01:51:12 +08:00
|
|
|
|
2009-01-03 Hans-Peter Nilsson <hp@axis.com>
|
|
|
|
|
|
|
|
|
|
|
|
* cris.cpu (cris-implemented-writable-specregs-v32): Correct size
|
|
|
|
|
|
of number 2, PID.
|
|
|
|
|
|
|
2008-12-24 03:10:25 +08:00
|
|
|
|
2008-12-23 Jon Beniston <jon@beniston.com>
|
|
|
|
|
|
|
|
|
|
|
|
* lm32.cpu: New file.
|
|
|
|
|
|
* lm32.opc: New file.
|
|
|
|
|
|
|
2008-01-29 11:50:23 +08:00
|
|
|
|
2008-01-29 Alan Modra <amodra@bigpond.net.au>
|
|
|
|
|
|
|
|
|
|
|
|
* mt.opc (parse_imm16): Apply 2007-09-26 opcodes/mt-asm.c change
|
|
|
|
|
|
to source.
|
|
|
|
|
|
|
2007-10-23 00:04:43 +08:00
|
|
|
|
2007-10-22 Hans-Peter Nilsson <hp@axis.com>
|
|
|
|
|
|
|
|
|
|
|
|
* cris.cpu (movs, movu): Use result of extension operation when
|
|
|
|
|
|
updating flags.
|
|
|
|
|
|
|
2007-07-05 17:49:03 +08:00
|
|
|
|
2007-07-04 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* cris.cpu: Update copyright notice to refer to GPLv3.
|
|
|
|
|
|
* frv.cpu, frv.opc, iq10.cpu, iq2000m.cpu, iq2000.opc, m32c.cpu,
|
|
|
|
|
|
m32c.opc, m32r.cpu, m32r.opc, mt.cpu, mt.opc, sh64-compact.cpu,
|
|
|
|
|
|
sh64-media.cpu, sh.cpu, sh.opc, simplify.inc, xc16x.cpu,
|
|
|
|
|
|
xc16x.opc: Likewise.
|
|
|
|
|
|
* iq2000.cpu: Fix copyright notice to refer to FSF.
|
|
|
|
|
|
|
2007-04-30 21:21:52 +08:00
|
|
|
|
2007-04-30 Mark Salter <msalter@sadr.localdomain>
|
|
|
|
|
|
|
|
|
|
|
|
* frv.cpu (spr-names): Support new coprocessor SPR registers.
|
|
|
|
|
|
|
2007-04-20 21:05:18 +08:00
|
|
|
|
2007-04-20 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* xc16x.cpu: Restore after accidentally overwriting this file with
|
|
|
|
|
|
xc16x.opc.
|
|
|
|
|
|
|
2007-03-30 07:56:39 +08:00
|
|
|
|
2007-03-29 DJ Delorie <dj@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* m32c.cpu (Imm-8-s4n): Fix print hook.
|
|
|
|
|
|
(Lab-24-8, Lab-32-8, Lab-40-8): Fix.
|
|
|
|
|
|
(arith-jnz-imm4-dst-defn): Make relaxable.
|
|
|
|
|
|
(arith-jnz16-imm4-dst-defn): Fix encodings.
|
|
|
|
|
|
|
2007-03-21 10:53:50 +08:00
|
|
|
|
2007-03-20 DJ Delorie <dj@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* m32c.cpu (f-dsp-40-u20, f-dsp-48-u20, Dsp-40-u20, Dsp-40-u20,
|
|
|
|
|
|
mem20): New.
|
|
|
|
|
|
(src16-16-20-An-relative-*): New.
|
|
|
|
|
|
(dst16-*-20-An-relative-*): New.
|
|
|
|
|
|
(dst16-16-16sa-*): New
|
|
|
|
|
|
(dst16-16-16ar-*): New
|
|
|
|
|
|
(dst32-16-16sa-Unprefixed-*): New
|
|
|
|
|
|
(jsri): Fix operands.
|
|
|
|
|
|
(setzx): Fix encoding.
|
2015-07-24 19:08:12 +08:00
|
|
|
|
|
2007-03-08 14:56:20 +08:00
|
|
|
|
2007-03-08 Alan Modra <amodra@bigpond.net.au>
|
|
|
|
|
|
|
|
|
|
|
|
* m32r.opc: Formatting.
|
|
|
|
|
|
|
2006-05-22 17:07:20 +08:00
|
|
|
|
2006-05-22 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* iq2000.cpu: Fix include paths for iq2000m.cpu and iq10.cpu.
|
|
|
|
|
|
|
2006-04-11 05:19:14 +08:00
|
|
|
|
2006-04-10 DJ Delorie <dj@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* m32c.opc (parse_unsigned_bitbase): Take a new parameter which
|
|
|
|
|
|
decides if this function accepts symbolic constants or not.
|
|
|
|
|
|
(parse_signed_bitbase): Likewise.
|
|
|
|
|
|
(parse_unsigned_bitbase8): Pass the new parameter.
|
|
|
|
|
|
(parse_unsigned_bitbase11): Likewise.
|
|
|
|
|
|
(parse_unsigned_bitbase16): Likewise.
|
|
|
|
|
|
(parse_unsigned_bitbase19): Likewise.
|
|
|
|
|
|
(parse_unsigned_bitbase27): Likewise.
|
|
|
|
|
|
(parse_signed_bitbase8): Likewise.
|
|
|
|
|
|
(parse_signed_bitbase11): Likewise.
|
|
|
|
|
|
(parse_signed_bitbase19): Likewise.
|
2015-07-24 19:08:12 +08:00
|
|
|
|
|
2006-03-14 08:29:59 +08:00
|
|
|
|
2006-03-13 DJ Delorie <dj@redhat.com>
|
|
|
|
|
|
|
2006-03-14 12:20:53 +08:00
|
|
|
|
* m32c.cpu (Bit3-S): New.
|
|
|
|
|
|
(btst:s): New.
|
|
|
|
|
|
* m32c.opc (parse_bit3_S): New.
|
|
|
|
|
|
|
2006-03-14 08:29:59 +08:00
|
|
|
|
* m32c.cpu (decimal-subtraction16-insn): Add second operand.
|
|
|
|
|
|
(btst): Add optional :G suffix for MACH32.
|
|
|
|
|
|
(or.b:S): New.
|
|
|
|
|
|
(pop.w:G): Add optional :G suffix for MACH16.
|
|
|
|
|
|
(push.b.imm): Fix syntax.
|
|
|
|
|
|
|
2006-03-11 10:23:19 +08:00
|
|
|
|
2006-03-10 DJ Delorie <dj@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* m32c.cpu (mul.l): New.
|
|
|
|
|
|
(mulu.l): New.
|
|
|
|
|
|
|
2006-03-03 23:57:43 +08:00
|
|
|
|
2006-03-03 Shrirang Khisti <shrirangk@kpitcummins.com)
|
|
|
|
|
|
|
|
|
|
|
|
* xc16x.opc (parse_hash): Return NULL if the input was parsed or
|
|
|
|
|
|
an error message otherwise.
|
|
|
|
|
|
(parse_dot, parse_pof, parse_pag, parse_sof, parse_seg): Likewise.
|
|
|
|
|
|
Fix up comments to correctly describe the functions.
|
|
|
|
|
|
|
[include/elf]
* m32c.h: Add relax relocs.
[cpu]
* m32c.cpu (RL_TYPE): New attribute, with macros.
(Lab-8-24): Add RELAX.
(unary-insn-defn-g, binary-arith-imm-dst-defn,
binary-arith-imm4-dst-defn): Add 1ADDR attribute.
(binary-arith-src-dst-defn): Add 2ADDR attribute.
(jcnd16-5, jcnd16, jcnd32, jmp16.s, jmp16.b, jmp16.w, jmp16.a,
jmp32.s, jmp32.b, jmp32.w, jmp32.a, jsr16.w, jsr16.a): Add JUMP
attribute.
(jsri16, jsri32): Add 1ADDR attribute.
(jsr32.w, jsr32.a): Add JUMP attribute.
[opcodes]
* m32c-desc.c: Regenerate with linker relaxation attributes.
* m32c-desc.h: Likewise.
* m32c-dis.c: Likewise.
* m32c-opc.c: Likewise.
[gas]
* config/tc-m32c.h (md_apply_fix): Define to m32c_apply_fix.
(tc_gen_reloc): Don't define.
* config/tc-m32c.c (rl_for, relaxable): New convenience macros.
(OPTION_LINKRELAX): New.
(md_longopts): Add it.
(m32c_relax): New.
(md_parse_options): Set it.
(md_assemble): Emit relaxation relocs as needed.
(md_convert_frag): Emit relaxation relocs as needed.
(md_cgen_lookup_reloc): Add LAB_8_8 and LAB_8_16.
(m32c_apply_fix): New.
(tc_gen_reloc): New.
(m32c_force_relocation): Force out jump relocs when relaxing.
(m32c_fix_adjustable): Return false if relaxing.
[bfd]
* elf32-m32c.c (m32c_elf_howto_table): Add relaxation relocs.
(m32c_elf_relocate_section): Don't relocate them.
(compare_reloc): New.
(relax_reloc): Remove.
(m32c_offset_for_reloc): New.
(m16c_addr_encodings): New.
(m16c_jmpaddr_encodings): New.
(m32c_addr_encodings): New.
(m32c_elf_relax_section): Relax jumps and address displacements.
(m32c_elf_relax_delete_bytes): Adjust for internal syms. Fix up
short jumps.
* reloc.c: Add m32c relax relocs.
* libbfd.h: Regenerate.
2006-02-25 06:10:36 +08:00
|
|
|
|
2006-02-24 DJ Delorie <dj@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* m32c.cpu (RL_TYPE): New attribute, with macros.
|
|
|
|
|
|
(Lab-8-24): Add RELAX.
|
|
|
|
|
|
(unary-insn-defn-g, binary-arith-imm-dst-defn,
|
|
|
|
|
|
binary-arith-imm4-dst-defn): Add 1ADDR attribute.
|
|
|
|
|
|
(binary-arith-src-dst-defn): Add 2ADDR attribute.
|
|
|
|
|
|
(jcnd16-5, jcnd16, jcnd32, jmp16.s, jmp16.b, jmp16.w, jmp16.a,
|
|
|
|
|
|
jmp32.s, jmp32.b, jmp32.w, jmp32.a, jsr16.w, jsr16.a): Add JUMP
|
|
|
|
|
|
attribute.
|
|
|
|
|
|
(jsri16, jsri32): Add 1ADDR attribute.
|
|
|
|
|
|
(jsr32.w, jsr32.a): Add JUMP attribute.
|
2015-07-24 19:08:12 +08:00
|
|
|
|
|
2006-02-17 22:36:28 +08:00
|
|
|
|
2006-02-17 Shrirang Khisti <shrirangk@kpitcummins.com>
|
2015-07-24 19:08:12 +08:00
|
|
|
|
Anil Paranjape <anilp1@kpitcummins.com>
|
|
|
|
|
|
Shilin Shakti <shilins@kpitcummins.com>
|
2006-02-17 22:36:28 +08:00
|
|
|
|
|
|
|
|
|
|
* xc16x.cpu: New file containing complete CGEN specific XC16X CPU
|
|
|
|
|
|
description.
|
|
|
|
|
|
* xc16x.opc: New file containing supporting XC16C routines.
|
|
|
|
|
|
|
2006-02-10 20:05:12 +08:00
|
|
|
|
2006-02-10 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* iq2000.opc (parse_hi16): Truncate shifted values to 16 bits.
|
|
|
|
|
|
|
2006-01-07 07:25:53 +08:00
|
|
|
|
2006-01-06 DJ Delorie <dj@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* m32c.cpu (mov.w:q): Fix mode.
|
|
|
|
|
|
(push32.b.imm): Likewise, for the comment.
|
|
|
|
|
|
|
Second part of ms1 to mt renaming.
* bfd/archures.c (bfd_arch_mt): Renamed.
(bfd_mt_arch): Renamed.
(bfd_archures_list): Adjusted.
* bfd/bfd-in2.h: Rebuilt.
* bfd/config.bfd (mt): Remove special case targ_archs.
(mt-*-elf): Rename bfd_elf32_mt_vec.
* bfd/configure: Rebuilt.
* bfd/configure.in (bfd_elf32_mt_vec): Renamed.
(selarchs) Remove mt special case.
* bfd/cpu-mt.c (arch_info_struct): Adjust.
(bfd_mt_arch): Renamed, adjust.
* bfd/elf32-mt.c (mt_reloc_type_lookup, mt_info_to_howto_rela,
mt_elf_relocate_hi16, mt_final_link_relocate, mt_relocate_section,
mt_elf_howto_table): Renamed, adjusted.
(mt_elf_gc_mark_hook, mt_elf_gc_sweep_hook, mt_elf_check_relocs,
elf32_mt_machine, mt_elf_object_p, mt_elf_set_private_flags,
mt_elf_copy_private_bfd_data, mt_elf_merge_private_bfd_data,
mt_elf_print_private_bfd_data): Renamed, adjusted.
(TARGET_BIG_SYM, TARGET_BIG_NAME, ELF_ARCH, ELF_MACHINE_CODE,
ELF_MAXPAGESIZE, elf_info_to_howto, elf_backend_relocate_section,
bfd_elf32_bfd_reloc_type_lookup, elf_backend_gc_mark_hook,
elf_backend_gc_sweep_hook, elf_backend_check_relocs,
eld_backend_object_p, bfd_elf32_bfd_set_private_flags,
bfd_elf32_bfd_copy_private_bfd_data,
bfd_elf32_bfd_merge_private_bfd_data,
bfd_elf32_bfd_print_private_bfd_data): Adjusted.
* bfd/libbfd.h: Regenerated.
* bfd/reloc.c (BFD_RELOC_MT_PC16, BFD_RELOC_MT_HI16,
BFD_RELOC_MT_LO16, BFD_RELOC_MT_GNU_VTINHERIT,
BFD_RELOC_MT_GNU_VTENTRY, BFD_RELOC_MT_PCINSN8): Renamed.
* bfd/targets.c (bfd_elf32_mt_vec): Renamed.
(_bfd_target_vector): Adjusted.
* binutils/readelf.c (guess_is_rela): Use EM_MT.
(dump_relocations, get_machine_name): Adjust.
* cpu/mt.cpu (define-arch, define-isa): Set name to mt.
(define-mach): Adjust.
* cpu/mt.opc (CGEN_ASM_HASH): Update.
(mt_asm_hash, mt_cgen_insn_supported): Renamed.
(parse_loopsize, parse_imm16): Adjust.
* gas/configure: Rebuilt.
* gas/configure.in (mt): Remove special case.
* gas/config/tc-mt.c (opcodes/mt-desc.h, opcodes/mt-opc.h): Change
#includes.
(mt_insn, mt_mach, mt_mach_bitmask, mt_flags, mt_architectures):
Rename, adjust.
(md_parse_option, md_show_usage, md_begin, md_assemble,
md_cgen_lookup_reloc, md_atof): Adjust.
(mt_force_relocation, mt_apply_fix, mt_fix_adjustable): Rename, adjust.
* gas/config/tc-mt.h (TC_MT): Rename.
(LISTING_HEADER, TARGET_ARCH, TARGET_FORMAT): Adjust.
(md_apply_fix): Adjust.
(mt_apply_fix, mt_fix_adjustable, mt_force_relocation): Rename.
(TC_FORCE_RELOCATION, tc_fix_adjustable): Adjust.
* gdb/mt-tdep.c (mt_arch_constants, mt_gdb_regnums): Rename, adjust.
(mt_register_name, mt_register_type, mt_register_reggroup_p,
mt_return_value, mt_skip_prologue, mt_breapoint_from_pc,
mt_pseudo_register_read, mt_pseudo_register_write, mt_frame_align,
mt_registers_info, mt_push_dummy_call, mt_unwind_cache,
mt_frame_unwind_cache, mt_unwind_pc, mt_unwind_dummy_id,
mt_frame_this_id, mt_frame_prev_register, mt_frame_base_address,
mt_frame_unwind, mt_frame_sniffer, mt_frame_base, mt_gdbarch_init,
_initialize_mt_tdep): Rename & adjust.
* include/dis-asm.h (print_insn_mt): Renamed.
* include/elf/common.h (EM_MT): Renamed.
* include/elf/mt.h: Rename relocs, cpu & other defines.
* ld/emulparams/elf32mt.sh (ARCH, OUTPUT_FORMAT): Adjust.
* opcodes/Makefile.am (HFILES, CFILES, ALL_MACHINES): Adjust.
(stamp-mt): Adjust rule.
(mt-asm.lo, mt-desc.lo, mt-dis.lo, mt-ibld.lo, mt-opc.lo): Rename &
adjust.
* opcodes/Makefile.in: Rebuilt.
* opcodes/configure: Rebuilt.
* opcodes/configure.in (bfd_mt_arch): Rename & adjust.
* opcodes/disassemble.c (ARCH_mt): Renamed.
(disassembler): Adjust.
* opcodes/mt-asm.c: Renamed, rebuilt.
* opcodes/mt-desc.c: Renamed, rebuilt.
* opcodes/mt-desc.h: Renamed, rebuilt.
* opcodes/mt-dis.c: Renamed, rebuilt.
* opcodes/mt-ibld.c: Renamed, rebuilt.
* opcodes/mt-opc.c: Renamed, rebuilt.
* opcodes/mt-opc.h: Renamed, rebuilt.
* sid/Makefile.in: Rebuilt.
* sid/aclocal.m4: Rebuilt.
* sid/configure: Rebuilt.
* sid/sid.spec: Adjust.
* sid/bsp/Makefile.am: Adjust.
* sid/bsp/Makefile.in: Rebuilt.
* sid/bsp/aclocal.m4: Rebuilt.
* sid/bsp/configrun-sid.in: Adjust.
* sid/bsp/pregen/Makefile.in: Rebuilt.
* sid/bsp/pregen/mt-gdb.conf: Renamed & rebuilt.
* sid/bsp/pregen/mt-gloss.conf: Renamed & rebuilt.
* sid/bsp/pregen/pregen-configs.in: Adjust.
* sid/component/aclocal.m4: Rebuilt.
* sid/component/configure: Rebuilt.
* sid/component/tconfig.in: Adjust.
* sid/component/bochs/aclocal.m4: Rebuilt.
* sid/component/cache/Makefile.in: Rebuilt.
* sid/component/cgen-cpu/Makefile.in: Rebuilt.
* sid/component/cgen-cpu/aclocal.m4: Rebuilt.
* sid/component/cgen-cpu/compCGEN.cxx: Adjust.
* sid/component/cgen-cpu/configure: Rebuilt.
* sid/component/cgen-cpu/configure.in: Rebult.
* sid/component/cgen-cpu/mt/Makefile.am: Adjust.
* sid/component/cgen-cpu/mt/Makefile.in: Rebuilt.
* sid/component/cgen-cpu/mt/hw-cpu-mt.txt: Adjust.
* sid/component/cgen-cpu/mt/mt-cpu.h: Rebuilt.
* sid/component/cgen-cpu/mt/mt-decode.cxx: Rebuilt.
* sid/component/cgen-cpu/mt/mt-decode.h: Rebuilt.
* sid/component/cgen-cpu/mt/mt-defs.h: Rebuilt.
* sid/component/cgen-cpu/mt/mt-desc.h: Rebuilt.
* sid/component/cgen-cpu/mt/mt-sem.cxx: Rebuilt.
* sid/component/cgen-cpu/mt/mt-write.cxx: Rebuilt.
* sid/component/cgen-cpu/mt/mt.cxx: Adjust.
* sid/component/cgen-cpu/mt/mt.h: Adjust.
* sid/component/consoles/Makefile.in: Rebuilt.
* sid/component/families/aclocal.m4: Rebuilt.
* sid/component/families/configure: Rebuilt.
* sid/component/gdb/Makefile.in: Rebuilt.
* sid/component/gloss/Makefile.in: Rebuilt.
* sid/component/glue/Makefile.in: Rebuilt.
* sid/component/ide/Makefile.in: Rebuilt.
* sid/component/interrupt/Makefile.in: Rebuilt.
* sid/component/lcd/Makefile.in: Rebuilt.
* sid/component/lcd/testsuite/Makefile.in: Rebuilt.
* sid/component/loader/Makefile.am: Rebuilt.
* sid/component/loader/Makefile.in: Rebuilt.
* sid/component/mapper/Makefile.in: Rebuilt.
* sid/component/mapper/testsuite/Makefile.in: Rebuilt.
* sid/component/memory/Makefile.in: Rebuilt.
* sid/component/mmu/Makefile.in: Rebuilt.
* sid/component/parport/Makefile.in: Rebuilt.
* sid/component/profiling/Makefile.in: Rebuilt.
* sid/component/rtc/Makefile.in: Rebuilt.
* sid/component/sched/Makefile.in: Rebuilt.
* sid/component/testsuite/Makefile.in: Rebuilt.
* sid/component/timers/aclocal.m4: Rebuilt.
* sid/component/timers/configure: Rebuilt.
* sid/component/uart/Makefile.in: Rebuilt.
* sid/component/uart/testsuite/Makefile.in: Rebuilt.
* sid/config/config.sub: Adjust.
* sid/config/info.tcl.in: Adjust.
* sid/config/sidtargets.m4: Adjust.
* sid/doc/Makefile.in: Rebuilt.
* sid/main/dynamic/Makefile.am: Rebuilt.
* sid/main/dynamic/Makefile.in: Rebuilt.
* sid/main/dynamic/aclocal.m4: Rebuilt.
* sid/main/dynamic/configure: Rebuilt.
2005-12-16 18:23:12 +08:00
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2005-12-16 Nathan Sidwell <nathan@codesourcery.com>
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Second part of ms1 to mt renaming.
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* mt.cpu (define-arch, define-isa): Set name to mt.
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(define-mach): Adjust.
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* mt.opc (CGEN_ASM_HASH): Update.
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(mt_asm_hash, mt_cgen_insn_supported): Renamed.
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(parse_loopsize, parse_imm16): Adjust.
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2005-12-14 11:30:07 +08:00
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2005-12-13 DJ Delorie <dj@redhat.com>
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* m32c.cpu (jsri): Fix order so register names aren't treated as
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symbols.
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(indexb, indexbd, indexbs, indexl, indexld, indexls, indexw,
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indexwd, indexws): Fix encodings.
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2005-12-12 19:25:08 +08:00
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2005-12-12 Nathan Sidwell <nathan@codesourcery.com>
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* mt.cpu: Rename from ms1.cpu.
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* mt.opc: Rename from ms1.opc.
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2005-12-07 05:48:28 +08:00
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2005-12-06 Hans-Peter Nilsson <hp@axis.com>
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* cris.cpu (simplecris-common-writable-specregs)
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(simplecris-common-readable-specregs): Split from
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simplecris-common-specregs. All users changed.
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(cris-implemented-writable-specregs-v0)
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(cris-implemented-readable-specregs-v0): Similar from
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cris-implemented-specregs-v0.
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(cris-implemented-writable-specregs-v3)
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(cris-implemented-readable-specregs-v3)
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(cris-implemented-writable-specregs-v8)
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(cris-implemented-readable-specregs-v8)
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(cris-implemented-writable-specregs-v10)
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(cris-implemented-readable-specregs-v10)
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(cris-implemented-writable-specregs-v32)
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(cris-implemented-readable-specregs-v32): Similar.
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(bdap-32-pc, move-m-pcplus-p0, move-m-spplus-p8): New
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insns and specializations.
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bfd:
Add ms2.
* archures.c (bfd_mach_ms2): Define.
* cpu-ms1.c (arch_info_struct): Add ms2 stanza.
* elf32-ms1.c (elf32_ms1_machine): Add ms2 case.
(ms1_elf_merge_private_bfd_data): Remove unused variables. Add
correct merging logic, with workaround.
(ms1_elf_print_private_bfd_data): Add ms2 case.
* reloc.c (BFD_RELOC_MS1_PCINSN8): Add ms2 specific reloc.
* libbfd.h: Regenerated.
* bfd-in2.h: Regenerated.
cpu:
Add ms2
* ms1.cpu (ms2, ms2bf): New architecture variant, cpu, machine and
model.
(f-uu8, f-uu1, f-imm16l, f-loopo, f-cb1sel, f-cb2sel, f-cb1incr,
f-cb2incr, f-rc3): New fields.
(LOOP): New instruction.
(JAL-HAZARD): New hazard.
(imm16o, loopsize, imm16l, rc3, cb1sel, cb2sel, cb1incr, cb2incr):
New operands.
(mul, muli, dbnz, iflush): Enable for ms2
(jal, reti): Has JAL-HAZARD.
(ldctxt, ldfb, stfb): Only ms1.
(fbcb): Only ms1,ms1-003.
(wfbinc, mefbinc, wfbincr, mwfbincr, fbcbincs, mfbcbincs,
fbcbincrs, mfbcbincrs): Enable for ms2.
(loop, loopu, dfbc, dwfb, fbwfb, dfbr): New ms2 insns.
* ms1.opc (parse_loopsize): New.
(parse_imm16): hi16/lo16 relocs are applicable to IMM16L.
(print_pcrel): New.
gas:
Add ms2.
* config/tc-ms1.c (ms1_mach_bitmask): Initialize to MS1.
(ms1_architectures): Add ms2.
(md_parse_option): Add ms2.
(md_show_usage): Add ms2.
(md_assemble): Add JAL_HAZARD detection logic.
(md_cgen_lookup_reloc): Add MS1_OPERAND_LOOPSIZE case.
* doc/c-ms1.texi: New.
* doc/all.texi: Add MS1.
* doc/Makefile.am (CPU_DOCS): Add c-ms1.texi.
* doc/Makefile.in: Rebuilt.
* doc/Makefile: Rebuilt.
gas/testsuite:
Add ms2.
* gas/ms1/allinsn.d: Adjust pcrel disassembly.
* gas/ms1/errors.exp: Fix target triplet.
* gas/ms1/ms1-16-003.d: Adjust pcrel disassembly.
* gas/ms1/ms1-16-003.s: Tweak label.
* gas/ms1/ms1.exp: Adjust target triplet. Add ms2 test.
* gas/ms1/ms2.d, gas/ms1/ms2.s: New.
* gas/ms1/relocs.d: Adjust expected machine name and pcrel
disassembly.
* gas/ms1/relocs.exp: Adjust target triplet.
include:
Add ms2.
* elf/ms1.h (EF_MS1_CPU_MS2): New.
opcodes:
Add ms2.
* ms1-asm.c, ms1-desc.c, ms1-desc.h, ms1-dis.c, ms1-ibld.c,
ms1-opc.c, ms1-opc.h: Regenerated.
2005-11-08 19:15:13 +08:00
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2005-11-08 Nathan Sidwell <nathan@codesourcery.com>
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Add ms2
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* ms1.cpu (ms2, ms2bf): New architecture variant, cpu, machine and
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model.
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(f-uu8, f-uu1, f-imm16l, f-loopo, f-cb1sel, f-cb2sel, f-cb1incr,
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f-cb2incr, f-rc3): New fields.
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(LOOP): New instruction.
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(JAL-HAZARD): New hazard.
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(imm16o, loopsize, imm16l, rc3, cb1sel, cb2sel, cb1incr, cb2incr):
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New operands.
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(mul, muli, dbnz, iflush): Enable for ms2
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(jal, reti): Has JAL-HAZARD.
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(ldctxt, ldfb, stfb): Only ms1.
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(fbcb): Only ms1,ms1-003.
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(wfbinc, mefbinc, wfbincr, mwfbincr, fbcbincs, mfbcbincs,
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fbcbincrs, mfbcbincrs): Enable for ms2.
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(loop, loopu, dfbc, dwfb, fbwfb, dfbr): New ms2 insns.
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* ms1.opc (parse_loopsize): New.
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(parse_imm16): hi16/lo16 relocs are applicable to IMM16L.
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(print_pcrel): New.
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2005-10-29 03:33:06 +08:00
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2005-10-28 Dave Brolley <brolley@redhat.com>
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Contribute the following change:
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2003-09-24 Dave Brolley <brolley@redhat.com>
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* frv.opc: Use CGEN_ATTR_VALUE_ENUM_TYPE in place of
|
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CGEN_ATTR_VALUE_TYPE.
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* m32c.opc (m32c_cgen_insn_supported): Use CGEN_INSN_BITSET_ATTR_VALUE.
|
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|
Use cgen_bitset_intersect_p.
|
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* m32c.cpu (Imm-8-s4n, Imm-12-s4n): New.
(arith-jnz16-imm4-dst-defn, arith-jnz32-imm4-dst-defn,
arith-jnz-imm4-dst-mach, arith-jnz-imm4-dst): Keep track of which
imm operand is needed.
(adjnz, sbjnz): Pass the right operands.
(unary-insn-defn, unary16-defn, unary32-defn, unary-insn-mach,
unary-insn): Add -g variants for opcodes that need to support :G.
(not.BW:G, push.BW:G): Call it.
(stzx16-imm8-imm8-dsp8sb, stzx16-imm8-imm8-dsp8fb,
stzx16-imm8-imm8-abs16): Fix operand typos.
* m32c.opc (m32c_asm_hash): Support bnCND.
(parse_signed4n, print_signed4n): New.
* m32c-asm.c: Regenerate.
* m32c-desc.c: Regenerate.
* m32c-desc.h: Regenerate.
* m32c-dis.c: Regenerate.
* m32c-ibld.c: Regenerate.
* m32c-opc.c: Regenerate.
* m32c-opc.h: Regenerate.
2005-10-28 07:54:17 +08:00
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2005-10-27 DJ Delorie <dj@redhat.com>
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* m32c.cpu (Imm-8-s4n, Imm-12-s4n): New.
|
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(arith-jnz16-imm4-dst-defn, arith-jnz32-imm4-dst-defn,
|
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|
arith-jnz-imm4-dst-mach, arith-jnz-imm4-dst): Keep track of which
|
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|
imm operand is needed.
|
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(adjnz, sbjnz): Pass the right operands.
|
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(unary-insn-defn, unary16-defn, unary32-defn, unary-insn-mach,
|
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unary-insn): Add -g variants for opcodes that need to support :G.
|
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(not.BW:G, push.BW:G): Call it.
|
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(stzx16-imm8-imm8-dsp8sb, stzx16-imm8-imm8-dsp8fb,
|
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|
stzx16-imm8-imm8-abs16): Fix operand typos.
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|
* m32c.opc (m32c_asm_hash): Support bnCND.
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(parse_signed4n, print_signed4n): New.
|
2015-07-24 19:08:12 +08:00
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2005-10-26 22:59:12 +08:00
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2005-10-26 DJ Delorie <dj@redhat.com>
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* m32c.cpu (f-dsp-8-s24, Dsp-8-s24): New.
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(mov-dspsp-dst-defn, mov-src-dspsp-defn, mov16-dspsp-dst-defn,
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mov16-src-dspsp-defn, mov32-dspsp-dst-defn, mov32-src-dspsp-defn):
|
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dsp8[sp] is signed.
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(mov.WL:S #imm,A0/A1): dsp24 is signed (i.e. -0x800000..0xffffff).
|
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(mov.BW:S r0,r1): Fix typo r1l->r1.
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(tst): Allow :G suffix.
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* m32c.opc (parse_signed24): New, for -0x800000..0xffffff.
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2005-10-26 15:49:05 +08:00
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2005-10-26 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
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* m32r.opc (parse_hi16): Do not assume a 32-bit host word size.
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2005-10-26 02:52:02 +08:00
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2005-10-25 DJ Delorie <dj@redhat.com>
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* m32c.cpu (add16-bQ-sp,add16-wQ-sp): Fix to allow either width by
|
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making one a macro of the other.
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[cpu]
* m32c.cpu (lde, ste): Add dsp[a0] and [a1a] addressing.
(indexb, indexbd, indexbs, indexw, indexwd, indexws, indexl,
indexld, indexls): .w variants have `1' bit.
(rot32.b): QI, not SI.
(rot32.w): HI, not SI.
(xchg16): HI for .w variant.
[opcodes]
* m32c-asm.c: Regenerate.
* m32c-desc.c: Regenerate.
* m32c-desc.h: Regenerate.
* m32c-dis.c: Regenerate.
* m32c-ibld.c: Regenerate.
* m32c-opc.c: Regenerate.
* m32c-opc.h: Regenerate.
2005-10-22 08:03:13 +08:00
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2005-10-21 DJ Delorie <dj@redhat.com>
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* m32c.cpu (lde, ste): Add dsp[a0] and [a1a] addressing.
|
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(indexb, indexbd, indexbs, indexw, indexwd, indexws, indexl,
|
|
|
|
|
|
indexld, indexls): .w variants have `1' bit.
|
|
|
|
|
|
(rot32.b): QI, not SI.
|
|
|
|
|
|
(rot32.w): HI, not SI.
|
|
|
|
|
|
(xchg16): HI for .w variant.
|
|
|
|
|
|
|
2005-10-19 22:44:17 +08:00
|
|
|
|
2005-10-19 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* m32r.opc (parse_slo16): Fix bad application of previous patch.
|
|
|
|
|
|
|
2005-10-18 15:53:17 +08:00
|
|
|
|
2005-10-18 Andreas Schwab <schwab@suse.de>
|
|
|
|
|
|
|
|
|
|
|
|
* m32r.opc (parse_slo16): Better version of previous patch.
|
|
|
|
|
|
|
2005-10-14 16:33:27 +08:00
|
|
|
|
2005-10-14 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
|
|
|
|
|
|
|
|
|
|
|
|
* cpu/m32r.opc (parse_slo16): Do not assume a 32-bit host word
|
|
|
|
|
|
size.
|
|
|
|
|
|
|
2005-07-26 11:21:53 +08:00
|
|
|
|
2005-07-25 DJ Delorie <dj@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* m32c.opc (parse_unsigned8): Add %dsp8().
|
|
|
|
|
|
(parse_signed8): Add %hi8().
|
|
|
|
|
|
(parse_unsigned16): Add %dsp16().
|
|
|
|
|
|
(parse_signed16): Add %lo16() and %hi16().
|
|
|
|
|
|
(parse_lab_5_3): Make valuep a bfd_vma *.
|
|
|
|
|
|
|
2005-07-19 18:01:32 +08:00
|
|
|
|
2005-07-18 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* m32c.cpu (f-16-8, f-24-8, f-32-16, f-dsp-8-u24): New opcode
|
|
|
|
|
|
components.
|
|
|
|
|
|
(f-lab32-jmp-s): Fix insertion sequence.
|
|
|
|
|
|
(Dsp-8-u24, Lab-5-3, Lab32-jmp-s): New operands.
|
|
|
|
|
|
(Dsp-40-s8): Make parameter be signed.
|
|
|
|
|
|
(Dsp-40-s16): Likewise.
|
|
|
|
|
|
(Dsp-48-s8): Likewise.
|
|
|
|
|
|
(Dsp-48-s16): Likewise.
|
|
|
|
|
|
(Imm-13-u3): Likewise. (Despite its name!)
|
|
|
|
|
|
(BitBase16-16-s8): Make the parameter be unsigned.
|
|
|
|
|
|
(BitBase16-8-u11-S): Likewise.
|
|
|
|
|
|
(Lab-8-8, Lab-8-16, Lab-16-8, jcnd16-5, jcnd16, jcnd32, jmp16.s,
|
|
|
|
|
|
jmp16.b, jmp16.w, jmp32.s, jmp32.b, jmp32.w, jsp16.w, jsr32.w): Allow
|
|
|
|
|
|
relaxation.
|
|
|
|
|
|
|
|
|
|
|
|
* m32c.opc: Fix formatting.
|
|
|
|
|
|
Use safe-ctype.h instead of ctype.h
|
|
|
|
|
|
Move duplicated code sequences into a macro.
|
|
|
|
|
|
Fix compile time warnings about signedness mismatches.
|
|
|
|
|
|
Remove dead code.
|
|
|
|
|
|
(parse_lab_5_3): New parser function.
|
2015-07-24 19:08:12 +08:00
|
|
|
|
|
2005-07-17 02:43:55 +08:00
|
|
|
|
2005-07-16 Jim Blandy <jimb@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* m32c.opc (m32c_cgen_insn_supported): Use int, not CGEN_BITSET,
|
|
|
|
|
|
to represent isa sets.
|
|
|
|
|
|
|
2005-07-16 04:31:17 +08:00
|
|
|
|
2005-07-15 Jim Blandy <jimb@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* m32c.cpu, m32c.opc: Fix copyright.
|
|
|
|
|
|
|
ChangeLog:
2005-07-14 Jim Blandy <jimb@redhat.com>
* configure.in: Add cases for Renesas m32c.
* configure: Regenerated.
bfd/ChangeLog:
2005-07-14 Jim Blandy <jimb@redhat.com>
Add support for m32c-*-elf (Renesas m32c and m16c).
* Makefile.am (ALL_MACHINES): Add cpu-m32c.lo.
(ALL_MACHINES_CFILES): Add cpu-m32c.c.
(BFD32_BACKENDS): Add elf32-m32c.lo.
(BFD32_BACKENDS_CFILES): Add elf32-m32c.c.
(cpu-m32c.lo, elf32-m32c.lo): New rules, generated by 'make dep-am'.
* Makefile.in: Regenerated.
* archures.c (bfd_arch_m32c, bfd_mach_m16c, bfd_mach_m32c): New
arch and mach codes.
(bfd_m32c_arch): New arch info object.
(bfd_archures_list): List bfd_m32c_arch.
* bfd-in2.h: Regenerated.
* config.bfd: Add case for the m32c.
* configure.in: Add case for the m32c.
* configure: Regenerated.
* cpu-m32c.c, elf32-m32c.c: New files.
* libbfd.h: Regenerated.
* targets.c (bfd_elf32_m32c_vec): Declare.
(_bfd_target_vector): List bfd_elf32_m32c_vec.
binutils/ChangeLog:
2005-07-14 Jim Blandy <jimb@redhat.com>
* readelf.c: #include "elf/m32c.h"
(guess_is_rela, dump_relocations, get_machine_name): Add cases for
EM_M32C.
* Makefile.am (readelf.o): Update dependencies.
* Makefile.in: Regenerated.
cpu/ChangeLog:
2005-07-14 Jim Blandy <jimb@redhat.com>
* m32c.cpu, m32c.opc: Machine description for the Renesas M32C.
gas/ChangeLog:
2005-07-14 Jim Blandy <jimb@redhat.com>
Add support for the Renesas M32C.
* Makefile.am (CPU_TYPES): List m32c.
(TARGET_CPU_CFILES): List config/tc-m32c.c.
(TARGET_CPU_HFILES): List config/tc-m32c.h.
* configure.in: Add case for m32c.
* configure.tgt: Add cases for m32c and m32c-*-elf.
* configure: Regenerated.
* config/tc-m32c.c, config/tc-m32c.h: New files.
* doc/Makefile.am (CPU_DOCS): Add c-m32c.texi.
* doc/Makefile.in: Regenerated.
* doc/all.texi: Set M32C.
* doc/as.texinfo: Add text for the M32C-specific options and line
comment characters, and refer to c-m32c.texi.
* doc/c-m32c.texi: New file.
include/ChangeLog:
2005-07-14 Jim Blandy <jimb@redhat.com>
* dis-asm.h (print_insn_m32c): New declaration.
include/elf/ChangeLog:
2005-07-14 Jim Blandy <jimb@redhat.com>
Add support for Renesas M32C and M16C.
* common.h (EM_M32C): New machine number.
* m32c.h: New file.
ld/ChangeLog:
2005-07-14 Jim Blandy <jimb@redhat.com>
Add support for the Renesas M32C and M16C.
* Makefile.am (ALL_EMULATIONS): Add eelf32m32c.o.
(eelf32m32c.c): New target.
* Makefile.in: Regenerated.
* configure.tgt: Add case for m32c-*-elf.
* emulparams/elf32m32c.sh: New file.
opcodes/ChangeLog:
2005-07-14 Jim Blandy <jimb@redhat.com>
Add support for the Renesas M32C and M16C.
* m32c-asm.c, m32c-desc.c, m32c-dis.c, m32c-ibld.c, m32c-opc.c: New.
* m32c-desc.h, m32c-opc.h: New.
* Makefile.am (HFILES): List m32c-desc.h and m32c-opc.h.
(CFILES): List m32c-asm.c, m32c-desc.c, m32c-dis.c, m32c-ibld.c,
m32c-opc.c.
(ALL_MACHINES): List m32c-asm.lo, m32c-desc.lo, m32c-dis.lo,
m32c-ibld.lo, m32c-opc.lo.
(CLEANFILES): List stamp-m32c.
(M32C_DEPS): List stamp-m32c, if CGEN_MAINT.
(CGEN_CPUS): Add m32c.
(m32c-asm.c, m32c-desc.c, m32c-dis.c, m32c-ibld.c, m32c-opc.c)
(m32c-desc.h, m32c-opc.h): Depend on M32C_DEPS.
(m32c_opc_h): New variable.
(stamp-m32c, m32c-asm.lo, m32c-desc.lo, m32c-dis.lo, m32c-ibld.lo)
(m32c-opc.lo): New rules.
* Makefile.in: Regenerated.
* configure.in: Add case for bfd_m32c_arch.
* configure: Regenerated.
* disassemble.c (ARCH_m32c): New.
[ARCH_m32c]: #include "m32c-desc.h".
(disassembler) [ARCH_m32c]: Add case for bfd_arch_m32c.
(disassemble_init_for_target) [ARCH_m32c]: Same.
* cgen-ops.h, cgen-types.h: New files.
* Makefile.am (HFILES): List them.
* Makefile.in: Regenerated.
2005-07-15 06:52:28 +08:00
|
|
|
|
2005-07-14 Jim Blandy <jimb@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* m32c.cpu, m32c.opc: Machine description for the Renesas M32C.
|
|
|
|
|
|
|
2005-07-14 21:59:51 +08:00
|
|
|
|
2005-07-14 Alan Modra <amodra@bigpond.net.au>
|
|
|
|
|
|
|
|
|
|
|
|
* ms1.opc (print_dollarhex): Correct format string.
|
|
|
|
|
|
|
2005-07-06 16:18:52 +08:00
|
|
|
|
2005-07-06 Alan Modra <amodra@bigpond.net.au>
|
|
|
|
|
|
|
|
|
|
|
|
* iq2000.cpu: Include from binutils cpu dir.
|
|
|
|
|
|
|
2005-07-05 23:07:46 +08:00
|
|
|
|
2005-07-05 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* iq2000.opc (parse_lo16, parse_mlo16): Make value parameter
|
|
|
|
|
|
unsigned in order to avoid compile time warnings about sign
|
|
|
|
|
|
conflicts.
|
|
|
|
|
|
|
|
|
|
|
|
* ms1.opc (parse_*): Likewise.
|
|
|
|
|
|
(parse_imm16): Use a "void *" as it is passed both signed and
|
|
|
|
|
|
unsigned arguments.
|
|
|
|
|
|
|
2005-07-01 19:16:33 +08:00
|
|
|
|
2005-07-01 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* frv.opc: Update to ISO C90 function declaration style.
|
|
|
|
|
|
* iq2000.opc: Likewise.
|
|
|
|
|
|
* m32r.opc: Likewise.
|
|
|
|
|
|
* sh.opc: Likewise.
|
|
|
|
|
|
|
2005-06-15 23:33:07 +08:00
|
|
|
|
2005-06-15 Dave Brolley <brolley@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
Contributed by Red Hat.
|
|
|
|
|
|
* ms1.cpu: New file. Written by Nick Clifton, Stan Cox.
|
|
|
|
|
|
* ms1.opc: New file. Written by Stan Cox.
|
|
|
|
|
|
|
2005-05-10 18:21:13 +08:00
|
|
|
|
2005-05-10 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* Update the address and phone number of the FSF organization in
|
|
|
|
|
|
the GPL notices in the following files:
|
|
|
|
|
|
cris.cpu, frv.cpu, frv.opc, iq10.cpu, iq2000.opc, iq2000m.cpu,
|
|
|
|
|
|
m32r.cpu, m32r.opc, sh.cpu, sh.opc, sh64-compact.cpu,
|
|
|
|
|
|
sh64-media.cpu, simplify.inc
|
|
|
|
|
|
|
2005-02-24 21:36:46 +08:00
|
|
|
|
2005-02-24 Alan Modra <amodra@bigpond.net.au>
|
|
|
|
|
|
|
|
|
|
|
|
* frv.opc (parse_A): Warning fix.
|
|
|
|
|
|
|
2005-02-24 00:04:40 +08:00
|
|
|
|
2005-02-23 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* frv.opc: Fixed compile time warnings about differing signed'ness
|
|
|
|
|
|
of pointers passed to functions.
|
|
|
|
|
|
* m32r.opc: Likewise.
|
|
|
|
|
|
|
2005-02-12 00:09:30 +08:00
|
|
|
|
2005-02-11 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* iq2000.opc (parse_jtargq10): Change type of valuep argument to
|
|
|
|
|
|
'bfd_vma *' in order avoid compile time warning message.
|
|
|
|
|
|
|
2005-01-28 09:50:18 +08:00
|
|
|
|
2005-01-28 Hans-Peter Nilsson <hp@axis.com>
|
|
|
|
|
|
|
|
|
|
|
|
* cris.cpu (mstep): Add missing insn.
|
|
|
|
|
|
|
2005-01-26 04:22:41 +08:00
|
|
|
|
2005-01-25 Alexandre Oliva <aoliva@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
2004-11-10 Alexandre Oliva <aoliva@redhat.com>
|
|
|
|
|
|
* frv.cpu: Add support for TLS annotations in loads and calll.
|
|
|
|
|
|
* frv.opc (parse_symbolic_address): New.
|
|
|
|
|
|
(parse_ldd_annotation): New.
|
|
|
|
|
|
(parse_call_annotation): New.
|
|
|
|
|
|
(parse_ld_annotation): New.
|
|
|
|
|
|
(parse_ulo16, parse_uslo16): Use parse_symbolic_address.
|
|
|
|
|
|
Introduce TLS relocations.
|
|
|
|
|
|
(parse_d12, parse_s12, parse_u12): Likewise.
|
|
|
|
|
|
(parse_uhi16): Likewise. Fix constant checking on 64-bit host.
|
|
|
|
|
|
(parse_call_label, print_at): New.
|
|
|
|
|
|
|
2004-12-21 12:37:58 +08:00
|
|
|
|
2004-12-21 Mikael Starvik <starvik@axis.com>
|
|
|
|
|
|
|
|
|
|
|
|
* cris.cpu (cris-set-mem): Correct integral write semantics.
|
|
|
|
|
|
|
2004-11-29 19:52:11 +08:00
|
|
|
|
2004-11-29 Hans-Peter Nilsson <hp@axis.com>
|
|
|
|
|
|
|
|
|
|
|
|
* cris.cpu: New file.
|
|
|
|
|
|
|
2004-11-15 22:30:12 +08:00
|
|
|
|
2004-11-15 Michael K. Lechner <mike.lechner@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* iq2000.cpu: Added quotes around macro arguments so that they
|
|
|
|
|
|
will work with newer versions of guile.
|
|
|
|
|
|
|
2004-10-27 17:30:09 +08:00
|
|
|
|
2004-10-27 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* iq2000m.cpu (pkrlr1, pkrlr30, rbr1, rbr30, rxr1, rxr30, wbr1,
|
|
|
|
|
|
wbr1u, wbr30, wbr30u, wxr1, wxr1u, wxr30, wxr30u): Add an index
|
|
|
|
|
|
operand.
|
|
|
|
|
|
* iq2000.cpu (dnop index): Rename to _index to avoid complications
|
|
|
|
|
|
with guile.
|
|
|
|
|
|
|
2004-08-27 17:32:02 +08:00
|
|
|
|
2004-08-27 Richard Sandiford <rsandifo@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* frv.cpu (cfmovs): Change UNIT attribute to FMALL.
|
|
|
|
|
|
|
2004-05-15 21:10:30 +08:00
|
|
|
|
2004-05-15 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* iq2000.opc (iq2000_cgen_insn_supported): Make 'insn' argument const.
|
|
|
|
|
|
|
2004-03-30 17:29:19 +08:00
|
|
|
|
2004-03-30 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
|
|
|
|
|
|
|
|
|
|
|
|
* m32r.opc (parse_hi16): Fixed shigh(0xffff8000) bug.
|
|
|
|
|
|
|
2004-03-01 18:11:46 +08:00
|
|
|
|
2004-03-01 Richard Sandiford <rsandifo@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* frv.cpu (define-arch frv): Add fr450 mach.
|
|
|
|
|
|
(define-mach fr450): New.
|
|
|
|
|
|
(define-model fr450): New. Add profile units to every fr450 insn.
|
|
|
|
|
|
(define-attr UNIT): Add MDCUTSSI.
|
|
|
|
|
|
(define-attr FR450-MAJOR): New enum. Add to every fr450 insn.
|
|
|
|
|
|
(define-attr AUDIO): New boolean.
|
|
|
|
|
|
(f-LRAE, f-LRAD, f-LRAS, f-TLBPRopx, f-TLBPRL)
|
|
|
|
|
|
(f-LRA-null, f-TLBPR-null): New fields.
|
|
|
|
|
|
(scr0, scr1, scr2, scr3, imavr1, damvr1, cxnr, ttbr)
|
|
|
|
|
|
(tplr, tppr, tpxr, timerh, timerl, timerd, btbr): New SPRs.
|
|
|
|
|
|
(LRAE, LRAD, LRAS, TLBPRopx, TLBPRL): New operands.
|
|
|
|
|
|
(LRA-null, TLBPR-null): New macros.
|
|
|
|
|
|
(iacc-multiply-r-r, slass, scutss, int-arith-ss-r-r): Add AUDIO attr.
|
|
|
|
|
|
(load-real-address): New macro.
|
|
|
|
|
|
(lrai, lrad, tlbpr): New instructions.
|
|
|
|
|
|
(media-cut-acc, media-cut-acc-ss): Add fr450-major argument.
|
|
|
|
|
|
(mcut, mcuti, mcutss, mcutssi): Adjust accordingly.
|
|
|
|
|
|
(mdcutssi): Change UNIT attribute to MDCUTSSI.
|
|
|
|
|
|
(media-low-clear-semantics, media-scope-limit-semantics)
|
|
|
|
|
|
(media-quad-limit, media-quad-shift): New macros.
|
|
|
|
|
|
(mqlclrhs, mqlmths, mqsllhi, mqsrahi): New instructions.
|
|
|
|
|
|
* frv.opc (frv_is_branch_major, frv_is_float_major, frv_is_media_major)
|
|
|
|
|
|
(frv_is_branch_insn, frv_is_float_insn, frv_is_media_insn)
|
|
|
|
|
|
(frv_vliw_reset, frv_vliw_add_insn): Handle bfd_mach_fr450.
|
|
|
|
|
|
(fr450_unit_mapping): New array.
|
|
|
|
|
|
(fr400_unit_mapping, fr500_unit_mapping, fr550_unit_mapping): Add entry
|
|
|
|
|
|
for new MDCUTSSI unit.
|
|
|
|
|
|
(fr450_check_insn_major_constraints): New function.
|
|
|
|
|
|
(check_insn_major_constraints): Use it.
|
|
|
|
|
|
|
2004-03-01 17:42:33 +08:00
|
|
|
|
2004-03-01 Richard Sandiford <rsandifo@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* frv.cpu (nsdiv, nudiv, nsdivi, nudivi): Remove fr400 profiling unit.
|
|
|
|
|
|
(scutss): Change unit to I0.
|
|
|
|
|
|
(calll, callil, ccalll): Add missing FR550-MAJOR and profile unit.
|
|
|
|
|
|
(mqsaths): Fix FR400-MAJOR categorization.
|
|
|
|
|
|
(media-quad-multiply-cross-acc, media-quad-cross-multiply-cross-acc)
|
|
|
|
|
|
(media-quad-cross-multiply-acc): Change unit from MDUALACC to FMALL.
|
|
|
|
|
|
* frv.opc (fr400_check_insn_major_constraints): Check for (M-2,M-1)
|
|
|
|
|
|
combinations.
|
|
|
|
|
|
|
cpu/
* frv.cpu (r-store, r-store-dual, r-store-quad): Delete.
(rstb, rsth, rst, rstd, rstq): Delete.
(rstbf, rsthf, rstf, rstdf, rstqf): Delete.
gas/testsuite/
* gas/frv/allinsn.s (rstb, rsth, rst, rstd, rstq): Replace with nops.
(rstbf, rsthf, rstf, rstdf, rstqf): Likewise.
* gas/frv/allinsn.d: Update accordingly.
opcodes/
* frv-desc.c, frv-opc.c, frv-opc.h: Regenerate.
sim/frv/
* decode.c, decode.h, model.c, sem.c: Regenerate.
sim/testsuite/
* sim/frv/{rstb,rsth,rst,rstd,rstq}.cgs: Delete.
* sim/frv/{rstbf,rsthf,rstf,rstdf,rstqf}.cgs: Delete.
2004-03-01 17:26:33 +08:00
|
|
|
|
2004-03-01 Richard Sandiford <rsandifo@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* frv.cpu (r-store, r-store-dual, r-store-quad): Delete.
|
|
|
|
|
|
(rstb, rsth, rst, rstd, rstq): Delete.
|
|
|
|
|
|
(rstbf, rsthf, rstf, rstdf, rstqf): Delete.
|
|
|
|
|
|
|
2004-02-24 00:46:46 +08:00
|
|
|
|
2004-02-23 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* Apply these patches from Renesas:
|
|
|
|
|
|
|
|
|
|
|
|
2004-02-10 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
|
|
|
|
|
|
|
|
|
|
|
|
* cpu/m32r.opc (my_print_insn): Fixed incorrect output when
|
|
|
|
|
|
disassembling codes for 0x*2 addresses.
|
|
|
|
|
|
|
|
|
|
|
|
2003-12-15 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
|
|
|
|
|
|
|
|
|
|
|
|
* cpu/m32r.cpu: Add PIPE_O attribute to "pop" instruction.
|
|
|
|
|
|
|
|
|
|
|
|
2003-12-03 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
|
|
|
|
|
|
|
|
|
|
|
|
* cpu/m32r.cpu : Add new model m32r2.
|
|
|
|
|
|
Add new instructions.
|
|
|
|
|
|
Replace occurrances of 'Mitsubishi' with 'Renesas'.
|
|
|
|
|
|
Changed PIPE attr of push from O to OS.
|
|
|
|
|
|
Care for Little-endian of M32R.
|
|
|
|
|
|
* cpu/m32r.opc (CGEN_DIS_HASH, my_print_insn):
|
|
|
|
|
|
Care for Little-endian of M32R.
|
|
|
|
|
|
(parse_slo16): signed extension for value.
|
|
|
|
|
|
|
2004-02-21 00:23:01 +08:00
|
|
|
|
2004-02-20 Andrew Cagney <cagney@redhat.com>
|
|
|
|
|
|
|
2004-02-21 00:26:45 +08:00
|
|
|
|
* m32r.opc, m32r.cpu: New files. Written by , Doug Evans, Nick
|
|
|
|
|
|
Clifton, Ben Elliston, Matthew Green, and Andrew Haley.
|
|
|
|
|
|
|
2004-02-21 00:23:01 +08:00
|
|
|
|
* sh.cpu, sh.opc, sh64-compact.cpu, sh64-media.cpu: New files, all
|
|
|
|
|
|
written by Ben Elliston.
|
|
|
|
|
|
|
2004-01-14 18:05:00 +08:00
|
|
|
|
2004-01-14 Richard Sandiford <rsandifo@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* frv.cpu (UNIT): Add IACC.
|
|
|
|
|
|
(iacc-multiply-r-r): Use it.
|
|
|
|
|
|
* frv.opc (fr400_unit_mapping): Add entry for IACC.
|
|
|
|
|
|
(fr500_unit_mapping, fr550_unit_mapping): Likewise.
|
|
|
|
|
|
|
2004-01-07 03:18:37 +08:00
|
|
|
|
2004-01-06 Alexandre Oliva <aoliva@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
2003-12-19 Alexandre Oliva <aoliva@redhat.com>
|
|
|
|
|
|
* frv.opc (parse_ulo16, parse_uhi16, parse_d12): Fix some
|
|
|
|
|
|
cut&paste errors in shifting/truncating numerical operands.
|
|
|
|
|
|
2003-08-08 Alexandre Oliva <aoliva@redhat.com>
|
|
|
|
|
|
* frv.opc (parse_ulo16): Parse gotofflo and gotofffuncdesclo.
|
|
|
|
|
|
(parse_uslo16): Likewise.
|
|
|
|
|
|
(parse_uhi16): Parse gotoffhi and gotofffuncdeschi.
|
|
|
|
|
|
(parse_d12): Parse gotoff12 and gotofffuncdesc12.
|
|
|
|
|
|
(parse_s12): Likewise.
|
|
|
|
|
|
2003-08-04 Alexandre Oliva <aoliva@redhat.com>
|
|
|
|
|
|
* frv.opc (parse_ulo16): Parse gotlo and gotfuncdesclo.
|
|
|
|
|
|
(parse_uslo16): Likewise.
|
|
|
|
|
|
(parse_uhi16): Parse gothi and gotfuncdeschi.
|
|
|
|
|
|
(parse_d12): Parse got12 and gotfuncdesc12.
|
|
|
|
|
|
(parse_s12): Likewise.
|
|
|
|
|
|
|
2003-10-11 03:29:38 +08:00
|
|
|
|
2003-10-10 Dave Brolley <brolley@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* frv.cpu (dnpmop): New p-macro.
|
|
|
|
|
|
(GRdoublek): Use dnpmop.
|
|
|
|
|
|
(CPRdoublek, FRdoublei, FRdoublej, FRdoublek): Ditto.
|
|
|
|
|
|
(store-double-r-r): Use (.sym regtype doublek).
|
|
|
|
|
|
(r-store-double): Ditto.
|
|
|
|
|
|
(store-double-r-r-u): Ditto.
|
|
|
|
|
|
(conditional-store-double): Ditto.
|
|
|
|
|
|
(conditional-store-double-u): Ditto.
|
|
|
|
|
|
(store-double-r-simm): Ditto.
|
|
|
|
|
|
(fmovs): Assign to UNIT FMALL.
|
|
|
|
|
|
|
2003-10-09 01:53:40 +08:00
|
|
|
|
2003-10-06 Dave Brolley <brolley@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* frv.cpu, frv.opc: Add support for fr550.
|
|
|
|
|
|
|
2003-09-25 03:04:54 +08:00
|
|
|
|
2003-09-24 Dave Brolley <brolley@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* frv.cpu (u-commit): New modelling unit for fr500.
|
|
|
|
|
|
(mwtaccg): Use frv_ref_SI to reference ACC40Sk as an input operand.
|
|
|
|
|
|
(commit-r): Use u-commit model for fr500.
|
|
|
|
|
|
(commit): Ditto.
|
|
|
|
|
|
(conditional-float-binary-op): Take profiling data as an argument.
|
|
|
|
|
|
Update callers.
|
|
|
|
|
|
(ne-float-binary-op): Ditto.
|
|
|
|
|
|
|
2003-09-20 02:59:13 +08:00
|
|
|
|
2003-09-19 Michael Snyder <msnyder@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* frv.cpu (nldqi): Delete unimplemented instruction.
|
|
|
|
|
|
|
2003-09-13 06:04:22 +08:00
|
|
|
|
2003-09-12 Dave Brolley <brolley@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* frv.cpu (u-clrgr, u-clrfr): New units of model fr500.
|
|
|
|
|
|
(clear-ne-flag-r): Pass insn profiling in as an argument. Call
|
|
|
|
|
|
frv_ref_SI to get input register referenced for profiling.
|
|
|
|
|
|
(clear-ne-flag-all): Pass insn profiling in as an argument.
|
|
|
|
|
|
(clrgr,clrfr,clrga,clrfa): Add profiling information.
|
|
|
|
|
|
|
2003-09-12 04:53:33 +08:00
|
|
|
|
2003-09-11 Michael Snyder <msnyder@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* frv.cpu: Typographical corrections.
|
|
|
|
|
|
|
2003-09-10 06:27:28 +08:00
|
|
|
|
2003-09-09 Dave Brolley <brolley@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* frv.cpu (media-dual-complex): Change UNIT to FMALL.
|
|
|
|
|
|
(conditional-media-dual-complex, media-quad-complex): Likewise.
|
|
|
|
|
|
|
2003-09-05 06:46:10 +08:00
|
|
|
|
2003-09-04 Dave Brolley <brolley@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* frv.cpu (register-transfer): Pass in all attributes in on argument.
|
|
|
|
|
|
Update all callers.
|
|
|
|
|
|
(conditional-register-transfer): Ditto.
|
|
|
|
|
|
(cache-preload): Ditto.
|
|
|
|
|
|
(floating-point-conversion): Ditto.
|
|
|
|
|
|
(floating-point-neg): Ditto.
|
|
|
|
|
|
(float-abs): Ditto.
|
|
|
|
|
|
(float-binary-op-s): Ditto.
|
|
|
|
|
|
(conditional-float-binary-op): Ditto.
|
|
|
|
|
|
(ne-float-binary-op): Ditto.
|
|
|
|
|
|
(float-dual-arith): Ditto.
|
|
|
|
|
|
(ne-float-dual-arith): Ditto.
|
|
|
|
|
|
|
2003-09-03 Dave Brolley <brolley@redhat.com>
* frv.opc (parse_A, parse_A0, parse_A1): New parse handlers.
* frv.cpu (UNIT): Add IALL, FMALL, FMLOW, STORE, SCAN, DCPL, MDUALACC,
MCLRACC-1.
(A): Removed operand.
(A0,A1): New operands replace operand A.
(mnop): Now a real insn
(mclracc): Removed insn.
(mclracc-0, mclracc-1): New insns replace mclracc.
(all insns): Use new UNIT attributes.
2003-09-04 07:03:45 +08:00
|
|
|
|
2003-09-03 Dave Brolley <brolley@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* frv.opc (parse_A, parse_A0, parse_A1): New parse handlers.
|
|
|
|
|
|
* frv.cpu (UNIT): Add IALL, FMALL, FMLOW, STORE, SCAN, DCPL, MDUALACC,
|
|
|
|
|
|
MCLRACC-1.
|
|
|
|
|
|
(A): Removed operand.
|
|
|
|
|
|
(A0,A1): New operands replace operand A.
|
|
|
|
|
|
(mnop): Now a real insn
|
|
|
|
|
|
(mclracc): Removed insn.
|
|
|
|
|
|
(mclracc-0, mclracc-1): New insns replace mclracc.
|
|
|
|
|
|
(all insns): Use new UNIT attributes.
|
|
|
|
|
|
|
2003-08-21 21:37:01 +08:00
|
|
|
|
2003-08-21 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* frv.cpu (mbtoh): Replace input parameter to u-media-dual-expand
|
|
|
|
|
|
and u-media-dual-btoh with output parameter.
|
|
|
|
|
|
(cmbtoh): Add profiling hack.
|
|
|
|
|
|
|
2003-08-20 23:40:02 +08:00
|
|
|
|
2003-08-19 Michael Snyder <msnyder@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* frv.cpu: Fix typo, Frintkeven -> FRintkeven
|
|
|
|
|
|
|
2003-06-11 05:24:48 +08:00
|
|
|
|
2003-06-10 Doug Evans <dje@sebabeach.org>
|
|
|
|
|
|
|
|
|
|
|
|
* frv.cpu: Add IDOC attribute.
|
|
|
|
|
|
|
2003-06-07 05:49:30 +08:00
|
|
|
|
2003-06-06 Andrew Cagney <cagney@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
Contributed by Red Hat.
|
|
|
|
|
|
* iq2000.cpu: New file. Written by Ben Elliston, Jeff Johnston,
|
|
|
|
|
|
Stan Cox, and Frank Ch. Eigler.
|
|
|
|
|
|
* iq2000.opc: New file. Written by Ben Elliston, Frank
|
|
|
|
|
|
Ch. Eigler, Chris Moller, Jeff Johnston, and Stan Cox.
|
|
|
|
|
|
* iq2000m.cpu: New file. Written by Jeff Johnston.
|
|
|
|
|
|
* iq10.cpu: New file. Written by Jeff Johnston.
|
|
|
|
|
|
|
2003-06-06 00:04:20 +08:00
|
|
|
|
2003-06-05 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* frv.cpu (FRintieven): New operand. An even-numbered only
|
|
|
|
|
|
version of the FRinti operand.
|
|
|
|
|
|
(FRintjeven): Likewise for FRintj.
|
|
|
|
|
|
(FRintkeven): Likewise for FRintk.
|
|
|
|
|
|
(mdcutssi, media-dual-word-rotate-r-r, mqsaths,
|
|
|
|
|
|
media-quad-arith-sat-semantics, media-quad-arith-sat,
|
|
|
|
|
|
conditional-media-quad-arith-sat, mdunpackh,
|
|
|
|
|
|
media-quad-multiply-semantics, media-quad-multiply,
|
|
|
|
|
|
conditional-media-quad-multiply, media-quad-complex-i,
|
|
|
|
|
|
media-quad-multiply-acc-semantics, media-quad-multiply-acc,
|
|
|
|
|
|
conditional-media-quad-multiply-acc, munpackh,
|
|
|
|
|
|
media-quad-multiply-cross-acc-semantics, mdpackh,
|
|
|
|
|
|
media-quad-multiply-cross-acc, mbtoh-semantics,
|
|
|
|
|
|
media-quad-cross-multiply-cross-acc-semantics,
|
|
|
|
|
|
media-quad-cross-multiply-cross-acc, mbtoh, mhtob-semantics,
|
|
|
|
|
|
media-quad-cross-multiply-acc-semantics, cmbtoh,
|
|
|
|
|
|
media-quad-cross-multiply-acc, media-quad-complex, mhtob,
|
|
|
|
|
|
media-expand-halfword-to-double-semantics, mexpdhd, cmexpdhd,
|
|
|
|
|
|
cmhtob): Use new operands.
|
|
|
|
|
|
* frv.opc (CGEN_VERBOSE_ASSEMBLER_ERRORS): Define.
|
2005-07-14 21:59:51 +08:00
|
|
|
|
(parse_even_register): New function.
|
2003-06-06 00:04:20 +08:00
|
|
|
|
|
2003-06-04 01:15:25 +08:00
|
|
|
|
2003-06-03 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* frv.cpu (media-dual-word-rotate-r-r): Use a signed 6-bit
|
|
|
|
|
|
immediate value not unsigned.
|
|
|
|
|
|
|
2003-06-03 23:41:12 +08:00
|
|
|
|
2003-06-03 Andrew Cagney <cagney@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
Contributed by Red Hat.
|
|
|
|
|
|
* frv.cpu: New file. Written by Dave Brolley, Catherine Moore,
|
|
|
|
|
|
and Eric Christopher.
|
|
|
|
|
|
* frv.opc: New file. Written by Catherine Moore, and Dave
|
|
|
|
|
|
Brolley.
|
|
|
|
|
|
* simplify.inc: New file. Written by Doug Evans.
|
|
|
|
|
|
|
2003-05-03 08:44:23 +08:00
|
|
|
|
2003-05-02 Andrew Cagney <cagney@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* New file.
|
|
|
|
|
|
|
|
|
|
|
|
|
2012-12-10 20:48:03 +08:00
|
|
|
|
Copyright (C) 2003-2012 Free Software Foundation, Inc.
|
|
|
|
|
|
|
|
|
|
|
|
Copying and distribution of this file, with or without modification,
|
|
|
|
|
|
are permitted in any medium without royalty provided the copyright
|
|
|
|
|
|
notice and this notice are preserved.
|
|
|
|
|
|
|
2003-05-03 08:44:23 +08:00
|
|
|
|
Local Variables:
|
|
|
|
|
|
mode: change-log
|
|
|
|
|
|
left-margin: 8
|
|
|
|
|
|
fill-column: 74
|
|
|
|
|
|
version-control: never
|
|
|
|
|
|
End:
|
