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binutils-gdb/opcodes/ChangeLog

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x86: reuse VEX entries for EVEX vperm{q,pd} By matching VEX decode order (L before W), some EVEX entries can refer back to VEX ones instead of carrying duplicates.
2021-03-10 15:18:24 +08:00
2021-03-10 Jan Beulich <jbeulich@suse.com>
* opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1):
Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively.
EVEX_W_0F3A00, EVEX_W_0F3A01): Delete.
* i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01
entries.
* i386-dis-evex-len.h (evex_len_table): Likewise.
* i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries.
x86: re-arrange order of decode for various EVEX opcodes The order of decodes influences the overall number of table entries. Reduce table size quite a bit by first decoding few-alternatives attributes common to all valid leaves. This also adds a PREFIX_DATA 7531c61332db ("x86: simplify decode of opcodes valid with (embedded) 66 prefix only") missed to apply to vbroadcastf64x4.
2021-03-10 15:16:54 +08:00
2021-03-10 Jan Beulich <jbeulich@suse.com>
* opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7,
MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0,
MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1,
MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1,
MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2,
MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,
MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6
EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0,
EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0,
EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0,
EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0,
EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1,
EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1,
EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1,
EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1,
EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1,
EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0,
EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0,
EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819,
EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B,
EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0,
EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0,
EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B,
EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A,
EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete.
REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0,
REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A,
MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B,
MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819,
EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0,
EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0,
EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0,
EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A,
EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38,
EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B,
EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n,
EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n,
EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2,
EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2,
EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n,
EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2,
EVEX_W_0F3A43_L_n): New.
* i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A,
0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B,
0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries.
* i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[]
for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7,
0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A,
0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6.
* i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A,
0F385B, 0F38C6, and 0F38C7 entries.
* i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes
0F38C6 and 0F38C7.
* i386-dis-evex-w.h: No longer link to evex_len_table[] for
opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23,
0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to
evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B.
x86: re-arrange order of decode for various mask reg opcodes The order of decodes influences the overall number of table entries. Reduce table size quite a bit by first decoding few-alternatives attributes common to all valid leaves.
2021-03-10 15:16:24 +08:00
2021-03-10 Jan Beulich <jbeulich@suse.com>
* opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1,
MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0,
MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47,
PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90,
PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0,
VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2,
VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0,
VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2,
VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2,
VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0,
VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2,
VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2,
VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2,
VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1,
VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1,
VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0,
VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1,
VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1,
VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1,
VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1,
VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0,
VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0,
VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0,
VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0,
VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0,
VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0,
VEX_W_0F99_P_2_LEN_0): Delete.
MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0,
MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1,
MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0,
MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0,
MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0,
PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0,
PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0,
PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0,
PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0,
PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0,
PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0,
PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0,
PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0,
PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0,
PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0,
PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0,
PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0,
PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0,
PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42,
VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47,
VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91,
VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99,
VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1,
VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1,
VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0,
VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1,
VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New.
(prefix_table): No longer link to vex_len_table[] for opcodes
0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91,
0F92, 0F93, 0F98, and 0F99.
(vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42,
0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
0F98, and 0F99.
(vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42,
0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
0F98, and 0F99.
(vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42,
0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
0F98, and 0F99.
(mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42,
0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
0F98, and 0F99.
x86: re-arrange order of decode for various VEX opcodes The order of decodes influences the overall number of table entries. Reduce table size quite a bit by first decoding few-alternatives attributes common to all valid leaves.
2021-03-10 15:15:46 +08:00
2021-03-10 Jan Beulich <jbeulich@suse.com>
* opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73):
Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and
REG_VEX_0F73_M_0 respectively.
(MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6,
MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6,
MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6,
MOD_VEX_0F73_REG_7): Delete.
(MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New.
(PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7,
PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0,
PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0,
PREFIX_VEX_0F3AF0_L_0 respectively.
(VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3,
VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3,
VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1,
VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete.
(VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6,
VEX_LEN_0F38F7): New.
(VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0.
(reg_table): No longer link to mod_table[] for VEX opcodes 0F71,
0F72, and 0F73. No longer link to vex_len_table[] for opcode
0F38F3.
(prefix_table): No longer link to vex_len_table[] for opcodes
0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
(vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and
0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5,
0F38F6, 0F38F7, and 0F3AF0.
(vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to
prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
(mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and
0F73.
x86: re-arrange order of decode for various legacy opcodes The order of decodes influences the overall number of table entries. Reduce table size quite a bit by first decoding few-alternatives attributes common to all valid leaves.
2021-03-10 15:15:10 +08:00
2021-03-10 Jan Beulich <jbeulich@suse.com>
* opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to
REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively.
(MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2,
MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3,
MOD_0F73_REG_6, MOD_0F73_REG_7): Delete.
(MOD_0F71, MOD_0F72, MOD_0F73): New.
(dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and
73.
(reg_table): No longer link to mod_table[] for opcodes 0F71,
0F72, and 0F73.
(mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and
0F73.
x86: correct decoding of nop/reserved space (0f18 ... 0x1f) All encodings not used in this range are (reserved) NOPs. Hence their decoding should be fully consistent. For this to work the PREFIX_IGNORED logic needs slightly extending, such that the attribute will also - have an effect when used inside prefix_table[], yet without always falling back to using slot 0, - cause prefixes marked as ignored while decoding through prefix_table[] to no longer be considered decoded, when encountered in a subsequent decoding step. In adjacent code also drop meaningless PREFIX_OPCODE.
2021-03-10 15:14:11 +08:00
2021-03-10 Jan Beulich <jbeulich@suse.com>
* opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5,
MOD_0F18_REG_6, MOD_0F18_REG_7): Delete.
(reg_table): Don't link to mod_table[] where not needed. Add
PREFIX_IGNORED to nop entries.
(prefix_table): Replace PREFIX_OPCODE in nop entries.
(mod_table): Add nop entries next to prefetch ones. Drop
MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and
MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries.
(rm_table): Add PREFIX_IGNORED to nop entries. Drop
PREFIX_OPCODE from endbr* entries.
(get_valid_dis386): Also consider entry's name when zapping
vindex.
(print_insn): Handle PREFIX_IGNORED.
x86: fold some prefix related attributes into a single one RepPrefixOk, HLEPrefixOk, and NoTrackPrefixOk can't be specified together, so can share an enum-like field. IsLockable can be inferred from HLE setting and hence only needs specifying when neither of them is present.
2021-03-09 15:54:32 +08:00
2021-03-09 Jan Beulich <jbeulich@suse.com>
* opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk,
IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk
element.
* opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone,
HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete.
(PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack,
PrefixLock, PrefixHLELock, PrefixHLEAny): Define.
(struct i386_opcode_modifier): Delete notrackprefixok,
islockable, hleprefixok, and repprefixok fields. Add prefixok
field.
* opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny,
HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define.
(mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg,
not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b):
Replace HLEPrefixOk.
* opcodes/i386-tbl.h: Re-generate.
x86-64: make SYSEXIT handling similar to SYSRET's Despite SYSEXIT being an Intel-only insn in long mode, its behavior there is similar to SYSRET's: Depending on REX.W execution continues in either 64-bit or compatibility mode. Hence distinguishing by suffix is as necessary here as it is there.
2021-03-09 15:53:38 +08:00
2021-03-09 Jan Beulich <jbeulich@suse.com>
* opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit.
* opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from
64-bit form.
* opcodes/i386-tbl.h: Re-generate.
x86: infer operand count of templates Having this count explicitly in the table is redundant and (even if just slightly) disturbs clarity. Infer the count from the number of operands actually found. Also convert the "no operands" indicator from "{ 0 }" to just "{}", as that (now) ends up being easier to parse.
2021-03-03 19:57:08 +08:00
2021-03-03 Jan Beulich <jbeulich@suse.com>
* i386-gen.c (output_i386_opcode): Don't get operand count. Look
for {} instead of {0}. Don't look for '0'.
* i386-opc.tbl: Drop operand count field. Drop redundant operand
size specifiers.
RISC-V: PR27158, fixed UJ/SB types and added CSS/CL/CS types for .insn. * Renamed obsolete UJ/SB types and RVC types, also added CSS/CL(CS) types, [VALID/EXTRACT/ENCODE macros] BTYPE_IMM: Renamed from SBTYPE_IMM. JTYPE_IMM: Renamed from UJTYPE_IMM. CITYPE_IMM: Renamed from RVC_IMM. CITYPE_LUI_IMM: Renamed from RVC_LUI_IMM. CITYPE_ADDI16SP_IMM: Renamed from RVC_ADDI16SP_IMM. CITYPE_LWSP_IMM: Renamed from RVC_LWSP_IMM. CITYPE_LDSP_IMM: Renamed from RVC_LDSP_IMM. CIWTYPE_IMM: Renamed from RVC_UIMM8. CIWTYPE_ADDI4SPN_IMM: Renamed from RVC_ADDI4SPN_IMM. CSSTYPE_IMM: Added for .insn without special encoding. CSSTYPE_SWSP_IMM: Renamed from RVC_SWSP_IMM. CSSTYPE_SDSP_IMM: Renamed from RVC_SDSP_IMM. CLTYPE_IMM: Added for .insn without special encoding. CLTYPE_LW_IMM: Renamed from RVC_LW_IMM. CLTYPE_LD_IMM: Renamed from RVC_LD_IMM. RVC_SIMM3: Unused and removed. CBTYPE_IMM: Renamed from RVC_B_IMM. CJTYPE_IMM: Renamed from RVC_J_IMM. * Added new operands and removed the unused ones, C5: Unsigned CL(CS) immediate, added for .insn directive. C6: Unsigned CSS immediate, added for .insn directive. Ci: Unused and removed. C<: Unused and removed. bfd/ PR 27158 * elfnn-riscv.c (perform_relocation): Updated encoding macros. (_bfd_riscv_relax_call): Likewise. (_bfd_riscv_relax_lui): Likewise. * elfxx-riscv.c (howto_table): Likewise. gas/ PR 27158 * config/tc-riscv.c (riscv_ip): Updated encoding macros. (md_apply_fix): Likewise. (md_convert_frag_branch): Likewise. (validate_riscv_insn): Likewise. Also arranged operands, including added C5 and C6 operands, and removed unused Ci and C< operands. * doc/c-riscv.texi: Updated and added CSS/CL/CS types. * testsuite/gas/riscv/insn.d: Added CSS/CL/CS instructions. * testsuite/gas/riscv/insn.s: Likewise. gdb/ PR 27158 * riscv-tdep.c (decode_ci_type_insn): Updated encoding macros. (decode_j_type_insn): Likewise. (decode_cj_type_insn): Likewise. (decode_b_type_insn): Likewise. (decode): Likewise. include/ PR 27158 * opcode/riscv.h: Updated encoding macros. opcodes/ PR 27158 * riscv-dis.c (print_insn_args): Updated encoding macros. * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM. (match_c_addi16sp): Updated encoding macros. (match_c_lui): Likewise. (match_c_lui_with_hint): Likewise. (match_c_addi4spn): Likewise. (match_c_slli): Likewise. (match_slli_as_c_slli): Likewise. (match_c_slli64): Likewise. (match_srxi_as_c_srxi): Likewise. (riscv_insn_types): Added .insn css/cl/cs. sim/ PR 27158 * riscv/sim-main.c (execute_i): Updated encoding macros.
2021-01-26 18:02:38 +08:00
2021-02-19 Nelson Chu <nelson.chu@sifive.com>
PR 27158
* riscv-dis.c (print_insn_args): Updated encoding macros.
* riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
(match_c_addi16sp): Updated encoding macros.
(match_c_lui): Likewise.
(match_c_lui_with_hint): Likewise.
(match_c_addi4spn): Likewise.
(match_c_slli): Likewise.
(match_slli_as_c_slli): Likewise.
(match_c_slli64): Likewise.
(match_srxi_as_c_srxi): Likewise.
(riscv_insn_types): Added .insn css/cl/cs.
RISC-V: Add bfd/cpu-riscv.h to support all spec versions controlling. Make the opcode/riscv-opc.c and include/opcode/riscv.h tidy, move the spec versions stuff to bfd/cpu-riscv.h. Also move the csr stuff and ext_version_table to gas/config/tc-riscv.c for internal use. To avoid too many repeated code, define general RISCV_GET_SPEC_NAME/SPEC_CLASS macros. Therefore, assembler/dis-assembler/linker/gdb can get all spec versions related stuff from cpu-riscv.h and cpu-riscv.c, since the stuff are defined there uniformly. bfd/ * Makefile.am: Added cpu-riscv.h. * Makefile.in: Regenerated. * po/SRC-POTFILES.in: Regenerated. * cpu-riscv.h: Added to support spec versions controlling. Also added extern arrays and functions for cpu-riscv.c. (enum riscv_spec_class): Define all spec classes here uniformly. (struct riscv_spec): Added for all specs. (RISCV_GET_SPEC_CLASS): Added to reduce repeated code. (RISCV_GET_SPEC_NAME): Likewise. (RISCV_GET_ISA_SPEC_CLASS): Added to get ISA spec class. (RISCV_GET_PRIV_SPEC_CLASS): Added to get privileged spec class. (RISCV_GET_PRIV_SPEC_NAME): Added to get privileged spec name. * cpu-riscv.c (struct priv_spec_t): Replaced with struct riscv_spec. (riscv_get_priv_spec_class): Replaced with RISCV_GET_PRIV_SPEC_CLASS. (riscv_get_priv_spec_name): Replaced with RISCV_GET_PRIV_SPEC_NAME. (riscv_priv_specs): Moved below. (riscv_get_priv_spec_class_from_numbers): Likewise, updated. (riscv_isa_specs): Moved from include/opcode/riscv.h. * elfnn-riscv.c: Included cpu-riscv.h. (riscv_merge_attributes): Initialize in_priv_spec and out_priv_spec. * elfxx-riscv.c: Included cpu-riscv.h and opcode/riscv.h. (RISCV_UNKNOWN_VERSION): Moved from include/opcode/riscv.h. * elfxx-riscv.h: Removed extern functions to cpu-riscv.h. gas/ * config/tc-riscv.c: Included cpu-riscv.h. (enum riscv_csr_clas): Moved from include/opcode/riscv.h. (struct riscv_csr_extra): Likewise. (struct riscv_ext_version): Likewise. (ext_version_table): Moved from opcodes/riscv-opc.c. (default_isa_spec): Updated type to riscv_spec_class. (default_priv_spec): Likewise. (riscv_set_default_isa_spec): Updated. (init_ext_version_hash): Likewise. (riscv_init_csr_hash): Likewise, also fixed indent. include/ * opcode/riscv.h: Moved stuff and make the file tidy. opcodes/ * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h. (default_priv_spec): Updated type to riscv_spec_class. (parse_riscv_dis_option): Updated. * riscv-opc.c: Moved stuff and make the file tidy.
2021-01-28 10:45:56 +08:00
2021-02-18 Nelson Chu <nelson.chu@sifive.com>
* riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
(default_priv_spec): Updated type to riscv_spec_class.
(parse_riscv_dis_option): Updated.
* riscv-opc.c: Moved stuff and make the file tidy.
read_leb128 overflow checking There is a tiny error left in dwarf.c:read_leb128 after Nick fixed the signed overflow problem in code I wrote. It's to do with sleb128 values that have unnecessary excess bytes. For example, -1 is represented as 0x7f, the most efficient encoding, but also as 0xff,0x7f or 0xff,0xff,0x7f and so on. None of these sequences overflow any size signed value, but read_leb128 will report an overflow given enough excess bytes. This patch fixes that problem, and since the proper test for signed values with excess bytes can easily be adapted to also test a sleb byte with just some bits that overflow the result, I changed the code to not use signed right shifts. (The C standard ISO/IEC 9899:1999 6.5.7 says signed right shifts of negative values have an implementation defined value. A long time ago I even used a C compiler for a certain microprocessor that always did unsigned right shifts. Mind you, it is very unlikely to be compiling binutils with such a compiler.) bfd/ * wasm-module.c: Guard include of limits.h. (CHAR_BIT): Provide backup define. (wasm_read_leb128): Use CHAR_BIT to size "result" in bits. Correct signed overflow checking. opcodes/ * wasm32-dis.c: Include limits.h. (CHAR_BIT): Provide backup define. (wasm_read_leb128): Use CHAR_BIT to size "result" in bits. Correct signed overflow checking. binutils/ * dwarf.c: Include limits.h. (CHAR_BIT): Provide backup define. (read_leb128): Use CHAR_BIT to size "result" in bits. Correct signed overflow checking. * testsuite/binutils-all/pr26548.s, * testsuite/binutils-all/pr26548.d, * testsuite/binutils-all/pr26548e.d: New tests. * testsuite/binutils-all/readelf.exp: Run them. (readelf_test): Drop unused "xfails" parameter. Update all uses.
2021-02-16 21:16:40 +08:00
2021-02-17 Alan Modra <amodra@gmail.com>
* wasm32-dis.c: Include limits.h.
(CHAR_BIT): Provide backup define.
(wasm_read_leb128): Use CHAR_BIT to size "result" in bits.
Correct signed overflow checking.
x86: CVTPI2PD has special behavior CVTPI2PD with a memory operand, unlike CVTPI2PS, doesn't engage MMX logic. Therefore it - has a proper AVX equivalent (CVTDQ2PD) and hence can be subject to SSE2AVX translation and SSE checking, - should not record MMX use in the respective ELF note.
2021-02-16 18:34:25 +08:00
2021-02-16 Jan Beulich <jbeulich@suse.com>
* i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant.
* i386-tbl.h: Re-generate.
x86: have preprocessor expand macros There's no point having i386-gen's set_bitfield() to handle any aliases, now that we pass the opcode table through the C preprocessor anyway.
2021-02-16 18:27:40 +08:00
2021-02-16 Jan Beulich <jbeulich@suse.com>
* i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor
Oword.
* i386-opc.tbl (CpuFP, Mmword, Oword): Define.
IBM Z: Implement instruction set extensions opcodes/ * s390-mkopc.c (main): Accept arch14 as cpu string. * s390-opc.txt: Add new arch14 instructions. include/ * opcode/s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_ARCH14. gas/ * config/tc-s390.c (s390_parse_cpu): New entry for arch14. * doc/c-s390.texi: Document arch14 march option. * testsuite/gas/s390/s390.exp: Run the arch14 related tests. * testsuite/gas/s390/zarch-arch14.d: New test. * testsuite/gas/s390/zarch-arch14.s: New test.
2021-02-15 21:20:00 +08:00
2021-02-15 Andreas Krebbel <krebbel@linux.ibm.com>
* s390-mkopc.c (main): Accept arch14 as cpu string.
* s390-opc.txt: Add new arch14 instructions.
bfd, opcodes, libctf: support --with-included-gettext Right now, these libraries hardwire -L../intl -lintl on a few fixed platforms, which works fine on those platforms but on other platforms leads to shared libraries that lack libintl_* symbols when configured --with-included-gettext, and/or static libraries that contain libintl as *another* static library. If we instead use the LIBINTL variable defined in ../intl/config.intl, this gives us the right thing on all three classes of platform (gettext in libc, gettext in system libintl, gettext in ../intl/libintl.a).. This also means we can rip out some Darwin-specific machinery from configure.ac and also simplify the Cygwin side. This also means that the libctf testsuite (and other places that include libbfd, libopcodes or libctf) don't need to grow libintl dependencies just on account of those libraries (though they still need such dependencies if they themselves use gettext machinery). bfd/ChangeLog 2021-02-03 Nick Alcock <nick.alcock@oracle.com> * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in favour of LIBINTL. * configure: Regenerated. libctf/ChangeLog 2021-02-02 Nick Alcock <nick.alcock@oracle.com> * configure.ac (CTF_LIBADD): Remove explicit -lintl population in favour of LIBINTL. * Makefile.am (libctf_nobfd_la_LIBADD): No longer explicitly include $(LIBINTL). (check-DEJAGNU): Pass down to tests as well. * configure: Regenerated. * Makefile.in: Likewise. opcodes/ChangeLog 2021-02-04 Nick Alcock <nick.alcock@oracle.com> * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in favour of LIBINTL. * configure: Regenerated.
2021-02-04 02:42:06 +08:00
2021-02-04 Nick Alcock <nick.alcock@oracle.com>
* configure.ac (SHARED_LIBADD): Remove explicit -lintl population in
favour of LIBINTL.
* configure: Regenerated.
opcodes: tic54x: namespace exported variables The tic54x exports some fairly generic variable names that can conflict with programs that use them, so put proper tic54x_ prefixes on all of them.
2021-01-16 14:00:45 +08:00
2021-02-08 Mike Frysinger <vapier@gentoo.org>
* tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs.
* tic54x-opc.c (regs): Rename to ...
(tic54x_regs): ... this.
(mmregs): Rename to ...
(tic54x_mmregs): ... this.
(condition_codes): Rename to ...
(tic54x_condition_codes): ... this.
(cc2_codes): Rename to ...
(tic54x_cc2_codes): ... this.
(cc3_codes): Rename to ...
(tic54x_cc3_codes): ... this.
(status_bits): Rename to ...
(tic54x_status_bits): ... this.
(misc_symbols): Rename to ...
(tic54x_misc_symbols): ... this.
RISC-V: Removed the v0.93 bitmanip ZBA/ZBB/ZBC instructions. bfd/ * elfxx-riscv.c (riscv_parse_prefixed_ext): Removed zb*. gas/ * config/tc-riscv.c (riscv_multi_subset_supports): Removed INSN_CLASS_ZB*. * testsuite/gas/riscv/bitmanip-insns-32.d: Removed. * testsuite/gas/riscv/bitmanip-insns-64.d: Removed. * testsuite/gas/riscv/bitmanip-insns.s: Removed. include/ * opcode/riscv-opc.h: Removed macros for zb* extensions. * opcode/riscv.h (riscv_insn_class): Removed INSN_CLASS_ZB*. opcodes/ * riscv-opc.c (MASK_RVB_IMM): Removed. (riscv_opcodes): Removed zb* instructions. (riscv_ext_version_table): Removed versions for zb*.
2021-02-04 16:15:03 +08:00
2021-02-04 Nelson Chu <nelson.chu@sifive.com>
* riscv-opc.c (MASK_RVB_IMM): Removed.
(riscv_opcodes): Removed zb* instructions.
(riscv_ext_version_table): Removed versions for zb*.
Segmentation fault i386-gen A case of inst->next being uninitialised. * i386-gen.c (parse_template): Ensure entire template_instance is initialised.
2021-01-26 09:50:23 +08:00
2021-01-26 Alan Modra <amodra@gmail.com>
* i386-gen.c (parse_template): Ensure entire template_instance
is initialised.
RISC-V: Indent and GNU coding standards tidy, also aligned the code. bfd/ * elfnn-riscv.c: Indent, labels and GNU coding standards tidy, also aligned the code. gas/ * config/tc-riscv.c: Indent and GNU coding standards tidy, also aligned the code. * config/tc-riscv.h: Likewise. include/ * opcode/riscv.h: Indent and GNU coding standards tidy, also aligned the code. opcodes/ * riscv-opc.c (riscv_gpr_names_abi): Aligned the code. (riscv_fpr_names_abi): Likewise. (riscv_opcodes): Likewise. (riscv_insn_types): Likewise.
2021-01-15 09:36:51 +08:00
2021-01-15 Nelson Chu <nelson.chu@sifive.com>
* riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
(riscv_fpr_names_abi): Likewise.
(riscv_opcodes): Likewise.
(riscv_insn_types): Likewise.
RISC-V: Error and warning messages tidy. Error and warning messages usually starting with lower case letter, and without the period at the end. Besides, add the prefixed "internel:" at the beginning of the messages when they are caused internally. Also fix indents and typos. bfd/ * elfnn-riscv.c (riscv_merge_attributes): Fix typos of messages. gas/ * config/tc-riscv.c: Error and warning messages tidy. * testsuite/gas/riscv/priv-reg-fail-fext.l: Updated. * testsuite/gas/riscv/priv-reg-fail-read-only-01.l: Likewise. * testsuite/gas/riscv/priv-reg-fail-read-only-02.l: Likewise. * testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise. * testsuite/gas/riscv/priv-reg-fail-version-1p10.l: Likewise. * testsuite/gas/riscv/priv-reg-fail-version-1p11.l: Likewise. * testsuite/gas/riscv/priv-reg-fail-version-1p9p1.l: Likewise. ld/ * testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-01.d: Updated. * testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-02.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-03.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-04.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-05.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-06.d: Likewise. opcodes/ * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
2021-01-13 16:52:14 +08:00
2021-01-15 Nelson Chu <nelson.chu@sifive.com>
* riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
RISC-V: Comments tidy and improvement. The GNU coding standards said the comments should be complete sentences and end with a period and two spaces. But sometimes it should be more cleaner when the comments only include a word or codes. Therefore, I made the following changes after referring to other target/generic codes, * Try to write sentences in comments, must end with a period and two spaces. * End with two spaces without a period for codes/instructions only. * End with one space without a period for a single word/variable only. Besids, also rewrite/remove some comments which are obsolete or too long, and fix indents for comments. bfd/ * elfnn-riscv.c: Comments tidy and improvement. * elfxx-riscv.c: Likewise. * elfxx-riscv.h: Likewise. gas/ * config/tc-riscv.c: Comments tidy and improvement. Also update comment "fallthru" to "Fall through" that end with a period and two spaces. include/ * elf/riscv.h: Comments tidy and improvement. * opcode/riscv-opc.h: Likewise. * opcode/riscv.h: Likewise. opcodes/ * riscv-dis.c: Comments tidy and improvement. * riscv-opc.c: Likewise.
2021-01-13 10:05:48 +08:00
2021-01-15 Nelson Chu <nelson.chu@sifive.com>
* riscv-dis.c: Comments tidy and improvement.
* riscv-opc.c: Likewise.
Regen Makefile.in for jobserver.m4 aclocal.m4 dependency bfd/ * Makefile.in: Regenerate. * doc/Makefile.in: Regenerate. binutils/ * Makefile.in: Regenerate. * doc/Makefile.in: Regenerate. gas/ * Makefile.in: Regenerate. * Makefile.in: Regenerate. gprof/ * Makefile.in: Regenerate. ld/ * Makefile.in: Regenerate. libctf/ * Makefile.in: Regenerate. opcodes/ * Makefile.in: Regenerate.
2021-01-13 16:43:23 +08:00
2021-01-13 Alan Modra <amodra@gmail.com>
* Makefile.in: Regenerate.
Implement a workaround for GNU mak jobserver Compiling binutils using -flto=jobserver with GCC 11 leads to libtool: link: gcc -W -Wall -Wstrict-prototypes -Wmissing-prototypes -Wshadow -Wstack-usage=262144 -Wwrite-strings -I../../gas/../zlib -g -O2 -fprofile-generate -flto=jobserver -o as-new app.o as.o atof-generic.o compress-debug.o cond.o depend.o dwarf2dbg.o dw2gencfi.o ecoff.o ehopt.o expr.o flonum-copy.o flonum-konst.o flonum-mult.o frags.o hash.o input-file.o input-scrub.o listing.o literal.o macro.o messages.o output-file.o read.o remap.o sb.o stabs.o subsegs.o symbols.o write.o config/tc-i386.o config/obj-elf.o config/atof-ieee.o ../opcodes/.libs/libopcodes.a ../bfd/.libs/libbfd.a -L/tmp/binutils-gdb/objdir/zlib -lz ../libiberty/libiberty.a -ldl lto-wrapper: warning: jobserver is not available: '--jobserver-auth=' is not present in 'MAKEFLAGS' since the '+' is missing on the recipe line in Makefiles generated by automake. Add the '+' to the recipe line by hand. bfd/ PR binutils/26792 * configure.ac: Use GNU_MAKE_JOBSERVER. * aclocal.m4: Regenerated. * configure: Likewise. binutils/ PR binutils/26792 * configure.ac: Use GNU_MAKE_JOBSERVER. * aclocal.m4: Regenerated. * configure: Likewise. config/ PR binutils/26792 * jobserver.m4: New file. gas/ PR binutils/26792 * configure.ac: Use GNU_MAKE_JOBSERVER. * aclocal.m4: Regenerated. * configure: Likewise. gprof/ PR binutils/26792 * configure.ac: Use GNU_MAKE_JOBSERVER. * aclocal.m4: Regenerated. * configure: Likewise. ld/ PR binutils/26792 * configure.ac: Use GNU_MAKE_JOBSERVER. * aclocal.m4: Regenerated. * configure: Likewise. libctf/ PR binutils/26792 * configure.ac: Use GNU_MAKE_JOBSERVER. * aclocal.m4: Regenerated. * configure: Likewise. opcodes/ PR binutils/26792 * configure.ac: Use GNU_MAKE_JOBSERVER. * aclocal.m4: Regenerated. * configure: Likewise.
2021-01-12 21:45:28 +08:00
2021-01-12 H.J. Lu <hongjiu.lu@intel.com>
PR binutils/26792
* configure.ac: Use GNU_MAKE_JOBSERVER.
* aclocal.m4: Regenerated.
* configure: Likewise.
Updated translations for some subdirectories
2021-01-12 21:18:50 +08:00
2021-01-12 Nick Clifton <nickc@redhat.com>
* po/sr.po: Updated Serbian translation.
Binutils: Check if AR works with --plugin and rc Check if AR works with --plugin and rc before passing --plugin to AR and RANLIB. bfd/ PR ld/27173 binutils/ PR ld/27173 * configure: Regenerated. gas/ PR ld/27173 * configure: Regenerated. gprof/ PR ld/27173 * configure: Regenerated. ld/ PR ld/27173 * configure: Regenerated. libctf/ PR ld/27173 * configure: Regenerated. opcodes/ PR ld/27173 * configure: Regenerated.
2021-01-12 08:29:31 +08:00
2021-01-11 H.J. Lu <hongjiu.lu@intel.com>
PR ld/27173
* configure: Regenerated.
aarch64: Remove support for CSRE This patch removes support for the CSRE extension from aarch64 gas/objdump. CSRE (FEAT_CSRE) is part of the Future Architecture Technologies program and at this time Arm is withdrawing this particular feature. The patch removes the system registers and the CSR PDEC instruction. gas/ChangeLog * NEWS: Remove CSRE. * config/tc-aarch64.c (parse_csr_operand): Delete. (parse_operands): Delete handling of AARCH64_OPND_CSRE_CSR. (aarch64_features): Remove csre. * doc/c-aarch64.texi: Remove CSRE. * testsuite/gas/aarch64/csre.d: Delete. * testsuite/gas/aarch64/csre-invalid.s: Likewise. * testsuite/gas/aarch64/csre-invalid.d: Likewise. * testsuite/gas/aarch64/csre_csr.s: Likewise. * testsuite/gas/aarch64/csre_csr.d: Likewise. * testsuite/gas/aarch64/csre_csr-invalid.s: Likewise. * testsuite/gas/aarch64/csre_csr-invalid.l: Likewise. * testsuite/gas/aarch64/csre_csr-invalid.d: Likewise. include/ChangeLog * opcode/aarch64.h (AARCH64_FEATURE_CSRE): Delete. (aarch64_opnd): Delete AARCH64_OPND_CSRE_CSR. opcodes/ChangeLog * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Likewise. * aarch64-opc-2.c: Likewise. * aarch64-opc.c (aarch64_print_operand): Delete handling of AARCH64_OPND_CSRE_CSR. * aarch64-tbl.h (aarch64_feature_csre): Delete. (CSRE): Likewise. (_CSRE_INSN): Likewise. (aarch64_opcode_table): Delete csr.
2021-01-06 01:39:04 +08:00
2021-01-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Likewise.
* aarch64-opc-2.c: Likewise.
* aarch64-opc.c (aarch64_print_operand):
Delete handling of AARCH64_OPND_CSRE_CSR.
* aarch64-tbl.h (aarch64_feature_csre): Delete.
(CSRE): Likewise.
(_CSRE_INSN): Likewise.
(aarch64_opcode_table): Delete csr.
Updated translations for multiple subdirectories
2021-01-11 20:55:33 +08:00
2021-01-11 Nick Clifton <nickc@redhat.com>
* po/de.po: Updated German translation.
* po/fr.po: Updated French translation.
* po/pt_BR.po: Updated Brazilian Portuguese translation.
* po/sv.po: Updated Swedish translation.
* po/uk.po: Updated Ukranian translation.
Binutils: Pass --plugin to AR and RANLIB Detect GCC LTO plugin. Pass --plugin to AR and RANLIB to support LTO build. bfd/ * configure: Regenerated. binutils/ * configure: Regenerated. gas/ * configure: Regenerated. gprof/ * configure: Regenerated. ld/ * configure: Regenerated. libctf/ * configure: Regenerated. opcodes/ * configure: Regenerated.
2021-01-09 22:47:58 +08:00
2021-01-09 H.J. Lu <hongjiu.lu@intel.com>
* configure: Regenerated.
Change version number to 2.36.50 and regenerate files
2021-01-09 19:01:01 +08:00
2021-01-09 Nick Clifton <nickc@redhat.com>
* configure: Regenerate.
* po/opcodes.pot: Regenerate.
Add Changelog entries and NEWS entries for 2.36 branch
2021-01-09 18:40:28 +08:00
2021-01-09 Nick Clifton <nickc@redhat.com>
* 2.36 release branch crated.
POWER10: Add Return-Oriented Programming instructions POWER10 adds some return-oriented programming (ROP) instructions and this patch adds support for them. You will notice that they are enabled for POWER8 and later, not just POWER10 and later. This is on purpose. This allows the instructions to be added to POWER8 binaries that can be run on POWER8, POWER9 and POWER10 cpus. On POWER8 and POWER9, these instructions just act as nop's. opcodes/ * ppc-opc.c (insert_dw, (extract_dw): New functions. (DW, (XRC_MASK): Define. (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics. gas/ * testsuite/gas/ppc/rop-checks.d, * testsuite/gas/ppc/rop-checks.l, * testsuite/gas/ppc/rop-checks.s, * testsuite/gas/ppc/rop.d, * testsuite/gas/ppc/rop.s: New tests. * testsuite/gas/ppc/ppc.exp: Run them.
2021-01-09 06:07:12 +08:00
2021-01-08 Peter Bergner <bergner@linux.ibm.com>
* ppc-opc.c (insert_dw, (extract_dw): New functions.
(DW, (XRC_MASK): Define.
(powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
configure regen commit f478212851 did the regen by hand, missed a change in ld/configure and didn't update line numbers. Fix that, and an old regen of ld/Makefile.in with the wrong automake. bfd/ * configure: Regenerate. binutils/ * configure: Regenerate. gas/ * configure: Regenerate. gprof/ * configure: Regenerate. ld/ * Makefile.in: Regenerate. * configure: Regenerate. libctf/ * configure: Regenerate. opcodes/ * configure: Regenerate. zlib/ * configure: Regenerate.
2021-01-09 08:33:29 +08:00
2021-01-09 Alan Modra <amodra@gmail.com>
* configure: Regenerate.
Updated Swedish translation for the opcodes/ subdirectory
2021-01-08 19:55:44 +08:00
2021-01-08 Nick Clifton <nickc@redhat.com>
* po/sv.po: Updated Swedish translation.
Treat the AArch64 register id_aa64mmfr2_el1 as a core system register. PR 27139 * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a core system register.
2021-01-08 19:29:43 +08:00
2021-01-08 Nick Clifton <nickc@redhat.com>
Fix places in the AArch64 opcodes library code where a call to assert() has side effects. PR 27129 * aarch64-dis.c (determine_disassembling_preference): Move call to aarch64_match_operands_constraint outside of the assertion. * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert. Replace with a return of FALSE.
2021-01-08 19:51:50 +08:00
PR 27129
* aarch64-dis.c (determine_disassembling_preference): Move call to
aarch64_match_operands_constraint outside of the assertion.
* aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
Replace with a return of FALSE.
Treat the AArch64 register id_aa64mmfr2_el1 as a core system register. PR 27139 * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a core system register.
2021-01-08 19:29:43 +08:00
PR 27139
* aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
core system register.
libtool.m4: update GNU/Hurd test from upstream. In upstream libtool, 47a889a4ca20 ("Improve GNU/Hurd support.") fixed detection of shlibpath_overrides_runpath, thus avoiding unnecessary relink. This backports it. . * libtool.m4: Match gnu* along other GNU systems. */ChangeLog: * configure: Re-generate.
2021-01-08 00:47:36 +08:00
2021-01-07 Samuel Thibault <samuel.thibault@gnu.org>
* configure: Regenerate.
Updated French translation for the opcodes/ subdirectory.
2021-01-07 22:47:20 +08:00
2021-01-07 Nick Clifton <nickc@redhat.com>
* po/fr.po: Updated French translation.
m68k: Require m68020up rather than m68000up for CHK.L instruction. * m68k-opc.c (chkl): Change minimum architecture requirement to m68020.
2021-01-07 22:44:27 +08:00
2021-01-07 Fredrik Noring <noring@nocrew.org>
* m68k-opc.c (chkl): Change minimum architecture requirement to
m68020.
RISC-V: Add pause hint instruction. Add support for the pause hint instruction, as specified in the Zihintpause extension. The pause instruction is encoded as a special form of a memory fence (which is available as part of the base instruction set). The chosen encoding does not mandate any particular memory ordering and therefore is a true hint. bfd/ * elfxx-riscv.c (riscv_std_z_ext_strtab): Added zihintpause. gas/ * config/tc-riscv.c (riscv_multi_subset_supports): Added INSN_CLASS_ZIHINTPAUSE. * testsuite/gas/riscv/pause.d: New testcase. Adding coverage for the pause hint instruction. * testsuite/gas/riscv/pause.s: Likewise. include/ * opcode/riscv-opc.h: Added MATCH_PAUSE, MASK_PAUSE and DECLARE_INSN for pause hint instruction. * opcode/riscv.h (enum riscv_insn_class): Added INSN_CLASS_ZIHINTPAUSE. opcodes/ * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
2021-01-07 15:53:25 +08:00
2021-01-07 Philipp Tomsich <prt@gnu.org>
* riscv-opc.c (riscv_opcodes): Add pause hint instruction.
RISC-V: Support riscv bitmanip frozen ZBA/ZBB/ZBC instructions (v0.93). In fact rev8/orc.b/zext.h are the aliases of grevi/gorci/pack[w], so we should update them to INSN_ALIAS when we have supported their true instruction in the future. Though we still use the [MATCH|MAKS]_[GREVI|GORCI|PACK|PACKW] to encode them. Besides, the orc.b has the same encoding both in rv32 and rv64, so we just keep one of them in the opcode table. This patch is implemented according to the following link, https://github.com/riscv/riscv-bitmanip/pull/101 2021-01-07 Claire Xenia Wolf <claire@symbioticeda.com> Jim Wilson <jimw@sifive.com> Andrew Waterman <andrew@sifive.com> Maxim Blinov <maxim.blinov@embecosm.com> Kito Cheng <kito.cheng@sifive.com> Nelson Chu <nelson.chu@sifive.com> bfd/ * elfxx-riscv.c (riscv_std_z_ext_strtab): Added zba, zbb and zbc. gas/ * config/tc-riscv.c (riscv_multi_subset_supports): Handle INSN_CLASS_ZB*. (riscv_get_default_ext_version): Do not check the default_isa_spec when the version defined in the riscv_opcodes table is ISA_SPEC_CLASS_DRAFT. * testsuite/gas/riscv/bitmanip-insns-32.d: New testcase. * testsuite/gas/riscv/bitmanip-insns-64.d: Likewise. * testsuite/gas/riscv/bitmanip-insns.s: Likewise. include/ * opcode/riscv-opc.h: Added MASK/MATCH/DECLARE_INSN for ZBA/ZBB/ZBC. * opcode/riscv.h (riscv_insn_class): Added INSN_CLASS_ZB*. (enum riscv_isa_spec_class): Added ISA_SPEC_CLASS_DRAFT for the frozen extensions. opcodes/ * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions. (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
2020-12-15 23:11:03 +08:00
2021-01-07 Claire Xenia Wolf <claire@symbioticeda.com>
Jim Wilson <jimw@sifive.com>
Andrew Waterman <andrew@sifive.com>
Maxim Blinov <maxim.blinov@embecosm.com>
Kito Cheng <kito.cheng@sifive.com>
Nelson Chu <nelson.chu@sifive.com>
* riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
(MASK_RVB_IMM): Used for rev8 and orc.b encoding.
Update year range in copyright notice of binutils files
2021-01-01 06:58:58 +08:00
2021-01-01 Alan Modra <amodra@gmail.com>
Update year range in copyright notice of all files.
ChangeLog rotation
2021-01-01 06:47:13 +08:00
For older changes see ChangeLog-2020
New 2016 binutils ChangeLog files Note that this does not create bfd/doc/ChangeLog, */testsuite/ChangeLog and include/*/ChangeLog files.
2016-01-01 18:44:31 +08:00
ChangeLog rotation
2021-01-01 06:47:13 +08:00
Copyright (C) 2021 Free Software Foundation, Inc.
New 2016 binutils ChangeLog files Note that this does not create bfd/doc/ChangeLog, */testsuite/ChangeLog and include/*/ChangeLog files.
2016-01-01 18:44:31 +08:00
Copying and distribution of this file, with or without modification,
are permitted in any medium without royalty provided the copyright
notice and this notice are preserved.
Local Variables:
mode: change-log
left-margin: 8
fill-column: 74
version-control: never
End:
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