2018-06-01 09:30:46 +08:00
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2018-06-01 Alan Modra <amodra@gmail.com>
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* sysdep.h (_bfd_error_handler): Don't declare.
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* msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here.
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* rl78-decode.opc: Likewise.
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* msp430-decode.c: Regenerate.
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* rl78-decode.c: Regenerate.
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2018-05-30 14:57:35 +08:00
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2018-05-30 Amit Pawar <Amit.Pawar@amd.com>
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* i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
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* i386-init.h : Regenerated.
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2018-05-25 14:35:30 +08:00
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2018-05-25 Alan Modra <amodra@gmail.com>
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* Makefile.in: Regenerate.
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* po/POTFILES.in: Regenerate.
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Remove fake operand handling for extended mnemonics.
opcodes/
* ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
(insert_bab, extract_bab, insert_btab, extract_btab,
insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
(BAT, BBA VBA RBS XB6S): Delete macros.
(BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
(BB, BD, RBX, XC6): Update for new macros.
(powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
* ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
include/
* opcode/ppc.h (PPC_OPERAND_FAKE): Delete macro.
gas/
* config/tc-ppc.c (md_assemble): Delete handling of fake operands.
* testsuite/gas/ppc/common.s (crmove, cror, or., or, nor., nor): Add
test of extended mnemonics.
* testsuite/gas/ppc/common.d: Likewise. Don't match instruction offset.
* testsuite/gas/ppc/spe.s (evor, evnor): Add test of extended mnemonics.
* testsuite/gas/ppc/spe.d: Likewise. Don't match instruction offset.
2018-05-22 06:31:07 +08:00
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2018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
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* ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
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insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
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(insert_bab, extract_bab, insert_btab, extract_btab,
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insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
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(BAT, BBA VBA RBS XB6S): Delete macros.
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(BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
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(BB, BD, RBX, XC6): Update for new macros.
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(powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
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crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
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e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
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* ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
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2018-05-18 22:26:18 +08:00
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2018-05-18 John Darrington <john@darrington.wattle.id.au>
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* Makefile.am: Add support for s12z architecture.
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* configure.ac: Likewise.
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* disassemble.c: Likewise.
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* disassemble.h: Likewise.
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* Makefile.in: Regenerate.
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* configure: Regenerate.
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* s12z-dis.c: New file.
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* s12z.h: New file.
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2018-05-18 07:01:13 +08:00
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2018-05-18 Alan Modra <amodra@gmail.com>
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* nfp-dis.c: Don't #include libbfd.h.
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(init_nfp3200_priv): Use bfd_get_section_contents.
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(nit_nfp6000_mecsr_sec): Likewise.
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2018-05-17 23:24:42 +08:00
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2018-05-17 Nick Clifton <nickc@redhat.com>
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* po/zh_CN.po: Updated simplified Chinese translation.
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2018-05-16 19:13:42 +08:00
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2018-05-16 Tamar Christina <tamar.christina@arm.com>
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PR binutils/23109
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* aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
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* aarch64-dis-2.c: Regenerate.
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Implement Read/Write constraints on system registers on AArch64
This patch adds constraints for read and write only system registers with the
msr and mrs instructions. The code will treat having both flags set and none
set as the same. These flags add constraints that must be matched up. e.g. a
system register with a READ only flag set, can only be used with mrs. If The
constraint fails a warning is emitted.
Examples of the warnings generated:
test.s: Assembler messages:
test.s:5: Warning: specified register cannot be written to at operand 1 -- `msr dbgdtrrx_el0,x3'
test.s:7: Warning: specified register cannot be read from at operand 2 -- `mrs x3,dbgdtrtx_el0'
test.s:8: Warning: specified register cannot be written to at operand 1 -- `msr midr_el1,x3'
and disassembly notes:
0000000000000000 <main>:
0: d5130503 msr dbgdtrtx_el0, x3
4: d5130503 msr dbgdtrtx_el0, x3
8: d5330503 mrs x3, dbgdtrrx_el0
c: d5330503 mrs x3, dbgdtrrx_el0
10: d5180003 msr midr_el1, x3 ; note: writing to a read-only register.
Note that because dbgdtrrx_el0 and dbgdtrtx_el0 have the same encoding, during
disassembly the constraints are use to disambiguate between the two. An exact
constraint match is always prefered over partial ones if available.
As always the warnings can be suppressed with -w and also be made errors using
warnings as errors.
binutils/
PR binutils/21446
* doc/binutils.texi (-M): Document AArch64 options.
gas/
PR binutils/21446
* testsuite/gas/aarch64/illegal-sysreg-2.s: Fix pmbidr_el1 test.
* testsuite/gas/aarch64/illegal-sysreg-2.l: Likewise.
* testsuite/gas/aarch64/illegal-sysreg-2.d: Likewise.
* testsuite/gas/aarch64/sysreg-diagnostic.s: New.
* testsuite/gas/aarch64/sysreg-diagnostic.l: New.
* testsuite/gas/aarch64/sysreg-diagnostic.d: New.
include/
PR binutils/21446
* opcode/aarch64.h (F_SYS_READ, F_SYS_WRITE): New.
opcodes/
PR binutils/21446
* aarch64-asm.c (opintl.h): Include.
(aarch64_ins_sysreg): Enforce read/write constraints.
* aarch64-dis.c (aarch64_ext_sysreg): Likewise.
* aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
(F_REG_READ, F_REG_WRITE): New.
* aarch64-opc.c (aarch64_print_operand): Generate notes for
AARCH64_OPND_SYSREG.
(F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
(aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
* aarch64-tbl.h (aarch64_opcode_table): Add constraints to
msr (F_SYS_WRITE), mrs (F_SYS_READ).
2018-05-15 23:37:20 +08:00
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2018-05-15 Tamar Christina <tamar.christina@arm.com>
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PR binutils/21446
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* aarch64-asm.c (opintl.h): Include.
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(aarch64_ins_sysreg): Enforce read/write constraints.
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* aarch64-dis.c (aarch64_ext_sysreg): Likewise.
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* aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
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(F_REG_READ, F_REG_WRITE): New.
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* aarch64-opc.c (aarch64_print_operand): Generate notes for
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AARCH64_OPND_SYSREG.
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(F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
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(aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
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mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
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id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
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id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
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id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
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mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
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id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
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id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
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id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
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csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
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rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
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mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
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mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
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pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
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* aarch64-tbl.h (aarch64_opcode_table): Add constraints to
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msr (F_SYS_WRITE), mrs (F_SYS_READ).
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2018-05-15 23:34:54 +08:00
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2018-05-15 Tamar Christina <tamar.christina@arm.com>
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PR binutils/21446
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* aarch64-dis.c (no_notes: New.
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(parse_aarch64_dis_option): Support notes.
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(aarch64_decode_insn, print_operands): Likewise.
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(print_aarch64_disassembler_options): Document notes.
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* aarch64-opc.c (aarch64_print_operand): Support notes.
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Modify AArch64 Assembly and disassembly functions to be able to fail and report why.
This patch if the first patch in a series to add the ability to add constraints
to system registers that an instruction must adhere to in order for the register
to be usable with that instruction.
These constraints can also be used to disambiguate between registers with the
same encoding during disassembly.
This patch adds a new flags entry in the sysreg structures and ensures it is
filled in and read out during assembly/disassembly. It also adds the ability for
the assemble and disassemble functions to be able to gracefully fail and re-use
the existing error reporting infrastructure.
The return type of these functions are changed to a boolean to denote success or
failure and the error structure is passed around to them. This requires
aarch64-gen changes so a lot of the changes here are just mechanical.
gas/
PR binutils/21446
* config/tc-aarch64.c (parse_sys_reg): Return register flags.
(parse_operands): Fill in register flags.
gdb/
PR binutils/21446
* aarch64-tdep.c (aarch64_analyze_prologue,
aarch64_software_single_step, aarch64_displaced_step_copy_insn):
Indicate not interested in errors.
include/
PR binutils/21446
* opcode/aarch64.h (aarch64_opnd_info): Change sysreg to struct.
(aarch64_decode_insn): Accept error struct.
opcodes/
PR binutils/21446
* aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
and take error struct.
* aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
aarch64_ins_reglist, aarch64_ins_ldst_reglist,
aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
* aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
* aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
aarch64_ext_reglist, aarch64_ext_ldst_reglist,
aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
(determine_disassembling_preference, aarch64_decode_insn,
print_insn_aarch64_word, print_insn_data): Take errors struct.
(print_insn_aarch64): Use errors.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-gen.c (print_operand_inserter): Use errors and change type to
boolean in aarch64_insert_operan.
(print_operand_extractor): Likewise.
* aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
2018-05-15 23:11:42 +08:00
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2018-05-15 Tamar Christina <tamar.christina@arm.com>
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PR binutils/21446
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* aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
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and take error struct.
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* aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
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aarch64_ins_reglist, aarch64_ins_ldst_reglist,
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aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
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aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
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|
|
aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
|
|
|
|
|
|
aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
|
|
|
|
|
|
aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
|
|
|
|
|
|
aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
|
|
|
|
|
|
aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
|
|
|
|
|
|
aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
|
|
|
|
|
|
aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
|
|
|
|
|
|
aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
|
|
|
|
|
|
aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
|
|
|
|
|
|
aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
|
|
|
|
|
|
aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
|
|
|
|
|
|
aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
|
|
|
|
|
|
aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
|
|
|
|
|
|
aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
|
|
|
|
|
|
aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
|
|
|
|
|
|
aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
|
|
|
|
|
|
aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
|
|
|
|
|
|
aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
|
|
|
|
|
|
aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
|
|
|
|
|
|
aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
|
|
|
|
|
|
aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
|
|
|
|
|
|
* aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
|
|
|
|
|
|
* aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
|
|
|
|
|
|
aarch64_ext_reglist, aarch64_ext_ldst_reglist,
|
|
|
|
|
|
aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
|
|
|
|
|
|
aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
|
|
|
|
|
|
aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
|
|
|
|
|
|
aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
|
|
|
|
|
|
aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
|
|
|
|
|
|
aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
|
|
|
|
|
|
aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
|
|
|
|
|
|
aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
|
|
|
|
|
|
aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
|
|
|
|
|
|
aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
|
|
|
|
|
|
aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
|
|
|
|
|
|
aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
|
|
|
|
|
|
aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
|
|
|
|
|
|
aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
|
|
|
|
|
|
aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
|
|
|
|
|
|
aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
|
|
|
|
|
|
aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
|
|
|
|
|
|
aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
|
|
|
|
|
|
aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
|
|
|
|
|
|
aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
|
|
|
|
|
|
aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
|
|
|
|
|
|
aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
|
|
|
|
|
|
aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
|
|
|
|
|
|
(determine_disassembling_preference, aarch64_decode_insn,
|
|
|
|
|
|
print_insn_aarch64_word, print_insn_data): Take errors struct.
|
|
|
|
|
|
(print_insn_aarch64): Use errors.
|
|
|
|
|
|
* aarch64-asm-2.c: Regenerate.
|
|
|
|
|
|
* aarch64-dis-2.c: Regenerate.
|
|
|
|
|
|
* aarch64-gen.c (print_operand_inserter): Use errors and change type to
|
|
|
|
|
|
boolean in aarch64_insert_operan.
|
|
|
|
|
|
(print_operand_extractor): Likewise.
|
|
|
|
|
|
* aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
|
|
|
|
|
|
|
2018-05-15 20:28:06 +08:00
|
|
|
|
2018-05-15 Francois H. Theron <francois.theron@netronome.com>
|
|
|
|
|
|
|
|
|
|
|
|
* nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
|
|
|
|
|
|
|
2018-05-10 02:17:26 +08:00
|
|
|
|
2018-05-09 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
|
|
|
|
|
|
|
2018-05-09 14:20:29 +08:00
|
|
|
|
2018-05-09 Sebastian Rasmussen <sebras@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* cr16-opc.c (cr16_instruction): Comment typo fix.
|
|
|
|
|
|
* hppa-dis.c (print_insn_hppa): Likewise.
|
|
|
|
|
|
|
RISC-V: Add missing hint instructions from RV128I.
gas/
* testsuite/gas/riscv/c-zero-imm.d: Add more tests.
* testsuite/gas/riscv/c-zero-imm.s: Likewise.
* testsuite/gas/riscv/c-zero-reg.d: Fix typo in test. Add disabled
future test for RV128 support.
* testsuite/gas/riscv/c-zero-reg.s: Likewise.
include/
* opcode/riscv-opc.h (MATCH_C_SRLI64, MASK_C_SRLI64): New.
(MATCH_C_SRAI64, MASK_C_SRAI64): New.
(MATCH_C_SLLI64, MASK_C_SLLI64): New.
opcodes/
* riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
(match_c_slli64, match_srxi_as_c_srxi): New.
(riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
<srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
<c.slli, c.srli, c.srai>: Use match_s_slli.
<c.slli64, c.srli64, c.srai64>: New.
2018-05-09 06:46:19 +08:00
|
|
|
|
2018-05-08 Jim Wilson <jimw@sifive.com>
|
|
|
|
|
|
|
|
|
|
|
|
* riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
|
|
|
|
|
|
(match_c_slli64, match_srxi_as_c_srxi): New.
|
|
|
|
|
|
(riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
|
|
|
|
|
|
<srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
|
|
|
|
|
|
<c.slli, c.srli, c.srai>: Use match_s_slli.
|
|
|
|
|
|
<c.slli64, c.srli64, c.srai64>: New.
|
|
|
|
|
|
|
2018-05-07 10:05:22 +08:00
|
|
|
|
2018-05-08 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
|
|
|
|
|
|
(VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
|
|
|
|
|
|
partition opcode space for index lookup.
|
|
|
|
|
|
|
2018-05-08 09:47:54 +08:00
|
|
|
|
2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
|
|
|
|
|
|
|
|
|
|
|
|
* ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
|
|
|
|
|
|
<insn_length>: ...with this. Update usage.
|
|
|
|
|
|
Remove duplicate call to *info->memory_error_func.
|
|
|
|
|
|
|
Enable Intel MOVDIRI, MOVDIR64B instructions
gas/
* config/tc-i386.c (cpu_arch): Add .movdir, .movdir64b.
(cpu_noarch): Likewise.
(process_suffix): Add check for register size.
* doc/c-i386.texi: Document movdiri, movdir64b.
* testsuite/gas/i386/i386.exp: Run MOVDIR{I,64B} tests.
* testsuite/gas/i386/movdir-intel.d: New file.
* testsuite/gas/i386/movdir.d: Likewise.
* testsuite/gas/i386/movdir.s: Likewise.
* testsuite/gas/i386/movdir64b-reg.s: Likewise.
* testsuite/gas/i386/movdir64b-reg.l: Likewise.
* testsuite/gas/i386/x86-64-movdir-intel.d: Likewise.
* testsuite/gas/i386/x86-64-movdir.d: Likewise.
* testsuite/gas/i386/x86-64-movdir.s: Likewise.
* testsuite/gas/i386/x86-64-movdir64b-reg.s: Likewise.
* testsuite/gas/i386/x86-64-movdir64b-reg.l: Likewise.
opcodes/
* i386-dis.c (Gva): New.
(enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
(prefix_table): New instructions (see prefix above).
(mod_table): New instructions (see prefix above).
(OP_G): Handle va_mode.
* i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
CPU_MOVDIR64B_FLAGS.
(cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
* i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
(i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
* i386-opc.tbl: Add movidir{i,64b}.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2018-05-08 00:30:02 +08:00
|
|
|
|
2018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
|
|
|
|
|
|
H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (Gva): New.
|
|
|
|
|
|
(enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
|
|
|
|
|
|
MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
|
|
|
|
|
|
(prefix_table): New instructions (see prefix above).
|
|
|
|
|
|
(mod_table): New instructions (see prefix above).
|
|
|
|
|
|
(OP_G): Handle va_mode.
|
|
|
|
|
|
* i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
|
|
|
|
|
|
CPU_MOVDIR64B_FLAGS.
|
|
|
|
|
|
(cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
|
|
|
|
|
|
* i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
|
|
|
|
|
|
(i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
|
|
|
|
|
|
* i386-opc.tbl: Add movidir{i,64b}.
|
|
|
|
|
|
* i386-init.h: Regenerated.
|
|
|
|
|
|
* i386-tbl.h: Likewise.
|
|
|
|
|
|
|
2018-05-08 00:57:06 +08:00
|
|
|
|
2018-05-07 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
|
|
|
|
|
|
AddrPrefixOpReg.
|
|
|
|
|
|
* i386-opc.h (AddrPrefixOp0): Renamed to ...
|
|
|
|
|
|
(AddrPrefixOpReg): This.
|
|
|
|
|
|
(i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
|
|
|
|
|
|
* i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
|
|
|
|
|
|
|
2018-05-07 22:40:59 +08:00
|
|
|
|
2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
|
|
|
|
|
|
|
|
|
|
|
|
* ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
|
|
|
|
|
|
(vle_num_opcodes): Likewise.
|
|
|
|
|
|
(spe2_num_opcodes): Likewise.
|
|
|
|
|
|
* ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
|
|
|
|
|
|
initialization loop.
|
|
|
|
|
|
(disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
|
|
|
|
|
|
(disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
|
|
|
|
|
|
only once.
|
|
|
|
|
|
|
2018-05-02 00:11:11 +08:00
|
|
|
|
2018-05-01 Tamar Christina <tamar.christina@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
|
|
|
|
|
|
|
2018-05-01 00:02:59 +08:00
|
|
|
|
2018-04-30 Francois H. Theron <francois.theron@netronome.com>
|
|
|
|
|
|
|
|
|
|
|
|
Makefile.am: Added nfp-dis.c.
|
|
|
|
|
|
configure.ac: Added bfd_nfp_arch.
|
|
|
|
|
|
disassemble.h: Added print_insn_nfp prototype.
|
|
|
|
|
|
disassemble.c: Added ARCH_nfp and call to print_insn_nfp
|
|
|
|
|
|
nfp-dis.c: New, for NFP support.
|
|
|
|
|
|
po/POTFILES.in: Added nfp-dis.c to the list.
|
|
|
|
|
|
Makefile.in: Regenerate.
|
|
|
|
|
|
configure: Regenerate.
|
|
|
|
|
|
|
2018-04-26 14:55:02 +08:00
|
|
|
|
2018-04-26 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl: Fold various non-memory operand AVX512VL
|
|
|
|
|
|
templates into their base ones.
|
|
|
|
|
|
* i386-tlb.h: Re-generate.
|
|
|
|
|
|
|
2018-04-26 14:48:56 +08:00
|
|
|
|
2018-04-26 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
|
|
|
|
|
|
CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
|
|
|
|
|
|
CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
|
|
|
|
|
|
CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
|
|
|
|
|
|
* i386-init.h: Re-generate.
|
|
|
|
|
|
|
2018-04-26 14:48:01 +08:00
|
|
|
|
2018-04-26 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
|
|
|
|
|
|
CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
|
|
|
|
|
|
CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
|
|
|
|
|
|
Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
|
|
|
|
|
|
comment.
|
|
|
|
|
|
(cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
|
|
|
|
|
|
and CpuRegMask.
|
|
|
|
|
|
* i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
|
|
|
|
|
|
CpuRegMask: Delete.
|
|
|
|
|
|
(union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
|
|
|
|
|
|
cpuregzmm, and cpuregmask.
|
|
|
|
|
|
* i386-init.h: Re-generate.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2018-04-26 14:45:35 +08:00
|
|
|
|
2018-04-26 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
|
|
|
|
|
|
CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
|
|
|
|
|
|
* i386-init.h: Re-generate.
|
|
|
|
|
|
|
2018-04-26 14:30:06 +08:00
|
|
|
|
2018-04-26 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-gen.c (VexImmExt): Delete.
|
|
|
|
|
|
* i386-opc.h (VexImmExt, veximmext): Delete.
|
|
|
|
|
|
* i386-opc.tbl: Drop all VexImmExt uses.
|
|
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|
|
* i386-tlb.h: Re-generate.
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|
2018-04-25 22:26:10 +08:00
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|
2018-04-25 Jan Beulich <jbeulich@suse.com>
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|
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* i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
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|
register-only forms.
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|
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* i386-tlb.h: Re-generate.
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|
2018-04-25 20:37:30 +08:00
|
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|
2018-04-25 Tamar Christina <tamar.christina@arm.com>
|
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* aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
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|
2018-04-17 05:09:01 +08:00
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2018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
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* i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
|
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|
PREFIX_0F1C.
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* i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
|
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|
|
(cpu_flags): Add CpuCLDEMOTE.
|
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* i386-init.h: Regenerate.
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* i386-opc.h (enum): Add CpuCLDEMOTE,
|
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(i386_cpu_flags): Add cpucldemote.
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* i386-opc.tbl: Add cldemote.
|
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|
|
* i386-tbl.h: Regenerate.
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2018-04-16 13:59:39 +08:00
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|
2018-04-16 Alan Modra <amodra@gmail.com>
|
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* Makefile.am: Remove sh5 and sh64 support.
|
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|
* configure.ac: Likewise.
|
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|
|
|
|
* disassemble.c: Likewise.
|
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|
|
|
* disassemble.h: Likewise.
|
|
|
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|
|
* sh-dis.c: Likewise.
|
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|
* sh64-dis.c: Delete.
|
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|
|
* sh64-opc.c: Delete.
|
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|
* sh64-opc.h: Delete.
|
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|
|
* Makefile.in: Regenerate.
|
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|
|
* configure: Regenerate.
|
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|
|
* po/POTFILES.in: Regenerate.
|
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|
|
2018-04-16 13:56:05 +08:00
|
|
|
|
2018-04-16 Alan Modra <amodra@gmail.com>
|
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|
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|
* Makefile.am: Remove w65 support.
|
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|
|
|
|
* configure.ac: Likewise.
|
|
|
|
|
|
* disassemble.c: Likewise.
|
|
|
|
|
|
* disassemble.h: Likewise.
|
|
|
|
|
|
* w65-dis.c: Delete.
|
|
|
|
|
|
* w65-opc.h: Delete.
|
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|
|
* Makefile.in: Regenerate.
|
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|
|
|
|
* configure: Regenerate.
|
|
|
|
|
|
* po/POTFILES.in: Regenerate.
|
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|
|
2018-04-16 13:54:43 +08:00
|
|
|
|
2018-04-16 Alan Modra <amodra@gmail.com>
|
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|
|
|
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|
|
* configure.ac: Remove we32k support.
|
|
|
|
|
|
* configure: Regenerate.
|
|
|
|
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|
|
2018-04-16 13:53:38 +08:00
|
|
|
|
2018-04-16 Alan Modra <amodra@gmail.com>
|
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|
|
|
|
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|
|
* Makefile.am: Remove m88k support.
|
|
|
|
|
|
* configure.ac: Likewise.
|
|
|
|
|
|
* disassemble.c: Likewise.
|
|
|
|
|
|
* disassemble.h: Likewise.
|
|
|
|
|
|
* m88k-dis.c: Delete.
|
|
|
|
|
|
* Makefile.in: Regenerate.
|
|
|
|
|
|
* configure: Regenerate.
|
|
|
|
|
|
* po/POTFILES.in: Regenerate.
|
|
|
|
|
|
|
2018-04-16 13:51:56 +08:00
|
|
|
|
2018-04-16 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* Makefile.am: Remove i370 support.
|
|
|
|
|
|
* configure.ac: Likewise.
|
|
|
|
|
|
* disassemble.c: Likewise.
|
|
|
|
|
|
* disassemble.h: Likewise.
|
|
|
|
|
|
* i370-dis.c: Delete.
|
|
|
|
|
|
* i370-opc.c: Delete.
|
|
|
|
|
|
* Makefile.in: Regenerate.
|
|
|
|
|
|
* configure: Regenerate.
|
|
|
|
|
|
* po/POTFILES.in: Regenerate.
|
|
|
|
|
|
|
2018-04-16 13:49:41 +08:00
|
|
|
|
2018-04-16 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* Makefile.am: Remove h8500 support.
|
|
|
|
|
|
* configure.ac: Likewise.
|
|
|
|
|
|
* disassemble.c: Likewise.
|
|
|
|
|
|
* disassemble.h: Likewise.
|
|
|
|
|
|
* h8500-dis.c: Delete.
|
|
|
|
|
|
* h8500-opc.h: Delete.
|
|
|
|
|
|
* Makefile.in: Regenerate.
|
|
|
|
|
|
* configure: Regenerate.
|
|
|
|
|
|
* po/POTFILES.in: Regenerate.
|
|
|
|
|
|
|
2018-04-16 13:38:40 +08:00
|
|
|
|
2018-04-16 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* configure.ac: Remove tahoe support.
|
|
|
|
|
|
* configure: Regenerate.
|
|
|
|
|
|
|
2018-04-15 23:38:23 +08:00
|
|
|
|
2018-04-15 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (prefix_table): Replace Em with Edq on tpause and
|
|
|
|
|
|
umwait.
|
|
|
|
|
|
* i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
|
|
|
|
|
|
64-bit mode.
|
|
|
|
|
|
* i386-tbl.h: Regenerated.
|
|
|
|
|
|
|
2018-04-09 18:58:50 +08:00
|
|
|
|
2018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
|
|
|
|
|
|
PREFIX_MOD_1_0FAE_REG_6.
|
|
|
|
|
|
(va_mode): New.
|
|
|
|
|
|
(OP_E_register): Use va_mode.
|
|
|
|
|
|
* i386-dis-evex.h (prefix_table):
|
|
|
|
|
|
New instructions (see prefixes above).
|
|
|
|
|
|
* i386-gen.c (cpu_flag_init): Add WAITPKG.
|
|
|
|
|
|
(cpu_flags): Likewise.
|
|
|
|
|
|
* i386-opc.h (enum): Likewise.
|
|
|
|
|
|
(i386_cpu_flags): Likewise.
|
|
|
|
|
|
* i386-opc.tbl: Add umonitor, umwait, tpause.
|
|
|
|
|
|
* i386-init.h: Regenerate.
|
|
|
|
|
|
* i386-tbl.h: Likewise.
|
|
|
|
|
|
|
Remove i860, i960, bout and aout-adobe targets
Plus remove a few leftovers from the 29k support.
include/
* aout/adobe.h: Delete.
* aout/reloc.h: Delete.
* coff/i860.h: Delete.
* coff/i960.h: Delete.
* elf/i860.h: Delete.
* elf/i960.h: Delete.
* opcode/i860.h: Delete.
* opcode/i960.h: Delete.
* aout/aout64.h (enum reloc_type): Trim off 29k and other unused values.
* aout/ar.h (ARMAGB): Remove.
* coff/internal.h (struct internal_aouthdr, struct internal_scnhdr,
union internal_auxent): Remove i960 support.
bfd/
* aout-adobe.c: Delete.
* bout.c: Delete.
* coff-i860.c: Delete.
* coff-i960.c: Delete.
* cpu-i860.c: Delete.
* cpu-i960.c: Delete.
* elf32-i860.c: Delete.
* elf32-i960.c: Delete.
* hosts/i860mach3.h: Delete.
* Makefile.am: Remove i860, i960, bout, and adobe support.
* archures.c: Remove i860 and i960 support.
* coffcode.h: Likewise.
* reloc.c: Likewise.
* aoutx.h: Comment updates.
* archive.c: Remove BOUT and i960 support.
* bfd.c: Remove BOUT support.
* coffswap.h: Remove i960 support.
* config.bfd: Remove i860, i960 and adobe targets.
* configure.ac: Remove adode, bout, i860, i960, icoff targets.
* targets.c: Likewise.
* ieee.c: Remove i960 support.
* mach-o.c: Remove i860 support.
* Makefile.in: Regenerate.
* bfd-in2.h: Regenerate.
* configure: Regenerate.
* libbfd.h: Regenerate.
* po/SRC-POTFILES.in: Regenerate.
opcodes/
* opcodes/i860-dis.c: Delete.
* opcodes/i960-dis.c: Delete.
* Makefile.am: Remove i860 and i960 support.
* configure.ac: Likewise.
* disassemble.c: Likewise.
* disassemble.h: Likewise.
* Makefile.in: Regenerate.
* configure: Regenerate.
* po/POTFILES.in: Regenerate.
binutils/
* ieee.c: Remove i960 support.
* od-macho.c: Remove i860 support.
* readelf.c: Remove i860 and i960 support.
* testsuite/binutils-all/objcopy.exp: Likewise.
* testsuite/binutils-all/objdump.exp: Likewise.
* testsuite/lib/binutils-common.exp: Likewise.
gas/
* config/aout_gnu.h: Delete.
* config/tc-i860.c: Delete.
* config/tc-i860.h: Delete.
* config/tc-i960.c: Delete.
* config/tc-i960.h: Delete.
* doc/c-i860.texi: Delete.
* doc/c-i960.texi: Delete.
* testsuite/gas/i860/README.i860: Delete.
* testsuite/gas/i860/bitwise.d: Delete.
* testsuite/gas/i860/bitwise.s: Delete.
* testsuite/gas/i860/branch.d: Delete.
* testsuite/gas/i860/branch.s: Delete.
* testsuite/gas/i860/bte.d: Delete.
* testsuite/gas/i860/bte.s: Delete.
* testsuite/gas/i860/dir-align01.d: Delete.
* testsuite/gas/i860/dir-align01.s: Delete.
* testsuite/gas/i860/dir-intel01.d: Delete.
* testsuite/gas/i860/dir-intel01.s: Delete.
* testsuite/gas/i860/dir-intel02.d: Delete.
* testsuite/gas/i860/dir-intel02.s: Delete.
* testsuite/gas/i860/dir-intel03-err.l: Delete.
* testsuite/gas/i860/dir-intel03-err.s: Delete.
* testsuite/gas/i860/dual01.d: Delete.
* testsuite/gas/i860/dual01.s: Delete.
* testsuite/gas/i860/dual02-err.l: Delete.
* testsuite/gas/i860/dual02-err.s: Delete.
* testsuite/gas/i860/dual03.d: Delete.
* testsuite/gas/i860/dual03.s: Delete.
* testsuite/gas/i860/fldst01.d: Delete.
* testsuite/gas/i860/fldst01.s: Delete.
* testsuite/gas/i860/fldst02.d: Delete.
* testsuite/gas/i860/fldst02.s: Delete.
* testsuite/gas/i860/fldst03.d: Delete.
* testsuite/gas/i860/fldst03.s: Delete.
* testsuite/gas/i860/fldst04.d: Delete.
* testsuite/gas/i860/fldst04.s: Delete.
* testsuite/gas/i860/fldst05.d: Delete.
* testsuite/gas/i860/fldst05.s: Delete.
* testsuite/gas/i860/fldst06.d: Delete.
* testsuite/gas/i860/fldst06.s: Delete.
* testsuite/gas/i860/fldst07.d: Delete.
* testsuite/gas/i860/fldst07.s: Delete.
* testsuite/gas/i860/fldst08.d: Delete.
* testsuite/gas/i860/fldst08.s: Delete.
* testsuite/gas/i860/float01.d: Delete.
* testsuite/gas/i860/float01.s: Delete.
* testsuite/gas/i860/float02.d: Delete.
* testsuite/gas/i860/float02.s: Delete.
* testsuite/gas/i860/float03.d: Delete.
* testsuite/gas/i860/float03.s: Delete.
* testsuite/gas/i860/float04.d: Delete.
* testsuite/gas/i860/float04.s: Delete.
* testsuite/gas/i860/form.d: Delete.
* testsuite/gas/i860/form.s: Delete.
* testsuite/gas/i860/i860.exp: Delete.
* testsuite/gas/i860/iarith.d: Delete.
* testsuite/gas/i860/iarith.s: Delete.
* testsuite/gas/i860/ldst01.d: Delete.
* testsuite/gas/i860/ldst01.s: Delete.
* testsuite/gas/i860/ldst02.d: Delete.
* testsuite/gas/i860/ldst02.s: Delete.
* testsuite/gas/i860/ldst03.d: Delete.
* testsuite/gas/i860/ldst03.s: Delete.
* testsuite/gas/i860/ldst04.d: Delete.
* testsuite/gas/i860/ldst04.s: Delete.
* testsuite/gas/i860/ldst05.d: Delete.
* testsuite/gas/i860/ldst05.s: Delete.
* testsuite/gas/i860/ldst06.d: Delete.
* testsuite/gas/i860/ldst06.s: Delete.
* testsuite/gas/i860/pfam.d: Delete.
* testsuite/gas/i860/pfam.s: Delete.
* testsuite/gas/i860/pfmam.d: Delete.
* testsuite/gas/i860/pfmam.s: Delete.
* testsuite/gas/i860/pfmsm.d: Delete.
* testsuite/gas/i860/pfmsm.s: Delete.
* testsuite/gas/i860/pfsm.d: Delete.
* testsuite/gas/i860/pfsm.s: Delete.
* testsuite/gas/i860/pseudo-ops01.d: Delete.
* testsuite/gas/i860/pseudo-ops01.s: Delete.
* testsuite/gas/i860/regress01.d: Delete.
* testsuite/gas/i860/regress01.s: Delete.
* testsuite/gas/i860/shift.d: Delete.
* testsuite/gas/i860/shift.s: Delete.
* testsuite/gas/i860/simd.d: Delete.
* testsuite/gas/i860/simd.s: Delete.
* testsuite/gas/i860/system.d: Delete.
* testsuite/gas/i860/system.s: Delete.
* testsuite/gas/i860/xp.d: Delete.
* testsuite/gas/i860/xp.s: Delete.
* Makefile.am: Remove i860 and i960 support.
* configure.tgt: Likewise.
* doc/Makefile.am: Likewise.
* doc/all.texi: Likewise.
* testsuite/gas/all/gas.exp
* config/obj-coff.h: Remove i960 support.
* doc/internals.texi: Likewise.
* expr.c: Likewise.
* read.c: Likewise.
* write.c: Likewise.
* write.h: Likewise.
* testsuite/gas/lns/lns.exp: Likewise.
* testsuite/gas/symver/symver.exp: Likewise.
* config/tc-m68k.c: Remove BOUT support.
* config/tc-score.c: Likewise.
* config/tc-score7.c: Likewise.
* config/tc-sparc.c: Likewise.
* symbols.c: Likewise.
* doc/h8.texi: Likewise.
* configure.ac: Remove BOUT and i860 support.
* doc/as.texinfo: Remove BOUT, i860 and i960 support
* Makefile.in: Regenerate.
* config.in: Regenerate.
* configure: Regenerate.
* doc/Makefile.in: Regenerate.
* po/POTFILES.in: Regenerate.
ld/
* emulparams/coff_i860.sh: Delete.
* emulparams/elf32_i860.sh: Delete.
* emulparams/elf32_i960.sh: Delete.
* emulparams/gld960.sh: Delete.
* emulparams/gld960coff.sh: Delete.
* emulparams/lnk960.sh: Delete.
* emultempl/gld960.em: Delete.
* emultempl/gld960c.em: Delete.
* emultempl/lnk960.em: Delete.
* scripttempl/i860coff.sc: Delete.
* scripttempl/i960.sc: Delete.
* ld.texinfo: Remove i960 support.
* Makefile.am: Remove i860 and i960 support.
* configure.tgt: Likewise.
* testsuite/ld-discard/extern.d: Likewise.
* testsuite/ld-discard/start.d: Likewise.
* testsuite/ld-discard/static.d: Likewise.
* testsuite/ld-elf/compressed1d.d: Likewise.
* testsuite/ld-elf/group1.d: Likewise.
* testsuite/ld-elf/group3b.d: Likewise.
* testsuite/ld-elf/group8a.d: Likewise.
* testsuite/ld-elf/group8b.d: Likewise.
* testsuite/ld-elf/group9a.d: Likewise.
* testsuite/ld-elf/group9b.d: Likewise.
* testsuite/ld-elf/linkonce2.d: Likewise.
* testsuite/ld-elf/merge.d: Likewise.
* testsuite/ld-elf/merge2.d: Likewise.
* testsuite/ld-elf/merge3.d: Likewise.
* testsuite/ld-elf/orphan-10.d: Likewise.
* testsuite/ld-elf/orphan-11.d: Likewise.
* testsuite/ld-elf/orphan-12.d: Likewise.
* testsuite/ld-elf/orphan-9.d: Likewise.
* testsuite/ld-elf/orphan-region.d: Likewise.
* testsuite/ld-elf/orphan.d: Likewise.
* testsuite/ld-elf/orphan3.d: Likewise.
* testsuite/ld-elf/pr12851.d: Likewise.
* testsuite/ld-elf/pr12975.d: Likewise.
* testsuite/ld-elf/pr13177.d: Likewise.
* testsuite/ld-elf/pr13195.d: Likewise.
* testsuite/ld-elf/pr17550a.d: Likewise.
* testsuite/ld-elf/pr17550b.d: Likewise.
* testsuite/ld-elf/pr17550c.d: Likewise.
* testsuite/ld-elf/pr17550d.d: Likewise.
* testsuite/ld-elf/pr17615.d: Likewise.
* testsuite/ld-elf/pr20528a.d: Likewise.
* testsuite/ld-elf/pr20528b.d: Likewise.
* testsuite/ld-elf/pr21562a.d: Likewise.
* testsuite/ld-elf/pr21562b.d: Likewise.
* testsuite/ld-elf/pr21562c.d: Likewise.
* testsuite/ld-elf/pr21562d.d: Likewise.
* testsuite/ld-elf/pr21562i.d: Likewise.
* testsuite/ld-elf/pr21562j.d: Likewise.
* testsuite/ld-elf/pr21562k.d: Likewise.
* testsuite/ld-elf/pr21562l.d: Likewise.
* testsuite/ld-elf/pr21562m.d: Likewise.
* testsuite/ld-elf/pr21562n.d: Likewise.
* testsuite/ld-elf/pr22677.d: Likewise.
* testsuite/ld-elf/pr22836-1a.d: Likewise.
* testsuite/ld-elf/pr22836-1b.d: Likewise.
* testsuite/ld-elf/pr349.d: Likewise.
* testsuite/ld-elf/sec-to-seg.exp: Likewise.
* testsuite/ld-elf/sec64k.exp: Likewise.
* testsuite/ld-elf/warn1.d: Likewise.
* testsuite/ld-elf/warn2.d: Likewise.
* testsuite/ld-elf/warn3.d: Likewise.
* testsuite/lib/ld-lib.exp: Likewise.
* Makefile.in: Regenerate.
* po/BLD-POTFILES.in: Regenerate.
2018-04-11 17:16:05 +08:00
|
|
|
|
2018-04-11 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* opcodes/i860-dis.c: Delete.
|
|
|
|
|
|
* opcodes/i960-dis.c: Delete.
|
|
|
|
|
|
* Makefile.am: Remove i860 and i960 support.
|
|
|
|
|
|
* configure.ac: Likewise.
|
|
|
|
|
|
* disassemble.c: Likewise.
|
|
|
|
|
|
* disassemble.h: Likewise.
|
|
|
|
|
|
* Makefile.in: Regenerate.
|
|
|
|
|
|
* configure: Regenerate.
|
|
|
|
|
|
* po/POTFILES.in: Regenerate.
|
|
|
|
|
|
|
2018-04-04 19:36:44 +08:00
|
|
|
|
2018-04-04 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR binutils/23025
|
|
|
|
|
|
* i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
|
|
|
|
|
|
to 0.
|
|
|
|
|
|
(print_insn): Clear vex instead of vex.evex.
|
|
|
|
|
|
|
2018-04-04 16:00:18 +08:00
|
|
|
|
2018-04-04 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* po/es.po: Updated Spanish translation.
|
|
|
|
|
|
|
2018-03-28 20:25:07 +08:00
|
|
|
|
2018-03-28 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-gen.c (opcode_modifiers): Delete VecESize.
|
|
|
|
|
|
* i386-opc.h (VecESize): Delete.
|
|
|
|
|
|
(struct i386_opcode_modifier): Delete vecesize.
|
|
|
|
|
|
* i386-opc.tbl: Drop VecESize.
|
|
|
|
|
|
* i386-tlb.h: Re-generate.
|
|
|
|
|
|
|
2018-03-28 20:24:05 +08:00
|
|
|
|
2018-03-28 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
|
|
|
|
|
|
BROADCAST_1TO4, BROADCAST_1TO2): Delete.
|
|
|
|
|
|
(struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
|
|
|
|
|
|
* i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
|
|
|
|
|
|
* i386-tlb.h: Re-generate.
|
|
|
|
|
|
|
2018-03-28 20:22:56 +08:00
|
|
|
|
2018-03-28 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
|
|
|
|
|
|
Fold AVX512 forms
|
|
|
|
|
|
* i386-tlb.h: Re-generate.
|
|
|
|
|
|
|
2018-03-28 20:22:00 +08:00
|
|
|
|
2018-03-28 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (prefix_table): Drop Y for cvt*2si.
|
|
|
|
|
|
(vex_len_table): Drop Y for vcvt*2si.
|
|
|
|
|
|
(putop): Replace plain 'Y' handling by abort().
|
|
|
|
|
|
|
2018-03-28 16:44:45 +08:00
|
|
|
|
2018-03-28 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR 22988
|
|
|
|
|
|
* aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
|
|
|
|
|
|
instructions with only a base address register.
|
|
|
|
|
|
* aarch64-opc.c (operand_general_constraint_met_p): Add code to
|
|
|
|
|
|
handle AARHC64_OPND_SVE_ADDR_R.
|
|
|
|
|
|
(aarch64_print_operand): Likewise.
|
|
|
|
|
|
* aarch64-asm-2.c: Regenerate.
|
|
|
|
|
|
* aarch64_dis-2.c: Regenerate.
|
|
|
|
|
|
* aarch64-opc-2.c: Regenerate.
|
|
|
|
|
|
|
2018-03-22 15:46:25 +08:00
|
|
|
|
2018-03-22 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl: Drop VecESize from register only insn forms and
|
|
|
|
|
|
memory forms not allowing broadcast.
|
|
|
|
|
|
* i386-tlb.h: Re-generate.
|
|
|
|
|
|
|
2018-03-22 15:34:24 +08:00
|
|
|
|
2018-03-22 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
|
|
|
|
|
|
vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
|
|
|
|
|
|
sha256*): Drop Disp<N>.
|
|
|
|
|
|
|
2018-03-22 15:32:50 +08:00
|
|
|
|
2018-03-22 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (EbndS, bnd_swap_mode): New.
|
|
|
|
|
|
(prefix_table): Use EbndS.
|
|
|
|
|
|
(OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
|
|
|
|
|
|
* i386-opc.tbl (bndmov): Move misplaced Load.
|
|
|
|
|
|
* i386-tlb.h: Re-generate.
|
|
|
|
|
|
|
2018-03-22 15:31:43 +08:00
|
|
|
|
2018-03-22 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
|
|
|
|
|
|
templates allowing memory operands and folded ones for register
|
|
|
|
|
|
only flavors.
|
|
|
|
|
|
* i386-tlb.h: Re-generate.
|
|
|
|
|
|
|
2018-03-22 15:29:45 +08:00
|
|
|
|
2018-03-22 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
|
|
|
|
|
|
256-bit templates. Drop redundant leftover Disp<N>.
|
|
|
|
|
|
* i386-tlb.h: Re-generate.
|
|
|
|
|
|
|
2018-03-15 07:04:03 +08:00
|
|
|
|
2018-03-14 Kito Cheng <kito.cheng@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* riscv-opc.c (riscv_insn_types): New.
|
|
|
|
|
|
|
2018-03-14 00:57:29 +08:00
|
|
|
|
2018-03-13 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* po/pt_BR.po: Updated Brazilian Portuguese translation.
|
|
|
|
|
|
|
2018-03-08 22:41:34 +08:00
|
|
|
|
2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl: Add Optimize to clr.
|
|
|
|
|
|
* i386-tbl.h: Regenerated.
|
|
|
|
|
|
|
2018-03-08 22:31:32 +08:00
|
|
|
|
2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-gen.c (opcode_modifiers): Remove OldGcc.
|
|
|
|
|
|
* i386-opc.h (OldGcc): Removed.
|
|
|
|
|
|
(i386_opcode_modifier): Remove oldgcc.
|
|
|
|
|
|
* i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
|
|
|
|
|
|
instructions for old (<= 2.8.1) versions of gcc.
|
|
|
|
|
|
* i386-tbl.h: Regenerated.
|
|
|
|
|
|
|
2018-03-08 15:58:55 +08:00
|
|
|
|
2018-03-08 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.h (EVEXDYN): New.
|
|
|
|
|
|
* i386-opc.tbl: Fold various AVX512VL templates.
|
|
|
|
|
|
* i386-tlb.h: Re-generate.
|
|
|
|
|
|
|
2018-03-08 15:58:05 +08:00
|
|
|
|
2018-03-08 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
|
|
|
|
|
|
vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
|
|
|
|
|
|
vpexpandd, vpexpandq): Fold AFX512VF templates.
|
|
|
|
|
|
* i386-tlb.h: Re-generate.
|
|
|
|
|
|
|
2018-03-08 15:57:19 +08:00
|
|
|
|
2018-03-08 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
|
|
|
|
|
|
Fold 128- and 256-bit VEX-encoded templates.
|
|
|
|
|
|
* i386-tlb.h: Re-generate.
|
|
|
|
|
|
|
2018-03-08 15:56:47 +08:00
|
|
|
|
2018-03-08 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
|
|
|
|
|
|
vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
|
|
|
|
|
|
vpexpandd, vpexpandq): Fold AVX512F templates.
|
|
|
|
|
|
* i386-tlb.h: Re-generate.
|
|
|
|
|
|
|
2018-03-08 15:56:08 +08:00
|
|
|
|
2018-03-08 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
|
|
|
|
|
|
64-bit templates. Drop Disp<N>.
|
|
|
|
|
|
* i386-tlb.h: Re-generate.
|
|
|
|
|
|
|
2018-03-08 15:55:37 +08:00
|
|
|
|
2018-03-08 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
|
|
|
|
|
|
and 256-bit templates.
|
|
|
|
|
|
* i386-tlb.h: Re-generate.
|
|
|
|
|
|
|
2018-03-08 15:52:27 +08:00
|
|
|
|
2018-03-08 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (cmpxchg8b): Add NoRex64.
|
|
|
|
|
|
* i386-tlb.h: Re-generate.
|
|
|
|
|
|
|
2018-03-08 15:36:41 +08:00
|
|
|
|
2018-03-08 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
|
|
|
|
|
|
Drop NoAVX.
|
|
|
|
|
|
* i386-tlb.h: Re-generate.
|
|
|
|
|
|
|
2018-03-08 15:35:48 +08:00
|
|
|
|
2018-03-08 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
|
|
|
|
|
|
* i386-tlb.h: Re-generate.
|
|
|
|
|
|
|
2018-03-08 15:34:09 +08:00
|
|
|
|
2018-03-08 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-gen.c (opcode_modifiers): Delete FloatD.
|
|
|
|
|
|
* i386-opc.h (FloatD): Delete.
|
|
|
|
|
|
(struct i386_opcode_modifier): Delete floatd.
|
|
|
|
|
|
* i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
|
|
|
|
|
|
FloatD by D.
|
|
|
|
|
|
* i386-tlb.h: Re-generate.
|
|
|
|
|
|
|
2018-03-08 15:33:06 +08:00
|
|
|
|
2018-03-08 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
|
|
|
|
|
|
|
2018-03-08 15:26:35 +08:00
|
|
|
|
2018-03-08 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (vmovd): Disallow Qword memory operands.
|
|
|
|
|
|
* i386-tlb.h: Re-generate.
|
|
|
|
|
|
|
2018-03-08 15:25:31 +08:00
|
|
|
|
2018-03-08 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
|
|
|
|
|
|
forms.
|
|
|
|
|
|
* i386-tlb.h: Re-generate.
|
|
|
|
|
|
|
2018-03-07 08:36:15 +08:00
|
|
|
|
2018-03-07 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* disassemble.c (disassembler): Use bfd_arch_powerpc entry for
|
|
|
|
|
|
bfd_arch_rs6000.
|
|
|
|
|
|
* disassemble.h (print_insn_rs6000): Delete.
|
|
|
|
|
|
* ppc-dis.c (powerpc_init_dialect): Handle rs6000.
|
|
|
|
|
|
(disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
|
|
|
|
|
|
(print_insn_rs6000): Delete.
|
|
|
|
|
|
|
opcodes error messages
Another patch aimed at making binutils comply with the GNU coding
standard. The generated files require
https://sourceware.org/ml/cgen/2018-q1/msg00004.html
cpu/
* frv.opc: Include opintl.h.
(add_next_to_vliw): Use opcodes_error_handler to print error.
Standardize error message.
(fr500_check_insn_major_constraints, frv_vliw_add_insn): Likewise.
opcodes/
* sysdep.h (opcodes_error_handler): Define.
(_bfd_error_handler): Declare.
* Makefile.am: Remove stray #.
* opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
EDIT" comment.
* aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
* d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
* riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
opcodes_error_handler to print errors. Standardize error messages.
* msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
and include opintl.h.
* nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
* i386-gen.c: Standardize error messages.
* msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
* Makefile.in: Regenerate.
* epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
* epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
* fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
* frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
* iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
* lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
* m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
* m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
* mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
* mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
* or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
* xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
* xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
2018-03-02 05:53:50 +08:00
|
|
|
|
2018-03-03 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* sysdep.h (opcodes_error_handler): Define.
|
|
|
|
|
|
(_bfd_error_handler): Declare.
|
|
|
|
|
|
* Makefile.am: Remove stray #.
|
|
|
|
|
|
* opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
|
|
|
|
|
|
EDIT" comment.
|
|
|
|
|
|
* aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
|
|
|
|
|
|
* d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
|
|
|
|
|
|
* riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
|
|
|
|
|
|
opcodes_error_handler to print errors. Standardize error messages.
|
|
|
|
|
|
* msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
|
|
|
|
|
|
and include opintl.h.
|
|
|
|
|
|
* nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
|
|
|
|
|
|
* i386-gen.c: Standardize error messages.
|
|
|
|
|
|
* msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
|
|
|
|
|
|
* Makefile.in: Regenerate.
|
|
|
|
|
|
* epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
|
|
|
|
|
|
* epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
|
|
|
|
|
|
* fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
|
|
|
|
|
|
* frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
|
|
|
|
|
|
* iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
|
|
|
|
|
|
* lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
|
|
|
|
|
|
* m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
|
|
|
|
|
|
* m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
|
|
|
|
|
|
* mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
|
|
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|
|
|
* mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
|
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|
|
|
* or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
|
|
|
|
|
|
* xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
|
|
|
|
|
|
* xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
|
|
|
|
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|
|
2018-03-01 22:08:04 +08:00
|
|
|
|
2018-03-01 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
|
|
|
|
|
|
vpsub[bwdq] instructions.
|
|
|
|
|
|
* i386-tbl.h: Regenerated.
|
|
|
|
|
|
|
2018-03-01 05:56:51 +08:00
|
|
|
|
2018-03-01 Alan Modra <amodra@gmail.com>
|
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|
|
|
|
|
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|
|
* configure.ac (ALL_LINGUAS): Sort.
|
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|
|
* configure: Regenerate.
|
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|
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|
|
2018-02-28 00:40:45 +08:00
|
|
|
|
2018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
|
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|
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|
|
|
* arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
|
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|
macro by assignements.
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x86: Add -O[2|s] assembler command-line options
On x86, some instructions have alternate shorter encodings:
1. When the upper 32 bits of destination registers of
andq $imm31, %r64
testq $imm31, %r64
xorq %r64, %r64
subq %r64, %r64
known to be zero, we can encode them without the REX_W bit:
andl $imm31, %r32
testl $imm31, %r32
xorl %r32, %r32
subl %r32, %r32
This optimization is enabled with -O, -O2 and -Os.
2. Since 0xb0 mov with 32-bit destination registers zero-extends 32-bit
immediate to 64-bit destination register, we can use it to encode 64-bit
mov with 32-bit immediates. This optimization is enabled with -O, -O2
and -Os.
3. Since the upper bits of destination registers of VEX128 and EVEX128
instructions are extended to zero, if all bits of destination registers
of AVX256 or AVX512 instructions are zero, we can use VEX128 or EVEX128
encoding to encode AVX256 or AVX512 instructions. When 2 source
registers are identical, AVX256 and AVX512 andn and xor instructions:
VOP %reg, %reg, %dest_reg
can be encoded with
VOP128 %reg, %reg, %dest_reg
This optimization is enabled with -O2 and -Os.
4. 16-bit, 32-bit and 64-bit register tests with immediate may be
encoded as 8-bit register test with immediate. This optimization is
enabled with -Os.
This patch does:
1. Add {nooptimize} pseudo prefix to disable instruction size
optimization.
2. Add optimize to i386_opcode_modifier to tell assembler that encoding
of an instruction may be optimized.
gas/
PR gas/22871
* NEWS: Mention -O[2|s].
* config/tc-i386.c (_i386_insn): Add no_optimize.
(optimize): New.
(optimize_for_space): Likewise.
(fits_in_imm7): New function.
(fits_in_imm31): Likewise.
(optimize_encoding): Likewise.
(md_assemble): Call optimize_encoding to optimize encoding.
(parse_insn): Handle {nooptimize}.
(md_shortopts): Append "O::".
(md_parse_option): Handle -On.
* doc/c-i386.texi: Document -O0, -O, -O1, -O2 and -Os as well
as {nooptimize}.
* testsuite/gas/cfi/cfi-x86_64.d: Pass -O0 to assembler.
* testsuite/gas/i386/ilp32/cfi/cfi-x86_64.d: Likewise.
* testsuite/gas/i386/i386.exp: Run optimize-1, optimize-2,
optimize-3, x86-64-optimize-1, x86-64-optimize-2,
x86-64-optimize-3 and x86-64-optimize-4.
* testsuite/gas/i386/optimize-1.d: New file.
* testsuite/gas/i386/optimize-1.s: Likewise.
* testsuite/gas/i386/optimize-2.d: Likewise.
* testsuite/gas/i386/optimize-2.s: Likewise.
* testsuite/gas/i386/optimize-3.d: Likewise.
* testsuite/gas/i386/optimize-3.s: Likewise.
* testsuite/gas/i386/x86-64-optimize-1.s: Likewise.
* testsuite/gas/i386/x86-64-optimize-1.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-2.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-2.s: Likewise.
* testsuite/gas/i386/x86-64-optimize-3.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-3.s: Likewise.
* testsuite/gas/i386/x86-64-optimize-4.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-4.s: Likewise.
opcodes/
PR gas/22871
* i386-gen.c (opcode_modifiers): Add Optimize.
* i386-opc.h (Optimize): New enum.
(i386_opcode_modifier): Add optimize.
* i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
"sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
"and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
"movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
vpxord and vpxorq.
* i386-tbl.h: Regenerated.
2018-02-27 23:36:33 +08:00
|
|
|
|
2018-02-27 H.J. Lu <hongjiu.lu@intel.com>
|
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|
|
PR gas/22871
|
|
|
|
|
|
* i386-gen.c (opcode_modifiers): Add Optimize.
|
|
|
|
|
|
* i386-opc.h (Optimize): New enum.
|
|
|
|
|
|
(i386_opcode_modifier): Add optimize.
|
|
|
|
|
|
* i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
|
|
|
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|
|
"sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
|
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|
|
"and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
|
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|
|
|
"movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
|
|
|
|
|
|
vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
|
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|
|
|
vpxord and vpxorq.
|
|
|
|
|
|
* i386-tbl.h: Regenerated.
|
|
|
|
|
|
|
2018-02-24 08:03:33 +08:00
|
|
|
|
2018-02-26 Alan Modra <amodra@gmail.com>
|
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|
|
|
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|
|
* crx-dis.c (getregliststring): Allocate a large enough buffer
|
|
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|
|
to silence false positive gcc8 warning.
|
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|
|
2018-02-23 03:28:51 +08:00
|
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|
|
2018-02-22 Shea Levy <shea@shealevy.com>
|
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|
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|
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|
|
* disassemble.c (ARCH_riscv): Define if ARCH_all.
|
|
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|
|
2018-02-22 22:18:27 +08:00
|
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|
|
2018-02-22 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl: Add {rex},
|
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|
|
|
* i386-tbl.h: Regenerated.
|
|
|
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|
|
2018-02-21 04:51:36 +08:00
|
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|
|
2018-02-20 Maciej W. Rozycki <macro@mips.com>
|
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|
|
* mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
|
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|
|
(mips16_opcodes): Replace `M' with `m' for "restore".
|
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|
|
2018-02-19 20:05:18 +08:00
|
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|
|
2018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
|
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|
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|
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|
|
* arm-dis.c (thumb_opcodes): Fix BXNS mask.
|
|
|
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|
|
2018-02-13 20:56:29 +08:00
|
|
|
|
2018-02-13 Maciej W. Rozycki <macro@mips.com>
|
|
|
|
|
|
|
|
|
|
|
|
* wasm32-dis.c (print_insn_wasm32): Rename `index' local
|
|
|
|
|
|
variable to `function_index'.
|
|
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|
|
2018-02-13 21:14:47 +08:00
|
|
|
|
2018-02-13 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR 22823
|
|
|
|
|
|
* metag-dis.c (print_fmmov): Double buffer size to avoid warning
|
|
|
|
|
|
about truncation of printing.
|
|
|
|
|
|
|
MIPS: Fix encoding for MIPSr6 sigrie instruction.
The instruction encoding for the MIPS r6 sigrie instruction seems to be
incorrect. It's currently 0x4170xxxx (which overlaps with ei, di, evp,
and dvp), but should be 0x0417xxxx. See ISA reference[1][2].
References:
[1] "MIPS Architecture for Programmers Volume II-A: The MIPS32
Instruction Set Manual", Imagination Technologies, Inc., Document
Number: MD00086, Revision 6.06, December 15, 2016, Table A.4 "MIPS32
REGIMM Encoding of rt Field", p. 452
[2] "MIPS Architecture For Programmers Volume II-A: The MIPS64
Instruction Set Reference Manual", Imagination Technologies, Inc.,
Document Number: MD00087, Revision 6.06, December 15, 2016, Table
A.4 "MIPS64 REGIMM Encoding of rt Field", p. 581
opcodes/
* mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
gas/
* testsuite/gas/mips/r6.d: Update for "sigrie" encoding fix.
* testsuite/gas/mips/r6-n32.d: Likewise.
* testsuite/gas/mips/r6-n64.d: Likewise.
2018-02-12 22:50:42 +08:00
|
|
|
|
2018-02-12 Henry Wong <henry@stuffedcow.net>
|
|
|
|
|
|
|
|
|
|
|
|
* mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
|
|
|
|
|
|
|
2018-02-05 21:09:15 +08:00
|
|
|
|
2018-02-05 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* po/pt_BR.po: Updated Brazilian Portuguese translation.
|
|
|
|
|
|
|
2018-01-24 00:56:30 +08:00
|
|
|
|
2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (enum): Add pconfig.
|
|
|
|
|
|
* i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
|
|
|
|
|
|
(cpu_flags): Add CpuPCONFIG.
|
|
|
|
|
|
* i386-opc.h (enum): Add CpuPCONFIG.
|
|
|
|
|
|
(i386_cpu_flags): Add cpupconfig.
|
|
|
|
|
|
* i386-opc.tbl: Add PCONFIG instruction.
|
|
|
|
|
|
* i386-init.h: Regenerate.
|
|
|
|
|
|
* i386-tbl.h: Likewise.
|
|
|
|
|
|
|
2018-01-24 00:39:05 +08:00
|
|
|
|
2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (enum): Add PREFIX_0F09.
|
|
|
|
|
|
* i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
|
|
|
|
|
|
(cpu_flags): Add CpuWBNOINVD.
|
|
|
|
|
|
* i386-opc.h (enum): Add CpuWBNOINVD.
|
|
|
|
|
|
(i386_cpu_flags): Add cpuwbnoinvd.
|
|
|
|
|
|
* i386-opc.tbl: Add WBNOINVD instruction.
|
|
|
|
|
|
* i386-init.h: Regenerate.
|
|
|
|
|
|
* i386-tbl.h: Likewise.
|
|
|
|
|
|
|
2018-01-18 06:04:16 +08:00
|
|
|
|
2018-01-17 Jim Wilson <jimw@sifive.com>
|
|
|
|
|
|
|
|
|
|
|
|
* riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
|
|
|
|
|
|
|
Replace CET bit with IBT and SHSTK bits.
The latest specification for Intel CET technology defined two
new bits instead of previously used CET bit. These are IBT and
SHSTK bits. The patch replaces CET bit with IBT and SHSTK bits.
gas/
* config/tc-i386.c (cpu_arch): Delete .cet. Add .ibt, .shstk.
(cpu_noarch): Add noibt, noshstk.
(parse_insn): Change cpucet to cpuibt.
* doc/c-i386.texi: Delete .cet. Add .ibt, .shstk.
* testsuite/gas/i386/cet-ibt-inval.l: New test.
* testsuite/gas/i386/cet-ibt-inval.s: Likewise.
* testsuite/gas/i386/cet-shstk-inval.l: Likewise.
* testsuite/gas/i386/cet-shstk-inval.s: Likewise.
* testsuite/gas/i386/x86-64-cet-ibt-inval.l: Likewise.
* testsuite/gas/i386/x86-64-cet-ibt-inval.s: Likewise.
* testsuite/gas/i386/x86-64-cet-shstk-inval.l: Likewise.
* testsuite/gas/i386/x86-64-cet-shstk-inval.s: Likewise.
opcodes/
* i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS,
CpuCET. Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
(cpu_flags): Add CpuIBT, CpuSHSTK.
* i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
(i386_cpu_flags): Add cpuibt, cpushstk.
* i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
* i386-init.h: Regenerate.
* i386-tbl.h: Likewise.
2018-01-18 00:45:52 +08:00
|
|
|
|
2018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
|
|
|
|
|
|
Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
|
|
|
|
|
|
CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
|
|
|
|
|
|
(cpu_flags): Add CpuIBT, CpuSHSTK.
|
|
|
|
|
|
* i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
|
|
|
|
|
|
(i386_cpu_flags): Add cpuibt, cpushstk.
|
|
|
|
|
|
* i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
|
|
|
|
|
|
* i386-init.h: Regenerate.
|
|
|
|
|
|
* i386-tbl.h: Likewise.
|
|
|
|
|
|
|
2018-01-16 20:45:44 +08:00
|
|
|
|
2018-01-16 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* po/pt_BR.po: Updated Brazilian Portugese translation.
|
|
|
|
|
|
* po/de.po: Updated German translation.
|
|
|
|
|
|
|
2018-01-16 06:53:44 +08:00
|
|
|
|
2018-01-15 Jim Wilson <jimw@sifive.com>
|
|
|
|
|
|
|
|
|
|
|
|
* riscv-opc.c (match_c_nop): New.
|
|
|
|
|
|
(riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
|
|
|
|
|
|
|
2018-01-15 20:09:11 +08:00
|
|
|
|
2018-01-15 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* po/uk.po: Updated Ukranian translation.
|
|
|
|
|
|
|
2018-01-13 21:56:48 +08:00
|
|
|
|
2018-01-13 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* po/opcodes.pot: Regenerated.
|
|
|
|
|
|
|
2018-01-13 21:31:12 +08:00
|
|
|
|
2018-01-13 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* configure: Regenerate.
|
|
|
|
|
|
|
2018-01-13 21:26:38 +08:00
|
|
|
|
2018-01-13 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
2.30 branch created.
|
|
|
|
|
|
|
2018-01-11 07:56:45 +08:00
|
|
|
|
2018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
|
|
|
|
|
|
* i386-tbl.h: Regenerate.
|
|
|
|
|
|
|
2018-01-10 21:53:43 +08:00
|
|
|
|
2018-01-10 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2018-01-10 21:53:05 +08:00
|
|
|
|
2018-01-10 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
|
|
|
|
|
|
vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
|
|
|
|
|
|
vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
|
|
|
|
|
|
vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
|
|
|
|
|
|
vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
|
|
|
|
|
|
Disp8MemShift of AVX512VL forms.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2018-01-10 08:40:06 +08:00
|
|
|
|
2018-01-09 Jim Wilson <jimw@sifive.com>
|
|
|
|
|
|
|
|
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* riscv-dis.c (maybe_print_address): If base_reg is zero,
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then the hi_addr value is zero.
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2018-01-09 22:15:00 +08:00
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2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
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* arm-dis.c (arm_opcodes): Add csdb.
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(thumb32_opcodes): Add csdb.
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2018-01-09 19:28:04 +08:00
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2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
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* aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
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* aarch64-asm-2.c: Regenerate.
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* aarch64-dis-2.c: Regenerate.
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* aarch64-opc-2.c: Regenerate.
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2018-01-08 20:36:59 +08:00
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2018-01-08 H.J. Lu <hongjiu.lu@intel.com>
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PR gas/22681
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* i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
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Remove AVX512 vmovd with 64-bit operands.
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* i386-tbl.h: Regenerated.
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2018-01-06 09:51:23 +08:00
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2018-01-05 Jim Wilson <jimw@sifive.com>
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* riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
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jalr.
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2018-01-03 13:17:27 +08:00
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2018-01-03 Alan Modra <amodra@gmail.com>
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Update year range in copyright notice of all files.
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2018-01-02 18:44:04 +08:00
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2018-01-02 Jan Beulich <jbeulich@suse.com>
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* i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
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and OPERAND_TYPE_REGZMM entries.
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2018-01-03 13:15:17 +08:00
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For older changes see ChangeLog-2017
|
2016-01-01 18:44:31 +08:00
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2018-01-03 13:15:17 +08:00
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Copyright (C) 2018 Free Software Foundation, Inc.
|
2016-01-01 18:44:31 +08:00
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Copying and distribution of this file, with or without modification,
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are permitted in any medium without royalty provided the copyright
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notice and this notice are preserved.
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Local Variables:
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mode: change-log
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left-margin: 8
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fill-column: 74
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version-control: never
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End:
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