binutils-gdb/sim/common/sim-bits.h

608 lines
19 KiB
C
Raw Permalink Normal View History

/* The common simulator framework for GDB, the GNU Debugger.
Copyright 2002-2024 Free Software Foundation, Inc.
Contributed by Andrew Cagney and Red Hat.
This file is part of GDB.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
#ifndef SIM_BITS_H
#define SIM_BITS_H
/* Bit manipulation routines:
Bit numbering: The bits are numbered according to the target ISA's
convention. That being controlled by WITH_TARGET_WORD_MSB. For
the PowerPC (WITH_TARGET_WORD_MSB == 0) the numbering is 0..31
while for the MIPS (WITH_TARGET_WORD_MSB == 31) it is 31..0.
Size convention: Each macro is in three forms - <MACRO>32 which
operates in 32bit quantity (bits are numbered 0..31); <MACRO>64
which operates using 64bit quantites (and bits are numbered 0..63);
and <MACRO> which operates using the bit size of the target
architecture (bits are still numbered 0..63), with 32bit
architectures ignoring the first 32bits leaving bit 32 as the most
significant.
NB: Use EXTRACTED, MSEXTRACTED and LSEXTRACTED as a guideline for
naming. LSMASK and LSMASKED are wrong.
BIT*(POS): `*' bit constant with just 1 bit set.
LSBIT*(OFFSET): `*' bit constant with just 1 bit set - LS bit is
zero.
MSBIT*(OFFSET): `*' bit constant with just 1 bit set - MS bit is
zero.
MASK*(FIRST, LAST): `*' bit constant with bits [FIRST .. LAST]
set. The <MACRO> (no size) version permits FIRST >= LAST and
generates a wrapped bit mask vis ([0..LAST] | [FIRST..LSB]).
LSMASK*(FIRST, LAST): Like MASK - LS bit is zero.
MSMASK*(FIRST, LAST): Like MASK - LS bit is zero.
MASKED*(VALUE, FIRST, LAST): Masks out all but bits [FIRST
.. LAST].
LSMASKED*(VALUE, FIRST, LAST): Like MASKED - LS bit is zero.
MSMASKED*(VALUE, FIRST, LAST): Like MASKED - MS bit is zero.
EXTRACTED*(VALUE, FIRST, LAST): Masks out bits [FIRST .. LAST] but
also right shifts the masked value so that bit LAST becomes the
least significant (right most).
LSEXTRACTED*(VALUE, FIRST, LAST): Same as extracted - LS bit is
zero.
MSEXTRACTED*(VALUE, FIRST, LAST): Same as extracted - MS bit is
zero.
SHUFFLED**(VALUE, OLD, NEW): Mask then move a single bit from OLD
new NEW.
MOVED**(VALUE, OLD_FIRST, OLD_LAST, NEW_FIRST, NEW_LAST): Moves
things around so that bits OLD_FIRST..OLD_LAST are masked then
moved to NEW_FIRST..NEW_LAST.
INSERTED*(VALUE, FIRST, LAST): Takes VALUE and `inserts' the (LAST
- FIRST + 1) least significant bits into bit positions [ FIRST
.. LAST ]. This is almost the complement to EXTRACTED.
IEA_MASKED(SHOULD_MASK, ADDR): Convert the address to the targets
natural size. If in 32bit mode, discard the high 32bits.
EXTEND*(VALUE): Convert the `*' bit value to the targets natural
word size. Sign extend the value if needed.
align_*(VALUE, BYTES): Round the value so that it is aligned to a
BYTES boundary.
ROT*(VALUE, NR_BITS): Return the `*' bit VALUE rotated by NR_BITS
right (positive) or left (negative).
ROTL*(VALUE, NR_BITS): Return the `*' bit value rotated by NR_BITS
left. 0 <= NR_BITS <= `*'.
ROTR*(VALUE, NR_BITS): Return the `*' bit value rotated by NR_BITS
right. 0 <= NR_BITS <= N.
SEXT*(VALUE, SIGN_BIT): Treat SIGN_BIT as VALUEs sign, extend it ti
`*' bits.
Note: Only the BIT* and MASK* macros return a constant that can be
used in variable declarations.
*/
/* compute the number of bits between START and STOP */
#if (WITH_TARGET_WORD_MSB == 0)
#define _MAKE_WIDTH(START, STOP) (STOP - START + 1)
#else
#define _MAKE_WIDTH(START, STOP) (START - STOP + 1)
#endif
/* compute the number shifts required to move a bit between LSB (MSB)
and POS */
#if (WITH_TARGET_WORD_MSB == 0)
#define _LSB_SHIFT(WIDTH, POS) (WIDTH - 1 - POS)
#else
#define _LSB_SHIFT(WIDTH, POS) (POS)
#endif
#if (WITH_TARGET_WORD_MSB == 0)
#define _MSB_SHIFT(WIDTH, POS) (POS)
#else
#define _MSB_SHIFT(WIDTH, POS) (WIDTH - 1 - POS)
#endif
/* compute the absolute bit position given the OFFSET from the MSB(LSB)
NB: _MAKE_xxx_POS (WIDTH, _MAKE_xxx_SHIFT (WIDTH, POS)) == POS */
#if (WITH_TARGET_WORD_MSB == 0)
#define _MSB_POS(WIDTH, SHIFT) (SHIFT)
#else
#define _MSB_POS(WIDTH, SHIFT) (WIDTH - 1 - SHIFT)
#endif
#if (WITH_TARGET_WORD_MSB == 0)
#define _LSB_POS(WIDTH, SHIFT) (WIDTH - 1 - SHIFT)
#else
#define _LSB_POS(WIDTH, SHIFT) (SHIFT)
#endif
/* convert a 64 bit position into a corresponding 32bit position. MSB
pos handles the posibility that the bit lies beyond the 32bit
boundary */
#if (WITH_TARGET_WORD_MSB == 0)
#define _MSB_32(START, STOP) (START <= STOP \
? (START < 32 ? 0 : START - 32) \
: (STOP < 32 ? 0 : STOP - 32))
#define _MSB_16(START, STOP) (START <= STOP \
? (START < 48 ? 0 : START - 48) \
: (STOP < 48 ? 0 : STOP - 48))
#else
#define _MSB_32(START, STOP) (START >= STOP \
? (START >= 32 ? 31 : START) \
: (STOP >= 32 ? 31 : STOP))
#define _MSB_16(START, STOP) (START >= STOP \
? (START >= 16 ? 15 : START) \
: (STOP >= 16 ? 15 : STOP))
#endif
#if (WITH_TARGET_WORD_MSB == 0)
#define _LSB_32(START, STOP) (START <= STOP \
? (STOP < 32 ? 0 : STOP - 32) \
: (START < 32 ? 0 : START - 32))
#define _LSB_16(START, STOP) (START <= STOP \
? (STOP < 48 ? 0 : STOP - 48) \
: (START < 48 ? 0 : START - 48))
#else
#define _LSB_32(START, STOP) (START >= STOP \
? (STOP >= 32 ? 31 : STOP) \
: (START >= 32 ? 31 : START))
#define _LSB_16(START, STOP) (START >= STOP \
? (STOP >= 16 ? 15 : STOP) \
: (START >= 16 ? 15 : START))
#endif
#if (WITH_TARGET_WORD_MSB == 0)
#define _MSB(START, STOP) (START <= STOP ? START : STOP)
#else
#define _MSB(START, STOP) (START >= STOP ? START : STOP)
#endif
#if (WITH_TARGET_WORD_MSB == 0)
#define _LSB(START, STOP) (START <= STOP ? STOP : START)
#else
#define _LSB(START, STOP) (START >= STOP ? STOP : START)
#endif
/* LS/MS Bit operations */
#define LSBIT8(POS) ((uint8_t) 1 << (POS))
#define LSBIT16(POS) ((uint16_t)1 << (POS))
#define LSBIT32(POS) ((uint32_t)1 << (POS))
#define LSBIT64(POS) ((uint64_t)1 << (POS))
#if (WITH_TARGET_WORD_BITSIZE == 64)
#define LSBIT(POS) LSBIT64 (POS)
#endif
#if (WITH_TARGET_WORD_BITSIZE == 32)
#define LSBIT(POS) ((uint32_t)((POS) >= 32 \
? 0 \
: (1 << ((POS) >= 32 ? 0 : (POS)))))
#endif
#if (WITH_TARGET_WORD_BITSIZE == 16)
#define LSBIT(POS) ((uint16_t)((POS) >= 16 \
? 0 \
: (1 << ((POS) >= 16 ? 0 : (POS)))))
#endif
#define MSBIT8(POS) ((uint8_t) 1 << ( 8 - 1 - (POS)))
#define MSBIT16(POS) ((uint16_t)1 << (16 - 1 - (POS)))
#define MSBIT32(POS) ((uint32_t)1 << (32 - 1 - (POS)))
#define MSBIT64(POS) ((uint64_t)1 << (64 - 1 - (POS)))
#if (WITH_TARGET_WORD_BITSIZE == 64)
#define MSBIT(POS) MSBIT64 (POS)
#endif
#if (WITH_TARGET_WORD_BITSIZE == 32)
#define MSBIT(POS) ((uint32_t)((POS) < 32 \
? 0 \
: (1 << ((POS) < 32 ? 0 : (64 - 1) - (POS)))))
#endif
#if (WITH_TARGET_WORD_BITSIZE == 16)
#define MSBIT(POS) ((uint16_t)((POS) < 48 \
? 0 \
: (1 << ((POS) < 48 ? 0 : (64 - 1) - (POS)))))
#endif
/* Bit operations */
#define BIT4(POS) (1 << _LSB_SHIFT (4, (POS)))
#define BIT5(POS) (1 << _LSB_SHIFT (5, (POS)))
#define BIT10(POS) (1 << _LSB_SHIFT (10, (POS)))
#if (WITH_TARGET_WORD_MSB == 0)
#define BIT8 MSBIT8
#define BIT16 MSBIT16
#define BIT32 MSBIT32
#define BIT64 MSBIT64
#define BIT MSBIT
#else
#define BIT8 LSBIT8
#define BIT16 LSBIT16
#define BIT32 LSBIT32
#define BIT64 LSBIT64
#define BIT LSBIT
#endif
/* multi bit mask */
/* 111111 -> mmll11 -> mm11ll */
#define _MASKn(WIDTH, START, STOP) (((uint##WIDTH##_t)(-1) \
>> (_MSB_SHIFT (WIDTH, START) \
+ _LSB_SHIFT (WIDTH, STOP))) \
<< _LSB_SHIFT (WIDTH, STOP))
#if (WITH_TARGET_WORD_MSB == 0)
#define _POS_LE(START, STOP) (START <= STOP)
#else
#define _POS_LE(START, STOP) (STOP <= START)
#endif
#if (WITH_TARGET_WORD_BITSIZE == 64)
#define MASK(START, STOP) \
(_POS_LE ((START), (STOP)) \
? _MASKn(64, \
_MSB ((START), (STOP)), \
_LSB ((START), (STOP)) ) \
: (_MASKn(64, _MSB_POS (64, 0), (STOP)) \
| _MASKn(64, (START), _LSB_POS (64, 0))))
#endif
#if (WITH_TARGET_WORD_BITSIZE == 32)
#define MASK(START, STOP) \
(_POS_LE ((START), (STOP)) \
? (_POS_LE ((STOP), _MSB_POS (64, 31)) \
? 0 \
: _MASKn (32, \
_MSB_32 ((START), (STOP)), \
_LSB_32 ((START), (STOP)))) \
: (_MASKn (32, \
_LSB_32 ((START), (STOP)), \
_LSB_POS (32, 0)) \
| (_POS_LE ((STOP), _MSB_POS (64, 31)) \
? 0 \
: _MASKn (32, \
_MSB_POS (32, 0), \
_MSB_32 ((START), (STOP))))))
#endif
#if (WITH_TARGET_WORD_BITSIZE == 16)
#define MASK(START, STOP) \
(_POS_LE ((START), (STOP)) \
? (_POS_LE ((STOP), _MSB_POS (64, 15)) \
? 0 \
: _MASKn (16, \
_MSB_16 ((START), (STOP)), \
_LSB_16 ((START), (STOP)))) \
: (_MASKn (16, \
_LSB_16 ((START), (STOP)), \
_LSB_POS (16, 0)) \
| (_POS_LE ((STOP), _MSB_POS (64, 15)) \
? 0 \
: _MASKn (16, \
_MSB_POS (16, 0), \
_MSB_16 ((START), (STOP))))))
#endif
#if !defined (MASK)
#error "MASK never undefined"
#endif
/* Multi-bit mask on least significant bits */
#define _LSMASKn(WIDTH, FIRST, LAST) _MASKn (WIDTH, \
_LSB_POS (WIDTH, FIRST), \
_LSB_POS (WIDTH, LAST))
#define LSMASK8(FIRST, LAST) _LSMASKn ( 8, (FIRST), (LAST))
#define LSMASK16(FIRST, LAST) _LSMASKn (16, (FIRST), (LAST))
#define LSMASK32(FIRST, LAST) _LSMASKn (32, (FIRST), (LAST))
#define LSMASK64(FIRST, LAST) _LSMASKn (64, (FIRST), (LAST))
#define LSMASK(FIRST, LAST) (MASK (_LSB_POS (64, FIRST), _LSB_POS (64, LAST)))
/* Multi-bit mask on most significant bits */
#define _MSMASKn(WIDTH, FIRST, LAST) _MASKn (WIDTH, \
_MSB_POS (WIDTH, FIRST), \
_MSB_POS (WIDTH, LAST))
#define MSMASK8(FIRST, LAST) _MSMASKn ( 8, (FIRST), (LAST))
#define MSMASK16(FIRST, LAST) _MSMASKn (16, (FIRST), (LAST))
#define MSMASK32(FIRST, LAST) _MSMASKn (32, (FIRST), (LAST))
#define MSMASK64(FIRST, LAST) _MSMASKn (64, (FIRST), (LAST))
#define MSMASK(FIRST, LAST) (MASK (_MSB_POS (64, FIRST), _MSB_POS (64, LAST)))
#if (WITH_TARGET_WORD_MSB == 0)
#define MASK8 MSMASK8
#define MASK16 MSMASK16
#define MASK32 MSMASK32
#define MASK64 MSMASK64
#else
#define MASK8 LSMASK8
#define MASK16 LSMASK16
#define MASK32 LSMASK32
#define MASK64 LSMASK64
#endif
/* mask the required bits, leaving them in place */
INLINE_SIM_BITS(uint8_t) LSMASKED8 (uint8_t word, int first, int last);
INLINE_SIM_BITS(uint16_t) LSMASKED16 (uint16_t word, int first, int last);
INLINE_SIM_BITS(uint32_t) LSMASKED32 (uint32_t word, int first, int last);
INLINE_SIM_BITS(uint64_t) LSMASKED64 (uint64_t word, int first, int last);
INLINE_SIM_BITS(unsigned_word) LSMASKED (unsigned_word word, int first, int last);
INLINE_SIM_BITS(uint8_t) MSMASKED8 (uint8_t word, int first, int last);
INLINE_SIM_BITS(uint16_t) MSMASKED16 (uint16_t word, int first, int last);
INLINE_SIM_BITS(uint32_t) MSMASKED32 (uint32_t word, int first, int last);
INLINE_SIM_BITS(uint64_t) MSMASKED64 (uint64_t word, int first, int last);
INLINE_SIM_BITS(unsigned_word) MSMASKED (unsigned_word word, int first, int last);
#if (WITH_TARGET_WORD_MSB == 0)
#define MASKED8 MSMASKED8
#define MASKED16 MSMASKED16
#define MASKED32 MSMASKED32
#define MASKED64 MSMASKED64
#define MASKED MSMASKED
#else
#define MASKED8 LSMASKED8
#define MASKED16 LSMASKED16
#define MASKED32 LSMASKED32
#define MASKED64 LSMASKED64
#define MASKED LSMASKED
#endif
/* extract the required bits aligning them with the lsb */
INLINE_SIM_BITS(uint8_t) LSEXTRACTED8 (uint8_t val, int start, int stop);
INLINE_SIM_BITS(uint16_t) LSEXTRACTED16 (uint16_t val, int start, int stop);
INLINE_SIM_BITS(uint32_t) LSEXTRACTED32 (uint32_t val, int start, int stop);
INLINE_SIM_BITS(uint64_t) LSEXTRACTED64 (uint64_t val, int start, int stop);
INLINE_SIM_BITS(unsigned_word) LSEXTRACTED (unsigned_word val, int start, int stop);
INLINE_SIM_BITS(uint8_t) MSEXTRACTED8 (uint8_t val, int start, int stop);
INLINE_SIM_BITS(uint16_t) MSEXTRACTED16 (uint16_t val, int start, int stop);
INLINE_SIM_BITS(uint32_t) MSEXTRACTED32 (uint32_t val, int start, int stop);
INLINE_SIM_BITS(uint64_t) MSEXTRACTED64 (uint64_t val, int start, int stop);
INLINE_SIM_BITS(unsigned_word) MSEXTRACTED (unsigned_word val, int start, int stop);
#if (WITH_TARGET_WORD_MSB == 0)
#define EXTRACTED8 MSEXTRACTED8
#define EXTRACTED16 MSEXTRACTED16
#define EXTRACTED32 MSEXTRACTED32
#define EXTRACTED64 MSEXTRACTED64
#define EXTRACTED MSEXTRACTED
#else
#define EXTRACTED8 LSEXTRACTED8
#define EXTRACTED16 LSEXTRACTED16
#define EXTRACTED32 LSEXTRACTED32
#define EXTRACTED64 LSEXTRACTED64
#define EXTRACTED LSEXTRACTED
#endif
/* move a single bit around */
/* NB: the wierdness (N>O?N-O:0) is to stop a warning from GCC */
#define _SHUFFLEDn(N, WORD, OLD, NEW) \
((OLD) < (NEW) \
? (((uint##N##_t)(WORD) \
>> (((NEW) > (OLD)) ? ((NEW) - (OLD)) : 0)) \
& MASK32((NEW), (NEW))) \
: (((uint##N##_t)(WORD) \
<< (((OLD) > (NEW)) ? ((OLD) - (NEW)) : 0)) \
& MASK32((NEW), (NEW))))
#define SHUFFLED32(WORD, OLD, NEW) _SHUFFLEDn (32, WORD, OLD, NEW)
#define SHUFFLED64(WORD, OLD, NEW) _SHUFFLEDn (64, WORD, OLD, NEW)
#define SHUFFLED(WORD, OLD, NEW) _SHUFFLEDn (_word, WORD, OLD, NEW)
/* Insert a group of bits into a bit position */
INLINE_SIM_BITS(uint8_t) LSINSERTED8 (uint8_t val, int start, int stop);
INLINE_SIM_BITS(uint16_t) LSINSERTED16 (uint16_t val, int start, int stop);
INLINE_SIM_BITS(uint32_t) LSINSERTED32 (uint32_t val, int start, int stop);
INLINE_SIM_BITS(uint64_t) LSINSERTED64 (uint64_t val, int start, int stop);
INLINE_SIM_BITS(unsigned_word) LSINSERTED (unsigned_word val, int start, int stop);
INLINE_SIM_BITS(uint8_t) MSINSERTED8 (uint8_t val, int start, int stop);
INLINE_SIM_BITS(uint16_t) MSINSERTED16 (uint16_t val, int start, int stop);
INLINE_SIM_BITS(uint32_t) MSINSERTED32 (uint32_t val, int start, int stop);
INLINE_SIM_BITS(uint64_t) MSINSERTED64 (uint64_t val, int start, int stop);
INLINE_SIM_BITS(unsigned_word) MSINSERTED (unsigned_word val, int start, int stop);
#if (WITH_TARGET_WORD_MSB == 0)
#define INSERTED8 MSINSERTED8
#define INSERTED16 MSINSERTED16
#define INSERTED32 MSINSERTED32
#define INSERTED64 MSINSERTED64
#define INSERTED MSINSERTED
#else
#define INSERTED8 LSINSERTED8
#define INSERTED16 LSINSERTED16
#define INSERTED32 LSINSERTED32
#define INSERTED64 LSINSERTED64
#define INSERTED LSINSERTED
#endif
/* MOVE bits from one loc to another (combination of extract/insert) */
#define MOVED8(VAL,OH,OL,NH,NL) INSERTED8 (EXTRACTED8 ((VAL), OH, OL), NH, NL)
#define MOVED16(VAL,OH,OL,NH,NL) INSERTED16(EXTRACTED16((VAL), OH, OL), NH, NL)
#define MOVED32(VAL,OH,OL,NH,NL) INSERTED32(EXTRACTED32((VAL), OH, OL), NH, NL)
#define MOVED64(VAL,OH,OL,NH,NL) INSERTED64(EXTRACTED64((VAL), OH, OL), NH, NL)
#define MOVED(VAL,OH,OL,NH,NL) INSERTED (EXTRACTED ((VAL), OH, OL), NH, NL)
/* Sign extend the quantity to the targets natural word size */
#define EXTEND4(X) (LSSEXT ((X), 3))
#define EXTEND5(X) (LSSEXT ((X), 4))
[PATCH] Add micromips support to the MIPS simulator 2015-09-25 Andrew Bennett <andrew.bennett@imgtec.com> Ali Lown <ali.lown@imgtec.com> sim/common/ * sim-bits.h (EXTEND6): New macro. (EXTEND12): New macro. (EXTEND25): New macro. sim/mips/ * Makefile.in (tmp-micromips): New rule. (tmp-mach-multi): Add support for micromips. * configure.ac (mips*-sde-elf* | mips*-mti-elf*): Made a multi sim that works for both mips64 and micromips64. (mipsisa32r2*-*-*): Made a multi sim that works for mips32 and micromips32. Add build support for micromips. * dsp.igen (do_ph_s_absq, do_w_s_absq, do_qb_s_absq, do_addsc, do_addwc, do_bitrev, do_extpv, do_extrv, do_extrv_s_h, do_insv, do_lxx do_modsub, do_mthlip, do_mulsaq_s_w_ph, do_ph_packrl, do_qb_pick do_ph_pick, do_qb_ph_precequ, do_qb_ph_preceu, do_w_preceq do_w_ph_precrq, do_ph_qb_precrq, do_w_ph_rs_precrq do_qb_w_raddu, do_rddsp, do_repl, do_shilov, do_ph_shl, do_qb_shl do_w_s_shllv, do_ph_shrlv, do_w_r_shrav, do_wrdsp, do_qb_shrav, do_append, do_balign, do_ph_w_mulsa, do_ph_qb_precr, do_prepend): New functions. Refactored instruction code to use these functions. * dsp2.igen: Refactored instruction code to use the new functions. * interp.c (decode_coproc): Refactored to work with any instruction encoding. (isa_mode): New variable (RSVD_INSTRUCTION): Changed to 0x00000039. * m16.igen (BREAK16): Refactored instruction to use do_break16. (JALX32): Add mips32, mips64, mips32r2 and mips64r2 models. * micromips.dc: New file. * micromips.igen: New file. * micromips16.dc: New file. * micromipsdsp.igen: New file. * micromipsrun.c: New file. * mips.igen (do_swc1): Changed to work with any instruction encoding. (do_add do_addi do_andi do_dadd do_daddi do_dsll32 do_dsra32 do_dsrl32, do_dsub, do_break, do_break16, do_clo, do_clz, do_dclo do_dclz, do_lb, do_lh, do_lwr, do_lwl, do_lwc, do_lw, do_lwu, do_lhu do_ldc, do_lbu, do_ll, do_lld, do_lui, do_madd, do_dsp_madd, do_maddu do_dsp_maddu, do_dsp_mfhi, do_dsp_mflo, do_movn, do_movz, do_msub do_dsp_msub, do_msubu, do_dsp_msubu, do_mthi, do_dsp_mthi, do_mtlo do_dsp_mtlo, do_mul, do_dsp_mult, do_dsp_multu, do_pref, do_sc, do_scd do_sub, do_sw, do_teq, do_teqi, do_tge, do_tgei, do_tgeiu, do_tgeu, do_tlt do_tlti, do_tltiu, do_tltu, do_tne, do_tnei, do_abs_fmt, do_add_fmt do_alnv_ps, do_c_cond_fmt, do_ceil_fmt, do_cfc1, do_ctc1, do_cvt_d_fmt do_cvt_l_fmt, do_cvt_ps_s, do_cvt_s_fmt, do_cvt_s_pl, do_cvt_s_pu do_cvt_w_fmt, do_div_fmt, do_dmfc1b, do_dmtc1b, do_floor_fmt, do_luxc1_32 do_luxc1_64, do_lwc1, do_lwxc1, do_madd_fmt, do_mfc1b, do_mov_fmt, do_movtf do_movtf_fmt, do_movn_fmt, do_movz_fmt, do_msub_fmt, do_mtc1b, do_mul_fmt do_neg_fmt, do_nmadd_fmt, do_nmsub_fmt, do_pll_ps, do_plu_ps, do_pul_ps do_puu_ps, do_recip_fmt, do_round_fmt, do_rsqrt_fmt, do_prefx, do_sdc1 do_suxc1_32, do_suxc1_64, do_sqrt_fmt, do_sub_fmt, do_swc1, do_swxc1 do_trunc_fmt): New functions, refactored from existing instructions. Refactored instruction code to use these functions. (RSVD): Changed to use new reserved instruction. (loadstore_ea, not_word_value, unpredictable, check_mt_hilo, check_mf_hilo, check_mult_hilo, check_div_hilo, check_u64, do_luxc1_32, do_sdc1, do_suxc1_32, check_fmt_p, check_fpu, do_load_double, do_store_double): Added micromips32 and micromips64 models. Added include for micromips.igen and micromipsdsp.igen Add micromips32 and micromips64 models. (DecodeCoproc): Updated to use new macro definition. * mips3264r2.igen (do_dsbh, do_dshd, do_dext, do_dextm, do_dextu, do_di, do_dins, do_dinsm, do_ei, do_ext, do_mfhc1, do_mthc1, do_ins, do_dinsu, do_seb, do_seh do_rdhwr, do_wsbh): New functions. Refactored instruction code to use these functions. * sim-main.h (CP0_operation): New enum. (DecodeCoproc): Updated macro. (IMEM32_MICROMIPS, IMEM16_MICROMIPS, MICROMIPS_MINOR_OPCODE, MICROMIPS_DELAYSLOT_SIZE_ANY, MICROMIPS_DELAYSLOT_SIZE_16, MICROMIPS_DELAYSLOT_SIZE_32, ISA_MODE_MIPS32 and ISA_MODE_MICROMIPS): New defines. (sim_state): Add isa_mode field. sim/testsuite/sim/mips/ * basic.exp (run_micromips_test, run_sim_tests): New functions Add support for micromips tests. * hilo-hazard-4.s: New file. * testutils.inc (_dowrite): Changed reserved instruction encoding. (writemsg): Moved the la and li instructions before the data they are assigned to, which prevents a bug where MIPS32 relocations are used instead of micromips relocations when building for micromips.
2015-09-25 22:52:18 +08:00
#define EXTEND6(X) (LSSEXT ((X), 5))
#define EXTEND8(X) ((signed_word)(int8_t)(X))
sim: mips: Add simulator support for mips32r6/mips64r6 2022-02-01 Ali Lown <ali.lown@imgtec.com> Andrew Bennett <andrew.bennett@imgtec.com> Dragan Mladjenovic <dragan.mladjenovic@rt-rk.com> Faraz Shahbazker <fshahbazker@wavecomp.com> sim/common/ChangeLog: * sim-bits.h (EXTEND9, EXTEND18 ,EXTEND19, EXTEND21, EXTEND26): New macros. sim/mips/ChangeLog: * Makefile.in (IGEN_INCLUDE): Add mips3264r6.igen. * configure: Regenerate. * configure.ac: Support mipsisa32r6 and mipsisa64r6. (sim_engine_run): Pick simulator model from processor specified in e_flags. * cp1.c (value_fpr): Handle fmt_dc32. (fp_unary, fp_binary): Zero initialize locals. (update_fcsr, fp_classify, fp_rint, fp_r6_cmp, inner_fmac, fp_fmac, fp_min, fp_max, fp_mina, fp_maxa, fp_fmadd, fp_fmsub): New functions. (sim_fpu_class_mips_mapping): New. * cp1.h (fcsr_ABS2008_mask, fcsr_ABS2008_shift): New define. * interp.c (MIPSR6_P): New. (load_word): Allow unaligned memory access for MIPSR6. * micromips.igen (sc, scd): Adapt to new do_sc* helper signature. * mips.igen: Add *r6 models. (signal_if_cti, forbiddenslot32): New helpers. (delayslot32): Use signal_if_cti. (do_sc, do_scd); Add store_ll_bit parameter. (sc, scd): Adapt to previous change. (nal, beq, bal): New definitions for *r6. (sll): Split nop and ssnop cases into ... (nop, ssnop): New definitions. (loadstore_ea): Use the 32-bit compatibility adressing. (cache): Split logic into ... (do_cache): New helper. (check_fpu): Select IEEE 754-2008 mode for R6. (not_word_value, unpredictable, check_mt_hilo, check_mf_hilo, check_multi_hilo, check_div_hilo, check_u64, do_dmfc1b, add, li, addu, and, andi, bgez, bgtz, blez, bltz, bne, break, dadd, daddiu, daddu, dror, dror32, drorv, dsll, dsll32, dsllv, dsra, dsra32, dsrav, dsrl, dsrl32, dsub, dsubu, j, jal, jalr, jalr.hb, lb, lbu, ld, lh, lhu, lui, lw, lwu, nor, or, ori, ror, rorv, sb, sd, sh, sll, sllv, slt, slti, sltiu, sltu, sra, srav, srl, srlv, sub, subu, sw, sync, syscall, teq, tge, tgeu, tlt, tltu, tne, xor, xori, check_fmt_p, do_load_double, do_store_double, abs.FMT, add.FMT, ceil.l.FMT, ceil.w.FMT, cfc1, ctc1, cvt.d.FMT, cvt.l.FMT, cvt.w.FMT, div.FMT, dfmc1, dmtc1, floor.l.FMT, floor.w.FMT, ldc1, lwc1, mfc1, mov.FMT, mtc1, mul.FMT, recip.FMT, round.l.FMT, round.w.FMT, rsqrt.FMT, sdc1, sqrt.FMT, sub.FMT, swc1, trunc.l.FMT, trunc.w.FMT, bc0f, bc0fl, bc0t, bc0tl, dmfc0, dmtc0, eret, mfc0, mtc0, cop, tlbp, tlbr, tlbwi, tlbwr): Enable on *r6 models. * mips3264r2.igen (dext, dextm, dextu, di, dins, dinsm, dinsu, dsbh, dshd, ei, ext, mfhc1, mthc1, ins, seb, seh, synci, rdhwr, wsbh): Likewise. * mips3264r6.igen: New file. * sim-main.h (FP_formats): Add fmt_dc32. (FORBIDDEN_SLOT): New macros. (simFORBIDDENSLOT, FP_R6CMP_*, FP_R6CLASS_*): New defines. (fp_r6_cmp, fp_classify, fp_rint, fp_min, fp_max, fp_mina, fp_maxa, fp_fmadd, fp_fmsub): New declarations. (R6Compare, Classify, RoundToIntegralExact, Min, Max, MinA, MaxA, FusedMultiplyAdd, FusedMultiplySub): New macros. Wrapping previous declarations. sim/testsuite/mips/ChangeLog: * basic.exp: Add r6-*.s tests. (run_r6_removed_test): New function. (run_endian_tests): New function. * hilo-hazard-3.s: Skip for mips*r6. * r2-fpu.s: New test. * r6-64.s: New test. * r6-branch.s: New test. * r6-forbidden.s: New test. * r6-fpu.s: New test. * r6-llsc-dp.s: New test. * r6-llsc-wp.s: New test. * r6-removed.csv: New test. * r6-removed.s: New test. * r6.s: New test. * utils-r6.inc: New inc.
2022-02-02 18:17:25 +08:00
#define EXTEND9(X) (LSSEXT ((X), 8))
#define EXTEND11(X) (LSSEXT ((X), 10))
[PATCH] Add micromips support to the MIPS simulator 2015-09-25 Andrew Bennett <andrew.bennett@imgtec.com> Ali Lown <ali.lown@imgtec.com> sim/common/ * sim-bits.h (EXTEND6): New macro. (EXTEND12): New macro. (EXTEND25): New macro. sim/mips/ * Makefile.in (tmp-micromips): New rule. (tmp-mach-multi): Add support for micromips. * configure.ac (mips*-sde-elf* | mips*-mti-elf*): Made a multi sim that works for both mips64 and micromips64. (mipsisa32r2*-*-*): Made a multi sim that works for mips32 and micromips32. Add build support for micromips. * dsp.igen (do_ph_s_absq, do_w_s_absq, do_qb_s_absq, do_addsc, do_addwc, do_bitrev, do_extpv, do_extrv, do_extrv_s_h, do_insv, do_lxx do_modsub, do_mthlip, do_mulsaq_s_w_ph, do_ph_packrl, do_qb_pick do_ph_pick, do_qb_ph_precequ, do_qb_ph_preceu, do_w_preceq do_w_ph_precrq, do_ph_qb_precrq, do_w_ph_rs_precrq do_qb_w_raddu, do_rddsp, do_repl, do_shilov, do_ph_shl, do_qb_shl do_w_s_shllv, do_ph_shrlv, do_w_r_shrav, do_wrdsp, do_qb_shrav, do_append, do_balign, do_ph_w_mulsa, do_ph_qb_precr, do_prepend): New functions. Refactored instruction code to use these functions. * dsp2.igen: Refactored instruction code to use the new functions. * interp.c (decode_coproc): Refactored to work with any instruction encoding. (isa_mode): New variable (RSVD_INSTRUCTION): Changed to 0x00000039. * m16.igen (BREAK16): Refactored instruction to use do_break16. (JALX32): Add mips32, mips64, mips32r2 and mips64r2 models. * micromips.dc: New file. * micromips.igen: New file. * micromips16.dc: New file. * micromipsdsp.igen: New file. * micromipsrun.c: New file. * mips.igen (do_swc1): Changed to work with any instruction encoding. (do_add do_addi do_andi do_dadd do_daddi do_dsll32 do_dsra32 do_dsrl32, do_dsub, do_break, do_break16, do_clo, do_clz, do_dclo do_dclz, do_lb, do_lh, do_lwr, do_lwl, do_lwc, do_lw, do_lwu, do_lhu do_ldc, do_lbu, do_ll, do_lld, do_lui, do_madd, do_dsp_madd, do_maddu do_dsp_maddu, do_dsp_mfhi, do_dsp_mflo, do_movn, do_movz, do_msub do_dsp_msub, do_msubu, do_dsp_msubu, do_mthi, do_dsp_mthi, do_mtlo do_dsp_mtlo, do_mul, do_dsp_mult, do_dsp_multu, do_pref, do_sc, do_scd do_sub, do_sw, do_teq, do_teqi, do_tge, do_tgei, do_tgeiu, do_tgeu, do_tlt do_tlti, do_tltiu, do_tltu, do_tne, do_tnei, do_abs_fmt, do_add_fmt do_alnv_ps, do_c_cond_fmt, do_ceil_fmt, do_cfc1, do_ctc1, do_cvt_d_fmt do_cvt_l_fmt, do_cvt_ps_s, do_cvt_s_fmt, do_cvt_s_pl, do_cvt_s_pu do_cvt_w_fmt, do_div_fmt, do_dmfc1b, do_dmtc1b, do_floor_fmt, do_luxc1_32 do_luxc1_64, do_lwc1, do_lwxc1, do_madd_fmt, do_mfc1b, do_mov_fmt, do_movtf do_movtf_fmt, do_movn_fmt, do_movz_fmt, do_msub_fmt, do_mtc1b, do_mul_fmt do_neg_fmt, do_nmadd_fmt, do_nmsub_fmt, do_pll_ps, do_plu_ps, do_pul_ps do_puu_ps, do_recip_fmt, do_round_fmt, do_rsqrt_fmt, do_prefx, do_sdc1 do_suxc1_32, do_suxc1_64, do_sqrt_fmt, do_sub_fmt, do_swc1, do_swxc1 do_trunc_fmt): New functions, refactored from existing instructions. Refactored instruction code to use these functions. (RSVD): Changed to use new reserved instruction. (loadstore_ea, not_word_value, unpredictable, check_mt_hilo, check_mf_hilo, check_mult_hilo, check_div_hilo, check_u64, do_luxc1_32, do_sdc1, do_suxc1_32, check_fmt_p, check_fpu, do_load_double, do_store_double): Added micromips32 and micromips64 models. Added include for micromips.igen and micromipsdsp.igen Add micromips32 and micromips64 models. (DecodeCoproc): Updated to use new macro definition. * mips3264r2.igen (do_dsbh, do_dshd, do_dext, do_dextm, do_dextu, do_di, do_dins, do_dinsm, do_ei, do_ext, do_mfhc1, do_mthc1, do_ins, do_dinsu, do_seb, do_seh do_rdhwr, do_wsbh): New functions. Refactored instruction code to use these functions. * sim-main.h (CP0_operation): New enum. (DecodeCoproc): Updated macro. (IMEM32_MICROMIPS, IMEM16_MICROMIPS, MICROMIPS_MINOR_OPCODE, MICROMIPS_DELAYSLOT_SIZE_ANY, MICROMIPS_DELAYSLOT_SIZE_16, MICROMIPS_DELAYSLOT_SIZE_32, ISA_MODE_MIPS32 and ISA_MODE_MICROMIPS): New defines. (sim_state): Add isa_mode field. sim/testsuite/sim/mips/ * basic.exp (run_micromips_test, run_sim_tests): New functions Add support for micromips tests. * hilo-hazard-4.s: New file. * testutils.inc (_dowrite): Changed reserved instruction encoding. (writemsg): Moved the la and li instructions before the data they are assigned to, which prevents a bug where MIPS32 relocations are used instead of micromips relocations when building for micromips.
2015-09-25 22:52:18 +08:00
#define EXTEND12(X) (LSSEXT ((X), 11))
#define EXTEND15(X) (LSSEXT ((X), 14))
#define EXTEND16(X) ((signed_word)(int16_t)(X))
sim: mips: Add simulator support for mips32r6/mips64r6 2022-02-01 Ali Lown <ali.lown@imgtec.com> Andrew Bennett <andrew.bennett@imgtec.com> Dragan Mladjenovic <dragan.mladjenovic@rt-rk.com> Faraz Shahbazker <fshahbazker@wavecomp.com> sim/common/ChangeLog: * sim-bits.h (EXTEND9, EXTEND18 ,EXTEND19, EXTEND21, EXTEND26): New macros. sim/mips/ChangeLog: * Makefile.in (IGEN_INCLUDE): Add mips3264r6.igen. * configure: Regenerate. * configure.ac: Support mipsisa32r6 and mipsisa64r6. (sim_engine_run): Pick simulator model from processor specified in e_flags. * cp1.c (value_fpr): Handle fmt_dc32. (fp_unary, fp_binary): Zero initialize locals. (update_fcsr, fp_classify, fp_rint, fp_r6_cmp, inner_fmac, fp_fmac, fp_min, fp_max, fp_mina, fp_maxa, fp_fmadd, fp_fmsub): New functions. (sim_fpu_class_mips_mapping): New. * cp1.h (fcsr_ABS2008_mask, fcsr_ABS2008_shift): New define. * interp.c (MIPSR6_P): New. (load_word): Allow unaligned memory access for MIPSR6. * micromips.igen (sc, scd): Adapt to new do_sc* helper signature. * mips.igen: Add *r6 models. (signal_if_cti, forbiddenslot32): New helpers. (delayslot32): Use signal_if_cti. (do_sc, do_scd); Add store_ll_bit parameter. (sc, scd): Adapt to previous change. (nal, beq, bal): New definitions for *r6. (sll): Split nop and ssnop cases into ... (nop, ssnop): New definitions. (loadstore_ea): Use the 32-bit compatibility adressing. (cache): Split logic into ... (do_cache): New helper. (check_fpu): Select IEEE 754-2008 mode for R6. (not_word_value, unpredictable, check_mt_hilo, check_mf_hilo, check_multi_hilo, check_div_hilo, check_u64, do_dmfc1b, add, li, addu, and, andi, bgez, bgtz, blez, bltz, bne, break, dadd, daddiu, daddu, dror, dror32, drorv, dsll, dsll32, dsllv, dsra, dsra32, dsrav, dsrl, dsrl32, dsub, dsubu, j, jal, jalr, jalr.hb, lb, lbu, ld, lh, lhu, lui, lw, lwu, nor, or, ori, ror, rorv, sb, sd, sh, sll, sllv, slt, slti, sltiu, sltu, sra, srav, srl, srlv, sub, subu, sw, sync, syscall, teq, tge, tgeu, tlt, tltu, tne, xor, xori, check_fmt_p, do_load_double, do_store_double, abs.FMT, add.FMT, ceil.l.FMT, ceil.w.FMT, cfc1, ctc1, cvt.d.FMT, cvt.l.FMT, cvt.w.FMT, div.FMT, dfmc1, dmtc1, floor.l.FMT, floor.w.FMT, ldc1, lwc1, mfc1, mov.FMT, mtc1, mul.FMT, recip.FMT, round.l.FMT, round.w.FMT, rsqrt.FMT, sdc1, sqrt.FMT, sub.FMT, swc1, trunc.l.FMT, trunc.w.FMT, bc0f, bc0fl, bc0t, bc0tl, dmfc0, dmtc0, eret, mfc0, mtc0, cop, tlbp, tlbr, tlbwi, tlbwr): Enable on *r6 models. * mips3264r2.igen (dext, dextm, dextu, di, dins, dinsm, dinsu, dsbh, dshd, ei, ext, mfhc1, mthc1, ins, seb, seh, synci, rdhwr, wsbh): Likewise. * mips3264r6.igen: New file. * sim-main.h (FP_formats): Add fmt_dc32. (FORBIDDEN_SLOT): New macros. (simFORBIDDENSLOT, FP_R6CMP_*, FP_R6CLASS_*): New defines. (fp_r6_cmp, fp_classify, fp_rint, fp_min, fp_max, fp_mina, fp_maxa, fp_fmadd, fp_fmsub): New declarations. (R6Compare, Classify, RoundToIntegralExact, Min, Max, MinA, MaxA, FusedMultiplyAdd, FusedMultiplySub): New macros. Wrapping previous declarations. sim/testsuite/mips/ChangeLog: * basic.exp: Add r6-*.s tests. (run_r6_removed_test): New function. (run_endian_tests): New function. * hilo-hazard-3.s: Skip for mips*r6. * r2-fpu.s: New test. * r6-64.s: New test. * r6-branch.s: New test. * r6-forbidden.s: New test. * r6-fpu.s: New test. * r6-llsc-dp.s: New test. * r6-llsc-wp.s: New test. * r6-removed.csv: New test. * r6-removed.s: New test. * r6.s: New test. * utils-r6.inc: New inc.
2022-02-02 18:17:25 +08:00
#define EXTEND18(X) (LSSEXT ((X), 17))
#define EXTEND19(X) (LSSEXT ((X), 18))
#define EXTEND21(X) (LSSEXT ((X), 20))
#define EXTEND24(X) (LSSEXT ((X), 23))
[PATCH] Add micromips support to the MIPS simulator 2015-09-25 Andrew Bennett <andrew.bennett@imgtec.com> Ali Lown <ali.lown@imgtec.com> sim/common/ * sim-bits.h (EXTEND6): New macro. (EXTEND12): New macro. (EXTEND25): New macro. sim/mips/ * Makefile.in (tmp-micromips): New rule. (tmp-mach-multi): Add support for micromips. * configure.ac (mips*-sde-elf* | mips*-mti-elf*): Made a multi sim that works for both mips64 and micromips64. (mipsisa32r2*-*-*): Made a multi sim that works for mips32 and micromips32. Add build support for micromips. * dsp.igen (do_ph_s_absq, do_w_s_absq, do_qb_s_absq, do_addsc, do_addwc, do_bitrev, do_extpv, do_extrv, do_extrv_s_h, do_insv, do_lxx do_modsub, do_mthlip, do_mulsaq_s_w_ph, do_ph_packrl, do_qb_pick do_ph_pick, do_qb_ph_precequ, do_qb_ph_preceu, do_w_preceq do_w_ph_precrq, do_ph_qb_precrq, do_w_ph_rs_precrq do_qb_w_raddu, do_rddsp, do_repl, do_shilov, do_ph_shl, do_qb_shl do_w_s_shllv, do_ph_shrlv, do_w_r_shrav, do_wrdsp, do_qb_shrav, do_append, do_balign, do_ph_w_mulsa, do_ph_qb_precr, do_prepend): New functions. Refactored instruction code to use these functions. * dsp2.igen: Refactored instruction code to use the new functions. * interp.c (decode_coproc): Refactored to work with any instruction encoding. (isa_mode): New variable (RSVD_INSTRUCTION): Changed to 0x00000039. * m16.igen (BREAK16): Refactored instruction to use do_break16. (JALX32): Add mips32, mips64, mips32r2 and mips64r2 models. * micromips.dc: New file. * micromips.igen: New file. * micromips16.dc: New file. * micromipsdsp.igen: New file. * micromipsrun.c: New file. * mips.igen (do_swc1): Changed to work with any instruction encoding. (do_add do_addi do_andi do_dadd do_daddi do_dsll32 do_dsra32 do_dsrl32, do_dsub, do_break, do_break16, do_clo, do_clz, do_dclo do_dclz, do_lb, do_lh, do_lwr, do_lwl, do_lwc, do_lw, do_lwu, do_lhu do_ldc, do_lbu, do_ll, do_lld, do_lui, do_madd, do_dsp_madd, do_maddu do_dsp_maddu, do_dsp_mfhi, do_dsp_mflo, do_movn, do_movz, do_msub do_dsp_msub, do_msubu, do_dsp_msubu, do_mthi, do_dsp_mthi, do_mtlo do_dsp_mtlo, do_mul, do_dsp_mult, do_dsp_multu, do_pref, do_sc, do_scd do_sub, do_sw, do_teq, do_teqi, do_tge, do_tgei, do_tgeiu, do_tgeu, do_tlt do_tlti, do_tltiu, do_tltu, do_tne, do_tnei, do_abs_fmt, do_add_fmt do_alnv_ps, do_c_cond_fmt, do_ceil_fmt, do_cfc1, do_ctc1, do_cvt_d_fmt do_cvt_l_fmt, do_cvt_ps_s, do_cvt_s_fmt, do_cvt_s_pl, do_cvt_s_pu do_cvt_w_fmt, do_div_fmt, do_dmfc1b, do_dmtc1b, do_floor_fmt, do_luxc1_32 do_luxc1_64, do_lwc1, do_lwxc1, do_madd_fmt, do_mfc1b, do_mov_fmt, do_movtf do_movtf_fmt, do_movn_fmt, do_movz_fmt, do_msub_fmt, do_mtc1b, do_mul_fmt do_neg_fmt, do_nmadd_fmt, do_nmsub_fmt, do_pll_ps, do_plu_ps, do_pul_ps do_puu_ps, do_recip_fmt, do_round_fmt, do_rsqrt_fmt, do_prefx, do_sdc1 do_suxc1_32, do_suxc1_64, do_sqrt_fmt, do_sub_fmt, do_swc1, do_swxc1 do_trunc_fmt): New functions, refactored from existing instructions. Refactored instruction code to use these functions. (RSVD): Changed to use new reserved instruction. (loadstore_ea, not_word_value, unpredictable, check_mt_hilo, check_mf_hilo, check_mult_hilo, check_div_hilo, check_u64, do_luxc1_32, do_sdc1, do_suxc1_32, check_fmt_p, check_fpu, do_load_double, do_store_double): Added micromips32 and micromips64 models. Added include for micromips.igen and micromipsdsp.igen Add micromips32 and micromips64 models. (DecodeCoproc): Updated to use new macro definition. * mips3264r2.igen (do_dsbh, do_dshd, do_dext, do_dextm, do_dextu, do_di, do_dins, do_dinsm, do_ei, do_ext, do_mfhc1, do_mthc1, do_ins, do_dinsu, do_seb, do_seh do_rdhwr, do_wsbh): New functions. Refactored instruction code to use these functions. * sim-main.h (CP0_operation): New enum. (DecodeCoproc): Updated macro. (IMEM32_MICROMIPS, IMEM16_MICROMIPS, MICROMIPS_MINOR_OPCODE, MICROMIPS_DELAYSLOT_SIZE_ANY, MICROMIPS_DELAYSLOT_SIZE_16, MICROMIPS_DELAYSLOT_SIZE_32, ISA_MODE_MIPS32 and ISA_MODE_MICROMIPS): New defines. (sim_state): Add isa_mode field. sim/testsuite/sim/mips/ * basic.exp (run_micromips_test, run_sim_tests): New functions Add support for micromips tests. * hilo-hazard-4.s: New file. * testutils.inc (_dowrite): Changed reserved instruction encoding. (writemsg): Moved the la and li instructions before the data they are assigned to, which prevents a bug where MIPS32 relocations are used instead of micromips relocations when building for micromips.
2015-09-25 22:52:18 +08:00
#define EXTEND25(X) (LSSEXT ((X), 24))
sim: mips: Add simulator support for mips32r6/mips64r6 2022-02-01 Ali Lown <ali.lown@imgtec.com> Andrew Bennett <andrew.bennett@imgtec.com> Dragan Mladjenovic <dragan.mladjenovic@rt-rk.com> Faraz Shahbazker <fshahbazker@wavecomp.com> sim/common/ChangeLog: * sim-bits.h (EXTEND9, EXTEND18 ,EXTEND19, EXTEND21, EXTEND26): New macros. sim/mips/ChangeLog: * Makefile.in (IGEN_INCLUDE): Add mips3264r6.igen. * configure: Regenerate. * configure.ac: Support mipsisa32r6 and mipsisa64r6. (sim_engine_run): Pick simulator model from processor specified in e_flags. * cp1.c (value_fpr): Handle fmt_dc32. (fp_unary, fp_binary): Zero initialize locals. (update_fcsr, fp_classify, fp_rint, fp_r6_cmp, inner_fmac, fp_fmac, fp_min, fp_max, fp_mina, fp_maxa, fp_fmadd, fp_fmsub): New functions. (sim_fpu_class_mips_mapping): New. * cp1.h (fcsr_ABS2008_mask, fcsr_ABS2008_shift): New define. * interp.c (MIPSR6_P): New. (load_word): Allow unaligned memory access for MIPSR6. * micromips.igen (sc, scd): Adapt to new do_sc* helper signature. * mips.igen: Add *r6 models. (signal_if_cti, forbiddenslot32): New helpers. (delayslot32): Use signal_if_cti. (do_sc, do_scd); Add store_ll_bit parameter. (sc, scd): Adapt to previous change. (nal, beq, bal): New definitions for *r6. (sll): Split nop and ssnop cases into ... (nop, ssnop): New definitions. (loadstore_ea): Use the 32-bit compatibility adressing. (cache): Split logic into ... (do_cache): New helper. (check_fpu): Select IEEE 754-2008 mode for R6. (not_word_value, unpredictable, check_mt_hilo, check_mf_hilo, check_multi_hilo, check_div_hilo, check_u64, do_dmfc1b, add, li, addu, and, andi, bgez, bgtz, blez, bltz, bne, break, dadd, daddiu, daddu, dror, dror32, drorv, dsll, dsll32, dsllv, dsra, dsra32, dsrav, dsrl, dsrl32, dsub, dsubu, j, jal, jalr, jalr.hb, lb, lbu, ld, lh, lhu, lui, lw, lwu, nor, or, ori, ror, rorv, sb, sd, sh, sll, sllv, slt, slti, sltiu, sltu, sra, srav, srl, srlv, sub, subu, sw, sync, syscall, teq, tge, tgeu, tlt, tltu, tne, xor, xori, check_fmt_p, do_load_double, do_store_double, abs.FMT, add.FMT, ceil.l.FMT, ceil.w.FMT, cfc1, ctc1, cvt.d.FMT, cvt.l.FMT, cvt.w.FMT, div.FMT, dfmc1, dmtc1, floor.l.FMT, floor.w.FMT, ldc1, lwc1, mfc1, mov.FMT, mtc1, mul.FMT, recip.FMT, round.l.FMT, round.w.FMT, rsqrt.FMT, sdc1, sqrt.FMT, sub.FMT, swc1, trunc.l.FMT, trunc.w.FMT, bc0f, bc0fl, bc0t, bc0tl, dmfc0, dmtc0, eret, mfc0, mtc0, cop, tlbp, tlbr, tlbwi, tlbwr): Enable on *r6 models. * mips3264r2.igen (dext, dextm, dextu, di, dins, dinsm, dinsu, dsbh, dshd, ei, ext, mfhc1, mthc1, ins, seb, seh, synci, rdhwr, wsbh): Likewise. * mips3264r6.igen: New file. * sim-main.h (FP_formats): Add fmt_dc32. (FORBIDDEN_SLOT): New macros. (simFORBIDDENSLOT, FP_R6CMP_*, FP_R6CLASS_*): New defines. (fp_r6_cmp, fp_classify, fp_rint, fp_min, fp_max, fp_mina, fp_maxa, fp_fmadd, fp_fmsub): New declarations. (R6Compare, Classify, RoundToIntegralExact, Min, Max, MinA, MaxA, FusedMultiplyAdd, FusedMultiplySub): New macros. Wrapping previous declarations. sim/testsuite/mips/ChangeLog: * basic.exp: Add r6-*.s tests. (run_r6_removed_test): New function. (run_endian_tests): New function. * hilo-hazard-3.s: Skip for mips*r6. * r2-fpu.s: New test. * r6-64.s: New test. * r6-branch.s: New test. * r6-forbidden.s: New test. * r6-fpu.s: New test. * r6-llsc-dp.s: New test. * r6-llsc-wp.s: New test. * r6-removed.csv: New test. * r6-removed.s: New test. * r6.s: New test. * utils-r6.inc: New inc.
2022-02-02 18:17:25 +08:00
#define EXTEND26(X) (LSSEXT ((X), 25))
#define EXTEND32(X) ((signed_word)(int32_t)(X))
#define EXTEND64(X) ((signed_word)(int64_t)(X))
/* depending on MODE return a 64bit or 32bit (sign extended) value */
#if (WITH_TARGET_WORD_BITSIZE == 64)
#define EXTENDED(X) ((int64_t)(int32_t)(X))
#endif
#if (WITH_TARGET_WORD_BITSIZE == 32)
#define EXTENDED(X) (X)
#endif
#if (WITH_TARGET_WORD_BITSIZE == 16)
#define EXTENDED(X) (X)
#endif
/* memory alignment macro's */
#define align_up(v, n) (((v) + (n) - 1) & -(n))
#define align_down(v, n) ((v) & -(n))
/* bit bliting macro's */
#define BLIT32(V, POS, BIT) \
do { \
if (BIT) \
V |= BIT32 (POS); \
else \
V &= ~BIT32 (POS); \
} while (0)
#define MBLIT32(V, LO, HI, VAL) \
do { \
(V) = (((V) & ~MASK32 ((LO), (HI))) \
| INSERTED32 (VAL, LO, HI)); \
} while (0)
/* some rotate functions. The generic macro's ROT, ROTL, ROTR are
[sim] Run spellcheck.sh in sim (part 1) Run gdb/contrib/spellcheck.sh on directory sim. Fix auto-corrected typos: ... accessable -> accessible accidently -> accidentally accomodate -> accommodate adress -> address afair -> affair agains -> against agressively -> aggressively annuled -> annulled arbitary -> arbitrary arround -> around auxillary -> auxiliary availablity -> availability clasic -> classic comming -> coming controled -> controlled controling -> controlling destory -> destroy existance -> existence explictly -> explicitly faciliate -> facilitate fouth -> fourth fullfilled -> fulfilled guarentee -> guarantee hinderance -> hindrance independant -> independent inital -> initial loosing -> losing occurance -> occurrence occured -> occurred occuring -> occurring omited -> omitted oportunity -> opportunity parallely -> parallelly permissable -> permissible postive -> positive powerfull -> powerful preceed -> precede preceeding -> preceding preceeds -> precedes primative -> primitive probaly -> probably programable -> programmable propogate -> propagate propper -> proper recieve -> receive reconized -> recognized refered -> referred refering -> referring relevent -> relevant responisble -> responsible retreive -> retrieve safty -> safety specifiying -> specifying spontanous -> spontaneous sqaure -> square successfull -> successful supress -> suppress sytem -> system thru -> through transfered -> transferred trigered -> triggered unfortunatly -> unfortunately upto -> up to usefull -> useful wierd -> weird writen -> written doesnt -> doesn't isnt -> isn't ... Manually undid the "andd -> and" transformation in sim/testsuite/cr16/andd.cgs and sim/cr16/simops.c. Tested by rebuilding on x86_64-linux. Approved-By: Tom Tromey <tom@tromey.com>
2024-11-23 20:07:38 +08:00
intentionally omitted. */
INLINE_SIM_BITS(uint8_t) ROT8 (uint8_t val, int shift);
INLINE_SIM_BITS(uint16_t) ROT16 (uint16_t val, int shift);
INLINE_SIM_BITS(uint32_t) ROT32 (uint32_t val, int shift);
INLINE_SIM_BITS(uint64_t) ROT64 (uint64_t val, int shift);
INLINE_SIM_BITS(uint8_t) ROTL8 (uint8_t val, int shift);
INLINE_SIM_BITS(uint16_t) ROTL16 (uint16_t val, int shift);
INLINE_SIM_BITS(uint32_t) ROTL32 (uint32_t val, int shift);
INLINE_SIM_BITS(uint64_t) ROTL64 (uint64_t val, int shift);
INLINE_SIM_BITS(uint8_t) ROTR8 (uint8_t val, int shift);
INLINE_SIM_BITS(uint16_t) ROTR16 (uint16_t val, int shift);
INLINE_SIM_BITS(uint32_t) ROTR32 (uint32_t val, int shift);
INLINE_SIM_BITS(uint64_t) ROTR64 (uint64_t val, int shift);
/* Sign extension operations */
INLINE_SIM_BITS(uint8_t) LSSEXT8 (int8_t val, int sign_bit);
INLINE_SIM_BITS(uint16_t) LSSEXT16 (int16_t val, int sign_bit);
INLINE_SIM_BITS(uint32_t) LSSEXT32 (int32_t val, int sign_bit);
INLINE_SIM_BITS(uint64_t) LSSEXT64 (int64_t val, int sign_bit);
INLINE_SIM_BITS(unsigned_word) LSSEXT (signed_word val, int sign_bit);
INLINE_SIM_BITS(uint8_t) MSSEXT8 (int8_t val, int sign_bit);
INLINE_SIM_BITS(uint16_t) MSSEXT16 (int16_t val, int sign_bit);
INLINE_SIM_BITS(uint32_t) MSSEXT32 (int32_t val, int sign_bit);
INLINE_SIM_BITS(uint64_t) MSSEXT64 (int64_t val, int sign_bit);
INLINE_SIM_BITS(unsigned_word) MSSEXT (signed_word val, int sign_bit);
#if (WITH_TARGET_WORD_MSB == 0)
#define SEXT8 MSSEXT8
#define SEXT16 MSSEXT16
#define SEXT32 MSSEXT32
#define SEXT64 MSSEXT64
#define SEXT MSSEXT
#else
#define SEXT8 LSSEXT8
#define SEXT16 LSSEXT16
#define SEXT32 LSSEXT32
#define SEXT64 LSSEXT64
#define SEXT LSSEXT
#endif
#if H_REVEALS_MODULE_P (SIM_BITS_INLINE)
#include "sim-bits.c"
#endif
#endif /* SIM_BITS_H */