binutils-gdb/gas/config/tc-i386.h

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/* tc-i386.h -- Header file for tc-i386.c
Copyright (C) 1989-2024 Free Software Foundation, Inc.
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This file is part of GAS, the GNU Assembler.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
GAS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GAS; see the file COPYING. If not, write to the Free
Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
02110-1301, USA. */
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#ifndef TC_I386
#define TC_I386 1
#include "opcodes/i386-opc.h"
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struct fix;
#define TARGET_BYTES_BIG_ENDIAN 0
bfd/ 2009-07-25 H.J. Lu <hongjiu.lu@intel.com> * archures.c (bfd_architecture): Add bfd_arch_l1om. (bfd_l1om_arch): New. (bfd_archures_list): Add &bfd_l1om_arch. * bfd-in2.h: Regenerated. * config.bfd (targ64_selvecs): Add bfd_elf64_l1om_vec if bfd_elf64_x86_64_vec is supported. Add bfd_elf64_l1om_freebsd_vec if bfd_elf64_x86_64_freebsd_vec is supported. (targ_selvecs): Likewise. * configure.in: Support bfd_elf64_l1om_vec and bfd_elf64_l1om_freebsd_vec. * configure: Regenerated. * cpu-l1om.c: New. * elf64-x86-64.c (elf64_l1om_elf_object_p): New. (bfd_elf64_l1om_vec): Likewise. (bfd_elf64_l1om_freebsd_vec): Likewise. * Makefile.am (ALL_MACHINES): Add cpu-l1om.lo. (ALL_MACHINES_CFILES): Add cpu-l1om.c. * Makefile.in: Regenerated. * targets.c (bfd_elf64_l1om_vec): New. (bfd_elf64_l1om_freebsd_vec): Likewise. (_bfd_target_vector): Add bfd_elf64_l1om_vec and bfd_elf64_l1om_freebsd_vec. binutils/ 2009-07-25 H.J. Lu <hongjiu.lu@intel.com> * readelf.c (guess_is_rela): Handle EM_L1OM. (dump_relocations): Likewise. (get_machine_name): Likewise. (get_section_type_name): Likewise. (get_elf_section_flags): Likewise. (get_symbol_index_type): Likewise. (is_32bit_abs_reloc): Likewise. (is_32bit_pcrel_reloc): Likewise. (is_64bit_abs_reloc): Likewise. (is_64bit_pcrel_reloc): Likewise. (is_none_reloc): Likewise. gas/ 2009-07-25 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (cpu_arch): Add l1om. (check_cpu_arch_compatible): New. (set_cpu_arch): Use it. (i386_arch): New. (i386_mach): Return bfd_mach_l1om for Intel L1OM. (md_show_usage): Display l1om. (i386_target_format): Return ELF_TARGET_L1OM_FORMAT if cpu_arch_isa_flags.bitfield.cpul1om is set. * config/tc-i386.h (TARGET_ARCH): Use (i386_arch ()). (i386_arch): New. (ELF_TARGET_L1OM_FORMAT): Likewise. * doc/c-i386.texi: Document l1om. gas/testsuite/ 2009-07-25 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/l1om.d: New. * gas/i386/l1om-inval.l: Likewise. * gas/i386/l1om-inval.s: Likewise. * gas/i386/i386.exp: Run l1om-inval and l1om. include/elf/ 2009-07-25 H.J. Lu <hongjiu.lu@intel.com> * common.h (EM_L1OM): New. ld/ 2009-07-25 H.J. Lu <hongjiu.lu@intel.com> * configure.tgt (targ64_extra_emuls): Add elf_l1om if elf_x86_64 is supported. Add elf_l1om_fbsd if elf_x86_64_fbsd is supported. (targ_extra_emuls): Likewise. * Makefile.am (ALL_64_EMULATIONS): Add eelf_l1om.o and eelf_l1om_fbsd.o (eelf_l1om.c): New. (eelf_l1om_fbsd.c): Likewise. * Makefile.in: Regenerated. * emulparams/elf_l1om.sh: New. * emulparams/elf_l1om_fbsd.sh: Likewise. ld/testsuite/ 2009-07-25 H.J. Lu <hongjiu.lu@intel.com> * ld-x86-64/abs-l1om.d: New. * ld-x86-64/protected2-l1om.d: Likewise. * ld-x86-64/protected3-l1om.d: Likewise. * ld-x86-64/x86-64.exp: Run abs-l1om, protected2-l1om and protected3-l1om. opcodes/ 2009-07-25 H.J. Lu <hongjiu.lu@intel.com> * configure.in: Handle bfd_l1om_arch. * disassemble.c (disassembler): Likewise. * configure: Regenerated. * i386-dis.c (print_insn): Handle bfd_mach_l1om and bfd_mach_l1om_intel_syntax. Use 8 bytes per line for Intel L1OM. * i386-gen.c (cpu_flag_init): Set CPU_UNKNOWN_FLAGS to ~CpuL1OM. Add CPU_L1OM_FLAGS. (cpu_flags): Add CpuL1OM. (set_bitfield): Take an argument to set the value field. (process_i386_cpu_flag): Support ~CpuXXX and ~(CpuXXX|CpuYYY). (process_i386_opcode_modifier): Updated. (process_i386_operand_type): Likewise. * i386-init.h: Regenerated. * i386-tbl.h: Likewise. * i386-opc.h (CpuL1OM): New. (CpuXsave): Updated. (i386_cpu_flags): Add cpul1om.
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#define TARGET_ARCH (i386_arch ())
#define TARGET_MACH (i386_mach ())
bfd/ 2009-07-25 H.J. Lu <hongjiu.lu@intel.com> * archures.c (bfd_architecture): Add bfd_arch_l1om. (bfd_l1om_arch): New. (bfd_archures_list): Add &bfd_l1om_arch. * bfd-in2.h: Regenerated. * config.bfd (targ64_selvecs): Add bfd_elf64_l1om_vec if bfd_elf64_x86_64_vec is supported. Add bfd_elf64_l1om_freebsd_vec if bfd_elf64_x86_64_freebsd_vec is supported. (targ_selvecs): Likewise. * configure.in: Support bfd_elf64_l1om_vec and bfd_elf64_l1om_freebsd_vec. * configure: Regenerated. * cpu-l1om.c: New. * elf64-x86-64.c (elf64_l1om_elf_object_p): New. (bfd_elf64_l1om_vec): Likewise. (bfd_elf64_l1om_freebsd_vec): Likewise. * Makefile.am (ALL_MACHINES): Add cpu-l1om.lo. (ALL_MACHINES_CFILES): Add cpu-l1om.c. * Makefile.in: Regenerated. * targets.c (bfd_elf64_l1om_vec): New. (bfd_elf64_l1om_freebsd_vec): Likewise. (_bfd_target_vector): Add bfd_elf64_l1om_vec and bfd_elf64_l1om_freebsd_vec. binutils/ 2009-07-25 H.J. Lu <hongjiu.lu@intel.com> * readelf.c (guess_is_rela): Handle EM_L1OM. (dump_relocations): Likewise. (get_machine_name): Likewise. (get_section_type_name): Likewise. (get_elf_section_flags): Likewise. (get_symbol_index_type): Likewise. (is_32bit_abs_reloc): Likewise. (is_32bit_pcrel_reloc): Likewise. (is_64bit_abs_reloc): Likewise. (is_64bit_pcrel_reloc): Likewise. (is_none_reloc): Likewise. gas/ 2009-07-25 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (cpu_arch): Add l1om. (check_cpu_arch_compatible): New. (set_cpu_arch): Use it. (i386_arch): New. (i386_mach): Return bfd_mach_l1om for Intel L1OM. (md_show_usage): Display l1om. (i386_target_format): Return ELF_TARGET_L1OM_FORMAT if cpu_arch_isa_flags.bitfield.cpul1om is set. * config/tc-i386.h (TARGET_ARCH): Use (i386_arch ()). (i386_arch): New. (ELF_TARGET_L1OM_FORMAT): Likewise. * doc/c-i386.texi: Document l1om. gas/testsuite/ 2009-07-25 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/l1om.d: New. * gas/i386/l1om-inval.l: Likewise. * gas/i386/l1om-inval.s: Likewise. * gas/i386/i386.exp: Run l1om-inval and l1om. include/elf/ 2009-07-25 H.J. Lu <hongjiu.lu@intel.com> * common.h (EM_L1OM): New. ld/ 2009-07-25 H.J. Lu <hongjiu.lu@intel.com> * configure.tgt (targ64_extra_emuls): Add elf_l1om if elf_x86_64 is supported. Add elf_l1om_fbsd if elf_x86_64_fbsd is supported. (targ_extra_emuls): Likewise. * Makefile.am (ALL_64_EMULATIONS): Add eelf_l1om.o and eelf_l1om_fbsd.o (eelf_l1om.c): New. (eelf_l1om_fbsd.c): Likewise. * Makefile.in: Regenerated. * emulparams/elf_l1om.sh: New. * emulparams/elf_l1om_fbsd.sh: Likewise. ld/testsuite/ 2009-07-25 H.J. Lu <hongjiu.lu@intel.com> * ld-x86-64/abs-l1om.d: New. * ld-x86-64/protected2-l1om.d: Likewise. * ld-x86-64/protected3-l1om.d: Likewise. * ld-x86-64/x86-64.exp: Run abs-l1om, protected2-l1om and protected3-l1om. opcodes/ 2009-07-25 H.J. Lu <hongjiu.lu@intel.com> * configure.in: Handle bfd_l1om_arch. * disassemble.c (disassembler): Likewise. * configure: Regenerated. * i386-dis.c (print_insn): Handle bfd_mach_l1om and bfd_mach_l1om_intel_syntax. Use 8 bytes per line for Intel L1OM. * i386-gen.c (cpu_flag_init): Set CPU_UNKNOWN_FLAGS to ~CpuL1OM. Add CPU_L1OM_FLAGS. (cpu_flags): Add CpuL1OM. (set_bitfield): Take an argument to set the value field. (process_i386_cpu_flag): Support ~CpuXXX and ~(CpuXXX|CpuYYY). (process_i386_opcode_modifier): Updated. (process_i386_operand_type): Likewise. * i386-init.h: Regenerated. * i386-tbl.h: Likewise. * i386-opc.h (CpuL1OM): New. (CpuXsave): Updated. (i386_cpu_flags): Add cpul1om.
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extern enum bfd_architecture i386_arch (void);
extern unsigned long i386_mach (void);
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#ifdef TE_FreeBSD
#define AOUT_TARGET_FORMAT "a.out-i386-freebsd"
#endif
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#ifdef TE_NetBSD
#define AOUT_TARGET_FORMAT "a.out-i386-netbsd"
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#endif
#ifdef TE_386BSD
#define AOUT_TARGET_FORMAT "a.out-i386-bsd"
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#endif
#ifdef TE_LINUX
#define AOUT_TARGET_FORMAT "a.out-i386-linux"
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#endif
#ifdef TE_Mach
#define AOUT_TARGET_FORMAT "a.out-mach3"
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#endif
#ifdef TE_DYNIX
#define AOUT_TARGET_FORMAT "a.out-i386-dynix"
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#endif
#ifndef AOUT_TARGET_FORMAT
#define AOUT_TARGET_FORMAT "a.out-i386"
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#endif
#ifdef TE_FreeBSD
#define ELF_TARGET_FORMAT "elf32-i386-freebsd"
#define ELF_TARGET_FORMAT64 "elf64-x86-64-freebsd"
2005-05-05 Paul Brook <paul@codesourcery.com> bfd/ * config.bfd: Use bfd_elf32_i386_vxworks_vec for i?86-*-vxworks. * configure.in: Add bfd_elf32_i386_vxworks_vec. i386 targets need elf-vxworks.lo. * configure: Regenerate. * Makefile.am (BFD32_BACKENDS): Add elf-vxworks.lo. (BFD32_BACKENDS_CFILES): Add elf-vxworks.c. (elf32-i386.lo): Depend on elf-vxworks.h. (elf-vxworks.lo): New rule. * Makefile.in: Regenerate. * elf-bfd.h (elf_backend_data): Update type of elf_backend_emit_relocs. (_bfd_elf_link_output_relocs): Update prototype. * elflink.c (_bfd_elf_link_output_relocs): Always use bed->elf_backend_emit_relocs when outputting relocations. * elfxx-target.h (elf_backend_emit_relocs): Default to _bfd_elf_link_output_relocs. * targets.c (bfd_elf32_i386_vxworks_vec): Declare. (_bfd_target_vector): Add bfd_elf32_i386_vxworks_vec. * elf32-i386.c: Add elf32-i386-vxworks target BFD. (elf_i386_plt0_entry): Remove padding. (elf_i386_pic_plt0_entry): Ditto. (PLTRESOLVE_RELOCS_SHLIB, PLTRESOLVE_RELOCS): Define. (PLT_NON_JUMP_SLOT_RELOCS): Define. (elf_i386_link_hash_table): Add srelplt2, hgot, hplt, is_vxworks and plt0_pad_byte fields. (elf_i386_link_hash_table_create): Zero them. (elf_i386_create_dynamic_sections): Create static relocation section. (allocate_dynrelocs): Allocate space for static PLT relocations. (elf_i386_size_dynamic_sections): Save shortcuts to PLT and GOT symbols. Give PLT symbols function type. Don't strip PLT sections if we have exported symbols from them. (elf_i386_finish_dynamic_symbol): Fill in VxWorks PLT static relocation section. Don't mark _GLOBAL_OFFSET_TABLE_ as absolute on VxWorks. (elf_i386_finish_dynamic_sections): Allow different pad bytes. Add relocation for GOT location. Fill in PLT static relocations. (elf_i386_vxworks_link_hash_table_create): New function. (elf_i386_vxworks_link_output_symbol_hook): New function. * elf-vxworks.h: New file. gas/ * config/tc-i386.h (ELF_TARGET_FORMAT): Define for TE_VXWORKS. gas/testsuite/ * gas/i386/i386.exp: Don't run divide test on vxworks. ld/ * Makefile.am: Add eelf_i386_vxworks. * Makefile.in: Regenerate. * configure.tgt: Make i?86-*-vxworks use targ_emul=elf_i386_vxworks. * emulparams/elf_i386_vxworks.sh: New file. * emulparams/vxworks.sh: New file. * scripttempl/elf.sc: Add DATA_END_SYMBOLS and ETEXT_NAME.
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#elif defined (TE_VXWORKS)
#define ELF_TARGET_FORMAT "elf32-i386-vxworks"
#elif defined TE_CLOUDABI
#define ELF_TARGET_FORMAT64 "elf64-x86-64-cloudabi"
#endif
2005-05-05 Paul Brook <paul@codesourcery.com> bfd/ * config.bfd: Use bfd_elf32_i386_vxworks_vec for i?86-*-vxworks. * configure.in: Add bfd_elf32_i386_vxworks_vec. i386 targets need elf-vxworks.lo. * configure: Regenerate. * Makefile.am (BFD32_BACKENDS): Add elf-vxworks.lo. (BFD32_BACKENDS_CFILES): Add elf-vxworks.c. (elf32-i386.lo): Depend on elf-vxworks.h. (elf-vxworks.lo): New rule. * Makefile.in: Regenerate. * elf-bfd.h (elf_backend_data): Update type of elf_backend_emit_relocs. (_bfd_elf_link_output_relocs): Update prototype. * elflink.c (_bfd_elf_link_output_relocs): Always use bed->elf_backend_emit_relocs when outputting relocations. * elfxx-target.h (elf_backend_emit_relocs): Default to _bfd_elf_link_output_relocs. * targets.c (bfd_elf32_i386_vxworks_vec): Declare. (_bfd_target_vector): Add bfd_elf32_i386_vxworks_vec. * elf32-i386.c: Add elf32-i386-vxworks target BFD. (elf_i386_plt0_entry): Remove padding. (elf_i386_pic_plt0_entry): Ditto. (PLTRESOLVE_RELOCS_SHLIB, PLTRESOLVE_RELOCS): Define. (PLT_NON_JUMP_SLOT_RELOCS): Define. (elf_i386_link_hash_table): Add srelplt2, hgot, hplt, is_vxworks and plt0_pad_byte fields. (elf_i386_link_hash_table_create): Zero them. (elf_i386_create_dynamic_sections): Create static relocation section. (allocate_dynrelocs): Allocate space for static PLT relocations. (elf_i386_size_dynamic_sections): Save shortcuts to PLT and GOT symbols. Give PLT symbols function type. Don't strip PLT sections if we have exported symbols from them. (elf_i386_finish_dynamic_symbol): Fill in VxWorks PLT static relocation section. Don't mark _GLOBAL_OFFSET_TABLE_ as absolute on VxWorks. (elf_i386_finish_dynamic_sections): Allow different pad bytes. Add relocation for GOT location. Fill in PLT static relocations. (elf_i386_vxworks_link_hash_table_create): New function. (elf_i386_vxworks_link_output_symbol_hook): New function. * elf-vxworks.h: New file. gas/ * config/tc-i386.h (ELF_TARGET_FORMAT): Define for TE_VXWORKS. gas/testsuite/ * gas/i386/i386.exp: Don't run divide test on vxworks. ld/ * Makefile.am: Add eelf_i386_vxworks. * Makefile.in: Regenerate. * configure.tgt: Make i?86-*-vxworks use targ_emul=elf_i386_vxworks. * emulparams/elf_i386_vxworks.sh: New file. * emulparams/vxworks.sh: New file. * scripttempl/elf.sc: Add DATA_END_SYMBOLS and ETEXT_NAME.
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#ifdef TE_SOLARIS
#define ELF_TARGET_FORMAT "elf32-i386-sol2"
#define ELF_TARGET_FORMAT64 "elf64-x86-64-sol2"
#endif
#ifndef ELF_TARGET_FORMAT
#define ELF_TARGET_FORMAT "elf32-i386"
#endif
#ifndef ELF_TARGET_FORMAT64
#define ELF_TARGET_FORMAT64 "elf64-x86-64"
#endif
Add x86-64 ILP32 support. bfd/ 2010-12-30 H.J. Lu <hongjiu.lu@intel.com> * archures.c (bfd_mach_x64_32): New. (bfd_mach_x64_32_intel_syntax): Likewise. * bfd-in2.h: Regenerated. * config.bfd (targ64_selvecs): Add bfd_elf32_x86_64_vec for i[3-7]86-*-linux-*. (targ_selvecs): Add bfd_elf32_x86_64_vec for x86_64-*-linux-*. * configure.in: Support bfd_elf32_x86_64_vec. * configure: Regenerated. * cpu-i386.c (bfd_x64_32_arch_intel_syntax): New. (bfd_x64_32_arch): Likewise. * elf-bfd.h (elf_append_rela): New prototype. (elf_append_rel): Likewise. (elf64_r_info): Likewise. (elf32_r_info): Likewise. (elf64_r_sym): Likewise. (elf32_r_sym): Likewise. * elf64-x86-64.c (ABI_64_P): New. (elf_x86_64_info_to_howto): Replace ELF64_R_TYPE with ELF32_R_TYPE. Replace ELF64_ST_TYPE with ELF_ST_TYPE. (elf_x86_64_check_tls_transition):Likewise. (elf_x86_64_check_relocs): Likewise. (elf_x86_64_gc_mark_hook):Likewise. (elf_x86_64_gc_sweep_hook): Likewise. (elf_x86_64_relocate_section): Likewise. (elf_x86_64_reloc_type_class): Likewise. (ELF_DYNAMIC_INTERPRETER): Renamed to ... (ELF64_DYNAMIC_INTERPRETER): This. (ELF32_DYNAMIC_INTERPRETER): New. (elf_x86_64_link_hash_table): Add r_info, r_sym, swap_reloca_out, dynamic_interpreter and dynamic_interpreter_size. (elf_x86_64_get_local_sym_hash): Replace ELF64_R_SYM with htab->r_sym. Replace ELF64_R_INFO with htab->r_info. (elf_x86_64_get_local_sym_hash): Likewise. (elf_x86_64_check_tls_transition):Likewise. (elf_x86_64_check_relocs): Likewise. (elf_x86_64_gc_mark_hook):Likewise. (elf_x86_64_gc_sweep_hook): Likewise. (elf_x86_64_relocate_section): Likewise. (elf_x86_64_finish_dynamic_symbol): Likewise. (elf_x86_64_finish_local_dynamic_symbol): Likewise. (elf_x86_64_link_hash_table_create): Initialize r_info, r_sym, swap_reloca_out, dynamic_interpreter and dynamic_interpreter_size. (elf_x86_64_check_relocs): Check ABI_64_P when requesting for PIC. (elf_x86_64_relocate_section): Likewise. (elf64_x86_64_adjust_dynamic_symbol): Replace sizeof (Elf64_External_Rela) with bed->s->sizeof_rela. (elf64_x86_64_allocate_dynrelocs): Likewise. (elf64_x86_64_size_dynamic_sections): Likewise. (elf64_x86_64_finish_dynamic_symbol): Likewise. (elf64_x86_64_append_rela): Removed. (elf32_x86_64_elf_object_p): New. Add bfd_elf32_x86_64_vec. * elf64-x86-64.c (elf64_x86_64_xxx): Renamed to ... (elf_x86_64_xxx): This. * elflink.c (bfd_elf_final_link): Check ELF file class on error. (elf_append_rela): New. (elf_append_rel): Likewise. (elf64_r_info): Likewise. (elf32_r_info): Likewise. (elf64_r_sym): Likewise. (elf32_r_sym): Likewise. * targets.c (bfd_elf32_x86_64_vec): New. (_bfd_target_vector): Add bfd_elf32_x86_64_vec. gas/ 2010-12-30 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (x86_elf_abi): New. (i386_mach): Return bfd_mach_x64_32 for ILP32. (OPTION_N32): Likewise. (md_longopts): Add "n32" for ELF. (md_parse_option): Handle OPTION_N32. (md_show_usage): Add --n32. (i386_target_format): Update and check x86_elf_abi. * config/tc-i386.h (ELF_TARGET_FORMAT32): New. * doc/as.texinfo: Document --n32. * doc/c-i386.texi: Likewise. gas/testsuite/ 2010-12-30 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/ilp32/lns/ilp32.exp: New. * gas/i386/ilp32/lns/lns-common-1.d: Likewise. * gas/i386/ilp32/lns/lns-duplicate.d: Likewise. * gas/i386/ilp32/cfi/cfi-common-1.d: New. * gas/i386/ilp32/cfi/cfi-common-2.d: Likewise. * gas/i386/ilp32/cfi/cfi-common-3.d: Likewise. * gas/i386/ilp32/cfi/cfi-common-4.d: Likewise. * gas/i386/ilp32/cfi/cfi-common-5.d: Likewise. * gas/i386/ilp32/cfi/cfi-common-6.d: Likewise. * gas/i386/ilp32/cfi/cfi-common-7.d: Likewise. * gas/i386/ilp32/cfi/cfi-x86_64.d: Likewise. * gas/i386/ilp32/cfi/ilp32.exp: Likewise. * gas/i386/ilp32/elf/ehopt0.d: Likewise. * gas/i386/ilp32/elf/equ-reloc.d: Likewise. * gas/i386/ilp32/elf/file.d: Likewise. * gas/i386/ilp32/elf/group0a.d: Likewise. * gas/i386/ilp32/elf/group0b.d: Likewise. * gas/i386/ilp32/elf/group1a.d: Likewise. * gas/i386/ilp32/elf/group1b.d: Likewise. * gas/i386/ilp32/elf/ifunc-1.d: Likewise. * gas/i386/ilp32/elf/ilp32.exp: Likewise. * gas/i386/ilp32/elf/redef.d: Likewise. * gas/i386/ilp32/elf/section0.d: Likewise. * gas/i386/ilp32/elf/section1.d: Likewise. * gas/i386/ilp32/elf/section3.d: Likewise. * gas/i386/ilp32/elf/section4.d: Likewise. * gas/i386/ilp32/elf/section6.d: Likewise. * gas/i386/ilp32/elf/section7.d: Likewise. * gas/i386/ilp32/elf/struct.d: Likewise. * gas/i386/ilp32/elf/symtab.d: Likewise. * gas/i386/ilp32/elf/symver.d: Likewise. * gas/i386/ilp32/ilp32.exp: New. * gas/i386/ilp32/immed64.d: Likewise. * gas/i386/ilp32/mixed-mode-reloc64.d: Likewise. * gas/i386/ilp32/reloc64.d: Likewise. * gas/i386/ilp32/rex.d: Likewise. * gas/i386/ilp32/rexw.d: Likewise. * gas/i386/ilp32/svme64.d: Likewise. * gas/i386/ilp32/x86-64-addr32.d: Likewise. * gas/i386/ilp32/x86-64-addr32-intel.d: Likewise. * gas/i386/ilp32/x86-64-aes.d: Likewise. * gas/i386/ilp32/x86-64-aes-intel.d: Likewise. * gas/i386/ilp32/x86-64-amdfam10.d: Likewise. * gas/i386/ilp32/x86-64-arch-1.d: Likewise. * gas/i386/ilp32/x86-64-arch-2.d: Likewise. * gas/i386/ilp32/x86-64-avx.d: Likewise. * gas/i386/ilp32/x86-64-avx-intel.d: Likewise. * gas/i386/ilp32/x86-64-avx-swap.d: Likewise. * gas/i386/ilp32/x86-64-avx-swap-intel.d: Likewise. * gas/i386/ilp32/x86-64-branch.d: Likewise. * gas/i386/ilp32/x86-64-cbw.d: Likewise. * gas/i386/ilp32/x86-64-cbw-intel.d: Likewise. * gas/i386/ilp32/x86-64-clmul.d: Likewise. * gas/i386/ilp32/x86-64-clmul-intel.d: Likewise. * gas/i386/ilp32/x86-64-crc32.d: Likewise. * gas/i386/ilp32/x86-64-crc32-intel.d: Likewise. * gas/i386/ilp32/x86-64-crx.d: Likewise. * gas/i386/ilp32/x86-64-crx-suffix.d: Likewise. * gas/i386/ilp32/x86-64.d: Likewise. * gas/i386/ilp32/x86-64-disp.d: Likewise. * gas/i386/ilp32/x86-64-disp-intel.d: Likewise. * gas/i386/ilp32/x86-64-drx.d: Likewise. * gas/i386/ilp32/x86-64-drx-suffix.d: Likewise. * gas/i386/ilp32/x86-64-ept.d: Likewise. * gas/i386/ilp32/x86-64-ept-intel.d: Likewise. * gas/i386/ilp32/x86-64-fma4.d: Likewise. * gas/i386/ilp32/x86-64-fma.d: Likewise. * gas/i386/ilp32/x86-64-fma-intel.d: Likewise. * gas/i386/ilp32/x86-64-gidt.d: Likewise. * gas/i386/ilp32/x86-64-ifunc.d: Likewise. * gas/i386/ilp32/x86-64-intel64.d: Likewise. * gas/i386/ilp32/x86-64-io.d: Likewise. * gas/i386/ilp32/x86-64-io-intel.d: Likewise. * gas/i386/ilp32/x86-64-io-suffix.d: Likewise. * gas/i386/ilp32/x86-64-localpic.d: Likewise. * gas/i386/ilp32/x86-64-mem.d: Likewise. * gas/i386/ilp32/x86-64-mem-intel.d: Likewise. * gas/i386/ilp32/x86-64-movbe.d: Likewise. * gas/i386/ilp32/x86-64-movbe-intel.d: Likewise. * gas/i386/ilp32/x86-64-nops-1-core2.d: Likewise. * gas/i386/ilp32/x86-64-nops-1.d: Likewise. * gas/i386/ilp32/x86-64-nops-1-k8.d: Likewise. * gas/i386/ilp32/x86-64-nops-1-nocona.d: Likewise. * gas/i386/ilp32/x86-64-nops-1-pentium.d: Likewise. * gas/i386/ilp32/x86-64-nops-2.d: Likewise. * gas/i386/ilp32/x86-64-nops-3.d: Likewise. * gas/i386/ilp32/x86-64-nops-4-core2.d: Likewise. * gas/i386/ilp32/x86-64-nops-4.d: Likewise. * gas/i386/ilp32/x86-64-nops-4-k8.d: Likewise. * gas/i386/ilp32/x86-64-nops-5.d: Likewise. * gas/i386/ilp32/x86-64-nops-5-k8.d: Likewise. * gas/i386/ilp32/x86-64-nops.d: Likewise. * gas/i386/ilp32/x86-64-opcode.d: Likewise. * gas/i386/ilp32/x86-64-opcode-inval.d: Likewise. * gas/i386/ilp32/x86-64-opcode-inval-intel.d: Likewise. * gas/i386/ilp32/x86-64-opts.d: Likewise. * gas/i386/ilp32/x86-64-opts-intel.d: Likewise. * gas/i386/ilp32/x86-64-pcrel.d: Likewise. * gas/i386/ilp32/x86-64-reg.d: Likewise. * gas/i386/ilp32/x86-64-reg-intel.d: Likewise. * gas/i386/ilp32/x86-64-rep.d: Likewise. * gas/i386/ilp32/x86-64-rep-suffix.d: Likewise. * gas/i386/ilp32/x86-64-rip.d: Likewise. * gas/i386/ilp32/x86-64-rip-intel.d: Likewise. * gas/i386/ilp32/x86-64-sib.d: Likewise. * gas/i386/ilp32/x86-64-sib-intel.d: Likewise. * gas/i386/ilp32/x86-64-simd.d: Likewise. * gas/i386/ilp32/x86-64-simd-intel.d: Likewise. * gas/i386/ilp32/x86-64-simd-suffix.d: Likewise. * gas/i386/ilp32/x86-64-sse2avx.d: Likewise. * gas/i386/ilp32/x86-64-sse2avx-opts.d: Likewise. * gas/i386/ilp32/x86-64-sse2avx-opts-intel.d: Likewise. * gas/i386/ilp32/x86-64-sse3.d: Likewise. * gas/i386/ilp32/x86-64-sse4_1.d: Likewise. * gas/i386/ilp32/x86-64-sse4_1-intel.d: Likewise. * gas/i386/ilp32/x86-64-sse4_2.d: Likewise. * gas/i386/ilp32/x86-64-sse4_2-intel.d: Likewise. * gas/i386/ilp32/x86-64-sse-check.d: Likewise. * gas/i386/ilp32/x86-64-sse-check-none.d: Likewise. * gas/i386/ilp32/x86-64-sse-check-warn.d: Likewise. * gas/i386/ilp32/x86-64-sse-noavx.d: Likewise. * gas/i386/ilp32/x86-64-ssse3.d: Likewise. * gas/i386/ilp32/x86-64-stack.d: Likewise. * gas/i386/ilp32/x86-64-stack-intel.d: Likewise. * gas/i386/ilp32/x86-64-stack-suffix.d: Likewise. * gas/i386/ilp32/x86-64-unwind.d: Likewise. * gas/i386/ilp32/x86-64-vmx.d: Likewise. * gas/i386/ilp32/x86-64-xsave.d: Likewise. * gas/i386/ilp32/x86-64-xsave-intel.d: Likewise. ld/ 2010-12-30 H.J. Lu <hongjiu.lu@intel.com> * emulparams/elf32_x86_64.sh: New. * configure.tgt (targ64_extra_emuls): Add elf32_x86_64 for i[3-7]86-*-linux-*. (targ_extra_libpath): Likewise. (targ_extra_emuls): Add elf32_x86_64 for x86_64-*-linux-*. (targ_extra_libpath): Likewise. * Makefile.am (ALL_64_EMULATION_SOURCES): Add eelf32_x86_64.c. (eelf32_x86_64.c): New. * Makefile.in: Regenerated. opcodes/ 2010-12-30 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (print_insn): Support bfd_mach_x64_32 and bfd_mach_x64_32_intel_syntax.
2010-12-31 08:33:36 +08:00
#ifndef ELF_TARGET_FORMAT32
#define ELF_TARGET_FORMAT32 "elf32-x86-64"
#endif
#ifndef ELF_TARGET_IAMCU_FORMAT
#define ELF_TARGET_IAMCU_FORMAT "elf32-iamcu"
#endif
#if (defined (OBJ_ELF) || defined (TE_PE) || defined (OBJ_MACH_O))
extern const char *i386_target_format (void);
#define TARGET_FORMAT i386_target_format ()
#else
#ifdef TE_GO32
#define TARGET_FORMAT "coff-go32"
#endif
#ifdef OBJ_AOUT
#define TARGET_FORMAT AOUT_TARGET_FORMAT
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#endif
#endif
#define SUB_SEGMENT_ALIGN(SEG, FRCHAIN) 0
/* '$' may be used as immediate prefix. */
#undef LOCAL_LABELS_DOLLAR
#define LOCAL_LABELS_DOLLAR 0
#undef LOCAL_LABELS_FB
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#define LOCAL_LABELS_FB 1
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extern const char extra_symbol_chars[];
#define tc_symbol_chars extra_symbol_chars
extern const char *i386_comment_chars;
#define tc_comment_chars i386_comment_chars
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/* The name of the global offset table generated by the compiler. Allow
this to be overridden if need be. */
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#ifndef GLOBAL_OFFSET_TABLE_NAME
#define GLOBAL_OFFSET_TABLE_NAME "_GLOBAL_OFFSET_TABLE_"
#endif
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#define TC_PARSE_CONS_EXPRESSION(EXP, NBYTES) x86_cons (EXP, NBYTES)
gas TC_PARSE_CONS_EXPRESSION communication with TC_CONS_FIX_NEW A number of targets pass extra information from TC_PARSE_CONS_EXPRESSION to TC_CONS_FIX_NEW via static variables. That's OK, but not best practice. tc-ppc.c goes further in implementing its own replacement for cons(), because the generic one doesn't allow relocation modifiers on constants. This patch fixes both of these warts. * gas/config/tc-alpha.h (TC_CONS_FIX_NEW): Add RELOC parameter. * gas/config/tc-arc.c (arc_cons_fix_new): Add reloc parameter. * gas/config/tc-arc.h (arc_cons_fix_new): Update prototype. (TC_CONS_FIX_NEW): Add RELOC parameter. * gas/config/tc-arm.c (cons_fix_new_arm): Similarly * gas/config/tc-arm.h (cons_fix_new_arm, TC_CONS_FIX_NEW): Similarly. * gas/config/tc-cr16.c (cr16_cons_fix_new): Similarly. * gas/config/tc-cr16.h (cr16_cons_fix_new, TC_CONS_FIX_NEW): Similarly. * gas/config/tc-crx.h (TC_CONS_FIX_NEW): Similarly. * gas/config/tc-m32c.c (m32c_cons_fix_new): Similarly. * gas/config/tc-m32c.h (m32c_cons_fix_new, TC_CONS_FIX_NEW): Similarly. * gas/config/tc-mn10300.c (mn10300_cons_fix_new): Similarly. * gas/config/tc-mn10300.h (mn10300_cons_fix_new, TC_CONS_FIX_NEW): Similarly. * gas/config/tc-ns32k.c (cons_fix_new_ns32k): Similarly. * gas/config/tc-ns32k.h (cons_fix_new_ns32k): Similarly. * gas/config/tc-pj.c (pj_cons_fix_new_pj): Similarly. * gas/config/tc-pj.h (pj_cons_fix_new_pj, TC_CONS_FIX_NEW): Similarly. * gas/config/tc-rx.c (rx_cons_fix_new): Similarly. * gas/config/tc-rx.h (rx_cons_fix_new, TC_CONS_FIX_NEW): Similarly. * gas/config/tc-sh.c (sh_cons_fix_new): Similarly. * gas/config/tc-sh.h (sh_cons_fix_new, TC_CONS_FIX_NEW): Similarly. * gas/config/tc-tic54x.c (tic54x_cons_fix_new): Similarly. * gas/config/tc-tic54x.h (tic54x_cons_fix_new, TC_CONS_FIX_NEW): Similarly. * gas/config/tc-tic6x.c (tic6x_cons_fix_new): Similarly. * gas/config/tc-tic6x.h (tic6x_cons_fix_new, TC_CONS_FIX_NEW): Similarly. * gas/config/tc-arc.c (arc_parse_cons_expression): Return reloc. * gas/config/tc-arc.h (arc_parse_cons_expression): Update proto. * gas/config/tc-avr.c (exp_mod_data): Make global. (pexp_mod_data): Delete. (avr_parse_cons_expression): Return exp_mod_data pointer. (avr_cons_fix_new): Add exp_mod_data_t pointer param. (exp_mod_data_t): Move typedef.. * gas/config/tc-avr.h: ..to here. (exp_mod_data): Declare. (TC_PARSE_CONS_RETURN_TYPE, TC_PARSE_CONS_RETURN_NONE): Define. (avr_parse_cons_expression, avr_cons_fix_new): Update prototype. (TC_CONS_FIX_NEW): Update. * gas/config/tc-hppa.c (hppa_field_selector): Delete static var. (cons_fix_new_hppa): Add hppa_field_selector param. (fix_new_hppa): Adjust. (parse_cons_expression_hppa): Return field selector. * gas/config/tc-hppa.h (parse_cons_expression_hppa): Update proto. (cons_fix_new_hppa): Likewise. (TC_PARSE_CONS_RETURN_TYPE, TC_PARSE_CONS_RETURN_NONE): Define. * gas/config/tc-i386.c (got_reloc): Delete static var. (x86_cons_fix_new): Add reloc param. (x86_cons): Return got reloc. * gas/config/tc-i386.h (x86_cons, x86_cons_fix_new): Update proto. (TC_CONS_FIX_NEW): Add RELOC param. * gas/config/tc-ia64.c (ia64_cons_fix_new): Add reloc param. Adjust calls. * gas/config/tc-ia64.h (ia64_cons_fix_new): Update prototype. (TC_CONS_FIX_NEW): Add reloc param. * gas/config/tc-microblaze.c (parse_cons_expression_microblaze): Return reloc. (cons_fix_new_microblaze): Add reloc param. * gas/config/tc-microblaze.h: Formatting. (parse_cons_expression_microblaze): Update proto. (cons_fix_new_microblaze): Likewise. * gas/config/tc-nios2.c (nios2_tls_ldo_reloc): Delete static var. (nios2_cons): Return ldo reloc. (nios2_cons_fix_new): Delete. * gas/config/tc-nios2.h (nios2_cons): Update prototype. (nios2_cons_fix_new, TC_CONS_FIX_NEW): Delete. * gas/config/tc-ppc.c (md_pseudo_table): Remove quad, long, word, short. Make llong use cons. (ppc_elf_suffix): Return BFD_RELOC_NONE rather than BFD_RELOC_UNUSED. (ppc_elf_cons): Delete. (ppc_elf_parse_cons): New function. (ppc_elf_validate_fix): Don't check for BFD_RELOC_UNUSED. (md_assemble): Use BFD_RELOC_NONE rather than BFD_RELOC_UNUSED. * gas/config/tc-ppc.h (TC_PARSE_CONS_EXPRESSION): Define (ppc_elf_parse_cons): Declare. * gas/config/tc-sparc.c (sparc_cons_special_reloc): Delete static var. (sparc_cons): Return reloc specifier. (cons_fix_new_sparc): Add reloc specifier param. (sparc_cfi_emit_pcrel_expr): Use emit_expr_with_reloc. * gas/config/tc-sparc.h (TC_PARSE_CONS_RETURN_TYPE): Define. (TC_PARSE_CONS_RETURN_NONE): Define. (sparc_cons, cons_fix_new_sparc): Update prototype. * gas/config/tc-v850.c (hold_cons_reloc): Delete static var. (v850_reloc_prefix): Use BFD_RELOC_NONE rather than BFD_RELOC_UNUSED. (md_assemble): Likewise. (parse_cons_expression_v850): Return reloc. (cons_fix_new_v850): Add reloc parameter. * gas/config/tc-v850.h (parse_cons_expression_v850): Update proto. (cons_fix_new_v850): Likewise. * gas/config/tc-vax.c (vax_cons_special_reloc): Delete static var. (vax_cons): Return reloc. (vax_cons_fix_new): Add reloc parameter. * gas/config/tc-vax.h (vax_cons, vax_cons_fix_new): Update proto. * gas/config/tc-xstormy16.c (xstormy16_cons_fix_new): Add reloc param. * gas/config/tc-xstormy16.h (xstormy16_cons_fix_new): Update proto. * gas/dwarf2dbg.c (TC_PARSE_CONS_RETURN_NONE): Provide default. (emit_fixed_inc_line_addr): Adjust exmit_expr_fix calls. * gas/read.c (TC_PARSE_CONS_EXPRESSION): Return value. (do_parse_cons_expression): Adjust. (cons_worker): Pass return value from TC_PARSE_CONS_EXPRESSION to emit_expr_with_reloc. (emit_expr_with_reloc): New function handling reloc, mostly extracted from.. (emit_expr): ..here. (emit_expr_fix): Add reloc param. Adjust TC_CONS_FIX_NEW invocation. Handle reloc. (parse_mri_cons): Convert to ISO. * gas/read.h (TC_PARSE_CONS_RETURN_TYPE): Define. (TC_PARSE_CONS_RETURN_NONE): Define. (emit_expr_with_reloc): Declare. (emit_expr_fix): Update prototype. * gas/write.c (write_object_file): Update TC_CONS_FIX_NEW invocation.
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extern bfd_reloc_code_real_type x86_cons (expressionS *, int);
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gas TC_PARSE_CONS_EXPRESSION communication with TC_CONS_FIX_NEW A number of targets pass extra information from TC_PARSE_CONS_EXPRESSION to TC_CONS_FIX_NEW via static variables. That's OK, but not best practice. tc-ppc.c goes further in implementing its own replacement for cons(), because the generic one doesn't allow relocation modifiers on constants. This patch fixes both of these warts. * gas/config/tc-alpha.h (TC_CONS_FIX_NEW): Add RELOC parameter. * gas/config/tc-arc.c (arc_cons_fix_new): Add reloc parameter. * gas/config/tc-arc.h (arc_cons_fix_new): Update prototype. (TC_CONS_FIX_NEW): Add RELOC parameter. * gas/config/tc-arm.c (cons_fix_new_arm): Similarly * gas/config/tc-arm.h (cons_fix_new_arm, TC_CONS_FIX_NEW): Similarly. * gas/config/tc-cr16.c (cr16_cons_fix_new): Similarly. * gas/config/tc-cr16.h (cr16_cons_fix_new, TC_CONS_FIX_NEW): Similarly. * gas/config/tc-crx.h (TC_CONS_FIX_NEW): Similarly. * gas/config/tc-m32c.c (m32c_cons_fix_new): Similarly. * gas/config/tc-m32c.h (m32c_cons_fix_new, TC_CONS_FIX_NEW): Similarly. * gas/config/tc-mn10300.c (mn10300_cons_fix_new): Similarly. * gas/config/tc-mn10300.h (mn10300_cons_fix_new, TC_CONS_FIX_NEW): Similarly. * gas/config/tc-ns32k.c (cons_fix_new_ns32k): Similarly. * gas/config/tc-ns32k.h (cons_fix_new_ns32k): Similarly. * gas/config/tc-pj.c (pj_cons_fix_new_pj): Similarly. * gas/config/tc-pj.h (pj_cons_fix_new_pj, TC_CONS_FIX_NEW): Similarly. * gas/config/tc-rx.c (rx_cons_fix_new): Similarly. * gas/config/tc-rx.h (rx_cons_fix_new, TC_CONS_FIX_NEW): Similarly. * gas/config/tc-sh.c (sh_cons_fix_new): Similarly. * gas/config/tc-sh.h (sh_cons_fix_new, TC_CONS_FIX_NEW): Similarly. * gas/config/tc-tic54x.c (tic54x_cons_fix_new): Similarly. * gas/config/tc-tic54x.h (tic54x_cons_fix_new, TC_CONS_FIX_NEW): Similarly. * gas/config/tc-tic6x.c (tic6x_cons_fix_new): Similarly. * gas/config/tc-tic6x.h (tic6x_cons_fix_new, TC_CONS_FIX_NEW): Similarly. * gas/config/tc-arc.c (arc_parse_cons_expression): Return reloc. * gas/config/tc-arc.h (arc_parse_cons_expression): Update proto. * gas/config/tc-avr.c (exp_mod_data): Make global. (pexp_mod_data): Delete. (avr_parse_cons_expression): Return exp_mod_data pointer. (avr_cons_fix_new): Add exp_mod_data_t pointer param. (exp_mod_data_t): Move typedef.. * gas/config/tc-avr.h: ..to here. (exp_mod_data): Declare. (TC_PARSE_CONS_RETURN_TYPE, TC_PARSE_CONS_RETURN_NONE): Define. (avr_parse_cons_expression, avr_cons_fix_new): Update prototype. (TC_CONS_FIX_NEW): Update. * gas/config/tc-hppa.c (hppa_field_selector): Delete static var. (cons_fix_new_hppa): Add hppa_field_selector param. (fix_new_hppa): Adjust. (parse_cons_expression_hppa): Return field selector. * gas/config/tc-hppa.h (parse_cons_expression_hppa): Update proto. (cons_fix_new_hppa): Likewise. (TC_PARSE_CONS_RETURN_TYPE, TC_PARSE_CONS_RETURN_NONE): Define. * gas/config/tc-i386.c (got_reloc): Delete static var. (x86_cons_fix_new): Add reloc param. (x86_cons): Return got reloc. * gas/config/tc-i386.h (x86_cons, x86_cons_fix_new): Update proto. (TC_CONS_FIX_NEW): Add RELOC param. * gas/config/tc-ia64.c (ia64_cons_fix_new): Add reloc param. Adjust calls. * gas/config/tc-ia64.h (ia64_cons_fix_new): Update prototype. (TC_CONS_FIX_NEW): Add reloc param. * gas/config/tc-microblaze.c (parse_cons_expression_microblaze): Return reloc. (cons_fix_new_microblaze): Add reloc param. * gas/config/tc-microblaze.h: Formatting. (parse_cons_expression_microblaze): Update proto. (cons_fix_new_microblaze): Likewise. * gas/config/tc-nios2.c (nios2_tls_ldo_reloc): Delete static var. (nios2_cons): Return ldo reloc. (nios2_cons_fix_new): Delete. * gas/config/tc-nios2.h (nios2_cons): Update prototype. (nios2_cons_fix_new, TC_CONS_FIX_NEW): Delete. * gas/config/tc-ppc.c (md_pseudo_table): Remove quad, long, word, short. Make llong use cons. (ppc_elf_suffix): Return BFD_RELOC_NONE rather than BFD_RELOC_UNUSED. (ppc_elf_cons): Delete. (ppc_elf_parse_cons): New function. (ppc_elf_validate_fix): Don't check for BFD_RELOC_UNUSED. (md_assemble): Use BFD_RELOC_NONE rather than BFD_RELOC_UNUSED. * gas/config/tc-ppc.h (TC_PARSE_CONS_EXPRESSION): Define (ppc_elf_parse_cons): Declare. * gas/config/tc-sparc.c (sparc_cons_special_reloc): Delete static var. (sparc_cons): Return reloc specifier. (cons_fix_new_sparc): Add reloc specifier param. (sparc_cfi_emit_pcrel_expr): Use emit_expr_with_reloc. * gas/config/tc-sparc.h (TC_PARSE_CONS_RETURN_TYPE): Define. (TC_PARSE_CONS_RETURN_NONE): Define. (sparc_cons, cons_fix_new_sparc): Update prototype. * gas/config/tc-v850.c (hold_cons_reloc): Delete static var. (v850_reloc_prefix): Use BFD_RELOC_NONE rather than BFD_RELOC_UNUSED. (md_assemble): Likewise. (parse_cons_expression_v850): Return reloc. (cons_fix_new_v850): Add reloc parameter. * gas/config/tc-v850.h (parse_cons_expression_v850): Update proto. (cons_fix_new_v850): Likewise. * gas/config/tc-vax.c (vax_cons_special_reloc): Delete static var. (vax_cons): Return reloc. (vax_cons_fix_new): Add reloc parameter. * gas/config/tc-vax.h (vax_cons, vax_cons_fix_new): Update proto. * gas/config/tc-xstormy16.c (xstormy16_cons_fix_new): Add reloc param. * gas/config/tc-xstormy16.h (xstormy16_cons_fix_new): Update proto. * gas/dwarf2dbg.c (TC_PARSE_CONS_RETURN_NONE): Provide default. (emit_fixed_inc_line_addr): Adjust exmit_expr_fix calls. * gas/read.c (TC_PARSE_CONS_EXPRESSION): Return value. (do_parse_cons_expression): Adjust. (cons_worker): Pass return value from TC_PARSE_CONS_EXPRESSION to emit_expr_with_reloc. (emit_expr_with_reloc): New function handling reloc, mostly extracted from.. (emit_expr): ..here. (emit_expr_fix): Add reloc param. Adjust TC_CONS_FIX_NEW invocation. Handle reloc. (parse_mri_cons): Convert to ISO. * gas/read.h (TC_PARSE_CONS_RETURN_TYPE): Define. (TC_PARSE_CONS_RETURN_NONE): Define. (emit_expr_with_reloc): Declare. (emit_expr_fix): Update prototype. * gas/write.c (write_object_file): Update TC_CONS_FIX_NEW invocation.
2014-04-08 13:08:22 +08:00
#define TC_CONS_FIX_NEW(FRAG, OFF, LEN, EXP, RELOC) \
x86_cons_fix_new(FRAG, OFF, LEN, EXP, RELOC)
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extern void x86_cons_fix_new
gas TC_PARSE_CONS_EXPRESSION communication with TC_CONS_FIX_NEW A number of targets pass extra information from TC_PARSE_CONS_EXPRESSION to TC_CONS_FIX_NEW via static variables. That's OK, but not best practice. tc-ppc.c goes further in implementing its own replacement for cons(), because the generic one doesn't allow relocation modifiers on constants. This patch fixes both of these warts. * gas/config/tc-alpha.h (TC_CONS_FIX_NEW): Add RELOC parameter. * gas/config/tc-arc.c (arc_cons_fix_new): Add reloc parameter. * gas/config/tc-arc.h (arc_cons_fix_new): Update prototype. (TC_CONS_FIX_NEW): Add RELOC parameter. * gas/config/tc-arm.c (cons_fix_new_arm): Similarly * gas/config/tc-arm.h (cons_fix_new_arm, TC_CONS_FIX_NEW): Similarly. * gas/config/tc-cr16.c (cr16_cons_fix_new): Similarly. * gas/config/tc-cr16.h (cr16_cons_fix_new, TC_CONS_FIX_NEW): Similarly. * gas/config/tc-crx.h (TC_CONS_FIX_NEW): Similarly. * gas/config/tc-m32c.c (m32c_cons_fix_new): Similarly. * gas/config/tc-m32c.h (m32c_cons_fix_new, TC_CONS_FIX_NEW): Similarly. * gas/config/tc-mn10300.c (mn10300_cons_fix_new): Similarly. * gas/config/tc-mn10300.h (mn10300_cons_fix_new, TC_CONS_FIX_NEW): Similarly. * gas/config/tc-ns32k.c (cons_fix_new_ns32k): Similarly. * gas/config/tc-ns32k.h (cons_fix_new_ns32k): Similarly. * gas/config/tc-pj.c (pj_cons_fix_new_pj): Similarly. * gas/config/tc-pj.h (pj_cons_fix_new_pj, TC_CONS_FIX_NEW): Similarly. * gas/config/tc-rx.c (rx_cons_fix_new): Similarly. * gas/config/tc-rx.h (rx_cons_fix_new, TC_CONS_FIX_NEW): Similarly. * gas/config/tc-sh.c (sh_cons_fix_new): Similarly. * gas/config/tc-sh.h (sh_cons_fix_new, TC_CONS_FIX_NEW): Similarly. * gas/config/tc-tic54x.c (tic54x_cons_fix_new): Similarly. * gas/config/tc-tic54x.h (tic54x_cons_fix_new, TC_CONS_FIX_NEW): Similarly. * gas/config/tc-tic6x.c (tic6x_cons_fix_new): Similarly. * gas/config/tc-tic6x.h (tic6x_cons_fix_new, TC_CONS_FIX_NEW): Similarly. * gas/config/tc-arc.c (arc_parse_cons_expression): Return reloc. * gas/config/tc-arc.h (arc_parse_cons_expression): Update proto. * gas/config/tc-avr.c (exp_mod_data): Make global. (pexp_mod_data): Delete. (avr_parse_cons_expression): Return exp_mod_data pointer. (avr_cons_fix_new): Add exp_mod_data_t pointer param. (exp_mod_data_t): Move typedef.. * gas/config/tc-avr.h: ..to here. (exp_mod_data): Declare. (TC_PARSE_CONS_RETURN_TYPE, TC_PARSE_CONS_RETURN_NONE): Define. (avr_parse_cons_expression, avr_cons_fix_new): Update prototype. (TC_CONS_FIX_NEW): Update. * gas/config/tc-hppa.c (hppa_field_selector): Delete static var. (cons_fix_new_hppa): Add hppa_field_selector param. (fix_new_hppa): Adjust. (parse_cons_expression_hppa): Return field selector. * gas/config/tc-hppa.h (parse_cons_expression_hppa): Update proto. (cons_fix_new_hppa): Likewise. (TC_PARSE_CONS_RETURN_TYPE, TC_PARSE_CONS_RETURN_NONE): Define. * gas/config/tc-i386.c (got_reloc): Delete static var. (x86_cons_fix_new): Add reloc param. (x86_cons): Return got reloc. * gas/config/tc-i386.h (x86_cons, x86_cons_fix_new): Update proto. (TC_CONS_FIX_NEW): Add RELOC param. * gas/config/tc-ia64.c (ia64_cons_fix_new): Add reloc param. Adjust calls. * gas/config/tc-ia64.h (ia64_cons_fix_new): Update prototype. (TC_CONS_FIX_NEW): Add reloc param. * gas/config/tc-microblaze.c (parse_cons_expression_microblaze): Return reloc. (cons_fix_new_microblaze): Add reloc param. * gas/config/tc-microblaze.h: Formatting. (parse_cons_expression_microblaze): Update proto. (cons_fix_new_microblaze): Likewise. * gas/config/tc-nios2.c (nios2_tls_ldo_reloc): Delete static var. (nios2_cons): Return ldo reloc. (nios2_cons_fix_new): Delete. * gas/config/tc-nios2.h (nios2_cons): Update prototype. (nios2_cons_fix_new, TC_CONS_FIX_NEW): Delete. * gas/config/tc-ppc.c (md_pseudo_table): Remove quad, long, word, short. Make llong use cons. (ppc_elf_suffix): Return BFD_RELOC_NONE rather than BFD_RELOC_UNUSED. (ppc_elf_cons): Delete. (ppc_elf_parse_cons): New function. (ppc_elf_validate_fix): Don't check for BFD_RELOC_UNUSED. (md_assemble): Use BFD_RELOC_NONE rather than BFD_RELOC_UNUSED. * gas/config/tc-ppc.h (TC_PARSE_CONS_EXPRESSION): Define (ppc_elf_parse_cons): Declare. * gas/config/tc-sparc.c (sparc_cons_special_reloc): Delete static var. (sparc_cons): Return reloc specifier. (cons_fix_new_sparc): Add reloc specifier param. (sparc_cfi_emit_pcrel_expr): Use emit_expr_with_reloc. * gas/config/tc-sparc.h (TC_PARSE_CONS_RETURN_TYPE): Define. (TC_PARSE_CONS_RETURN_NONE): Define. (sparc_cons, cons_fix_new_sparc): Update prototype. * gas/config/tc-v850.c (hold_cons_reloc): Delete static var. (v850_reloc_prefix): Use BFD_RELOC_NONE rather than BFD_RELOC_UNUSED. (md_assemble): Likewise. (parse_cons_expression_v850): Return reloc. (cons_fix_new_v850): Add reloc parameter. * gas/config/tc-v850.h (parse_cons_expression_v850): Update proto. (cons_fix_new_v850): Likewise. * gas/config/tc-vax.c (vax_cons_special_reloc): Delete static var. (vax_cons): Return reloc. (vax_cons_fix_new): Add reloc parameter. * gas/config/tc-vax.h (vax_cons, vax_cons_fix_new): Update proto. * gas/config/tc-xstormy16.c (xstormy16_cons_fix_new): Add reloc param. * gas/config/tc-xstormy16.h (xstormy16_cons_fix_new): Update proto. * gas/dwarf2dbg.c (TC_PARSE_CONS_RETURN_NONE): Provide default. (emit_fixed_inc_line_addr): Adjust exmit_expr_fix calls. * gas/read.c (TC_PARSE_CONS_EXPRESSION): Return value. (do_parse_cons_expression): Adjust. (cons_worker): Pass return value from TC_PARSE_CONS_EXPRESSION to emit_expr_with_reloc. (emit_expr_with_reloc): New function handling reloc, mostly extracted from.. (emit_expr): ..here. (emit_expr_fix): Add reloc param. Adjust TC_CONS_FIX_NEW invocation. Handle reloc. (parse_mri_cons): Convert to ISO. * gas/read.h (TC_PARSE_CONS_RETURN_TYPE): Define. (TC_PARSE_CONS_RETURN_NONE): Define. (emit_expr_with_reloc): Declare. (emit_expr_fix): Update prototype. * gas/write.c (write_object_file): Update TC_CONS_FIX_NEW invocation.
2014-04-08 13:08:22 +08:00
(fragS *, unsigned int, unsigned int, expressionS *, bfd_reloc_code_real_type);
2002-08-09 20:37:41 +08:00
#define X_PRECISION 5
#define X_PRECISION_PAD 0
#define TC_ADDRESS_BYTES x86_address_bytes
extern int x86_address_bytes (void);
2002-08-09 20:37:41 +08:00
#define DIFF_EXPR_OK /* foo-. gets turned into PC relative relocs */
#define NO_RELOC BFD_RELOC_NONE
int i386_validate_fix (struct fix *);
#define TC_VALIDATE_FIX(FIX,SEGTYPE,SKIP) do { \
if (!i386_validate_fix(FIX)) goto SKIP; \
} while (0)
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#ifdef OBJ_ELF
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#define tc_fix_adjustable(X) tc_i386_fix_adjustable(X)
extern int tc_i386_fix_adjustable (struct fix *);
#else
#define tc_fix_adjustable(X) ((void)(X), 1)
#endif
2002-08-09 20:37:41 +08:00
gas: * cgen.c, cgen.h, tc.h, write.c, config/obj-coff.c * config/tc-a29k.c, config/tc-alpha.c, config/tc-alpha.h * config/tc-arc.c, config/tc-arc.h, config/tc-arm.c * config/tc-arm.h, config/tc-avr.c, config/tc-avr.h * config/tc-cris.c, config/tc-crx.c, config/tc-d10v.c * config/tc-d10v.h, config/tc-d30v.c, config/tc-d30v.h * config/tc-dlx.c, config/tc-dlx.h, config/tc-fr30.h * config/tc-frv.c, config/tc-frv.h, config/tc-h8300.c * config/tc-h8500.c, config/tc-hppa.c, config/tc-hppa.h * config/tc-i370.c, config/tc-i370.h, config/tc-i386.c * config/tc-i386.h, config/tc-i860.c, config/tc-i860.h * config/tc-i960.c, config/tc-i960.h, config/tc-ia64.c * config/tc-ip2k.c, config/tc-ip2k.h, config/tc-iq2000.c * config/tc-iq2000.h, config/tc-m32r.c, config/tc-m32r.h * config/tc-m68hc11.c, config/tc-m68hc11.h, config/tc-m68k.c * config/tc-m68k.h, config/tc-m88k.c, config/tc-maxq.c * config/tc-mcore.c, config/tc-mcore.h, config/tc-mips.c * config/tc-mips.h, config/tc-mmix.c, config/tc-mn10200.c * config/tc-mn10300.c, config/tc-msp430.c, config/tc-ns32k.c * config/tc-openrisc.h, config/tc-or32.c, config/tc-or32.h * config/tc-pdp11.c, config/tc-pj.c, config/tc-pj.h * config/tc-ppc.c, config/tc-ppc.h, config/tc-s390.c * config/tc-s390.h, config/tc-sh64.c, config/tc-sh.c * config/tc-sh.h, config/tc-sparc.c, config/tc-sparc.h * config/tc-tahoe.c, config/tc-tic30.c, config/tc-tic4x.c * config/tc-tic54x.c, config/tc-tic80.c, config/tc-v850.c * config/tc-v850.h, config/tc-vax.c, config/tc-vax.h * config/tc-w65.c, config/tc-xstormy16.c, config/tc-xstormy16.h * config/tc-xtensa.c, config/tc-z8k.c: Replace all instances of the string "_apply_fix3" with "_apply_fix". * po/POTFILES.in, po/gas.pot: Regenerate. bfd: * coff-i386.c: Change md_apply_fix3 to md_apply_fix in comment. cgen: * doc/porting.texi: Change all mention of md_apply_fix3 and gas_cgen_md_apply_fix3 to md_apply_fix and gas_cgen_md_apply_fix respectively.
2005-06-08 01:54:22 +08:00
/* Values passed to md_apply_fix don't include the symbol value. */
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#define MD_APPLY_SYM_VALUE(FIX) 0
/* ELF wants external syms kept, as does PE COFF. */
* symbols.c (S_FORCE_RELOC): Add "strict" param. * symbols.h (S_FORCE_RELOC): Likewise. * config/obj-aout.h (S_FORCE_RELOC): Likewise. * config/obj-bout.h (S_FORCE_RELOC): Likewise. * config/obj-coff.h (S_FORCE_RELOC): Likewise. * config/obj-ieee.h (S_FORCE_RELOC): Likewise. * config/obj-vms.h (S_FORCE_RELOC): Likewise. * write.c (generic_force_reloc): New function. (TC_FORCE_RELOCATION): Use it here instead of S_FORCE_RELOC. (TC_FORCE_RELOCATION_SUB_SAME): Test TC_FORCE_RELOCATION too. (adjust_reloc_syms): Adjust S_FORCE_RELOC call. * as.h (generic_force_reloc): Declare. * doc/internals.texi (S_FORCE_RELOC): Update. (TC_FORCE_RELOCATION_SUB_SAME): Update. * config/tc-alpha.c (alpha_force_relocation): Adjust to use generic_force_reloc. (alpha_fix_adjustable): Likewise. * config/tc-arm.c (arm_force_relocation): Likewise. * config/tc-cris.c (md_cris_force_relocation): Likewise. * config/tc-frv.c (frv_force_relocation): Likewise. * config/tc-i386.c (md_apply_fix3): Likewise. * config/tc-ia64.c (ia64_force_relocation): Likewise. * config/tc-ip2k.c (ip2k_force_relocation): Likewise. * config/tc-m32r.c (m32r_force_relocation): Likewise. * config/tc-m68hc11.c (tc_m68hc11_force_relocation): Likewise. * config/tc-mcore.c (mcore_force_relocation): Likewise. * config/tc-mips.c (mips_force_relocation): Likewise. * config/tc-mmix.c (mmix_force_relocation): Likewise. * config/tc-ppc.c (ppc_force_relocation): Likewise. * config/tc-s390.c (tc_s390_force_relocation): Likewise. * config/tc-sh.c (sh_force_relocation): Likewise. (md_pcrel_from_section): Likewise. * config/tc-sparc.c (tc_gen_reloc): Likewise. * config/tc-v850.c (v850_force_relocation): Likewise. * config/tc-xstormy16.c (xstormy16_force_relocation): Likewise. * config/tc-i386.h (TC_FORCE_RELOCATION): Likewise. * config/tc-mcore.h (TC_FORCE_RELOCATION): Likewise. * config/tc-sparc.h (tc_fix_adjustable): Likewise. * config/tc-d10v.c (d10v_force_relocation): Delete. * config/tc-d10v.h (TC_FORCE_RELOCATION): Don't define. * config/tc-dlx.c (md_dlx_force_relocation): Delete. * config/tc-dlx.h (TC_FORCE_RELOCATION): Don't define. * config/tc-fr30.c (fr30_force_relocation): Delete. * config/tc-fr30.h (TC_FORCE_RELOCATION): Don't define. * config/tc-mn10300.c (mn10300_force_relocation): Delete. * config/tc-mn10300.h (TC_FORCE_RELOCATION): Don't define. (TC_FORCE_RELOCATION_SUB_SAME): Test TC_FORCE_RELOCATION too. * config/tc-i960.h (TC_FORCE_RELOCATION_SUB_SAME): Likewise. * config/tc-hppa.c (hppa_force_relocation): Adjust S_FORCE_RELOC call. * config/tc-mips.c (RELAX_BRANCH_TOOFAR): Warning fix. * config/tc-mips.h (TC_FORCE_RELOCATION_SUB_SAME): Don't define. * config/tc-openrisc.c (openrisc_force_relocation): Delete. * config/tc-openrisc.h (TC_FORCE_RELOCATION): Don't define. * config/tc-sparc.c (elf32_sparc_force_relocation): Delete. * config/tc-sparc.h (TC_FORCE_RELOCATION): Don't define for ELF. * config/tc-i386.c (i386_force_relocation): Delete. * config/tc-i386.h (TC_FORCE_RELOCATION): Don't define for BFD_ASSEMBLER. (EXTERN_FORCE_RELOC): Fix TE_PE and STRICT_PE_FORMAT nesting. * config/tc-m68k.h (TC_FORCE_RELOCATION): Don't define. * config/tc-pj.h (TC_FORCE_RELOCATION): Don't define. * config/tc-sh.h (TC_FORCE_RELOCATION_SUB_ABS): Don't call S_FORCE_RELOC. (TC_FORCE_RELOCATION_SUB_SAME): Test TC_FORCE_RELOCATION too. * config/tc-sh64.h (TC_FORCE_RELOCATION_SUB_SAME): Likewise.
2003-01-23 20:51:05 +08:00
#if defined (TE_PE) && defined (STRICT_PE_FORMAT)
#define EXTERN_FORCE_RELOC \
(IS_ELF || OUTPUT_FLAVOR == bfd_target_coff_flavour)
#else
#define EXTERN_FORCE_RELOC IS_ELF
1999-05-03 15:29:11 +08:00
#endif
2002-09-05 08:01:18 +08:00
/* This expression evaluates to true if the relocation is for a local
object for which we still want to do the relocation at runtime.
False if we are willing to perform this relocation while building
the .o file. GOTOFF and GOT32 do not need to be checked here because
they are not pcrel. .*/
2002-08-09 20:37:41 +08:00
Add R_X86_64_[REX_]GOTPCRELX support to gas and ld This patch adds support for the R_X86_64_GOTPCRELX and R_X86_64_REX_GOTPCRELX relocations proposed in https://groups.google.com/forum/#!topic/x86-64-abi/n9AWHogmVY0 to gas and ld. It updates gas to generate R_X86_64_GOTPCRELX, R_X86_64_REX_GOTPCRELX if there is a REX prefix, relocation for memory operand, foo@GOTPCREL(%rip). With the locally defined symbol, foo, we convert mov foo@GOTPCREL(%rip), %reg to lea foo(%rip), %reg and convert call/jmp *foo@GOTPCREL(%rip) to nop call foo/jmp foo nop When PIC is false, convert test %reg, foo@GOTPCREL(%rip) to test $foo, %reg and convert binop foo@GOTPCREL(%rip), %reg to binop $foo, %reg where binop is one of adc, add, and, cmp, or, sbb, sub, xor instructions. bfd/ * elf64-x86-64.c: Include opcode/i386.h. (x86_64_elf_howto_table): Add R_X86_64_GOTPCRELX and R_X86_64_REX_GOTPCRELX. (R_X86_64_standard): Replace R_X86_64_PLT32_BND with R_X86_64_REX_GOTPCRELX. (x86_64_reloc_map): Add BFD_RELOC_X86_64_GOTPCRELX and BFD_RELOC_X86_64_REX_GOTPCRELX. (need_convert_mov_to_lea): Renamed to ... (need_convert_load): This. (elf_x86_64_check_relocs): Handle R_X86_64_GOTPCRELX and R_X86_64_REX_GOTPCRELX. Replace need_convert_mov_to_lea with need_convert_load. (elf_x86_64_gc_sweep_hook): Handle R_X86_64_GOTPCRELX and R_X86_64_REX_GOTPCRELX. (elf_x86_64_size_dynamic_sections): Likewise. (elf_x86_64_relocate_section): Likewise. (elf_x86_64_convert_mov_to_lea): Renamed to ... (elf_x86_64_convert_load): This. Replace need_convert_mov_to_lea with need_convert_load. Support R_X86_64_GOTPCRELX and R_X86_64_REX_GOTPCRELX transformations. * reloc.c (BFD_RELOC_X86_64_GOTPCRELX): New. (BFD_RELOC_X86_64_REX_GOTPCRELX): Likewise. * bfd-in2.h: Regenerated. * libbfd.h: Likewise. gas/ * config/tc-i386.c (tc_i386_fix_adjustable): Handle BFD_RELOC_X86_64_GOTPCRELX and BFD_RELOC_X86_64_REX_GOTPCRELX. (tc_gen_reloc): Likewise. (i386_validate_fix): Generate BFD_RELOC_X86_64_GOTPCRELX or BFD_RELOC_X86_64_REX_GOTPCRELX if fx_tcbit2 is set. * config/tc-i386.h (TC_FORCE_RELOCATION_LOCAL): Also return true for BFD_RELOC_X86_64_GOTPCRELX and BFD_RELOC_X86_64_REX_GOTPCRELX. gas/testsuite/ * gas/i386/i386.exp: Run x86-64-gotpcrel. * gas/i386/x86-64-gotpcrel.d: New file. * gas/i386/x86-64-gotpcrel.s: Likewise. * gas/i386/ilp32/x86-64-gotpcrel.d: Likewise. * gas/i386/x86-64-localpic.d: Replace R_X86_64_GOTPCREL with R_X86_64_REX_GOTPCRELX. * gas/i386/ilp32/x86-64-localpic.d: Likewise. include/elf/ * x86-64.h (R_X86_64_GOTPCRELX): New. (R_X86_64_REX_GOTPCRELX): Likewise. ld/testsuite/ * ld-ifunc/ifunc-5r-local-x86-64.d: Replace R_X86_64_GOTPCREL with R_X86_64_REX_GOTPCRELX. * ld-x86-64/plt-main1.rd: Likewise. * ld-x86-64/plt-main3.rd: Likewise. * ld-x86-64/plt-main4.rd: Likewise. * ld-x86-64/gotpcrel1.dd: New file. * ld-x86-64/gotpcrel1.out: Likewise. * ld-x86-64/gotpcrel1a.S: Likewise. * ld-x86-64/gotpcrel1b.c: Likewise. * ld-x86-64/gotpcrel1c.c: Likewise. * ld-x86-64/gotpcrel1d.S: Likewise. * ld-x86-64/load1.s: Likewise. * ld-x86-64/load1a.d: Likewise. * ld-x86-64/load1b.d: Likewise. * ld-x86-64/load1c.d: Likewise. * ld-x86-64/load1d.d: Likewise. * ld-x86-64/x86-64.exp: Run load1a, load1b, load1c and load1d tests. Run gotpcrel1 test.
2015-10-22 19:49:20 +08:00
#define TC_FORCE_RELOCATION_LOCAL(FIX) \
(GENERIC_FORCE_RELOCATION_LOCAL (FIX) \
Add R_X86_64_[REX_]GOTPCRELX support to gas and ld This patch adds support for the R_X86_64_GOTPCRELX and R_X86_64_REX_GOTPCRELX relocations proposed in https://groups.google.com/forum/#!topic/x86-64-abi/n9AWHogmVY0 to gas and ld. It updates gas to generate R_X86_64_GOTPCRELX, R_X86_64_REX_GOTPCRELX if there is a REX prefix, relocation for memory operand, foo@GOTPCREL(%rip). With the locally defined symbol, foo, we convert mov foo@GOTPCREL(%rip), %reg to lea foo(%rip), %reg and convert call/jmp *foo@GOTPCREL(%rip) to nop call foo/jmp foo nop When PIC is false, convert test %reg, foo@GOTPCREL(%rip) to test $foo, %reg and convert binop foo@GOTPCREL(%rip), %reg to binop $foo, %reg where binop is one of adc, add, and, cmp, or, sbb, sub, xor instructions. bfd/ * elf64-x86-64.c: Include opcode/i386.h. (x86_64_elf_howto_table): Add R_X86_64_GOTPCRELX and R_X86_64_REX_GOTPCRELX. (R_X86_64_standard): Replace R_X86_64_PLT32_BND with R_X86_64_REX_GOTPCRELX. (x86_64_reloc_map): Add BFD_RELOC_X86_64_GOTPCRELX and BFD_RELOC_X86_64_REX_GOTPCRELX. (need_convert_mov_to_lea): Renamed to ... (need_convert_load): This. (elf_x86_64_check_relocs): Handle R_X86_64_GOTPCRELX and R_X86_64_REX_GOTPCRELX. Replace need_convert_mov_to_lea with need_convert_load. (elf_x86_64_gc_sweep_hook): Handle R_X86_64_GOTPCRELX and R_X86_64_REX_GOTPCRELX. (elf_x86_64_size_dynamic_sections): Likewise. (elf_x86_64_relocate_section): Likewise. (elf_x86_64_convert_mov_to_lea): Renamed to ... (elf_x86_64_convert_load): This. Replace need_convert_mov_to_lea with need_convert_load. Support R_X86_64_GOTPCRELX and R_X86_64_REX_GOTPCRELX transformations. * reloc.c (BFD_RELOC_X86_64_GOTPCRELX): New. (BFD_RELOC_X86_64_REX_GOTPCRELX): Likewise. * bfd-in2.h: Regenerated. * libbfd.h: Likewise. gas/ * config/tc-i386.c (tc_i386_fix_adjustable): Handle BFD_RELOC_X86_64_GOTPCRELX and BFD_RELOC_X86_64_REX_GOTPCRELX. (tc_gen_reloc): Likewise. (i386_validate_fix): Generate BFD_RELOC_X86_64_GOTPCRELX or BFD_RELOC_X86_64_REX_GOTPCRELX if fx_tcbit2 is set. * config/tc-i386.h (TC_FORCE_RELOCATION_LOCAL): Also return true for BFD_RELOC_X86_64_GOTPCRELX and BFD_RELOC_X86_64_REX_GOTPCRELX. gas/testsuite/ * gas/i386/i386.exp: Run x86-64-gotpcrel. * gas/i386/x86-64-gotpcrel.d: New file. * gas/i386/x86-64-gotpcrel.s: Likewise. * gas/i386/ilp32/x86-64-gotpcrel.d: Likewise. * gas/i386/x86-64-localpic.d: Replace R_X86_64_GOTPCREL with R_X86_64_REX_GOTPCRELX. * gas/i386/ilp32/x86-64-localpic.d: Likewise. include/elf/ * x86-64.h (R_X86_64_GOTPCRELX): New. (R_X86_64_REX_GOTPCRELX): Likewise. ld/testsuite/ * ld-ifunc/ifunc-5r-local-x86-64.d: Replace R_X86_64_GOTPCREL with R_X86_64_REX_GOTPCRELX. * ld-x86-64/plt-main1.rd: Likewise. * ld-x86-64/plt-main3.rd: Likewise. * ld-x86-64/plt-main4.rd: Likewise. * ld-x86-64/gotpcrel1.dd: New file. * ld-x86-64/gotpcrel1.out: Likewise. * ld-x86-64/gotpcrel1a.S: Likewise. * ld-x86-64/gotpcrel1b.c: Likewise. * ld-x86-64/gotpcrel1c.c: Likewise. * ld-x86-64/gotpcrel1d.S: Likewise. * ld-x86-64/load1.s: Likewise. * ld-x86-64/load1a.d: Likewise. * ld-x86-64/load1b.d: Likewise. * ld-x86-64/load1c.d: Likewise. * ld-x86-64/load1d.d: Likewise. * ld-x86-64/x86-64.exp: Run load1a, load1b, load1c and load1d tests. Run gotpcrel1 test.
2015-10-22 19:49:20 +08:00
|| (FIX)->fx_r_type == BFD_RELOC_386_PLT32 \
|| (FIX)->fx_r_type == BFD_RELOC_386_GOTPC \
|| (FIX)->fx_r_type == BFD_RELOC_X86_64_GOTPCREL \
Add R_X86_64_[REX_]GOTPCRELX support to gas and ld This patch adds support for the R_X86_64_GOTPCRELX and R_X86_64_REX_GOTPCRELX relocations proposed in https://groups.google.com/forum/#!topic/x86-64-abi/n9AWHogmVY0 to gas and ld. It updates gas to generate R_X86_64_GOTPCRELX, R_X86_64_REX_GOTPCRELX if there is a REX prefix, relocation for memory operand, foo@GOTPCREL(%rip). With the locally defined symbol, foo, we convert mov foo@GOTPCREL(%rip), %reg to lea foo(%rip), %reg and convert call/jmp *foo@GOTPCREL(%rip) to nop call foo/jmp foo nop When PIC is false, convert test %reg, foo@GOTPCREL(%rip) to test $foo, %reg and convert binop foo@GOTPCREL(%rip), %reg to binop $foo, %reg where binop is one of adc, add, and, cmp, or, sbb, sub, xor instructions. bfd/ * elf64-x86-64.c: Include opcode/i386.h. (x86_64_elf_howto_table): Add R_X86_64_GOTPCRELX and R_X86_64_REX_GOTPCRELX. (R_X86_64_standard): Replace R_X86_64_PLT32_BND with R_X86_64_REX_GOTPCRELX. (x86_64_reloc_map): Add BFD_RELOC_X86_64_GOTPCRELX and BFD_RELOC_X86_64_REX_GOTPCRELX. (need_convert_mov_to_lea): Renamed to ... (need_convert_load): This. (elf_x86_64_check_relocs): Handle R_X86_64_GOTPCRELX and R_X86_64_REX_GOTPCRELX. Replace need_convert_mov_to_lea with need_convert_load. (elf_x86_64_gc_sweep_hook): Handle R_X86_64_GOTPCRELX and R_X86_64_REX_GOTPCRELX. (elf_x86_64_size_dynamic_sections): Likewise. (elf_x86_64_relocate_section): Likewise. (elf_x86_64_convert_mov_to_lea): Renamed to ... (elf_x86_64_convert_load): This. Replace need_convert_mov_to_lea with need_convert_load. Support R_X86_64_GOTPCRELX and R_X86_64_REX_GOTPCRELX transformations. * reloc.c (BFD_RELOC_X86_64_GOTPCRELX): New. (BFD_RELOC_X86_64_REX_GOTPCRELX): Likewise. * bfd-in2.h: Regenerated. * libbfd.h: Likewise. gas/ * config/tc-i386.c (tc_i386_fix_adjustable): Handle BFD_RELOC_X86_64_GOTPCRELX and BFD_RELOC_X86_64_REX_GOTPCRELX. (tc_gen_reloc): Likewise. (i386_validate_fix): Generate BFD_RELOC_X86_64_GOTPCRELX or BFD_RELOC_X86_64_REX_GOTPCRELX if fx_tcbit2 is set. * config/tc-i386.h (TC_FORCE_RELOCATION_LOCAL): Also return true for BFD_RELOC_X86_64_GOTPCRELX and BFD_RELOC_X86_64_REX_GOTPCRELX. gas/testsuite/ * gas/i386/i386.exp: Run x86-64-gotpcrel. * gas/i386/x86-64-gotpcrel.d: New file. * gas/i386/x86-64-gotpcrel.s: Likewise. * gas/i386/ilp32/x86-64-gotpcrel.d: Likewise. * gas/i386/x86-64-localpic.d: Replace R_X86_64_GOTPCREL with R_X86_64_REX_GOTPCRELX. * gas/i386/ilp32/x86-64-localpic.d: Likewise. include/elf/ * x86-64.h (R_X86_64_GOTPCRELX): New. (R_X86_64_REX_GOTPCRELX): Likewise. ld/testsuite/ * ld-ifunc/ifunc-5r-local-x86-64.d: Replace R_X86_64_GOTPCREL with R_X86_64_REX_GOTPCRELX. * ld-x86-64/plt-main1.rd: Likewise. * ld-x86-64/plt-main3.rd: Likewise. * ld-x86-64/plt-main4.rd: Likewise. * ld-x86-64/gotpcrel1.dd: New file. * ld-x86-64/gotpcrel1.out: Likewise. * ld-x86-64/gotpcrel1a.S: Likewise. * ld-x86-64/gotpcrel1b.c: Likewise. * ld-x86-64/gotpcrel1c.c: Likewise. * ld-x86-64/gotpcrel1d.S: Likewise. * ld-x86-64/load1.s: Likewise. * ld-x86-64/load1a.d: Likewise. * ld-x86-64/load1b.d: Likewise. * ld-x86-64/load1c.d: Likewise. * ld-x86-64/load1d.d: Likewise. * ld-x86-64/x86-64.exp: Run load1a, load1b, load1c and load1d tests. Run gotpcrel1 test.
2015-10-22 19:49:20 +08:00
|| (FIX)->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX \
x86-64: Add R_X86_64_CODE_4_GOTPCRELX For mov name@GOTPCREL(%rip), %reg test %reg, name@GOTPCREL(%rip) binop name@GOTPCREL(%rip), %reg where binop is one of adc, add, add, cmp, or, sbb, sub, xor instructions, add # define R_X86_64_CODE_4_GOTPCRELX 43 if the instruction starts at 4 bytes before the relocation offset. It similar to R_X86_64_GOTPCRELX. Linker can treat R_X86_64_CODE_4_GOTPCRELX as R_X86_64_GOTPCREL or convert the above instructions to lea name(%rip), %reg mov $name, %reg test $name, %reg binop $name, %reg if the instruction is encoded with the REX2 prefix when possible. bfd/ * elf64-x86-64.c (x86_64_elf_howto_table): Add R_X86_64_CODE_4_GOTPCRELX. (R_X86_64_standard): Updated. (x86_64_reloc_map): Add BFD_RELOC_X86_64_CODE_4_GOTPCRELX. (elf_x86_64_convert_load_reloc): Handle R_X86_64_CODE_4_GOTPCRELX. (elf_x86_64_scan_relocs): Likewise. (elf_x86_64_relocate_section): Likewise. * reloc.c (bfd_reloc_code_real): Add BFD_RELOC_X86_64_CODE_4_GOTPCRELX. * bfd-in2.h: Regenerated. * libbfd.h: Likewise. gas/ * write.h (fix): Add fx_tcbit3. Change fx_unused to 1 bit. * config/tc-i386.c (tc_i386_fix_adjustable): Handle BFD_RELOC_X86_64_CODE_4_GOTPCRELX. (tc_gen_reloc): Likewise. (output_disp): Set fixP->fx_tcbit3 for REX2 prefix. (i386_validate_fix): Generate BFD_RELOC_X86_64_CODE_4_GOTPCRELX if fixp->fx_tcbit3 is set. * config/tc-i386.h (TC_FORCE_RELOCATION_LOCAL): Add BFD_RELOC_X86_64_CODE_4_GOTPCRELX. (TC_FORCE_RELOCATION_ABS): Likewise. * testsuite/gas/i386/x86-64-gotpcrel.s: Add tests for R_X86_64_CODE_4_GOTPCRELX. * testsuite/gas/i386/x86-64-localpic.s: Likewise. * testsuite/gas/i386/x86-64-gotpcrel.d: Updated. * testsuite/gas/i386/x86-64-localpic.d: Likewise. * testsuite/gas/i386/ilp32/x86-64-localpic.d: Likewise. include/ * elf/x86-64.h (elf_x86_64_reloc_type): Add R_X86_64_CODE_4_GOTPCRELX. ld/ * testsuite/ld-x86-64/apx-load1.s: New file. * testsuite/ld-x86-64/apx-load1a.d: Likewise. * testsuite/ld-x86-64/apx-load1b.d: Likewise. * testsuite/ld-x86-64/apx-load1c.d: Likewise. * testsuite/ld-x86-64/apx-load1d.d: Likewise. * testsuite/ld-x86-64/x86-64.exp: Run apx-load1a, apx-load1b, apx-load1c and apx-load1d.
2023-06-09 01:01:03 +08:00
|| (FIX)->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX \
|| (FIX)->fx_r_type == BFD_RELOC_X86_64_CODE_4_GOTPCRELX)
2002-08-09 20:37:41 +08:00
#define TC_FORCE_RELOCATION_ABS(FIX) \
(TC_FORCE_RELOCATION (FIX) \
|| (FIX)->fx_r_type == BFD_RELOC_386_GOT32 \
|| (FIX)->fx_r_type == BFD_RELOC_386_GOT32X \
|| (FIX)->fx_r_type == BFD_RELOC_X86_64_GOTPCREL \
|| (FIX)->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX \
x86-64: Add R_X86_64_CODE_4_GOTPCRELX For mov name@GOTPCREL(%rip), %reg test %reg, name@GOTPCREL(%rip) binop name@GOTPCREL(%rip), %reg where binop is one of adc, add, add, cmp, or, sbb, sub, xor instructions, add # define R_X86_64_CODE_4_GOTPCRELX 43 if the instruction starts at 4 bytes before the relocation offset. It similar to R_X86_64_GOTPCRELX. Linker can treat R_X86_64_CODE_4_GOTPCRELX as R_X86_64_GOTPCREL or convert the above instructions to lea name(%rip), %reg mov $name, %reg test $name, %reg binop $name, %reg if the instruction is encoded with the REX2 prefix when possible. bfd/ * elf64-x86-64.c (x86_64_elf_howto_table): Add R_X86_64_CODE_4_GOTPCRELX. (R_X86_64_standard): Updated. (x86_64_reloc_map): Add BFD_RELOC_X86_64_CODE_4_GOTPCRELX. (elf_x86_64_convert_load_reloc): Handle R_X86_64_CODE_4_GOTPCRELX. (elf_x86_64_scan_relocs): Likewise. (elf_x86_64_relocate_section): Likewise. * reloc.c (bfd_reloc_code_real): Add BFD_RELOC_X86_64_CODE_4_GOTPCRELX. * bfd-in2.h: Regenerated. * libbfd.h: Likewise. gas/ * write.h (fix): Add fx_tcbit3. Change fx_unused to 1 bit. * config/tc-i386.c (tc_i386_fix_adjustable): Handle BFD_RELOC_X86_64_CODE_4_GOTPCRELX. (tc_gen_reloc): Likewise. (output_disp): Set fixP->fx_tcbit3 for REX2 prefix. (i386_validate_fix): Generate BFD_RELOC_X86_64_CODE_4_GOTPCRELX if fixp->fx_tcbit3 is set. * config/tc-i386.h (TC_FORCE_RELOCATION_LOCAL): Add BFD_RELOC_X86_64_CODE_4_GOTPCRELX. (TC_FORCE_RELOCATION_ABS): Likewise. * testsuite/gas/i386/x86-64-gotpcrel.s: Add tests for R_X86_64_CODE_4_GOTPCRELX. * testsuite/gas/i386/x86-64-localpic.s: Likewise. * testsuite/gas/i386/x86-64-gotpcrel.d: Updated. * testsuite/gas/i386/x86-64-localpic.d: Likewise. * testsuite/gas/i386/ilp32/x86-64-localpic.d: Likewise. include/ * elf/x86-64.h (elf_x86_64_reloc_type): Add R_X86_64_CODE_4_GOTPCRELX. ld/ * testsuite/ld-x86-64/apx-load1.s: New file. * testsuite/ld-x86-64/apx-load1a.d: Likewise. * testsuite/ld-x86-64/apx-load1b.d: Likewise. * testsuite/ld-x86-64/apx-load1c.d: Likewise. * testsuite/ld-x86-64/apx-load1d.d: Likewise. * testsuite/ld-x86-64/x86-64.exp: Run apx-load1a, apx-load1b, apx-load1c and apx-load1d.
2023-06-09 01:01:03 +08:00
|| (FIX)->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX \
|| (FIX)->fx_r_type == BFD_RELOC_X86_64_CODE_4_GOTPCRELX)
extern void i386_start_line (void);
#define md_start_line_hook i386_start_line
extern bool i386_check_label (void);
#define TC_START_LABEL(STR, NUL_CHAR, NEXT_CHAR) \
(NEXT_CHAR == ':' && i386_check_label ())
extern int i386_unrecognized_line (int);
#define tc_unrecognized_line i386_unrecognized_line
extern int i386_parse_name (char *, expressionS *, char *);
#define md_parse_name(s, e, m, c) i386_parse_name (s, e, c)
1999-05-03 15:29:11 +08:00
gas/ 2009-04-20 Jan Beulich <jbeulich@novell.com> * Makefile.am: Add explicit dependency of tc-i386.o on tc-i386-intel.c. * Makefile.in: Likewise. * config/tc-i386.c (i386_finalize_immediate): Declare, broken out from i386_immediate. (i386_immediate): Slightly re-arrange, call i386_finalize_immediate. (i386_finalize_displacement): Declare, broken out from i386_displacement. (i386_displacement): Slightly re-arrange, call i386_finalize_displacement. (i386_intel_simplify, i386_intel_parse_name): Declare. (this_operand): Initialize to -1. (set_intel_syntax): Set expression rank for O_full_ptr. (md_assemble): Set this_operand back to -1 after parsing operands. (x86_cons): Negate intel_syntax to indicate state. Call i386_intel_simplify. (md_operand): Convert if to switch. Handle '[' for Intel syntax. (i386_intel_operand): Delete, including all helper functions and data. * config/tc-i386-intel.c: New file, all new code. * config/tc-i386.h (i386_operator): Declare. (md_operator): Define to i386_operator. (i386_need_index_operator): Declare. (md_need_index_operator): Define to i386_need_index_operator. (O_full_ptr): Define. gas/testsuite/ 2009-04-20 Jan Beulich <jbeulich@novell.com> * gas/i386/equ.s: Adjust. * gas/i386/equ.d: Remove reference to equ.e. * gas/i386/equ.e: Delete. * gas/i386/intel-expr.s: New. * gas/i386/intel-expr.d: New. * gas/i386/i386.exp: Run new test. * gas/i386/intel.s: Adjust. * gas/i386/intel.e: Remove no longer valid warning messages. * gas/i386/intel16.s: Adjust. * gas/i386/intel16.d: Remove reference to intel16.e. * gas/i386/intel16.e: Delete. * gas/i386/intelbad.s: Add more tests. * gas/i386/intelbad.l: Adjust. * gas/i386/intelok.s: Remove now unneeded equates. Add more tests. * gas/i386/intelok.d: Remove reference to intelok.e. Adjust. * gas/i386/intelok.e: Delete. * gas/i386/x86_64.s: Adjust. * gas/i386/x86_64.d: Remove reference to x86_64.e. * gas/i386/x86_64.e: Delete.
2009-04-20 14:31:50 +08:00
extern operatorT i386_operator (const char *name, unsigned int operands, char *);
#define md_operator i386_operator
extern int i386_need_index_operator (void);
#define md_need_index_operator i386_need_index_operator
#ifdef BFD64
extern bool i386_record_operator
(operatorT, const expressionS *, const expressionS *);
#define md_optimize_expr(l, o, r) i386_record_operator (o, l, r)
#endif
#define md_register_arithmetic 0
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extern const struct relax_type md_relax_table[];
#define TC_GENERIC_RELAX_TABLE md_relax_table
extern int optimize_align_code;
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#define md_do_align(n, fill, len, max, around) \
if ((n) \
&& !need_pass_2 \
&& optimize_align_code \
&& (!(fill) \
|| ((char)*(fill) == (char)0x90 && (len) == 1)) \
&& subseg_text_p (now_seg)) \
1999-05-03 15:29:11 +08:00
{ \
* as.h (rs_align_test): New. * frags.c (NOP_OPCODE): Move default from read.c. (MAX_MEM_FOR_RS_ALIGN_CODE): New default. (frag_align_code): New. * frags.h (frag_align_code): Declare. * read.c (NOP_OPCODE): Remove. (do_align): Use frag_align_code. * write.c (NOP_OPCODE): Remove. (get_recorded_alignment): New. (cvt_frag_to_fill): Handle rs_align_test. (relax_segment): Likewise. (subsegs_finish): Align last subseg in section to the section alignment. Use frag_align_code. * write.h (get_recorded_alignment): Declare. * config/obj-coff.c (size_section): Handle rs_align_test. (fill_section, fixup_mdeps): Likewise. (write_object_file): Use frag_align_code. * config/tc-alpha.c (alpha_align): Use frag_align_code. (alpha_handle_align): New. * config/tc-alpha.h (HANDLE_ALIGN): New. (MAX_MEM_FOR_RS_ALIGN_CODE): New. * config/tc-i386.h (md_do_align): Use frag_align_code. (MAX_MEM_FOR_RS_ALIGN_CODE): New. * config/tc-ia64.c (ia64_md_do_align): Don't do code alignment. (ia64_handle_align): New. * config/tc-ia64.h (HANDLE_ALIGN): New. (MAX_MEM_FOR_RS_ALIGN_CODE): New. * config/tc-m32r.c (m32r_do_align): Remove. (m32r_handle_align): New. (fill_insn): Use frag_align_code. * config/tc-m32r.h (md_do_align): Remove. (HANDLE_ALIGN, MAX_MEM_FOR_RS_ALIGN_CODE): New. * config/tc-m88k.c, config/tc-m88k.h: Similarly. * config/tc-mips.c, config/tc-mips.h: Similarly. * config/tc-sh.c (sh_cons_align): Use rs_align_test. (sh_handle_align): Likewise. Handle rs_align_code. (sh_do_align): Remove. * config/tc-sh.h (md_do_align): Remove. (MAX_MEM_FOR_RS_ALIGN_CODE): New. * config/tc-sparc.c (sparc_cons_align): Use rs_align_test. (sparc_handle_align): Likewise. Handle rs_align_code. * config/tc-sparc.h (md_do_align): Remove. (MAX_MEM_FOR_RS_ALIGN_CODE): New.
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frag_align_code ((n), (max)); \
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goto around; \
}
#define MAX_MEM_FOR_RS_ALIGN_CODE \
(alignment ? ((size_t) 1 << alignment) - 1 : (size_t) 1)
1999-05-03 15:29:11 +08:00
i386: Align branches within a fixed boundary Add 3 command-line options to align branches within a fixed boundary with segment prefixes or NOPs: 1. -malign-branch-boundary=NUM aligns branches within NUM byte boundary. 2. -malign-branch=TYPE[+TYPE...] specifies types of branches to align. The supported branches are: a. Conditional jump. b. Fused conditional jump. c. Unconditional jump. d. Call. e. Ret. f. Indirect jump and call. 3. -malign-branch-prefix-size=NUM aligns branches with NUM segment prefixes per instruction. 3 new rs_machine_dependent frag types are added: 1. BRANCH_PADDING. The variable size frag to insert NOP before branch. 2. BRANCH_PREFIX. The variable size frag to insert segment prefixes to an instruction. The choices of prefixes are: a. Use the existing segment prefix if there is one. b. Use CS segment prefix in 64-bit mode. c. In 32-bit mode, use SS segment prefix with ESP/EBP base register and use DS segment prefix without ESP/EBP base register. 3. FUSED_JCC_PADDING. The variable size frag to insert NOP before fused conditional jump. The new rs_machine_dependent frags aren't inserted if the previous item is a prefix or a constant directive, which may be used to hardcode an instruction, since there is no clear instruction boundary. Segment prefixes and NOP padding are disabled before relaxable TLS relocations and tls_get_addr calls to keep TLS instruction sequence unchanged. md_estimate_size_before_relax() and i386_generic_table_relax_frag() are used to handled BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags. i386_generic_table_relax_frag() grows or shrinks sizes of segment prefix and NOP to align the next branch frag: 1. First try to add segment prefixes to instructions before a branch. 2. If there is no sufficient room to add segment prefixes, NOP will be inserted before a branch. * config/tc-i386.c (_i386_insn): Add has_gotpc_tls_reloc. (tls_get_addr): New. (last_insn): New. (align_branch_power): New. (align_branch_kind): New. (align_branch_bit): New. (align_branch): New. (MAX_FUSED_JCC_PADDING_SIZE): New. (align_branch_prefix_size): New. (BRANCH_PADDING): New. (BRANCH_PREFIX): New. (FUSED_JCC_PADDING): New. (i386_generate_nops): Support BRANCH_PADDING and FUSED_JCC_PADDING. (md_begin): Abort if align_branch_prefix_size < MAX_FUSED_JCC_PADDING_SIZE. (md_assemble): Set last_insn. (maybe_fused_with_jcc_p): New. (add_fused_jcc_padding_frag_p): New. (add_branch_prefix_frag_p): New. (add_branch_padding_frag_p): New. (output_insn): Generate a BRANCH_PADDING, FUSED_JCC_PADDING or BRANCH_PREFIX frag and terminate each frag to align branches. (output_disp): Set i.has_gotpc_tls_reloc to TRUE for GOTPC and relaxable TLS relocations. (output_imm): Likewise. (i386_next_non_empty_frag): New. (i386_next_jcc_frag): New. (i386_classify_machine_dependent_frag): New. (i386_branch_padding_size): New. (i386_generic_table_relax_frag): New. (md_estimate_size_before_relax): Handle COND_JUMP_PADDING, FUSED_JCC_PADDING and COND_JUMP_PREFIX frags. (md_convert_frag): Handle BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags. (OPTION_MALIGN_BRANCH_BOUNDARY): New. (OPTION_MALIGN_BRANCH_PREFIX_SIZE): New. (OPTION_MALIGN_BRANCH): New. (md_longopts): Add -malign-branch-boundary=, -malign-branch-prefix-size= and -malign-branch=. (md_parse_option): Handle -malign-branch-boundary=, -malign-branch-prefix-size= and -malign-branch=. (md_show_usage): Display -malign-branch-boundary=, -malign-branch-prefix-size= and -malign-branch=. (i386_target_format): Set tls_get_addr. (i386_cons_align): New. * config/tc-i386.h (i386_cons_align): New. (md_cons_align): New. (i386_generic_table_relax_frag): New. (md_generic_table_relax_frag): New. (i386_tc_frag_data): Add u, padding_address, length, max_prefix_length, prefix_length, default_prefix, cmp_size, classified and branch_type. (TC_FRAG_INIT): Initialize u, padding_address, length, max_prefix_length, prefix_length, default_prefix, cmp_size, classified and branch_type. * doc/c-i386.texi: Document -malign-branch-boundary=, -malign-branch= and -malign-branch-prefix-size=.
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extern void i386_cons_align (int);
#define md_cons_align(nbytes) i386_cons_align (nbytes)
#ifndef OBJ_AOUT
#define md_section_align(seg, value) ((void)(seg), (value))
#endif
void i386_print_statistics (FILE *);
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#define tc_print_statistics i386_print_statistics
void i386_md_end (void);
#define md_end i386_md_end
gas/ 2012-03-12 Roland McGrath <mcgrathr@google.com> * config/tc-arm.c (arm_frag_max_var): New function. * config/tc-arm.h: Declare it. (md_frag_max_var): New macro. * config/tc-i386.c (i386_frag_max_var): New function. * config/tc-i386.h: Declare it. (md_frag_max_var): New macro. * doc/as.texinfo (Bundle directives): New node. (Pseudo Ops): Add it to the menu. * NEWS: Mention new feature. * read.c [md_frag_max_var] (HANDLE_BUNDLE): New macro. [HANDLE_BUNDLE] (bundle_align_p2): New variable. [HANDLE_BUNDLE] (bundle_lock_frchain, bundle_lock_frag): New variables. [HANDLE_BUNDLE] (start_bundle, pending_bundle_size, finish_bundle): New functions. (assemble_one): New function if [HANDLE_BUNDLE], #define directly to md_assembly if not. (read_a_source_file): Call assemble_one in place of md_assemble. (read_a_source_file) [HANDLE_BUNDLE]: Check for unterminated .bundle_lock at end of processing. [HANDLE_BUNDLE] (s_bundle_align_mode, s_bundle_lock, s_bundle_unlock): New functions. [HANDLE_BUNDLE] (potable): Add their entries. * read.h: Declare new functions. gas/testsuite/ 2012-03-12 Roland McGrath <mcgrathr@google.com> * gas/i386/bundle-bad.s: New file. * gas/i386/bundle-bad.d: New file. * gas/i386/bundle-bad.l: New file. * gas/i386/i386.exp: Run it. * gas/arm/bundle.s: New file. * gas/arm/bundle.d: New file. * gas/arm/bundle-lock.s: New file. * gas/arm/bundle-lock.d: New file. * gas/i386/bundle.s: New file. * gas/i386/bundle.d: New file. * gas/i386/x86-64-bundle.s: New file. * gas/i386/x86-64-bundle.d: New file. * gas/i386/bundle-lock.s: New file. * gas/i386/bundle-lock.d: New file. * gas/i386/i386.exp: Run them.
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extern unsigned int i386_frag_max_var (fragS *);
#define md_frag_max_var i386_frag_max_var
i386: Align branches within a fixed boundary Add 3 command-line options to align branches within a fixed boundary with segment prefixes or NOPs: 1. -malign-branch-boundary=NUM aligns branches within NUM byte boundary. 2. -malign-branch=TYPE[+TYPE...] specifies types of branches to align. The supported branches are: a. Conditional jump. b. Fused conditional jump. c. Unconditional jump. d. Call. e. Ret. f. Indirect jump and call. 3. -malign-branch-prefix-size=NUM aligns branches with NUM segment prefixes per instruction. 3 new rs_machine_dependent frag types are added: 1. BRANCH_PADDING. The variable size frag to insert NOP before branch. 2. BRANCH_PREFIX. The variable size frag to insert segment prefixes to an instruction. The choices of prefixes are: a. Use the existing segment prefix if there is one. b. Use CS segment prefix in 64-bit mode. c. In 32-bit mode, use SS segment prefix with ESP/EBP base register and use DS segment prefix without ESP/EBP base register. 3. FUSED_JCC_PADDING. The variable size frag to insert NOP before fused conditional jump. The new rs_machine_dependent frags aren't inserted if the previous item is a prefix or a constant directive, which may be used to hardcode an instruction, since there is no clear instruction boundary. Segment prefixes and NOP padding are disabled before relaxable TLS relocations and tls_get_addr calls to keep TLS instruction sequence unchanged. md_estimate_size_before_relax() and i386_generic_table_relax_frag() are used to handled BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags. i386_generic_table_relax_frag() grows or shrinks sizes of segment prefix and NOP to align the next branch frag: 1. First try to add segment prefixes to instructions before a branch. 2. If there is no sufficient room to add segment prefixes, NOP will be inserted before a branch. * config/tc-i386.c (_i386_insn): Add has_gotpc_tls_reloc. (tls_get_addr): New. (last_insn): New. (align_branch_power): New. (align_branch_kind): New. (align_branch_bit): New. (align_branch): New. (MAX_FUSED_JCC_PADDING_SIZE): New. (align_branch_prefix_size): New. (BRANCH_PADDING): New. (BRANCH_PREFIX): New. (FUSED_JCC_PADDING): New. (i386_generate_nops): Support BRANCH_PADDING and FUSED_JCC_PADDING. (md_begin): Abort if align_branch_prefix_size < MAX_FUSED_JCC_PADDING_SIZE. (md_assemble): Set last_insn. (maybe_fused_with_jcc_p): New. (add_fused_jcc_padding_frag_p): New. (add_branch_prefix_frag_p): New. (add_branch_padding_frag_p): New. (output_insn): Generate a BRANCH_PADDING, FUSED_JCC_PADDING or BRANCH_PREFIX frag and terminate each frag to align branches. (output_disp): Set i.has_gotpc_tls_reloc to TRUE for GOTPC and relaxable TLS relocations. (output_imm): Likewise. (i386_next_non_empty_frag): New. (i386_next_jcc_frag): New. (i386_classify_machine_dependent_frag): New. (i386_branch_padding_size): New. (i386_generic_table_relax_frag): New. (md_estimate_size_before_relax): Handle COND_JUMP_PADDING, FUSED_JCC_PADDING and COND_JUMP_PREFIX frags. (md_convert_frag): Handle BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags. (OPTION_MALIGN_BRANCH_BOUNDARY): New. (OPTION_MALIGN_BRANCH_PREFIX_SIZE): New. (OPTION_MALIGN_BRANCH): New. (md_longopts): Add -malign-branch-boundary=, -malign-branch-prefix-size= and -malign-branch=. (md_parse_option): Handle -malign-branch-boundary=, -malign-branch-prefix-size= and -malign-branch=. (md_show_usage): Display -malign-branch-boundary=, -malign-branch-prefix-size= and -malign-branch=. (i386_target_format): Set tls_get_addr. (i386_cons_align): New. * config/tc-i386.h (i386_cons_align): New. (md_cons_align): New. (i386_generic_table_relax_frag): New. (md_generic_table_relax_frag): New. (i386_tc_frag_data): Add u, padding_address, length, max_prefix_length, prefix_length, default_prefix, cmp_size, classified and branch_type. (TC_FRAG_INIT): Initialize u, padding_address, length, max_prefix_length, prefix_length, default_prefix, cmp_size, classified and branch_type. * doc/c-i386.texi: Document -malign-branch-boundary=, -malign-branch= and -malign-branch-prefix-size=.
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extern long i386_generic_table_relax_frag (segT, fragS *, long);
#define md_generic_table_relax_frag(segment, fragP, stretch) \
i386_generic_table_relax_frag (segment, fragP, stretch)
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#define md_number_to_chars number_to_chars_littleendian
enum processor_type
{
PROCESSOR_UNKNOWN,
PROCESSOR_GENERIC32,
PROCESSOR_GENERIC64,
PROCESSOR_I386,
PROCESSOR_I486,
PROCESSOR_PENTIUM,
PROCESSOR_I686,
PROCESSOR_PENTIUMPRO,
PROCESSOR_PENTIUM4,
PROCESSOR_NOCONA,
PROCESSOR_CORE,
PROCESSOR_CORE2,
gas/ 2009-01-10 H.J. Lu <hongjiu.lu@intel.com> * gas/config/tc-i386.c (cpu_arch): Add corei7, .clflush and .syscall. (i386_align_code): Handle PROCESSOR_COREI7. (md_show_usage): Add corei7, clflush and syscall. (i386_target_format): Replace cpup4 with cpuclflush. * gas/config/tc-i386.h (processor_type): Add PROCESSOR_COREI7. * doc/c-i386.texi: Document corei7, clflush and syscall. gas/testsuite/ 2009-01-10 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/arch-10.s: Add clflush and syscall. * gas/i386/x86-64-arch-2.s: Likewise. * gas/i386/arch-10.d: Updated. * gas/i386/arch-10-1.l: Likewise. * gas/i386/arch-10-2.l: Likewise. * gas/i386/arch-10-3.l: Likewise. * gas/i386/arch-10-4.l: Likewise. * gas/i386/x86-64-arch-2.d: Likewise. opcodes/ 2009-01-10 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (cpu_flag_init): Replace CpuP4 and CpuK6 with CpuClflush and CpuSYSCALL, respectively. Remove CpuK8. Add CPU_COREI7_FLAGS, CPU_CLFLUSH_FLAGS and CPU_SYSCALL_FLAGS. (cpu_flags): Remove CpuP4, CpuK6 and CpuK8. Add CpuClflush and CpuSYSCALL. (lineno): Removed. (set_bitfield): Take an argument, lineno. Don't report lineno on error if it is -1. (process_i386_cpu_flag): Take an argument, lineno. (process_i386_opcode_modifier): Likewise. (process_i386_operand_type): Likewise. (output_i386_opcode): Likewise. (opcode_hash_entry): Add lineno. (process_i386_opcodes): Updated. (process_i386_registers): Likewise. (process_i386_initializers): Likewise. * i386-opc.h (CpuP4): Removed. (CpuK6): Likewise. (CpuK8): Likewise. (CpuClflush): New. (CpuSYSCALL): Likewise. (CpuMMX): Updated. (i386_cpu_flags): Remove cpup4, cpuk6 and cpuk8. Add cpuclflush and cpusyscall. * i386-opc.tbl: Update movnti, clflush, lfence, mfence, pause, syscall and sysret. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
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PROCESSOR_COREI7,
PROCESSOR_IAMCU,
PROCESSOR_K6,
PROCESSOR_ATHLON,
PROCESSOR_K8,
PROCESSOR_AMDFAM10,
PROCESSOR_BD,
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PROCESSOR_ZNVER,
PROCESSOR_BT,
/* Keep this last. */
PROCESSOR_NONE
};
extern i386_cpu_flags cpu_arch_flags;
extern enum processor_type cpu_arch_tune;
extern enum processor_type cpu_arch_isa;
extern i386_cpu_flags cpu_arch_isa_flags;
/* We support four different modes. I386_FLAG_CODE variable is used to
distinguish three of these. */
extern enum i386_flag_code {
CODE_32BIT,
CODE_16BIT,
CODE_64BIT
} i386_flag_code;
struct i386_segment_info {
/* Type of previous "instruction", e.g. .byte or stand-alone prefix. */
struct last_insn {
const char *file;
const char *name;
unsigned int line;
enum last_insn_kind
{
last_insn_other = 0,
last_insn_directive,
last_insn_prefix
} kind;
} last_insn;
subsegT subseg;
struct i386_segment_info *next;
};
#define TC_SEGMENT_INFO_TYPE struct i386_segment_info
struct i386_tc_frag_data
{
i386: Align branches within a fixed boundary Add 3 command-line options to align branches within a fixed boundary with segment prefixes or NOPs: 1. -malign-branch-boundary=NUM aligns branches within NUM byte boundary. 2. -malign-branch=TYPE[+TYPE...] specifies types of branches to align. The supported branches are: a. Conditional jump. b. Fused conditional jump. c. Unconditional jump. d. Call. e. Ret. f. Indirect jump and call. 3. -malign-branch-prefix-size=NUM aligns branches with NUM segment prefixes per instruction. 3 new rs_machine_dependent frag types are added: 1. BRANCH_PADDING. The variable size frag to insert NOP before branch. 2. BRANCH_PREFIX. The variable size frag to insert segment prefixes to an instruction. The choices of prefixes are: a. Use the existing segment prefix if there is one. b. Use CS segment prefix in 64-bit mode. c. In 32-bit mode, use SS segment prefix with ESP/EBP base register and use DS segment prefix without ESP/EBP base register. 3. FUSED_JCC_PADDING. The variable size frag to insert NOP before fused conditional jump. The new rs_machine_dependent frags aren't inserted if the previous item is a prefix or a constant directive, which may be used to hardcode an instruction, since there is no clear instruction boundary. Segment prefixes and NOP padding are disabled before relaxable TLS relocations and tls_get_addr calls to keep TLS instruction sequence unchanged. md_estimate_size_before_relax() and i386_generic_table_relax_frag() are used to handled BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags. i386_generic_table_relax_frag() grows or shrinks sizes of segment prefix and NOP to align the next branch frag: 1. First try to add segment prefixes to instructions before a branch. 2. If there is no sufficient room to add segment prefixes, NOP will be inserted before a branch. * config/tc-i386.c (_i386_insn): Add has_gotpc_tls_reloc. (tls_get_addr): New. (last_insn): New. (align_branch_power): New. (align_branch_kind): New. (align_branch_bit): New. (align_branch): New. (MAX_FUSED_JCC_PADDING_SIZE): New. (align_branch_prefix_size): New. (BRANCH_PADDING): New. (BRANCH_PREFIX): New. (FUSED_JCC_PADDING): New. (i386_generate_nops): Support BRANCH_PADDING and FUSED_JCC_PADDING. (md_begin): Abort if align_branch_prefix_size < MAX_FUSED_JCC_PADDING_SIZE. (md_assemble): Set last_insn. (maybe_fused_with_jcc_p): New. (add_fused_jcc_padding_frag_p): New. (add_branch_prefix_frag_p): New. (add_branch_padding_frag_p): New. (output_insn): Generate a BRANCH_PADDING, FUSED_JCC_PADDING or BRANCH_PREFIX frag and terminate each frag to align branches. (output_disp): Set i.has_gotpc_tls_reloc to TRUE for GOTPC and relaxable TLS relocations. (output_imm): Likewise. (i386_next_non_empty_frag): New. (i386_next_jcc_frag): New. (i386_classify_machine_dependent_frag): New. (i386_branch_padding_size): New. (i386_generic_table_relax_frag): New. (md_estimate_size_before_relax): Handle COND_JUMP_PADDING, FUSED_JCC_PADDING and COND_JUMP_PREFIX frags. (md_convert_frag): Handle BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags. (OPTION_MALIGN_BRANCH_BOUNDARY): New. (OPTION_MALIGN_BRANCH_PREFIX_SIZE): New. (OPTION_MALIGN_BRANCH): New. (md_longopts): Add -malign-branch-boundary=, -malign-branch-prefix-size= and -malign-branch=. (md_parse_option): Handle -malign-branch-boundary=, -malign-branch-prefix-size= and -malign-branch=. (md_show_usage): Display -malign-branch-boundary=, -malign-branch-prefix-size= and -malign-branch=. (i386_target_format): Set tls_get_addr. (i386_cons_align): New. * config/tc-i386.h (i386_cons_align): New. (md_cons_align): New. (i386_generic_table_relax_frag): New. (md_generic_table_relax_frag): New. (i386_tc_frag_data): Add u, padding_address, length, max_prefix_length, prefix_length, default_prefix, cmp_size, classified and branch_type. (TC_FRAG_INIT): Initialize u, padding_address, length, max_prefix_length, prefix_length, default_prefix, cmp_size, classified and branch_type. * doc/c-i386.texi: Document -malign-branch-boundary=, -malign-branch= and -malign-branch-prefix-size=.
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union
{
fragS *padding_fragP;
fragS *branch_fragP;
} u;
addressT padding_address;
enum processor_type isa;
enum processor_type tune;
enum i386_flag_code code;
gas: Pass max_bytes to TC_FRAG_INIT ommit 3ae729d5a4f63740ed9a778960b17c2912b0bbdd Author: H.J. Lu <hjl.tools@gmail.com> Date: Wed Mar 7 04:18:45 2018 -0800 x86: Rewrite NOP generation for fill and alignment increased MAX_MEM_FOR_RS_ALIGN_CODE to 4095 which resulted in increase of assembler time and memory usage by 5 times for inputs with many .p2align directives, which is typical for LTO output. This patch passes max_bytes to TC_FRAG_INIT so that MAX_MEM_FOR_RS_ALIGN_CODE can be set as needed and tracked by backend it so that HANDLE_ALIGN can check the maximum alignment for each rs_align_code frag. Wall time to assemble the same cc1plus.s: before: 423.78user 0.89system 7:05.71elapsed 99%CPU after: 102.35user 0.27system 1:42.89elapsed 99%CPU PR gas/24165 * frags.c (frag_var_init): Pass max_chars to TC_FRAG_INIT as max_bytes. * config/tc-aarch64.h (TC_FRAG_INIT): Add and pass max_bytes to aarch64_init_frag. * /config/tc-arm.h (TC_FRAG_INIT): And and pass max_bytes to arm_init_frag. * config/tc-avr.h (TC_FRAG_INIT): And and ignore max_bytes. * config/tc-ia64.h (TC_FRAG_INIT): Likewise. * config/tc-mmix.h (TC_FRAG_INIT): Likewise. * config/tc-nds32.h (TC_FRAG_INIT): Likewise. * config/tc-ns32k.h (TC_FRAG_INIT): Likewise. * config/tc-rl78.h (TC_FRAG_INIT): Likewise. * config/tc-rx.h (TC_FRAG_INIT): Likewise. * config/tc-score.h (TC_FRAG_INIT): Likewise. * config/tc-tic54x.h (TC_FRAG_INIT): Likewise. * config/tc-tic6x.h (TC_FRAG_INIT): Likewise. * config/tc-xtensa.h (TC_FRAG_INIT): Likewise. * config/tc-i386.h (MAX_MEM_FOR_RS_ALIGN_CODE): Set to (alignment ? ((1 << alignment) - 1) : 1) (i386_tc_frag_data): Add max_bytes. (TC_FRAG_INIT): Add and track max_bytes. (HANDLE_ALIGN): Replace MAX_MEM_FOR_RS_ALIGN_CODE with fragP->tc_frag_data.max_bytes. * doc/internals.texi: Update TC_FRAG_TYPE with max_bytes.
2019-02-10 20:34:10 +08:00
unsigned int max_bytes;
i386: Align branches within a fixed boundary Add 3 command-line options to align branches within a fixed boundary with segment prefixes or NOPs: 1. -malign-branch-boundary=NUM aligns branches within NUM byte boundary. 2. -malign-branch=TYPE[+TYPE...] specifies types of branches to align. The supported branches are: a. Conditional jump. b. Fused conditional jump. c. Unconditional jump. d. Call. e. Ret. f. Indirect jump and call. 3. -malign-branch-prefix-size=NUM aligns branches with NUM segment prefixes per instruction. 3 new rs_machine_dependent frag types are added: 1. BRANCH_PADDING. The variable size frag to insert NOP before branch. 2. BRANCH_PREFIX. The variable size frag to insert segment prefixes to an instruction. The choices of prefixes are: a. Use the existing segment prefix if there is one. b. Use CS segment prefix in 64-bit mode. c. In 32-bit mode, use SS segment prefix with ESP/EBP base register and use DS segment prefix without ESP/EBP base register. 3. FUSED_JCC_PADDING. The variable size frag to insert NOP before fused conditional jump. The new rs_machine_dependent frags aren't inserted if the previous item is a prefix or a constant directive, which may be used to hardcode an instruction, since there is no clear instruction boundary. Segment prefixes and NOP padding are disabled before relaxable TLS relocations and tls_get_addr calls to keep TLS instruction sequence unchanged. md_estimate_size_before_relax() and i386_generic_table_relax_frag() are used to handled BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags. i386_generic_table_relax_frag() grows or shrinks sizes of segment prefix and NOP to align the next branch frag: 1. First try to add segment prefixes to instructions before a branch. 2. If there is no sufficient room to add segment prefixes, NOP will be inserted before a branch. * config/tc-i386.c (_i386_insn): Add has_gotpc_tls_reloc. (tls_get_addr): New. (last_insn): New. (align_branch_power): New. (align_branch_kind): New. (align_branch_bit): New. (align_branch): New. (MAX_FUSED_JCC_PADDING_SIZE): New. (align_branch_prefix_size): New. (BRANCH_PADDING): New. (BRANCH_PREFIX): New. (FUSED_JCC_PADDING): New. (i386_generate_nops): Support BRANCH_PADDING and FUSED_JCC_PADDING. (md_begin): Abort if align_branch_prefix_size < MAX_FUSED_JCC_PADDING_SIZE. (md_assemble): Set last_insn. (maybe_fused_with_jcc_p): New. (add_fused_jcc_padding_frag_p): New. (add_branch_prefix_frag_p): New. (add_branch_padding_frag_p): New. (output_insn): Generate a BRANCH_PADDING, FUSED_JCC_PADDING or BRANCH_PREFIX frag and terminate each frag to align branches. (output_disp): Set i.has_gotpc_tls_reloc to TRUE for GOTPC and relaxable TLS relocations. (output_imm): Likewise. (i386_next_non_empty_frag): New. (i386_next_jcc_frag): New. (i386_classify_machine_dependent_frag): New. (i386_branch_padding_size): New. (i386_generic_table_relax_frag): New. (md_estimate_size_before_relax): Handle COND_JUMP_PADDING, FUSED_JCC_PADDING and COND_JUMP_PREFIX frags. (md_convert_frag): Handle BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags. (OPTION_MALIGN_BRANCH_BOUNDARY): New. (OPTION_MALIGN_BRANCH_PREFIX_SIZE): New. (OPTION_MALIGN_BRANCH): New. (md_longopts): Add -malign-branch-boundary=, -malign-branch-prefix-size= and -malign-branch=. (md_parse_option): Handle -malign-branch-boundary=, -malign-branch-prefix-size= and -malign-branch=. (md_show_usage): Display -malign-branch-boundary=, -malign-branch-prefix-size= and -malign-branch=. (i386_target_format): Set tls_get_addr. (i386_cons_align): New. * config/tc-i386.h (i386_cons_align): New. (md_cons_align): New. (i386_generic_table_relax_frag): New. (md_generic_table_relax_frag): New. (i386_tc_frag_data): Add u, padding_address, length, max_prefix_length, prefix_length, default_prefix, cmp_size, classified and branch_type. (TC_FRAG_INIT): Initialize u, padding_address, length, max_prefix_length, prefix_length, default_prefix, cmp_size, classified and branch_type. * doc/c-i386.texi: Document -malign-branch-boundary=, -malign-branch= and -malign-branch-prefix-size=.
2019-12-13 03:56:06 +08:00
unsigned char length;
unsigned char last_length;
unsigned char max_prefix_length;
unsigned char prefix_length;
unsigned char default_prefix;
unsigned char cmp_size;
x86: Improve -malign-branch According to intel SDM manual, not all compare flag-modifying instructions are marcro-fusible with subsequent jcc instructions. For those non-fusible instructions, -malign-branch doesn't need to align them, only jcc itself needs to be aligned. Here are 2 restrictions which separate macro-fusible instruction from not Restriction 1: If TEST/AND/CMP/ADD/SUB/INC/DEC is one of the following format: cmp m, imm add m, imm sub m, imm test m, imm and m, imm inc m dec m it is unfusible with any jcc instruction. Restriction 2: /* Table 3-2. Macro-Fusible Instructions in Haswell Microarchitecture Note it also works for Skylake and Cascadelake. --------------------------------------------------------------------- | JCC | ADD/SUB/CMP | INC/DEC | TEST/AND | | ------ | ----------- | ------- | -------- | | Jo | N | N | Y | | Jno | N | N | Y | | Jc/Jb | Y | N | Y | | Jae/Jnb | Y | N | Y | | Je/Jz | Y | Y | Y | | Jne/Jnz | Y | Y | Y | | Jna/Jbe | Y | N | Y | | Ja/Jnbe | Y | N | Y | | Js | N | N | Y | | Jns | N | N | Y | | Jp/Jpe | N | N | Y | | Jnp/Jpo | N | N | Y | | Jl/Jnge | Y | Y | Y | | Jge/Jnl | Y | Y | Y | | Jle/Jng | Y | Y | Y | | Jg/Jnle | Y | Y | Y | Update maybe_fused_with_jcc_p to check if operands of CMP like instructions can be fused with condition jump. * gas/config/tc-i386.h (i386_tc_frag_data): Add member mf_type. (TC_FRAG_INIT): Init mf_type. * gas/config/tc-i386.c (enum mf_jcc_kind): New enum. (enum mf_cmp_kind): Ditto. (maybe_fused_with_jcc_p): Add argument mf_cmp_p to get mf_type of corresponding instructons, exclude unfusible instructions. (add_fused_jcc_padding_frag_p): Likewise. (add_branch_padding_frag_p): Likewise. (output_insn): Record mf_type for corresponding instructions. (i386_macro_fusible_p): New function. (i386_next_fusible_jcc_frag): Rename from i386_next_jcc_frag, add argument cmp_fragP to return next fusible jcc frag only. (i386_classify_machine_dependant_frag): Seperate macro-fusible instructions from condition jump. * gas/testsuite/gas/i386/align-branch-9.s: New file. * gas/testsuite/gas/i386/align-branch-9.d: Ditto. * gas/testsuite/gas/i386/x86-64-align-branch-9.s: Ditto. * gas/testsuite/gas/i386/x86-64-align-branch-9.d: Ditto. * gas/testsuite/gas/i386/i386.exp: Run new tests.
2020-03-03 22:21:37 +08:00
unsigned int mf_type : 3;
i386: Align branches within a fixed boundary Add 3 command-line options to align branches within a fixed boundary with segment prefixes or NOPs: 1. -malign-branch-boundary=NUM aligns branches within NUM byte boundary. 2. -malign-branch=TYPE[+TYPE...] specifies types of branches to align. The supported branches are: a. Conditional jump. b. Fused conditional jump. c. Unconditional jump. d. Call. e. Ret. f. Indirect jump and call. 3. -malign-branch-prefix-size=NUM aligns branches with NUM segment prefixes per instruction. 3 new rs_machine_dependent frag types are added: 1. BRANCH_PADDING. The variable size frag to insert NOP before branch. 2. BRANCH_PREFIX. The variable size frag to insert segment prefixes to an instruction. The choices of prefixes are: a. Use the existing segment prefix if there is one. b. Use CS segment prefix in 64-bit mode. c. In 32-bit mode, use SS segment prefix with ESP/EBP base register and use DS segment prefix without ESP/EBP base register. 3. FUSED_JCC_PADDING. The variable size frag to insert NOP before fused conditional jump. The new rs_machine_dependent frags aren't inserted if the previous item is a prefix or a constant directive, which may be used to hardcode an instruction, since there is no clear instruction boundary. Segment prefixes and NOP padding are disabled before relaxable TLS relocations and tls_get_addr calls to keep TLS instruction sequence unchanged. md_estimate_size_before_relax() and i386_generic_table_relax_frag() are used to handled BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags. i386_generic_table_relax_frag() grows or shrinks sizes of segment prefix and NOP to align the next branch frag: 1. First try to add segment prefixes to instructions before a branch. 2. If there is no sufficient room to add segment prefixes, NOP will be inserted before a branch. * config/tc-i386.c (_i386_insn): Add has_gotpc_tls_reloc. (tls_get_addr): New. (last_insn): New. (align_branch_power): New. (align_branch_kind): New. (align_branch_bit): New. (align_branch): New. (MAX_FUSED_JCC_PADDING_SIZE): New. (align_branch_prefix_size): New. (BRANCH_PADDING): New. (BRANCH_PREFIX): New. (FUSED_JCC_PADDING): New. (i386_generate_nops): Support BRANCH_PADDING and FUSED_JCC_PADDING. (md_begin): Abort if align_branch_prefix_size < MAX_FUSED_JCC_PADDING_SIZE. (md_assemble): Set last_insn. (maybe_fused_with_jcc_p): New. (add_fused_jcc_padding_frag_p): New. (add_branch_prefix_frag_p): New. (add_branch_padding_frag_p): New. (output_insn): Generate a BRANCH_PADDING, FUSED_JCC_PADDING or BRANCH_PREFIX frag and terminate each frag to align branches. (output_disp): Set i.has_gotpc_tls_reloc to TRUE for GOTPC and relaxable TLS relocations. (output_imm): Likewise. (i386_next_non_empty_frag): New. (i386_next_jcc_frag): New. (i386_classify_machine_dependent_frag): New. (i386_branch_padding_size): New. (i386_generic_table_relax_frag): New. (md_estimate_size_before_relax): Handle COND_JUMP_PADDING, FUSED_JCC_PADDING and COND_JUMP_PREFIX frags. (md_convert_frag): Handle BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags. (OPTION_MALIGN_BRANCH_BOUNDARY): New. (OPTION_MALIGN_BRANCH_PREFIX_SIZE): New. (OPTION_MALIGN_BRANCH): New. (md_longopts): Add -malign-branch-boundary=, -malign-branch-prefix-size= and -malign-branch=. (md_parse_option): Handle -malign-branch-boundary=, -malign-branch-prefix-size= and -malign-branch=. (md_show_usage): Display -malign-branch-boundary=, -malign-branch-prefix-size= and -malign-branch=. (i386_target_format): Set tls_get_addr. (i386_cons_align): New. * config/tc-i386.h (i386_cons_align): New. (md_cons_align): New. (i386_generic_table_relax_frag): New. (md_generic_table_relax_frag): New. (i386_tc_frag_data): Add u, padding_address, length, max_prefix_length, prefix_length, default_prefix, cmp_size, classified and branch_type. (TC_FRAG_INIT): Initialize u, padding_address, length, max_prefix_length, prefix_length, default_prefix, cmp_size, classified and branch_type. * doc/c-i386.texi: Document -malign-branch-boundary=, -malign-branch= and -malign-branch-prefix-size=.
2019-12-13 03:56:06 +08:00
unsigned int classified : 1;
unsigned int branch_type : 3;
unsigned int cpunop : 1;
unsigned int isanop : 1;
unsigned int last_insn_normal : 1;
};
/* We need to emit the right NOP pattern in .align frags. This is
done after the text-to-bits assembly pass, so we need to mark it with
the isa/tune settings at the time the .align was assembled. */
#define TC_FRAG_TYPE struct i386_tc_frag_data
gas: Pass max_bytes to TC_FRAG_INIT ommit 3ae729d5a4f63740ed9a778960b17c2912b0bbdd Author: H.J. Lu <hjl.tools@gmail.com> Date: Wed Mar 7 04:18:45 2018 -0800 x86: Rewrite NOP generation for fill and alignment increased MAX_MEM_FOR_RS_ALIGN_CODE to 4095 which resulted in increase of assembler time and memory usage by 5 times for inputs with many .p2align directives, which is typical for LTO output. This patch passes max_bytes to TC_FRAG_INIT so that MAX_MEM_FOR_RS_ALIGN_CODE can be set as needed and tracked by backend it so that HANDLE_ALIGN can check the maximum alignment for each rs_align_code frag. Wall time to assemble the same cc1plus.s: before: 423.78user 0.89system 7:05.71elapsed 99%CPU after: 102.35user 0.27system 1:42.89elapsed 99%CPU PR gas/24165 * frags.c (frag_var_init): Pass max_chars to TC_FRAG_INIT as max_bytes. * config/tc-aarch64.h (TC_FRAG_INIT): Add and pass max_bytes to aarch64_init_frag. * /config/tc-arm.h (TC_FRAG_INIT): And and pass max_bytes to arm_init_frag. * config/tc-avr.h (TC_FRAG_INIT): And and ignore max_bytes. * config/tc-ia64.h (TC_FRAG_INIT): Likewise. * config/tc-mmix.h (TC_FRAG_INIT): Likewise. * config/tc-nds32.h (TC_FRAG_INIT): Likewise. * config/tc-ns32k.h (TC_FRAG_INIT): Likewise. * config/tc-rl78.h (TC_FRAG_INIT): Likewise. * config/tc-rx.h (TC_FRAG_INIT): Likewise. * config/tc-score.h (TC_FRAG_INIT): Likewise. * config/tc-tic54x.h (TC_FRAG_INIT): Likewise. * config/tc-tic6x.h (TC_FRAG_INIT): Likewise. * config/tc-xtensa.h (TC_FRAG_INIT): Likewise. * config/tc-i386.h (MAX_MEM_FOR_RS_ALIGN_CODE): Set to (alignment ? ((1 << alignment) - 1) : 1) (i386_tc_frag_data): Add max_bytes. (TC_FRAG_INIT): Add and track max_bytes. (HANDLE_ALIGN): Replace MAX_MEM_FOR_RS_ALIGN_CODE with fragP->tc_frag_data.max_bytes. * doc/internals.texi: Update TC_FRAG_TYPE with max_bytes.
2019-02-10 20:34:10 +08:00
#define TC_FRAG_INIT(FRAGP, MAX_BYTES) \
do \
{ \
i386: Align branches within a fixed boundary Add 3 command-line options to align branches within a fixed boundary with segment prefixes or NOPs: 1. -malign-branch-boundary=NUM aligns branches within NUM byte boundary. 2. -malign-branch=TYPE[+TYPE...] specifies types of branches to align. The supported branches are: a. Conditional jump. b. Fused conditional jump. c. Unconditional jump. d. Call. e. Ret. f. Indirect jump and call. 3. -malign-branch-prefix-size=NUM aligns branches with NUM segment prefixes per instruction. 3 new rs_machine_dependent frag types are added: 1. BRANCH_PADDING. The variable size frag to insert NOP before branch. 2. BRANCH_PREFIX. The variable size frag to insert segment prefixes to an instruction. The choices of prefixes are: a. Use the existing segment prefix if there is one. b. Use CS segment prefix in 64-bit mode. c. In 32-bit mode, use SS segment prefix with ESP/EBP base register and use DS segment prefix without ESP/EBP base register. 3. FUSED_JCC_PADDING. The variable size frag to insert NOP before fused conditional jump. The new rs_machine_dependent frags aren't inserted if the previous item is a prefix or a constant directive, which may be used to hardcode an instruction, since there is no clear instruction boundary. Segment prefixes and NOP padding are disabled before relaxable TLS relocations and tls_get_addr calls to keep TLS instruction sequence unchanged. md_estimate_size_before_relax() and i386_generic_table_relax_frag() are used to handled BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags. i386_generic_table_relax_frag() grows or shrinks sizes of segment prefix and NOP to align the next branch frag: 1. First try to add segment prefixes to instructions before a branch. 2. If there is no sufficient room to add segment prefixes, NOP will be inserted before a branch. * config/tc-i386.c (_i386_insn): Add has_gotpc_tls_reloc. (tls_get_addr): New. (last_insn): New. (align_branch_power): New. (align_branch_kind): New. (align_branch_bit): New. (align_branch): New. (MAX_FUSED_JCC_PADDING_SIZE): New. (align_branch_prefix_size): New. (BRANCH_PADDING): New. (BRANCH_PREFIX): New. (FUSED_JCC_PADDING): New. (i386_generate_nops): Support BRANCH_PADDING and FUSED_JCC_PADDING. (md_begin): Abort if align_branch_prefix_size < MAX_FUSED_JCC_PADDING_SIZE. (md_assemble): Set last_insn. (maybe_fused_with_jcc_p): New. (add_fused_jcc_padding_frag_p): New. (add_branch_prefix_frag_p): New. (add_branch_padding_frag_p): New. (output_insn): Generate a BRANCH_PADDING, FUSED_JCC_PADDING or BRANCH_PREFIX frag and terminate each frag to align branches. (output_disp): Set i.has_gotpc_tls_reloc to TRUE for GOTPC and relaxable TLS relocations. (output_imm): Likewise. (i386_next_non_empty_frag): New. (i386_next_jcc_frag): New. (i386_classify_machine_dependent_frag): New. (i386_branch_padding_size): New. (i386_generic_table_relax_frag): New. (md_estimate_size_before_relax): Handle COND_JUMP_PADDING, FUSED_JCC_PADDING and COND_JUMP_PREFIX frags. (md_convert_frag): Handle BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags. (OPTION_MALIGN_BRANCH_BOUNDARY): New. (OPTION_MALIGN_BRANCH_PREFIX_SIZE): New. (OPTION_MALIGN_BRANCH): New. (md_longopts): Add -malign-branch-boundary=, -malign-branch-prefix-size= and -malign-branch=. (md_parse_option): Handle -malign-branch-boundary=, -malign-branch-prefix-size= and -malign-branch=. (md_show_usage): Display -malign-branch-boundary=, -malign-branch-prefix-size= and -malign-branch=. (i386_target_format): Set tls_get_addr. (i386_cons_align): New. * config/tc-i386.h (i386_cons_align): New. (md_cons_align): New. (i386_generic_table_relax_frag): New. (md_generic_table_relax_frag): New. (i386_tc_frag_data): Add u, padding_address, length, max_prefix_length, prefix_length, default_prefix, cmp_size, classified and branch_type. (TC_FRAG_INIT): Initialize u, padding_address, length, max_prefix_length, prefix_length, default_prefix, cmp_size, classified and branch_type. * doc/c-i386.texi: Document -malign-branch-boundary=, -malign-branch= and -malign-branch-prefix-size=.
2019-12-13 03:56:06 +08:00
(FRAGP)->tc_frag_data.u.padding_fragP = NULL; \
(FRAGP)->tc_frag_data.padding_address = 0; \
(FRAGP)->tc_frag_data.isa = cpu_arch_isa; \
(FRAGP)->tc_frag_data.tune = cpu_arch_tune; \
(FRAGP)->tc_frag_data.cpunop = cpu_arch_flags.bitfield.cpunop; \
(FRAGP)->tc_frag_data.isanop = cpu_arch_isa_flags.bitfield.cpunop; \
(FRAGP)->tc_frag_data.code = i386_flag_code; \
gas: Pass max_bytes to TC_FRAG_INIT ommit 3ae729d5a4f63740ed9a778960b17c2912b0bbdd Author: H.J. Lu <hjl.tools@gmail.com> Date: Wed Mar 7 04:18:45 2018 -0800 x86: Rewrite NOP generation for fill and alignment increased MAX_MEM_FOR_RS_ALIGN_CODE to 4095 which resulted in increase of assembler time and memory usage by 5 times for inputs with many .p2align directives, which is typical for LTO output. This patch passes max_bytes to TC_FRAG_INIT so that MAX_MEM_FOR_RS_ALIGN_CODE can be set as needed and tracked by backend it so that HANDLE_ALIGN can check the maximum alignment for each rs_align_code frag. Wall time to assemble the same cc1plus.s: before: 423.78user 0.89system 7:05.71elapsed 99%CPU after: 102.35user 0.27system 1:42.89elapsed 99%CPU PR gas/24165 * frags.c (frag_var_init): Pass max_chars to TC_FRAG_INIT as max_bytes. * config/tc-aarch64.h (TC_FRAG_INIT): Add and pass max_bytes to aarch64_init_frag. * /config/tc-arm.h (TC_FRAG_INIT): And and pass max_bytes to arm_init_frag. * config/tc-avr.h (TC_FRAG_INIT): And and ignore max_bytes. * config/tc-ia64.h (TC_FRAG_INIT): Likewise. * config/tc-mmix.h (TC_FRAG_INIT): Likewise. * config/tc-nds32.h (TC_FRAG_INIT): Likewise. * config/tc-ns32k.h (TC_FRAG_INIT): Likewise. * config/tc-rl78.h (TC_FRAG_INIT): Likewise. * config/tc-rx.h (TC_FRAG_INIT): Likewise. * config/tc-score.h (TC_FRAG_INIT): Likewise. * config/tc-tic54x.h (TC_FRAG_INIT): Likewise. * config/tc-tic6x.h (TC_FRAG_INIT): Likewise. * config/tc-xtensa.h (TC_FRAG_INIT): Likewise. * config/tc-i386.h (MAX_MEM_FOR_RS_ALIGN_CODE): Set to (alignment ? ((1 << alignment) - 1) : 1) (i386_tc_frag_data): Add max_bytes. (TC_FRAG_INIT): Add and track max_bytes. (HANDLE_ALIGN): Replace MAX_MEM_FOR_RS_ALIGN_CODE with fragP->tc_frag_data.max_bytes. * doc/internals.texi: Update TC_FRAG_TYPE with max_bytes.
2019-02-10 20:34:10 +08:00
(FRAGP)->tc_frag_data.max_bytes = (MAX_BYTES); \
i386: Align branches within a fixed boundary Add 3 command-line options to align branches within a fixed boundary with segment prefixes or NOPs: 1. -malign-branch-boundary=NUM aligns branches within NUM byte boundary. 2. -malign-branch=TYPE[+TYPE...] specifies types of branches to align. The supported branches are: a. Conditional jump. b. Fused conditional jump. c. Unconditional jump. d. Call. e. Ret. f. Indirect jump and call. 3. -malign-branch-prefix-size=NUM aligns branches with NUM segment prefixes per instruction. 3 new rs_machine_dependent frag types are added: 1. BRANCH_PADDING. The variable size frag to insert NOP before branch. 2. BRANCH_PREFIX. The variable size frag to insert segment prefixes to an instruction. The choices of prefixes are: a. Use the existing segment prefix if there is one. b. Use CS segment prefix in 64-bit mode. c. In 32-bit mode, use SS segment prefix with ESP/EBP base register and use DS segment prefix without ESP/EBP base register. 3. FUSED_JCC_PADDING. The variable size frag to insert NOP before fused conditional jump. The new rs_machine_dependent frags aren't inserted if the previous item is a prefix or a constant directive, which may be used to hardcode an instruction, since there is no clear instruction boundary. Segment prefixes and NOP padding are disabled before relaxable TLS relocations and tls_get_addr calls to keep TLS instruction sequence unchanged. md_estimate_size_before_relax() and i386_generic_table_relax_frag() are used to handled BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags. i386_generic_table_relax_frag() grows or shrinks sizes of segment prefix and NOP to align the next branch frag: 1. First try to add segment prefixes to instructions before a branch. 2. If there is no sufficient room to add segment prefixes, NOP will be inserted before a branch. * config/tc-i386.c (_i386_insn): Add has_gotpc_tls_reloc. (tls_get_addr): New. (last_insn): New. (align_branch_power): New. (align_branch_kind): New. (align_branch_bit): New. (align_branch): New. (MAX_FUSED_JCC_PADDING_SIZE): New. (align_branch_prefix_size): New. (BRANCH_PADDING): New. (BRANCH_PREFIX): New. (FUSED_JCC_PADDING): New. (i386_generate_nops): Support BRANCH_PADDING and FUSED_JCC_PADDING. (md_begin): Abort if align_branch_prefix_size < MAX_FUSED_JCC_PADDING_SIZE. (md_assemble): Set last_insn. (maybe_fused_with_jcc_p): New. (add_fused_jcc_padding_frag_p): New. (add_branch_prefix_frag_p): New. (add_branch_padding_frag_p): New. (output_insn): Generate a BRANCH_PADDING, FUSED_JCC_PADDING or BRANCH_PREFIX frag and terminate each frag to align branches. (output_disp): Set i.has_gotpc_tls_reloc to TRUE for GOTPC and relaxable TLS relocations. (output_imm): Likewise. (i386_next_non_empty_frag): New. (i386_next_jcc_frag): New. (i386_classify_machine_dependent_frag): New. (i386_branch_padding_size): New. (i386_generic_table_relax_frag): New. (md_estimate_size_before_relax): Handle COND_JUMP_PADDING, FUSED_JCC_PADDING and COND_JUMP_PREFIX frags. (md_convert_frag): Handle BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags. (OPTION_MALIGN_BRANCH_BOUNDARY): New. (OPTION_MALIGN_BRANCH_PREFIX_SIZE): New. (OPTION_MALIGN_BRANCH): New. (md_longopts): Add -malign-branch-boundary=, -malign-branch-prefix-size= and -malign-branch=. (md_parse_option): Handle -malign-branch-boundary=, -malign-branch-prefix-size= and -malign-branch=. (md_show_usage): Display -malign-branch-boundary=, -malign-branch-prefix-size= and -malign-branch=. (i386_target_format): Set tls_get_addr. (i386_cons_align): New. * config/tc-i386.h (i386_cons_align): New. (md_cons_align): New. (i386_generic_table_relax_frag): New. (md_generic_table_relax_frag): New. (i386_tc_frag_data): Add u, padding_address, length, max_prefix_length, prefix_length, default_prefix, cmp_size, classified and branch_type. (TC_FRAG_INIT): Initialize u, padding_address, length, max_prefix_length, prefix_length, default_prefix, cmp_size, classified and branch_type. * doc/c-i386.texi: Document -malign-branch-boundary=, -malign-branch= and -malign-branch-prefix-size=.
2019-12-13 03:56:06 +08:00
(FRAGP)->tc_frag_data.length = 0; \
(FRAGP)->tc_frag_data.last_length = 0; \
(FRAGP)->tc_frag_data.max_prefix_length = 0; \
(FRAGP)->tc_frag_data.prefix_length = 0; \
(FRAGP)->tc_frag_data.default_prefix = 0; \
(FRAGP)->tc_frag_data.cmp_size = 0; \
(FRAGP)->tc_frag_data.classified = 0; \
(FRAGP)->tc_frag_data.branch_type = 0; \
(FRAGP)->tc_frag_data.mf_type = 0; \
(FRAGP)->tc_frag_data.last_insn_normal \
= (seg_info(now_seg)->tc_segment_info_data.last_insn.kind \
== last_insn_other); \
} \
while (0)
#define WORKING_DOT_WORD 1
Add .nop assembler directive Implement the '.nop SIZE[, CONTROL]' assembler directive, which emits SIZE bytes filled with no-op instructions. SIZE is absolute expression. The optional CONTROL byte controls how no-op instructions should be generated. If the comma and @var{control} are omitted, CONTROL is assumed to be zero. For Intel 80386 and AMD x86-64 targets, CONTROL byte specifies the size limit of a single no-op instruction. The valid values of CONTROL byte are between 0 and 8 for 16-bit mode, between 0 and 10 for 32-bit mode, between 0 and 11 for 64-bit mode. When 0 is used, the no-op size limit is set to the maximum supported size. 2 new relax states, rs_space_nop and rs_fill_nop, are added to enum _relax_state, which are similar to rs_space and rs_fill, respectively, but they fill with no-op instructions, instead of a single byte. A target backend must override the default md_generate_nops to generate proper no-op instructions. Otherwise, an error of unimplemented .nop directive will be issued whenever .nop directive is used. * NEWS: Mention .nop directive. * as.h (_relax_state): Add rs_space_nop and rs_fill_nop. * read.c (potable): Add .nop. (s_nop): New function. * read.h (s_nop): New prototype. * write.c (cvt_frag_to_fill): Handle rs_space_nop and rs_fill_nop. (md_generate_nops): New function. (relax_segment): Likewise. (write_contents): Use md_generate_nops for rs_fill_nop. * config/tc-i386.c (alt64_11): New. (alt64_patt): Likewise. (md_convert_frag): Handle rs_space_nop. (i386_output_nops): New function. (i386_generate_nops): Likewise. (i386_align_code): Call i386_output_nops. * config/tc-i386.h (i386_generate_nops): New. (md_generate_nops): Likewise. * doc/as.texinfo: Document .nop directive. * testsuite/gas/i386/i386.exp: Run .nop directive tests. * testsuite/gas/i386/nop-1.d: New file. * testsuite/gas/i386/nop-1.s: Likewise. * testsuite/gas/i386/nop-2.d: Likewise. * testsuite/gas/i386/nop-2.s: Likewise. * testsuite/gas/i386/nop-3.d: Likewise. * testsuite/gas/i386/nop-3.s: Likewise. * testsuite/gas/i386/nop-4.d: Likewise. * testsuite/gas/i386/nop-4.s: Likewise. * testsuite/gas/i386/nop-5.d: Likewise. * testsuite/gas/i386/nop-5.s: Likewise. * testsuite/gas/i386/nop-6.d: Likewise. * testsuite/gas/i386/nop-6.s: Likewise. * testsuite/gas/i386/nop-bad-1.l: Likewise. * testsuite/gas/i386/nop-bad-1.s: Likewise. * testsuite/gas/i386/x86-64-nop-1.d: Likewise. * testsuite/gas/i386/x86-64-nop-2.d: Likewise. * testsuite/gas/i386/x86-64-nop-3.d: Likewise. * testsuite/gas/i386/x86-64-nop-4.d: Likewise. * testsuite/gas/i386/x86-64-nop-5.d: Likewise. * testsuite/gas/i386/x86-64-nop-6.d: Likewise.
2018-02-17 21:20:42 +08:00
/* How to generate NOPs for .nop direct directive. */
extern void i386_generate_nops (fragS *, char *, offsetT, int);
#define md_generate_nops(frag, where, amount, control) \
i386_generate_nops ((frag), (where), (amount), (control))
x86: Rewrite NOP generation for fill and alignment Rewrite NOP generation for fill and code alignment by: 1. Add a 11-byte NOP with another 0x66 prefix. 2. Remove the multi-byte NOP entries which consist of 2 instructions. 3. Select proper NOPs based on ISA and processor tuning. 4. Generate multiple NOPs with the longer NOPs first followed by the shorter NOP. 5. Use jump for larger NOP padding: a. > 8 bytes (2 NOPs) in 16-bit mode. b. > 14 bytes (2 NOPs) for older processors. c. > 77 bytes (7 NOPs) for newer processors. 6. Update MAX_MEM_FOR_RS_ALIGN_CODE to 4095. PR gas/22874 * config/tc-i386.c (f32_5): Removed. (f32_8): Likewise. (f32_9): Likewise. (f32_10): Likewise. (f32_11): Likewise. (f32_12): Likewise. (f32_13): Likewise. (f32_14): Likewise. (f16_5): Likewise. (f16_6): Likewise. (f16_7): Likewise. (f16_8): Likewise. (jump_31): Likewise. (alt64_11): Likewise. (alt64_patt): Likewise. (jump_disp8): New. (jump32_disp32): Likewise. (jump16_disp32): Likewise. (alt_11): Likewise. (f32_patt): Updated. (f16_patt): Likewise. (alt_patt): Add alt_11. (i386_align_code): Merged with ... (i386_generate_nops): This. Rewritten. (fits_in_imm7): Moved before i386_generate_nops. (fits_in_imm31): Likewise. * config/tc-i386.h (MAX_MEM_FOR_RS_ALIGN_CODE): Updated to 4095. (i386_align_code): Removed. (HANDLE_ALIGN): Rewritten with i386_generate_nops. * doc/as.texinfo: Update limits of control byte for x86 .nops directive. * testsuite/gas/i386/i386.exp: Run nops-7 and x86-64-nops-7. * gas/testsuite/gas/i386/noavx-3.l: Updated. * gas/testsuite/gas/i386/nop-1.d: Likewise. * gas/testsuite/gas/i386/nop-1.s: Likewise. * gas/testsuite/gas/i386/nop-2.d: Likewise. * gas/testsuite/gas/i386/nop-2.s: Likewise. * gas/testsuite/gas/i386/nop-3.d: Likewise. * gas/testsuite/gas/i386/nop-4.d: Likewise. * gas/testsuite/gas/i386/nop-5.d: Likewise. * gas/testsuite/gas/i386/nop-5.s: Likewise. * gas/testsuite/gas/i386/nop-6.d: Likewise. * gas/testsuite/gas/i386/nop-bad-1.l: Likewise. * gas/testsuite/gas/i386/nops-1-core2.d: Likewise. * gas/testsuite/gas/i386/nops-1-i386-i686.d: Likewise. * gas/testsuite/gas/i386/nops-1-i386.d: Likewise. * gas/testsuite/gas/i386/nops-1-i686.d: Likewise. * gas/testsuite/gas/i386/nops-1-k8.d: Likewise. * gas/testsuite/gas/i386/nops-1.d: Likewise. * gas/testsuite/gas/i386/nops-2-core2.d: Likewise. * gas/testsuite/gas/i386/nops-2-i386.d: Likewise. * gas/testsuite/gas/i386/nops-2.d: Likewise. * gas/testsuite/gas/i386/nops-3-i386.d: Likewise. * gas/testsuite/gas/i386/nops-3-i686.d: Likewise. * gas/testsuite/gas/i386/nops-3.d: Likewise. * gas/testsuite/gas/i386/nops-4-i386.d: Likewise. * gas/testsuite/gas/i386/nops-4-i686.d: Likewise. * gas/testsuite/gas/i386/nops-4.d: Likewise. * gas/testsuite/gas/i386/nops-4a-i686.d: Likewise. * gas/testsuite/gas/i386/nops-5-i686.d: Likewise. * gas/testsuite/gas/i386/nops-5.d: Likewise. * gas/testsuite/gas/i386/nops-6.d: Likewise. * gas/testsuite/gas/i386/nops16-1.d: Likewise. * gas/testsuite/gas/i386/x86-64-nop-1.d: Likewise. * gas/testsuite/gas/i386/x86-64-nop-2.d: Likewise. * gas/testsuite/gas/i386/x86-64-nop-5.d: Likewise. * gas/testsuite/gas/i386/x86-64-nops-1-core2.d: Likewise. * gas/testsuite/gas/i386/x86-64-nops-1-g64.d: Likewise. * gas/testsuite/gas/i386/x86-64-nops-1-k8.d: Likewise. * gas/testsuite/gas/i386/x86-64-nops-1-pentium.d: Likewise. * gas/testsuite/gas/i386/x86-64-nops-1.d: Likewise. * gas/testsuite/gas/i386/x86-64-nops-2.d: Likewise. * gas/testsuite/gas/i386/x86-64-nops-3.d: Likewise. * gas/testsuite/gas/i386/x86-64-nops-4-core2.d: Likewise. * gas/testsuite/gas/i386/x86-64-nops-4-k8.d: Likewise. * gas/testsuite/gas/i386/x86-64-nops-4.d: Likewise. * gas/testsuite/gas/i386/x86-64-nops-5-k8.d: Likewise. * gas/testsuite/gas/i386/x86-64-nops-5.d: Likewise. * gas/testsuite/gas/i386/ilp32/x86-64-nops-1-core2.d: Likewise. * gas/testsuite/gas/i386/ilp32/x86-64-nops-1-k8.d: Likewise. * gas/testsuite/gas/i386/ilp32/x86-64-nops-1-pentium.d: Likewise. * gas/testsuite/gas/i386/ilp32/x86-64-nops-1.d: Likewise. * gas/testsuite/gas/i386/ilp32/x86-64-nops-2.d: Likewise. * gas/testsuite/gas/i386/ilp32/x86-64-nops-3.d: Likewise. * gas/testsuite/gas/i386/ilp32/x86-64-nops-4-core2.d: Likewise. * gas/testsuite/gas/i386/ilp32/x86-64-nops-4-k8.d: Likewise. * gas/testsuite/gas/i386/ilp32/x86-64-nops-4.d: Likewise. * gas/testsuite/gas/i386/ilp32/x86-64-nops-5-k8.d: Likewise. * gas/testsuite/gas/i386/ilp32/x86-64-nops-5.d: Likewise. * gas/testsuite/gas/i386/nops-7.d: New file. * gas/testsuite/gas/i386/nops-7.s: Likewise. * gas/testsuite/gas/i386/x86-64-nops-7.d: Likewise.
2018-03-07 20:18:45 +08:00
#define HANDLE_ALIGN(fragP) \
if (fragP->fr_type == rs_align_code) \
{ \
offsetT __count = (fragP->fr_next->fr_address \
- fragP->fr_address \
- fragP->fr_fix); \
gas: Pass max_bytes to TC_FRAG_INIT ommit 3ae729d5a4f63740ed9a778960b17c2912b0bbdd Author: H.J. Lu <hjl.tools@gmail.com> Date: Wed Mar 7 04:18:45 2018 -0800 x86: Rewrite NOP generation for fill and alignment increased MAX_MEM_FOR_RS_ALIGN_CODE to 4095 which resulted in increase of assembler time and memory usage by 5 times for inputs with many .p2align directives, which is typical for LTO output. This patch passes max_bytes to TC_FRAG_INIT so that MAX_MEM_FOR_RS_ALIGN_CODE can be set as needed and tracked by backend it so that HANDLE_ALIGN can check the maximum alignment for each rs_align_code frag. Wall time to assemble the same cc1plus.s: before: 423.78user 0.89system 7:05.71elapsed 99%CPU after: 102.35user 0.27system 1:42.89elapsed 99%CPU PR gas/24165 * frags.c (frag_var_init): Pass max_chars to TC_FRAG_INIT as max_bytes. * config/tc-aarch64.h (TC_FRAG_INIT): Add and pass max_bytes to aarch64_init_frag. * /config/tc-arm.h (TC_FRAG_INIT): And and pass max_bytes to arm_init_frag. * config/tc-avr.h (TC_FRAG_INIT): And and ignore max_bytes. * config/tc-ia64.h (TC_FRAG_INIT): Likewise. * config/tc-mmix.h (TC_FRAG_INIT): Likewise. * config/tc-nds32.h (TC_FRAG_INIT): Likewise. * config/tc-ns32k.h (TC_FRAG_INIT): Likewise. * config/tc-rl78.h (TC_FRAG_INIT): Likewise. * config/tc-rx.h (TC_FRAG_INIT): Likewise. * config/tc-score.h (TC_FRAG_INIT): Likewise. * config/tc-tic54x.h (TC_FRAG_INIT): Likewise. * config/tc-tic6x.h (TC_FRAG_INIT): Likewise. * config/tc-xtensa.h (TC_FRAG_INIT): Likewise. * config/tc-i386.h (MAX_MEM_FOR_RS_ALIGN_CODE): Set to (alignment ? ((1 << alignment) - 1) : 1) (i386_tc_frag_data): Add max_bytes. (TC_FRAG_INIT): Add and track max_bytes. (HANDLE_ALIGN): Replace MAX_MEM_FOR_RS_ALIGN_CODE with fragP->tc_frag_data.max_bytes. * doc/internals.texi: Update TC_FRAG_TYPE with max_bytes.
2019-02-10 20:34:10 +08:00
if (__count > 0 \
&& (unsigned int) __count <= fragP->tc_frag_data.max_bytes) \
x86: Rewrite NOP generation for fill and alignment Rewrite NOP generation for fill and code alignment by: 1. Add a 11-byte NOP with another 0x66 prefix. 2. Remove the multi-byte NOP entries which consist of 2 instructions. 3. Select proper NOPs based on ISA and processor tuning. 4. Generate multiple NOPs with the longer NOPs first followed by the shorter NOP. 5. Use jump for larger NOP padding: a. > 8 bytes (2 NOPs) in 16-bit mode. b. > 14 bytes (2 NOPs) for older processors. c. > 77 bytes (7 NOPs) for newer processors. 6. Update MAX_MEM_FOR_RS_ALIGN_CODE to 4095. PR gas/22874 * config/tc-i386.c (f32_5): Removed. (f32_8): Likewise. (f32_9): Likewise. (f32_10): Likewise. (f32_11): Likewise. (f32_12): Likewise. (f32_13): Likewise. (f32_14): Likewise. (f16_5): Likewise. (f16_6): Likewise. (f16_7): Likewise. (f16_8): Likewise. (jump_31): Likewise. (alt64_11): Likewise. (alt64_patt): Likewise. (jump_disp8): New. (jump32_disp32): Likewise. (jump16_disp32): Likewise. (alt_11): Likewise. (f32_patt): Updated. (f16_patt): Likewise. (alt_patt): Add alt_11. (i386_align_code): Merged with ... (i386_generate_nops): This. Rewritten. (fits_in_imm7): Moved before i386_generate_nops. (fits_in_imm31): Likewise. * config/tc-i386.h (MAX_MEM_FOR_RS_ALIGN_CODE): Updated to 4095. (i386_align_code): Removed. (HANDLE_ALIGN): Rewritten with i386_generate_nops. * doc/as.texinfo: Update limits of control byte for x86 .nops directive. * testsuite/gas/i386/i386.exp: Run nops-7 and x86-64-nops-7. * gas/testsuite/gas/i386/noavx-3.l: Updated. * gas/testsuite/gas/i386/nop-1.d: Likewise. * gas/testsuite/gas/i386/nop-1.s: Likewise. * gas/testsuite/gas/i386/nop-2.d: Likewise. * gas/testsuite/gas/i386/nop-2.s: Likewise. * gas/testsuite/gas/i386/nop-3.d: Likewise. * gas/testsuite/gas/i386/nop-4.d: Likewise. * gas/testsuite/gas/i386/nop-5.d: Likewise. * gas/testsuite/gas/i386/nop-5.s: Likewise. * gas/testsuite/gas/i386/nop-6.d: Likewise. * gas/testsuite/gas/i386/nop-bad-1.l: Likewise. * gas/testsuite/gas/i386/nops-1-core2.d: Likewise. * gas/testsuite/gas/i386/nops-1-i386-i686.d: Likewise. * gas/testsuite/gas/i386/nops-1-i386.d: Likewise. * gas/testsuite/gas/i386/nops-1-i686.d: Likewise. * gas/testsuite/gas/i386/nops-1-k8.d: Likewise. * gas/testsuite/gas/i386/nops-1.d: Likewise. * gas/testsuite/gas/i386/nops-2-core2.d: Likewise. * gas/testsuite/gas/i386/nops-2-i386.d: Likewise. * gas/testsuite/gas/i386/nops-2.d: Likewise. * gas/testsuite/gas/i386/nops-3-i386.d: Likewise. * gas/testsuite/gas/i386/nops-3-i686.d: Likewise. * gas/testsuite/gas/i386/nops-3.d: Likewise. * gas/testsuite/gas/i386/nops-4-i386.d: Likewise. * gas/testsuite/gas/i386/nops-4-i686.d: Likewise. * gas/testsuite/gas/i386/nops-4.d: Likewise. * gas/testsuite/gas/i386/nops-4a-i686.d: Likewise. * gas/testsuite/gas/i386/nops-5-i686.d: Likewise. * gas/testsuite/gas/i386/nops-5.d: Likewise. * gas/testsuite/gas/i386/nops-6.d: Likewise. * gas/testsuite/gas/i386/nops16-1.d: Likewise. * gas/testsuite/gas/i386/x86-64-nop-1.d: Likewise. * gas/testsuite/gas/i386/x86-64-nop-2.d: Likewise. * gas/testsuite/gas/i386/x86-64-nop-5.d: Likewise. * gas/testsuite/gas/i386/x86-64-nops-1-core2.d: Likewise. * gas/testsuite/gas/i386/x86-64-nops-1-g64.d: Likewise. * gas/testsuite/gas/i386/x86-64-nops-1-k8.d: Likewise. * gas/testsuite/gas/i386/x86-64-nops-1-pentium.d: Likewise. * gas/testsuite/gas/i386/x86-64-nops-1.d: Likewise. * gas/testsuite/gas/i386/x86-64-nops-2.d: Likewise. * gas/testsuite/gas/i386/x86-64-nops-3.d: Likewise. * gas/testsuite/gas/i386/x86-64-nops-4-core2.d: Likewise. * gas/testsuite/gas/i386/x86-64-nops-4-k8.d: Likewise. * gas/testsuite/gas/i386/x86-64-nops-4.d: Likewise. * gas/testsuite/gas/i386/x86-64-nops-5-k8.d: Likewise. * gas/testsuite/gas/i386/x86-64-nops-5.d: Likewise. * gas/testsuite/gas/i386/ilp32/x86-64-nops-1-core2.d: Likewise. * gas/testsuite/gas/i386/ilp32/x86-64-nops-1-k8.d: Likewise. * gas/testsuite/gas/i386/ilp32/x86-64-nops-1-pentium.d: Likewise. * gas/testsuite/gas/i386/ilp32/x86-64-nops-1.d: Likewise. * gas/testsuite/gas/i386/ilp32/x86-64-nops-2.d: Likewise. * gas/testsuite/gas/i386/ilp32/x86-64-nops-3.d: Likewise. * gas/testsuite/gas/i386/ilp32/x86-64-nops-4-core2.d: Likewise. * gas/testsuite/gas/i386/ilp32/x86-64-nops-4-k8.d: Likewise. * gas/testsuite/gas/i386/ilp32/x86-64-nops-4.d: Likewise. * gas/testsuite/gas/i386/ilp32/x86-64-nops-5-k8.d: Likewise. * gas/testsuite/gas/i386/ilp32/x86-64-nops-5.d: Likewise. * gas/testsuite/gas/i386/nops-7.d: New file. * gas/testsuite/gas/i386/nops-7.s: Likewise. * gas/testsuite/gas/i386/x86-64-nops-7.d: Likewise.
2018-03-07 20:18:45 +08:00
md_generate_nops (fragP, fragP->fr_literal + fragP->fr_fix, \
__count, 0); \
}
/* We want .cfi_* pseudo-ops for generating unwind info. */
#define TARGET_USE_CFIPOP 1
extern unsigned int x86_dwarf2_return_column;
#define DWARF2_DEFAULT_RETURN_COLUMN x86_dwarf2_return_column
extern int x86_cie_data_alignment;
#define DWARF2_CIE_DATA_ALIGNMENT x86_cie_data_alignment
Check R_X86_64_32 overflow and allow R_X86_64_64 for x32. bfd/ 2011-08-01 H.J. Lu <hongjiu.lu@intel.com> PR ld/13048 * archures.c (bfd_mach_i386_intel_syntax): New. (bfd_mach_i386_i8086): Updated. (bfd_mach_i386_i386): Likewise. (bfd_mach_x86_64): Likewise. (bfd_mach_x64_32): Likewise. (bfd_mach_i386_i386_intel_syntax): Likewise. (bfd_mach_x86_64_intel_syntax): Likewise. (bfd_mach_x64_32_intel_syntax): Likewise. (bfd_mach_l1om): Likewise. (bfd_mach_l1om_intel_syntax): Likewise. (bfd_mach_k1om): Likewise. (bfd_mach_k1om_intel_syntax): Likewise. * bfd-in2.h: Regenerated. * cpu-i386.c (bfd_i386_compatible): Check mach instead of bits_per_address. (bfd_x64_32_arch_intel_syntax): Set bits_per_address to 64. (bfd_x64_32_arch): Likewise. * elf64-x86-64.c: Include "libiberty.h". (x86_64_elf_howto_table): Append x32 R_X86_64_32. (elf_x86_64_rtype_to_howto): Support x32 R_X86_64_32. (elf_x86_64_reloc_type_lookup): Likewise. (elf_x86_64_reloc_name_lookup): Likewise. (elf_x86_64_relocate_section): Likewise. (elf_x86_64_check_relocs): Allow R_X86_64_64 relocations for x32. gas/ 2011-08-01 H.J. Lu <hongjiu.lu@intel.com> PR ld/13048 * config/tc-i386.c (handle_quad): Removed. (md_pseudo_table): Remove "quad". (tc_gen_reloc): Don't check BFD_RELOC_64 for disallow_64bit_reloc. (x86_dwarf2_addr_size): New. * config/tc-i386.h (x86_dwarf2_addr_size): New. (DWARF2_ADDR_SIZE): Likewise. gas/testsuite/ 2011-08-01 H.J. Lu <hongjiu.lu@intel.com> PR ld/13048 * gas/i386/ilp32/ilp32.exp: Don't run inval. * gas/i386/ilp32/inval.l: Removed. * gas/i386/ilp32/inval.s: Likewise. * gas/i386/ilp32/quad.d: Expect R_X86_64_64 instead of R_X86_64_32. * gas/i386/ilp32/x86-64-pcrel.s: Add tests for movabs. * gas/i386/ilp32/x86-64-pcrel.d: Updated. ld/testsuite/ 2011-08-01 H.J. Lu <hongjiu.lu@intel.com> PR ld/13048 * ld-x86-64/ilp32-6.d: New. * ld-x86-64/ilp32-6.s: Likewise. * ld-x86-64/ilp32-7.d: Likewise. * ld-x86-64/ilp32-7.s: Likewise. * ld-x86-64/ilp32-8.d: Likewise. * ld-x86-64/ilp32-8.s: Likewise. * ld-x86-64/ilp32-9.d: Likewise. * ld-x86-64/ilp32-9.s: Likewise. * ld-x86-64/x86-64.exp: Run ilp32-6, ilp32-7, ilp32-8 and ilp32-9. opcodes/ 2011-08-01 H.J. Lu <hongjiu.lu@intel.com> PR ld/13048 * i386-dis.c (print_insn): Optimize info->mach check.
2011-08-02 07:04:23 +08:00
extern int x86_dwarf2_addr_size (void);
#define DWARF2_ADDR_SIZE(bfd) x86_dwarf2_addr_size ()
#define tc_parse_to_dw2regnum tc_x86_parse_to_dw2regnum
extern void tc_x86_parse_to_dw2regnum (expressionS *);
#define tc_cfi_frame_initial_instructions tc_x86_frame_initial_instructions
extern void tc_x86_frame_initial_instructions (void);
/* DWARF register number of the frame-pointer register in 64-bit mode. */
#define REG_FP 6
/* DWARF register number of the stack-pointer register in 64-bit mode. */
#define REG_SP 7
#define md_elf_section_type(str,len) i386_elf_section_type (str, len)
extern int i386_elf_section_type (const char *, size_t);
#define md_elf_section_change_hook i386_elf_section_change_hook
extern void i386_elf_section_change_hook (void);
#ifdef TE_SOLARIS
#define md_fix_up_eh_frame(sec) i386_solaris_fix_up_eh_frame (sec)
extern void i386_solaris_fix_up_eh_frame (segT);
#endif
bfd/ 2005-07-25 Jan Hubicka <jh@suse.cz> H.J. Lu <hongjiu.lu@intel.com> * elf-bfd.h (_bfd_elf_large_com_section): New. * elf.c (_bfd_elf_large_com_section): New. Defined. * elf64-x86-64.c (elf64_x86_64_add_symbol_hook): New. (elf64_x86_64_elf_section_from_bfd_section): New. (elf64_x86_64_symbol_processing): New. (elf64_x86_64_common_definition): New. (elf64_x86_64_common_section_index): New. (elf64_x86_64_common_section): New. (elf64_x86_64_merge_symbol): New. (elf64_x86_64_additional_program_headers): New. (elf64_x86_64_special_sections): New. (elf_backend_section_from_bfd_section): New. Defined. (elf_backend_add_symbol_hook): Likewise. (elf_backend_common_section_index): Likewise. (elf_backend_common_section): Likewise. (elf_backend_common_definition): Likewise. (elf_backend_merge_symbol): Likewise. (elf_backend_special_sections): Likewise. (elf_backend_additional_program_headers): Likewise. binutils/ 2005-07-25 H.J. Lu <hongjiu.lu@intel.com> * readelf.c (dump_relocations): Handle SHN_X86_64_LCOMMON. (get_symbol_index_type): Likewise. (get_elf_section_flags): Handle SHF_X86_64_LARGE. gas/ 2005-07-25 Jan Hubicka <jh@suse.cz> H.J. Lu <hongjiu.lu@intel.com> * config/obj-elf.c: Include "elf/x86-64.h" if TC_I386 is defined. (elf_com_section_ptr): New. (elf_begin): Set elf_com_section_ptr to bfd_com_section_ptr. (elf_common_parse): Make it global. Use elf_com_section_ptr instead of bfd_com_section_ptr. (obj_elf_change_section): Handle x86-64 large bss sections. * config/obj-elf.h (elf_com_section_ptr): New. (elf_common_parse): New. * config/tc-i386.c (handle_large_common): New. (md_pseudo_table): Add "largecomm". (x86_64_section_letter): New. (x86_64_section_word): New. * config/tc-i386.h (x86_64_section_word): New. (x86_64_section_letter): New. (md_elf_section_letter): New. Defined. (md_elf_section_word): Likewise. include/elf/ 2005-07-25 Jan Hubicka <jh@suse.cz> * x86-64.h (SHN_X86_64_LCOMMON): New. (SHF_X86_64_LARGE): New. ld/ 2005-07-25 Jan Hubicka <jh@suse.cz> H.J. Lu <hongjiu.lu@intel.com> * emulparams/elf_x86_64.sh (LARGE_SECTIONS): New. * scripttempl/elf.sc: Updated for large section support.
2005-07-25 23:41:08 +08:00
/* Support for SHF_X86_64_LARGE */
Constify more * cgen.c (weak_operand_overflow_check): Return const char*. * messages.c (as_internal_value_out_of_range): Formatting. (as_warn_value_out_of_range): Consify prefix param. (as_bad_value_out_of_range): Likewise. * read.c (s_errwarn): Constify msg.. (s_float_space, float_cons): ..and err. * as.h (as_warn_value_out_of_range, as_bad_value_out_of_range, ieee_md_atof, vax_md_atof): Update prototypes. * tc.h (md_atof): Update prototype. * config/atof-ieee.c (ieee_md_atof): Return const char*. * config/atof-vax.c (vax_md_atof): Likewise. * config/obj-elf.c (obj_elf_parse_section_letters): Constify bad_msg. * config/tc-aarch64.c (md_atof): Return const char*. * config/tc-alpha.c (s_alpha_section_name): Likewise. (s_alpha_comm): Constify sec_name. (section_name): Constify. (s_alpha_section): Consify name.. (alpha_elf_section_letter): ..and ptr_msg param.. (md_atof): ..and return. * config/tc-alpha.h (alpha_elf_section_letter): Update prototype. * config/tc-arc.c (md_atof): Return const char*. * config/tc-arm.c (md_atof): Likewise. * config/tc-avr.c (md_atof): Likewise. * config/tc-bfin.c (md_atof): Likewise. * config/tc-cr16.c (md_atof): Likewise. * config/tc-cris.c (md_atof): Likewise. * config/tc-crx.c (md_atof): Likewise. * config/tc-d10v.c (md_atof): Likewise. * config/tc-d30v.c (md_atof): Likewise. * config/tc-dlx.c (md_atof): Likewise. * config/tc-epiphany.c (md_atof): Likewise. * config/tc-fr30.c (md_atof): Likewise. * config/tc-frv.c (md_atof): Likewise. * config/tc-ft32.c (md_atof): Likewise. * config/tc-h8300.c (md_atof): Likewise. * config/tc-hppa.c (struct default_subspace_dict): Constify name. (struct default_space_dict): Likewise. (create_new_space): Constify name param. (create_new_subspace): Likewise. (is_defined_space, is_defined_subspace): Likewise. (pa_parse_space_stmt): Constify space_name param. (md_atof): Return const char*. (pa_spaces_begin): Constify name. * config/tc-i370.c (md_atof): Return const char*. * config/tc-i386.c (md_atof): Likewise. (x86_64_section_letter): Constify ptr_msg param. * config/tc-i386.h (x86_64_section_letter): Update prototype. * config/tc-i860.c (struct i860_it): Constify error. (md_atof): Return const char*. * config/tc-i960.c (md_atof): Likewise. * config/tc-ia64.c (md_atof): Likewise. (ia64_elf_section_letter): Constify ptr_msg param. * config/tc-ia64.h (ia64_elf_section_letter): Update prototype. * config/tc-ip2k.c (md_atof): Return const char*. * config/tc-iq2000.c (md_atof): Likewise. * config/tc-lm32.c (md_atof): Likewise. * config/tc-m32c.c (md_atof): Likewise. * config/tc-m32r.c (md_atof): Likewise. * config/tc-m68hc11.c (md_atof): Likewise. * config/tc-m68k.c (md_atof): Likewise. * config/tc-mcore.c (md_atof): Likewise. * config/tc-mep.c (md_atof): Likewise. (mep_elf_section_letter): Constify ptr_msg param. * config/tc-mep.h (mep_elf_section_letter): Update prototype. * config/tc-metag.c (md_atof): Return const char*. * config/tc-microblaze.c (md_atof): Likewise. * config/tc-microblaze.h (md_atof): Delete prototype. * config/tc-mips.c (mips_parse_argument_token): Constify err. (md_atof): Return const char*. * config/tc-mmix.c (md_atof): Likewise. * config/tc-mn10200.c (md_atof): Likewise. * config/tc-mn10300.c (md_atof): Likewise. * config/tc-moxie.c (md_atof): Likewise. * config/tc-msp430.c (md_atof): Likewise. * config/tc-mt.c (md_atof): Likewise. * config/tc-nds32.c (md_atof): Likewise. * config/tc-nios2.c (md_atof): Likewise. (nios2_elf_section_letter): Constify ptr_msg param. * config/tc-nios2.h (nios2_elf_section_letter): Update prototype. * config/tc-ns32k.c (md_atof): Return const char*. * config/tc-or1k.c (md_atof): Likewise. * config/tc-pdp11.c (struct pdp11_code): Constify error. (md_atof): Return const char*. * config/tc-pj.c (md_atof): Likewise. * config/tc-ppc.c (md_atof): Likewise. * config/tc-rl78.c (md_atof): Likewise. * config/tc-rx.c (md_atof): Likewise. * config/tc-s390.c (md_atof): Likewise. * config/tc-score.c (s3_atof, md_atof): Likewise. * config/tc-sh.c (md_atof): Likewise. * config/tc-sparc.c (struct sparc_it): Constify error. (md_atof): Return const char*. * config/tc-spu.c (md_atof): Likewise. * config/tc-tic30.c (md_atof): Likewise. * config/tc-tic4x.c (md_atof): Likewise. * config/tc-tic54x.c (md_atof): Likewise. * config/tc-tic6x.c (md_atof): Likewise. * config/tc-tilegx.c (md_atof): Likewise. * config/tc-tilepro.c (md_atof): Likewise. * config/tc-v850.c (parse_register_list, md_atof): Likewise. * config/tc-vax.c (md_atof): Likewise. * config/tc-visium.c (md_atof): Likewise. * config/tc-xc16x.c (md_atof): Likewise. * config/tc-xgate.c (md_atof): Likewise. * config/tc-xstormy16.c (md_atof): Likewise. * config/tc-xtensa.c (md_atof): Likewise. * config/tc-z80.c (md_atof): Likewise. * config/tc-z8k.c (md_atof): Likewise.
2016-04-01 20:07:50 +08:00
extern bfd_vma x86_64_section_letter (int, const char **);
bfd/ 2005-07-25 Jan Hubicka <jh@suse.cz> H.J. Lu <hongjiu.lu@intel.com> * elf-bfd.h (_bfd_elf_large_com_section): New. * elf.c (_bfd_elf_large_com_section): New. Defined. * elf64-x86-64.c (elf64_x86_64_add_symbol_hook): New. (elf64_x86_64_elf_section_from_bfd_section): New. (elf64_x86_64_symbol_processing): New. (elf64_x86_64_common_definition): New. (elf64_x86_64_common_section_index): New. (elf64_x86_64_common_section): New. (elf64_x86_64_merge_symbol): New. (elf64_x86_64_additional_program_headers): New. (elf64_x86_64_special_sections): New. (elf_backend_section_from_bfd_section): New. Defined. (elf_backend_add_symbol_hook): Likewise. (elf_backend_common_section_index): Likewise. (elf_backend_common_section): Likewise. (elf_backend_common_definition): Likewise. (elf_backend_merge_symbol): Likewise. (elf_backend_special_sections): Likewise. (elf_backend_additional_program_headers): Likewise. binutils/ 2005-07-25 H.J. Lu <hongjiu.lu@intel.com> * readelf.c (dump_relocations): Handle SHN_X86_64_LCOMMON. (get_symbol_index_type): Likewise. (get_elf_section_flags): Handle SHF_X86_64_LARGE. gas/ 2005-07-25 Jan Hubicka <jh@suse.cz> H.J. Lu <hongjiu.lu@intel.com> * config/obj-elf.c: Include "elf/x86-64.h" if TC_I386 is defined. (elf_com_section_ptr): New. (elf_begin): Set elf_com_section_ptr to bfd_com_section_ptr. (elf_common_parse): Make it global. Use elf_com_section_ptr instead of bfd_com_section_ptr. (obj_elf_change_section): Handle x86-64 large bss sections. * config/obj-elf.h (elf_com_section_ptr): New. (elf_common_parse): New. * config/tc-i386.c (handle_large_common): New. (md_pseudo_table): Add "largecomm". (x86_64_section_letter): New. (x86_64_section_word): New. * config/tc-i386.h (x86_64_section_word): New. (x86_64_section_letter): New. (md_elf_section_letter): New. Defined. (md_elf_section_word): Likewise. include/elf/ 2005-07-25 Jan Hubicka <jh@suse.cz> * x86-64.h (SHN_X86_64_LCOMMON): New. (SHF_X86_64_LARGE): New. ld/ 2005-07-25 Jan Hubicka <jh@suse.cz> H.J. Lu <hongjiu.lu@intel.com> * emulparams/elf_x86_64.sh (LARGE_SECTIONS): New. * scripttempl/elf.sc: Updated for large section support.
2005-07-25 23:41:08 +08:00
#define md_elf_section_letter(LETTER, PTR_MSG) x86_64_section_letter (LETTER, PTR_MSG)
#ifdef OBJ_ELF
extern void x86_cleanup (void);
#define md_cleanup() x86_cleanup ()
gas: generate .sframe from CFI directives Currently supported for x86_64 and aarch64 only. [PS: Currently, the compiler has not been adapted to generate ".cfi_sections" with ".sframe" in it. The newly added command line option of --gsframe provides an easy way to try out .sframe support in the toolchain.] gas interprets the CFI directives to generate DWARF-based .eh_frame info. These internal DWARF structures are now consumed by gen-sframe.[ch] sub-system to, in turn, create the SFrame unwind information. These internal DWARF structures are read-only for the purpose of SFrame unwind info generation. SFrame unwind info generation does not impact .eh_frame unwind info generation. Both .eh_frame and .sframe can co-exist in an ELF file, if so desired by the user. Recall that SFrame unwind information only contains the minimal necessary information to generate backtraces and does not provide information to recover all callee-saved registers. The reason being that callee-saved registers other than FP are not needed for stack unwinding, and hence are not included in the .sframe section. Consequently, gen-sframe.[ch] only needs to interpret a subset of DWARF opcodes in gas. More details follow. [Set 1, Interpreted] The following opcodes are interpreted: - DW_CFA_advance_loc - DW_CFA_def_cfa - DW_CFA_def_cfa_register - DW_CFA_def_cfa_offset - DW_CFA_offset - DW_CFA_remember_state - DW_CFA_restore_state - DW_CFA_restore [Set 2, Bypassed] The following opcodes are acknowledged but are not necessary for generating SFrame unwind info: - DW_CFA_undefined - DW_CFA_same_value Anything else apart from the two above-mentioned sets is skipped altogether. This means that any function containing a CFI directive not in Set 1 or Set 2 above, will not have any SFrame unwind information generated for them. Holes in instructions covered by FREs of a single FDE are not representable in the SFrame unwind format. As few examples, following opcodes are not processed for .sframe generation, and are skipped: - .cfi_personality* - .cfi_*lsda - .cfi_escape - .cfi_negate_ra_state - ... Not processing .cfi_escape, .cfi_negate_ra_state will cause SFrame unwind information to be absent for SFrame FDEs that contain these CFI directives, hence affecting the asynchronicity. x86-64 and aarch64 backends need to have a few new definitions and functions for .sframe generation. These provide gas with architecture specific information like the SP/FP/RA register numbers and an SFrame-specific ABI marker. Lastly, the patch also implements an optimization for size, where specific fragments containing SFrame FRE start address and SFrame FDE function are fixed up. This is similar to other similar optimizations in gas, where fragments are sized and fixed up when the associated symbols can be resolved. This optimization is controlled by a #define SFRAME_FRE_TYPE_SELECTION_OPT and should be easy to turn off if needed. The optimization is on by default for both x86_64 and aarch64. ChangeLog: * gas/Makefile.am: Include gen-sframe.c and sframe-opt.c. * gas/Makefile.in: Regenerated. * gas/as.h (enum _relax_state): Add new state rs_sframe. (sframe_estimate_size_before_relax): New function. (sframe_relax_frag): Likewise. (sframe_convert_frag): Likewise. * gas/config/tc-aarch64.c (aarch64_support_sframe_p): New definition. (aarch64_sframe_ra_tracking_p): Likewise. (aarch64_sframe_cfa_ra_offset): Likewise. (aarch64_sframe_get_abi_arch): Likewise. (md_begin): Set values of sp/fp/ra registers. * gas/config/tc-aarch64.h (aarch64_support_sframe_p): New declaration. (support_sframe_p): Likewise. (SFRAME_CFA_SP_REG): Likewise. (SFRAME_CFA_FP_REG): Likewise. (SFRAME_CFA_RA_REG): Likewise. (aarch64_sframe_ra_tracking_p): Likewise. (sframe_ra_tracking_p): Likewise. (aarch64_sframe_cfa_ra_offset): Likewise. (sframe_cfa_ra_offset): Likewise. (aarch64_sframe_get_abi_arch): Likewise. (sframe_get_abi_arch): Likewise. * gas/config/tc-i386.c (x86_support_sframe_p): New definition. (x86_sframe_ra_tracking_p): Likewise. (x86_sframe_cfa_ra_offset): Likewise. (x86_sframe_get_abi_arch): Likewise. * gas/config/tc-i386.h (x86_support_sframe_p): New declaration. (support_sframe_p): Likewise. (SFRAME_CFA_SP_REG): Likewise. (SFRAME_CFA_FP_REG): Likewise. (x86_sframe_ra_tracking_p): Likewise. (sframe_ra_tracking_p): Likewise. (x86_sframe_cfa_ra_offset): Likewise. (sframe_cfa_ra_offset): Likewise. (x86_sframe_get_abi_arch): Likewise. (sframe_get_abi_arch): Likewise. * gas/config/tc-xtensa.c (unrelaxed_frag_max_size): Add case for rs_sframe. * gas/doc/as.texi: Add .sframe to the documentation for .cfi_sections. * gas/dw2gencfi.c (cfi_finish): Create a .sframe section. * gas/dw2gencfi.h (CFI_EMIT_sframe): New definition. * gas/write.c (cvt_frag_to_fill): Handle rs_sframe. (relax_segment): Likewise. * gas/gen-sframe.c: New file. * gas/gen-sframe.h: New file. * gas/sframe-opt.c: New file.
2022-11-16 07:06:46 +08:00
gas: x86: synthesize CFI for hand-written asm This patch adds support in GAS to create generic GAS instructions (a.k.a., the ginsn) for the x86 backend (AMD64 ABI only at this time). Using this ginsn infrastructure, GAS can then synthesize CFI for hand-written asm for x86_64. A ginsn is a target-independent representation of the machine instructions. One machine instruction may need one or more ginsn. This patch also adds skeleton support for printing ginsn in the listing output for debugging purposes. Since the current use-case of ginsn is to synthesize CFI, the x86 target needs to generate ginsns necessary for the following machine instructions only: - All change of flow instructions, including all conditional and unconditional branches, call and return from functions. - All register saves and unsaves to the stack. - All instructions affecting the two registers that could potentially be used as the base register for CFA tracking. For SCFI, the base register for CFA tracking is limited to REG_SP and REG_FP only for now. The representation of ginsn is kept simple: - GAS instruction has GINSN_NUM_SRC_OPNDS (defined to be 2 at this time) number of source operands and one destination operand at this time. - GAS instruction uses DWARF register numbers in its representation and does not track register size. - GAS instructions carry location information (file name and line number). - GAS instructions are ID's with a natural number in order of their addtion to the list. This can be used as a proxy for the static program order of the corresponding machine instructions. Note that, GAS instruction (ginsn) format does not support GINSN_TYPE_PUSH and GINSN_TYPE_POP. Some architectures, like aarch64, do not have push and pop instructions, but rather STP/LDP/STR/LDR etc. instructions. Further these instructions have a variety of addressing modes, like offset, pre-indexing and post-indexing etc. Among other things, one of differences in these addressing modes is _when_ the addr register is updated with the result of the address calculation: before or after the memory operation. To best support such needs, the generic instructions like GINSN_TYPE_LOAD, GINSN_TYPE_STORE together with GINSN_TYPE_ADD, and GINSN_TYPE_SUB may be used. The functionality provided in ginsn.c and scfi.c is compiled in when a target defines TARGET_USE_SCFI and TARGET_USE_GINSN. This can be revisited later when there are other use-cases of creating ginsn's in GAS, apart from the current use-case of synthesizing CFI for hand-written asm. Support is added only for System V AMD64 ABI for ELF at this time. If the user enables SCFI with --32, GAS issues an error: "Fatal error: SCFI is not supported for this ABI" For synthesizing (DWARF) CFI, the SCFI machinery requires the programmer to adhere to some pre-requisites for their asm: - Hand-written asm block must begin with a .type foo, @function It is highly recommended to, additionally, also ensure that: - Hand-written asm block ends with a .size foo, .-foo The SCFI machinery encodes some rules which align with the standard calling convention specified by the ABI. Apart from the rules, the SCFI machinery employs some heuristics. For example: - The base register for CFA tracking may be either REG_SP or REG_FP. - If the base register for CFA tracking is REG_SP, the precise amount of stack usage (and hence, the value of REG_SP) must be known at all times. - If using dynamic stack allocation, the function must switch to FP-based CFA. This means using instructions like the following (in AMD64) in prologue: pushq %rbp movq %rsp, %rbp and analogous instructions in epilogue. - Save and Restore of callee-saved registers must be symmetrical. However, the SCFI machinery at this time only warns if any such asymmetry is seen. These heuristics/rules are architecture-independent and are meant to employed for all architectures/ABIs using SCFI in the future. gas/ * Makefile.am: Add new files. * Makefile.in: Regenerated. * as.c (defined): Handle documentation and listing option for ginsns and SCFI. * config/obj-elf.c (obj_elf_size): Invoke ginsn_data_end. (obj_elf_type): Invoke ginsn_data_begin. * config/tc-i386.c (x86_scfi_callee_saved_p): New function. (ginsn_prefix_66H_p): Likewise. (ginsn_dw2_regnum): Likewise. (x86_ginsn_addsub_reg_mem): Likewise. (x86_ginsn_addsub_mem_reg): Likewise. (x86_ginsn_alu_imm): Likewise. (x86_ginsn_move): Likewise. (x86_ginsn_lea): Likewise. (x86_ginsn_jump): Likewise. (x86_ginsn_jump_cond): Likewise. (x86_ginsn_enter): Likewise. (x86_ginsn_safe_to_skip): Likewise. (x86_ginsn_unhandled): Likewise. (x86_ginsn_new): New functionality to generate ginsns. (md_assemble): Invoke x86_ginsn_new. (s_insn): Likewise. (i386_target_format): Add hard error for usage of SCFI with non AMD64 ABIs. * config/tc-i386.h (TARGET_USE_GINSN): New definition. (TARGET_USE_SCFI): Likewise. (SCFI_MAX_REG_ID): Likewise. (REG_FP): Likewise. (REG_SP): Likewise. (SCFI_INIT_CFA_OFFSET): Likewise. (SCFI_CALLEE_SAVED_REG_P): Likewise. (x86_scfi_callee_saved_p): Likewise. * gas/listing.h (LISTING_GINSN_SCFI): New define for ginsn and SCFI. * gas/read.c (read_a_source_file): Close SCFI processing at end of file read. * gas/scfidw2gen.c (scfi_process_cfi_label): Add implementation. (scfi_process_cfi_signal_frame): Likewise. * subsegs.h (struct frch_ginsn_data): New forward declaration. (struct frchain): New member for ginsn data. * gas/subsegs.c (subseg_set_rest): Initialize the new member. * symbols.c (colon): Invoke ginsn_frob_label to convey user-defined labels to ginsn infrastructure. * ginsn.c: New file. * ginsn.h: New file. * scfi.c: New file. * scfi.h: New file.
2024-01-15 17:00:31 +08:00
#define TARGET_USE_GINSN 1
/* Allow GAS to synthesize DWARF CFI for hand-written asm.
PS: TARGET_USE_CFIPOP is a pre-condition. */
#define TARGET_USE_SCFI 1
/* Identify the maximum DWARF register number of all the registers being
tracked for SCFI. This is the last DWARF register number of the set
of SP, BP, and all callee-saved registers. For AMD64, this means
R15 (15). Use SCFI_CALLEE_SAVED_REG_P to identify which registers
are callee-saved from this set. */
#define SCFI_MAX_REG_ID 15
/* Some ABIs, like AMD64, use stack for call instruction. For such an ABI,
identify the initial (CFA) offset from RSP at the entry of function. */
#define SCFI_INIT_CFA_OFFSET 8
#define SCFI_CALLEE_SAVED_REG_P(dw2reg) x86_scfi_callee_saved_p (dw2reg)
extern bool x86_scfi_callee_saved_p (uint32_t dw2reg_num);
/* Whether SFrame stack trace info is supported. */
gas: generate .sframe from CFI directives Currently supported for x86_64 and aarch64 only. [PS: Currently, the compiler has not been adapted to generate ".cfi_sections" with ".sframe" in it. The newly added command line option of --gsframe provides an easy way to try out .sframe support in the toolchain.] gas interprets the CFI directives to generate DWARF-based .eh_frame info. These internal DWARF structures are now consumed by gen-sframe.[ch] sub-system to, in turn, create the SFrame unwind information. These internal DWARF structures are read-only for the purpose of SFrame unwind info generation. SFrame unwind info generation does not impact .eh_frame unwind info generation. Both .eh_frame and .sframe can co-exist in an ELF file, if so desired by the user. Recall that SFrame unwind information only contains the minimal necessary information to generate backtraces and does not provide information to recover all callee-saved registers. The reason being that callee-saved registers other than FP are not needed for stack unwinding, and hence are not included in the .sframe section. Consequently, gen-sframe.[ch] only needs to interpret a subset of DWARF opcodes in gas. More details follow. [Set 1, Interpreted] The following opcodes are interpreted: - DW_CFA_advance_loc - DW_CFA_def_cfa - DW_CFA_def_cfa_register - DW_CFA_def_cfa_offset - DW_CFA_offset - DW_CFA_remember_state - DW_CFA_restore_state - DW_CFA_restore [Set 2, Bypassed] The following opcodes are acknowledged but are not necessary for generating SFrame unwind info: - DW_CFA_undefined - DW_CFA_same_value Anything else apart from the two above-mentioned sets is skipped altogether. This means that any function containing a CFI directive not in Set 1 or Set 2 above, will not have any SFrame unwind information generated for them. Holes in instructions covered by FREs of a single FDE are not representable in the SFrame unwind format. As few examples, following opcodes are not processed for .sframe generation, and are skipped: - .cfi_personality* - .cfi_*lsda - .cfi_escape - .cfi_negate_ra_state - ... Not processing .cfi_escape, .cfi_negate_ra_state will cause SFrame unwind information to be absent for SFrame FDEs that contain these CFI directives, hence affecting the asynchronicity. x86-64 and aarch64 backends need to have a few new definitions and functions for .sframe generation. These provide gas with architecture specific information like the SP/FP/RA register numbers and an SFrame-specific ABI marker. Lastly, the patch also implements an optimization for size, where specific fragments containing SFrame FRE start address and SFrame FDE function are fixed up. This is similar to other similar optimizations in gas, where fragments are sized and fixed up when the associated symbols can be resolved. This optimization is controlled by a #define SFRAME_FRE_TYPE_SELECTION_OPT and should be easy to turn off if needed. The optimization is on by default for both x86_64 and aarch64. ChangeLog: * gas/Makefile.am: Include gen-sframe.c and sframe-opt.c. * gas/Makefile.in: Regenerated. * gas/as.h (enum _relax_state): Add new state rs_sframe. (sframe_estimate_size_before_relax): New function. (sframe_relax_frag): Likewise. (sframe_convert_frag): Likewise. * gas/config/tc-aarch64.c (aarch64_support_sframe_p): New definition. (aarch64_sframe_ra_tracking_p): Likewise. (aarch64_sframe_cfa_ra_offset): Likewise. (aarch64_sframe_get_abi_arch): Likewise. (md_begin): Set values of sp/fp/ra registers. * gas/config/tc-aarch64.h (aarch64_support_sframe_p): New declaration. (support_sframe_p): Likewise. (SFRAME_CFA_SP_REG): Likewise. (SFRAME_CFA_FP_REG): Likewise. (SFRAME_CFA_RA_REG): Likewise. (aarch64_sframe_ra_tracking_p): Likewise. (sframe_ra_tracking_p): Likewise. (aarch64_sframe_cfa_ra_offset): Likewise. (sframe_cfa_ra_offset): Likewise. (aarch64_sframe_get_abi_arch): Likewise. (sframe_get_abi_arch): Likewise. * gas/config/tc-i386.c (x86_support_sframe_p): New definition. (x86_sframe_ra_tracking_p): Likewise. (x86_sframe_cfa_ra_offset): Likewise. (x86_sframe_get_abi_arch): Likewise. * gas/config/tc-i386.h (x86_support_sframe_p): New declaration. (support_sframe_p): Likewise. (SFRAME_CFA_SP_REG): Likewise. (SFRAME_CFA_FP_REG): Likewise. (x86_sframe_ra_tracking_p): Likewise. (sframe_ra_tracking_p): Likewise. (x86_sframe_cfa_ra_offset): Likewise. (sframe_cfa_ra_offset): Likewise. (x86_sframe_get_abi_arch): Likewise. (sframe_get_abi_arch): Likewise. * gas/config/tc-xtensa.c (unrelaxed_frag_max_size): Add case for rs_sframe. * gas/doc/as.texi: Add .sframe to the documentation for .cfi_sections. * gas/dw2gencfi.c (cfi_finish): Create a .sframe section. * gas/dw2gencfi.h (CFI_EMIT_sframe): New definition. * gas/write.c (cvt_frag_to_fill): Handle rs_sframe. (relax_segment): Likewise. * gas/gen-sframe.c: New file. * gas/gen-sframe.h: New file. * gas/sframe-opt.c: New file.
2022-11-16 07:06:46 +08:00
extern bool x86_support_sframe_p (void);
#define support_sframe_p x86_support_sframe_p
/* The stack pointer DWARF register number for SFrame CFA tracking. */
gas: generate .sframe from CFI directives Currently supported for x86_64 and aarch64 only. [PS: Currently, the compiler has not been adapted to generate ".cfi_sections" with ".sframe" in it. The newly added command line option of --gsframe provides an easy way to try out .sframe support in the toolchain.] gas interprets the CFI directives to generate DWARF-based .eh_frame info. These internal DWARF structures are now consumed by gen-sframe.[ch] sub-system to, in turn, create the SFrame unwind information. These internal DWARF structures are read-only for the purpose of SFrame unwind info generation. SFrame unwind info generation does not impact .eh_frame unwind info generation. Both .eh_frame and .sframe can co-exist in an ELF file, if so desired by the user. Recall that SFrame unwind information only contains the minimal necessary information to generate backtraces and does not provide information to recover all callee-saved registers. The reason being that callee-saved registers other than FP are not needed for stack unwinding, and hence are not included in the .sframe section. Consequently, gen-sframe.[ch] only needs to interpret a subset of DWARF opcodes in gas. More details follow. [Set 1, Interpreted] The following opcodes are interpreted: - DW_CFA_advance_loc - DW_CFA_def_cfa - DW_CFA_def_cfa_register - DW_CFA_def_cfa_offset - DW_CFA_offset - DW_CFA_remember_state - DW_CFA_restore_state - DW_CFA_restore [Set 2, Bypassed] The following opcodes are acknowledged but are not necessary for generating SFrame unwind info: - DW_CFA_undefined - DW_CFA_same_value Anything else apart from the two above-mentioned sets is skipped altogether. This means that any function containing a CFI directive not in Set 1 or Set 2 above, will not have any SFrame unwind information generated for them. Holes in instructions covered by FREs of a single FDE are not representable in the SFrame unwind format. As few examples, following opcodes are not processed for .sframe generation, and are skipped: - .cfi_personality* - .cfi_*lsda - .cfi_escape - .cfi_negate_ra_state - ... Not processing .cfi_escape, .cfi_negate_ra_state will cause SFrame unwind information to be absent for SFrame FDEs that contain these CFI directives, hence affecting the asynchronicity. x86-64 and aarch64 backends need to have a few new definitions and functions for .sframe generation. These provide gas with architecture specific information like the SP/FP/RA register numbers and an SFrame-specific ABI marker. Lastly, the patch also implements an optimization for size, where specific fragments containing SFrame FRE start address and SFrame FDE function are fixed up. This is similar to other similar optimizations in gas, where fragments are sized and fixed up when the associated symbols can be resolved. This optimization is controlled by a #define SFRAME_FRE_TYPE_SELECTION_OPT and should be easy to turn off if needed. The optimization is on by default for both x86_64 and aarch64. ChangeLog: * gas/Makefile.am: Include gen-sframe.c and sframe-opt.c. * gas/Makefile.in: Regenerated. * gas/as.h (enum _relax_state): Add new state rs_sframe. (sframe_estimate_size_before_relax): New function. (sframe_relax_frag): Likewise. (sframe_convert_frag): Likewise. * gas/config/tc-aarch64.c (aarch64_support_sframe_p): New definition. (aarch64_sframe_ra_tracking_p): Likewise. (aarch64_sframe_cfa_ra_offset): Likewise. (aarch64_sframe_get_abi_arch): Likewise. (md_begin): Set values of sp/fp/ra registers. * gas/config/tc-aarch64.h (aarch64_support_sframe_p): New declaration. (support_sframe_p): Likewise. (SFRAME_CFA_SP_REG): Likewise. (SFRAME_CFA_FP_REG): Likewise. (SFRAME_CFA_RA_REG): Likewise. (aarch64_sframe_ra_tracking_p): Likewise. (sframe_ra_tracking_p): Likewise. (aarch64_sframe_cfa_ra_offset): Likewise. (sframe_cfa_ra_offset): Likewise. (aarch64_sframe_get_abi_arch): Likewise. (sframe_get_abi_arch): Likewise. * gas/config/tc-i386.c (x86_support_sframe_p): New definition. (x86_sframe_ra_tracking_p): Likewise. (x86_sframe_cfa_ra_offset): Likewise. (x86_sframe_get_abi_arch): Likewise. * gas/config/tc-i386.h (x86_support_sframe_p): New declaration. (support_sframe_p): Likewise. (SFRAME_CFA_SP_REG): Likewise. (SFRAME_CFA_FP_REG): Likewise. (x86_sframe_ra_tracking_p): Likewise. (sframe_ra_tracking_p): Likewise. (x86_sframe_cfa_ra_offset): Likewise. (sframe_cfa_ra_offset): Likewise. (x86_sframe_get_abi_arch): Likewise. (sframe_get_abi_arch): Likewise. * gas/config/tc-xtensa.c (unrelaxed_frag_max_size): Add case for rs_sframe. * gas/doc/as.texi: Add .sframe to the documentation for .cfi_sections. * gas/dw2gencfi.c (cfi_finish): Create a .sframe section. * gas/dw2gencfi.h (CFI_EMIT_sframe): New definition. * gas/write.c (cvt_frag_to_fill): Handle rs_sframe. (relax_segment): Likewise. * gas/gen-sframe.c: New file. * gas/gen-sframe.h: New file. * gas/sframe-opt.c: New file.
2022-11-16 07:06:46 +08:00
extern unsigned int x86_sframe_cfa_sp_reg;
#define SFRAME_CFA_SP_REG x86_sframe_cfa_sp_reg
/* The frame pointer DWARF register number for SFrame CFA and FP tracking. */
gas: generate .sframe from CFI directives Currently supported for x86_64 and aarch64 only. [PS: Currently, the compiler has not been adapted to generate ".cfi_sections" with ".sframe" in it. The newly added command line option of --gsframe provides an easy way to try out .sframe support in the toolchain.] gas interprets the CFI directives to generate DWARF-based .eh_frame info. These internal DWARF structures are now consumed by gen-sframe.[ch] sub-system to, in turn, create the SFrame unwind information. These internal DWARF structures are read-only for the purpose of SFrame unwind info generation. SFrame unwind info generation does not impact .eh_frame unwind info generation. Both .eh_frame and .sframe can co-exist in an ELF file, if so desired by the user. Recall that SFrame unwind information only contains the minimal necessary information to generate backtraces and does not provide information to recover all callee-saved registers. The reason being that callee-saved registers other than FP are not needed for stack unwinding, and hence are not included in the .sframe section. Consequently, gen-sframe.[ch] only needs to interpret a subset of DWARF opcodes in gas. More details follow. [Set 1, Interpreted] The following opcodes are interpreted: - DW_CFA_advance_loc - DW_CFA_def_cfa - DW_CFA_def_cfa_register - DW_CFA_def_cfa_offset - DW_CFA_offset - DW_CFA_remember_state - DW_CFA_restore_state - DW_CFA_restore [Set 2, Bypassed] The following opcodes are acknowledged but are not necessary for generating SFrame unwind info: - DW_CFA_undefined - DW_CFA_same_value Anything else apart from the two above-mentioned sets is skipped altogether. This means that any function containing a CFI directive not in Set 1 or Set 2 above, will not have any SFrame unwind information generated for them. Holes in instructions covered by FREs of a single FDE are not representable in the SFrame unwind format. As few examples, following opcodes are not processed for .sframe generation, and are skipped: - .cfi_personality* - .cfi_*lsda - .cfi_escape - .cfi_negate_ra_state - ... Not processing .cfi_escape, .cfi_negate_ra_state will cause SFrame unwind information to be absent for SFrame FDEs that contain these CFI directives, hence affecting the asynchronicity. x86-64 and aarch64 backends need to have a few new definitions and functions for .sframe generation. These provide gas with architecture specific information like the SP/FP/RA register numbers and an SFrame-specific ABI marker. Lastly, the patch also implements an optimization for size, where specific fragments containing SFrame FRE start address and SFrame FDE function are fixed up. This is similar to other similar optimizations in gas, where fragments are sized and fixed up when the associated symbols can be resolved. This optimization is controlled by a #define SFRAME_FRE_TYPE_SELECTION_OPT and should be easy to turn off if needed. The optimization is on by default for both x86_64 and aarch64. ChangeLog: * gas/Makefile.am: Include gen-sframe.c and sframe-opt.c. * gas/Makefile.in: Regenerated. * gas/as.h (enum _relax_state): Add new state rs_sframe. (sframe_estimate_size_before_relax): New function. (sframe_relax_frag): Likewise. (sframe_convert_frag): Likewise. * gas/config/tc-aarch64.c (aarch64_support_sframe_p): New definition. (aarch64_sframe_ra_tracking_p): Likewise. (aarch64_sframe_cfa_ra_offset): Likewise. (aarch64_sframe_get_abi_arch): Likewise. (md_begin): Set values of sp/fp/ra registers. * gas/config/tc-aarch64.h (aarch64_support_sframe_p): New declaration. (support_sframe_p): Likewise. (SFRAME_CFA_SP_REG): Likewise. (SFRAME_CFA_FP_REG): Likewise. (SFRAME_CFA_RA_REG): Likewise. (aarch64_sframe_ra_tracking_p): Likewise. (sframe_ra_tracking_p): Likewise. (aarch64_sframe_cfa_ra_offset): Likewise. (sframe_cfa_ra_offset): Likewise. (aarch64_sframe_get_abi_arch): Likewise. (sframe_get_abi_arch): Likewise. * gas/config/tc-i386.c (x86_support_sframe_p): New definition. (x86_sframe_ra_tracking_p): Likewise. (x86_sframe_cfa_ra_offset): Likewise. (x86_sframe_get_abi_arch): Likewise. * gas/config/tc-i386.h (x86_support_sframe_p): New declaration. (support_sframe_p): Likewise. (SFRAME_CFA_SP_REG): Likewise. (SFRAME_CFA_FP_REG): Likewise. (x86_sframe_ra_tracking_p): Likewise. (sframe_ra_tracking_p): Likewise. (x86_sframe_cfa_ra_offset): Likewise. (sframe_cfa_ra_offset): Likewise. (x86_sframe_get_abi_arch): Likewise. (sframe_get_abi_arch): Likewise. * gas/config/tc-xtensa.c (unrelaxed_frag_max_size): Add case for rs_sframe. * gas/doc/as.texi: Add .sframe to the documentation for .cfi_sections. * gas/dw2gencfi.c (cfi_finish): Create a .sframe section. * gas/dw2gencfi.h (CFI_EMIT_sframe): New definition. * gas/write.c (cvt_frag_to_fill): Handle rs_sframe. (relax_segment): Likewise. * gas/gen-sframe.c: New file. * gas/gen-sframe.h: New file. * gas/sframe-opt.c: New file.
2022-11-16 07:06:46 +08:00
extern unsigned int x86_sframe_cfa_fp_reg;
#define SFRAME_CFA_FP_REG x86_sframe_cfa_fp_reg
/* Whether SFrame return address tracking is needed. */
gas: generate .sframe from CFI directives Currently supported for x86_64 and aarch64 only. [PS: Currently, the compiler has not been adapted to generate ".cfi_sections" with ".sframe" in it. The newly added command line option of --gsframe provides an easy way to try out .sframe support in the toolchain.] gas interprets the CFI directives to generate DWARF-based .eh_frame info. These internal DWARF structures are now consumed by gen-sframe.[ch] sub-system to, in turn, create the SFrame unwind information. These internal DWARF structures are read-only for the purpose of SFrame unwind info generation. SFrame unwind info generation does not impact .eh_frame unwind info generation. Both .eh_frame and .sframe can co-exist in an ELF file, if so desired by the user. Recall that SFrame unwind information only contains the minimal necessary information to generate backtraces and does not provide information to recover all callee-saved registers. The reason being that callee-saved registers other than FP are not needed for stack unwinding, and hence are not included in the .sframe section. Consequently, gen-sframe.[ch] only needs to interpret a subset of DWARF opcodes in gas. More details follow. [Set 1, Interpreted] The following opcodes are interpreted: - DW_CFA_advance_loc - DW_CFA_def_cfa - DW_CFA_def_cfa_register - DW_CFA_def_cfa_offset - DW_CFA_offset - DW_CFA_remember_state - DW_CFA_restore_state - DW_CFA_restore [Set 2, Bypassed] The following opcodes are acknowledged but are not necessary for generating SFrame unwind info: - DW_CFA_undefined - DW_CFA_same_value Anything else apart from the two above-mentioned sets is skipped altogether. This means that any function containing a CFI directive not in Set 1 or Set 2 above, will not have any SFrame unwind information generated for them. Holes in instructions covered by FREs of a single FDE are not representable in the SFrame unwind format. As few examples, following opcodes are not processed for .sframe generation, and are skipped: - .cfi_personality* - .cfi_*lsda - .cfi_escape - .cfi_negate_ra_state - ... Not processing .cfi_escape, .cfi_negate_ra_state will cause SFrame unwind information to be absent for SFrame FDEs that contain these CFI directives, hence affecting the asynchronicity. x86-64 and aarch64 backends need to have a few new definitions and functions for .sframe generation. These provide gas with architecture specific information like the SP/FP/RA register numbers and an SFrame-specific ABI marker. Lastly, the patch also implements an optimization for size, where specific fragments containing SFrame FRE start address and SFrame FDE function are fixed up. This is similar to other similar optimizations in gas, where fragments are sized and fixed up when the associated symbols can be resolved. This optimization is controlled by a #define SFRAME_FRE_TYPE_SELECTION_OPT and should be easy to turn off if needed. The optimization is on by default for both x86_64 and aarch64. ChangeLog: * gas/Makefile.am: Include gen-sframe.c and sframe-opt.c. * gas/Makefile.in: Regenerated. * gas/as.h (enum _relax_state): Add new state rs_sframe. (sframe_estimate_size_before_relax): New function. (sframe_relax_frag): Likewise. (sframe_convert_frag): Likewise. * gas/config/tc-aarch64.c (aarch64_support_sframe_p): New definition. (aarch64_sframe_ra_tracking_p): Likewise. (aarch64_sframe_cfa_ra_offset): Likewise. (aarch64_sframe_get_abi_arch): Likewise. (md_begin): Set values of sp/fp/ra registers. * gas/config/tc-aarch64.h (aarch64_support_sframe_p): New declaration. (support_sframe_p): Likewise. (SFRAME_CFA_SP_REG): Likewise. (SFRAME_CFA_FP_REG): Likewise. (SFRAME_CFA_RA_REG): Likewise. (aarch64_sframe_ra_tracking_p): Likewise. (sframe_ra_tracking_p): Likewise. (aarch64_sframe_cfa_ra_offset): Likewise. (sframe_cfa_ra_offset): Likewise. (aarch64_sframe_get_abi_arch): Likewise. (sframe_get_abi_arch): Likewise. * gas/config/tc-i386.c (x86_support_sframe_p): New definition. (x86_sframe_ra_tracking_p): Likewise. (x86_sframe_cfa_ra_offset): Likewise. (x86_sframe_get_abi_arch): Likewise. * gas/config/tc-i386.h (x86_support_sframe_p): New declaration. (support_sframe_p): Likewise. (SFRAME_CFA_SP_REG): Likewise. (SFRAME_CFA_FP_REG): Likewise. (x86_sframe_ra_tracking_p): Likewise. (sframe_ra_tracking_p): Likewise. (x86_sframe_cfa_ra_offset): Likewise. (sframe_cfa_ra_offset): Likewise. (x86_sframe_get_abi_arch): Likewise. (sframe_get_abi_arch): Likewise. * gas/config/tc-xtensa.c (unrelaxed_frag_max_size): Add case for rs_sframe. * gas/doc/as.texi: Add .sframe to the documentation for .cfi_sections. * gas/dw2gencfi.c (cfi_finish): Create a .sframe section. * gas/dw2gencfi.h (CFI_EMIT_sframe): New definition. * gas/write.c (cvt_frag_to_fill): Handle rs_sframe. (relax_segment): Likewise. * gas/gen-sframe.c: New file. * gas/gen-sframe.h: New file. * gas/sframe-opt.c: New file.
2022-11-16 07:06:46 +08:00
extern bool x86_sframe_ra_tracking_p (void);
#define sframe_ra_tracking_p x86_sframe_ra_tracking_p
/* The fixed offset from CFA for SFrame to recover the return address.
(useful only when SFrame RA tracking is not needed). */
gas: generate .sframe from CFI directives Currently supported for x86_64 and aarch64 only. [PS: Currently, the compiler has not been adapted to generate ".cfi_sections" with ".sframe" in it. The newly added command line option of --gsframe provides an easy way to try out .sframe support in the toolchain.] gas interprets the CFI directives to generate DWARF-based .eh_frame info. These internal DWARF structures are now consumed by gen-sframe.[ch] sub-system to, in turn, create the SFrame unwind information. These internal DWARF structures are read-only for the purpose of SFrame unwind info generation. SFrame unwind info generation does not impact .eh_frame unwind info generation. Both .eh_frame and .sframe can co-exist in an ELF file, if so desired by the user. Recall that SFrame unwind information only contains the minimal necessary information to generate backtraces and does not provide information to recover all callee-saved registers. The reason being that callee-saved registers other than FP are not needed for stack unwinding, and hence are not included in the .sframe section. Consequently, gen-sframe.[ch] only needs to interpret a subset of DWARF opcodes in gas. More details follow. [Set 1, Interpreted] The following opcodes are interpreted: - DW_CFA_advance_loc - DW_CFA_def_cfa - DW_CFA_def_cfa_register - DW_CFA_def_cfa_offset - DW_CFA_offset - DW_CFA_remember_state - DW_CFA_restore_state - DW_CFA_restore [Set 2, Bypassed] The following opcodes are acknowledged but are not necessary for generating SFrame unwind info: - DW_CFA_undefined - DW_CFA_same_value Anything else apart from the two above-mentioned sets is skipped altogether. This means that any function containing a CFI directive not in Set 1 or Set 2 above, will not have any SFrame unwind information generated for them. Holes in instructions covered by FREs of a single FDE are not representable in the SFrame unwind format. As few examples, following opcodes are not processed for .sframe generation, and are skipped: - .cfi_personality* - .cfi_*lsda - .cfi_escape - .cfi_negate_ra_state - ... Not processing .cfi_escape, .cfi_negate_ra_state will cause SFrame unwind information to be absent for SFrame FDEs that contain these CFI directives, hence affecting the asynchronicity. x86-64 and aarch64 backends need to have a few new definitions and functions for .sframe generation. These provide gas with architecture specific information like the SP/FP/RA register numbers and an SFrame-specific ABI marker. Lastly, the patch also implements an optimization for size, where specific fragments containing SFrame FRE start address and SFrame FDE function are fixed up. This is similar to other similar optimizations in gas, where fragments are sized and fixed up when the associated symbols can be resolved. This optimization is controlled by a #define SFRAME_FRE_TYPE_SELECTION_OPT and should be easy to turn off if needed. The optimization is on by default for both x86_64 and aarch64. ChangeLog: * gas/Makefile.am: Include gen-sframe.c and sframe-opt.c. * gas/Makefile.in: Regenerated. * gas/as.h (enum _relax_state): Add new state rs_sframe. (sframe_estimate_size_before_relax): New function. (sframe_relax_frag): Likewise. (sframe_convert_frag): Likewise. * gas/config/tc-aarch64.c (aarch64_support_sframe_p): New definition. (aarch64_sframe_ra_tracking_p): Likewise. (aarch64_sframe_cfa_ra_offset): Likewise. (aarch64_sframe_get_abi_arch): Likewise. (md_begin): Set values of sp/fp/ra registers. * gas/config/tc-aarch64.h (aarch64_support_sframe_p): New declaration. (support_sframe_p): Likewise. (SFRAME_CFA_SP_REG): Likewise. (SFRAME_CFA_FP_REG): Likewise. (SFRAME_CFA_RA_REG): Likewise. (aarch64_sframe_ra_tracking_p): Likewise. (sframe_ra_tracking_p): Likewise. (aarch64_sframe_cfa_ra_offset): Likewise. (sframe_cfa_ra_offset): Likewise. (aarch64_sframe_get_abi_arch): Likewise. (sframe_get_abi_arch): Likewise. * gas/config/tc-i386.c (x86_support_sframe_p): New definition. (x86_sframe_ra_tracking_p): Likewise. (x86_sframe_cfa_ra_offset): Likewise. (x86_sframe_get_abi_arch): Likewise. * gas/config/tc-i386.h (x86_support_sframe_p): New declaration. (support_sframe_p): Likewise. (SFRAME_CFA_SP_REG): Likewise. (SFRAME_CFA_FP_REG): Likewise. (x86_sframe_ra_tracking_p): Likewise. (sframe_ra_tracking_p): Likewise. (x86_sframe_cfa_ra_offset): Likewise. (sframe_cfa_ra_offset): Likewise. (x86_sframe_get_abi_arch): Likewise. (sframe_get_abi_arch): Likewise. * gas/config/tc-xtensa.c (unrelaxed_frag_max_size): Add case for rs_sframe. * gas/doc/as.texi: Add .sframe to the documentation for .cfi_sections. * gas/dw2gencfi.c (cfi_finish): Create a .sframe section. * gas/dw2gencfi.h (CFI_EMIT_sframe): New definition. * gas/write.c (cvt_frag_to_fill): Handle rs_sframe. (relax_segment): Likewise. * gas/gen-sframe.c: New file. * gas/gen-sframe.h: New file. * gas/sframe-opt.c: New file.
2022-11-16 07:06:46 +08:00
extern offsetT x86_sframe_cfa_ra_offset (void);
#define sframe_cfa_ra_offset x86_sframe_cfa_ra_offset
/* The abi/arch indentifier for SFrame. */
extern unsigned char x86_sframe_get_abi_arch (void);
#define sframe_get_abi_arch x86_sframe_get_abi_arch
#endif
#ifdef TE_PE
#define O_secrel O_md1
#define TC_DWARF2_EMIT_OFFSET tc_pe_dwarf2_emit_offset
void tc_pe_dwarf2_emit_offset (symbolS *, unsigned int);
#endif /* TE_PE */
gas/ 2009-04-20 Jan Beulich <jbeulich@novell.com> * Makefile.am: Add explicit dependency of tc-i386.o on tc-i386-intel.c. * Makefile.in: Likewise. * config/tc-i386.c (i386_finalize_immediate): Declare, broken out from i386_immediate. (i386_immediate): Slightly re-arrange, call i386_finalize_immediate. (i386_finalize_displacement): Declare, broken out from i386_displacement. (i386_displacement): Slightly re-arrange, call i386_finalize_displacement. (i386_intel_simplify, i386_intel_parse_name): Declare. (this_operand): Initialize to -1. (set_intel_syntax): Set expression rank for O_full_ptr. (md_assemble): Set this_operand back to -1 after parsing operands. (x86_cons): Negate intel_syntax to indicate state. Call i386_intel_simplify. (md_operand): Convert if to switch. Handle '[' for Intel syntax. (i386_intel_operand): Delete, including all helper functions and data. * config/tc-i386-intel.c: New file, all new code. * config/tc-i386.h (i386_operator): Declare. (md_operator): Define to i386_operator. (i386_need_index_operator): Declare. (md_need_index_operator): Define to i386_need_index_operator. (O_full_ptr): Define. gas/testsuite/ 2009-04-20 Jan Beulich <jbeulich@novell.com> * gas/i386/equ.s: Adjust. * gas/i386/equ.d: Remove reference to equ.e. * gas/i386/equ.e: Delete. * gas/i386/intel-expr.s: New. * gas/i386/intel-expr.d: New. * gas/i386/i386.exp: Run new test. * gas/i386/intel.s: Adjust. * gas/i386/intel.e: Remove no longer valid warning messages. * gas/i386/intel16.s: Adjust. * gas/i386/intel16.d: Remove reference to intel16.e. * gas/i386/intel16.e: Delete. * gas/i386/intelbad.s: Add more tests. * gas/i386/intelbad.l: Adjust. * gas/i386/intelok.s: Remove now unneeded equates. Add more tests. * gas/i386/intelok.d: Remove reference to intelok.e. Adjust. * gas/i386/intelok.e: Delete. * gas/i386/x86_64.s: Adjust. * gas/i386/x86_64.d: Remove reference to x86_64.e. * gas/i386/x86_64.e: Delete.
2009-04-20 14:31:50 +08:00
/* X_add_symbol:X_op_symbol (Intel mode only) */
#define O_full_ptr O_md2
#ifdef OBJ_MACH_O
#define TC_FORCE_RELOCATION(FIX) (obj_mach_o_force_reloc (FIX))
#define TC_FORCE_RELOCATION_SUB_SAME(FIX,SEG) \
(obj_mach_o_force_reloc_sub_same (FIX, SEG))
#define TC_FORCE_RELOCATION_SUB_LOCAL(FIX,SEG) \
(obj_mach_o_force_reloc_sub_local (FIX, SEG))
#define TC_VALIDATE_FIX_SUB(FIX, SEG) 1
#endif /* OBJ_MACH_O */
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#endif /* TC_I386 */