From 8e59b9f42374aaa641409b6469c8fe9245a33107 Mon Sep 17 00:00:00 2001 From: Jit Loon Lim Date: Wed, 17 May 2023 12:26:11 +0800 Subject: [PATCH] feat(intel): mailbox and SMC support for Agilex5 SoC FPGA This patch is used to enable mailbox and SMC support for Agilex5 SoC FPGA. 1. Enabled mailbox and SMC support. 2. Updated product name -> Agilex5 3. Updated register address based on y22ww52.2 RTL 4. Updated TSN register base address Signed-off-by: Jit Loon Lim Change-Id: I152bee5668b96ef599ded09945167f27a71f23fe --- .../soc/common/include/socfpga_mailbox.h | 14 +++++--- plat/intel/soc/common/soc/socfpga_emac.c | 2 +- plat/intel/soc/common/soc/socfpga_mailbox.c | 21 ++++++++--- plat/intel/soc/common/socfpga_sip_svc.c | 35 +++++++++++++++++++ 4 files changed, 61 insertions(+), 11 deletions(-) diff --git a/plat/intel/soc/common/include/socfpga_mailbox.h b/plat/intel/soc/common/include/socfpga_mailbox.h index 564b4eeb5..77d3af95c 100644 --- a/plat/intel/soc/common/include/socfpga_mailbox.h +++ b/plat/intel/soc/common/include/socfpga_mailbox.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2022, Intel Corporation. All rights reserved. + * Copyright (c) 2019-2023, Intel Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,8 +9,11 @@ #include - +#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 +#define MBOX_OFFSET 0x10a30000 +#else #define MBOX_OFFSET 0xffa30000 +#endif #define MBOX_ATF_CLIENT_ID 0x1U #define MBOX_MAX_JOB_ID 0xFU @@ -193,9 +196,9 @@ #define RSU_VERSION_ACMF_MASK 0xff00 /* Config Status Macros */ -#define CONFIG_STATUS_WORD_SIZE 16U -#define CONFIG_STATUS_FW_VER_OFFSET 1 -#define CONFIG_STATUS_FW_VER_MASK 0x00FFFFFF +#define CONFIG_STATUS_WORD_SIZE 16U +#define CONFIG_STATUS_FW_VER_OFFSET 1 +#define CONFIG_STATUS_FW_VER_MASK 0x00FFFFFF /* Data structure */ @@ -233,6 +236,7 @@ int iterate_resp(uint32_t mbox_resp_len, uint32_t *resp_buf, unsigned int *resp_len); void mailbox_reset_cold(void); +void mailbox_reset_warm(uint32_t reset_type); void mailbox_clear_response(void); int intel_mailbox_get_config_status(uint32_t cmd, bool init_done); diff --git a/plat/intel/soc/common/soc/socfpga_emac.c b/plat/intel/soc/common/soc/socfpga_emac.c index 02ff89e63..49c92c30f 100644 --- a/plat/intel/soc/common/soc/socfpga_emac.c +++ b/plat/intel/soc/common/soc/socfpga_emac.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020-2023, Intel Corporation. All rights reserved. + * Copyright (c) 2020-2022, Intel Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/plat/intel/soc/common/soc/socfpga_mailbox.c b/plat/intel/soc/common/soc/socfpga_mailbox.c index 525ac2b3f..d93fc8a5b 100644 --- a/plat/intel/soc/common/soc/socfpga_mailbox.c +++ b/plat/intel/soc/common/soc/socfpga_mailbox.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020-2023, Intel Corporation. All rights reserved. + * Copyright (c) 2020-2022, Intel Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -523,8 +523,18 @@ void mailbox_hps_qspi_enable(void) void mailbox_reset_cold(void) { mailbox_set_int(MBOX_INT_FLAG_COE | MBOX_INT_FLAG_RIE); - mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_REBOOT_HPS, NULL, 0U, - CMD_CASUAL, NULL, NULL); + + mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_REBOOT_HPS, 0U, 0U, + CMD_CASUAL, NULL, NULL); +} + +void mailbox_reset_warm(uint32_t reset_type) +{ + mailbox_set_int(MBOX_INT_FLAG_COE | MBOX_INT_FLAG_RIE); + + reset_type = 0x01; // Warm reset header data must be 1 + mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_REBOOT_HPS, &reset_type, 1U, + CMD_CASUAL, NULL, NULL); } int mailbox_rsu_get_spt_offset(uint32_t *resp_buf, unsigned int resp_buf_len) @@ -679,9 +689,10 @@ int mailbox_hwmon_readvolt(uint32_t chan, uint32_t *resp_buf) &resp_len); } -int mailbox_seu_err_status(uint32_t *resp_buf, uint32_t resp_buf_len) +int mailbox_seu_err_status(uint32_t *resp_buf, unsigned int resp_buf_len) { + return mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_SEU_ERR_READ, NULL, 0U, CMD_CASUAL, resp_buf, - &resp_buf_len);; + &resp_buf_len); } diff --git a/plat/intel/soc/common/socfpga_sip_svc.c b/plat/intel/soc/common/socfpga_sip_svc.c index 1a18ee1b4..c6530cf31 100644 --- a/plat/intel/soc/common/socfpga_sip_svc.c +++ b/plat/intel/soc/common/socfpga_sip_svc.c @@ -335,6 +335,7 @@ static int is_out_of_sec_range(uint64_t reg_addr) return 0; #endif +#if PLATFORM_MODEL != PLAT_SOCFPGA_AGILEX5 switch (reg_addr) { case(0xF8011100): /* ECCCTRL1 */ case(0xF8011104): /* ECCCTRL2 */ @@ -386,7 +387,41 @@ static int is_out_of_sec_range(uint64_t reg_addr) case(0xFFD12220): /* BOOT_SCRATCH_COLD8 */ case(0xFFD12224): /* BOOT_SCRATCH_COLD9 */ return 0; +#else + switch (reg_addr) { + case(0xF8011104): /* ECCCTRL2 */ + case(0xFFD12028): /* SDMMCGRP_CTRL */ + case(0xFFD120C4): /* NOC_IDLEREQ_SET */ + case(0xFFD120C8): /* NOC_IDLEREQ_CLR */ + case(0xFFD120D0): /* NOC_IDLEACK */ + + + case(SOCFPGA_MEMCTRL(ECCCTRL1)): /* ECCCTRL1 */ + case(SOCFPGA_MEMCTRL(ERRINTEN)): /* ERRINTEN */ + case(SOCFPGA_MEMCTRL(ERRINTENS)): /* ERRINTENS */ + case(SOCFPGA_MEMCTRL(ERRINTENR)): /* ERRINTENR */ + case(SOCFPGA_MEMCTRL(INTMODE)): /* INTMODE */ + case(SOCFPGA_MEMCTRL(INTSTAT)): /* INTSTAT */ + case(SOCFPGA_MEMCTRL(DIAGINTTEST)): /* DIAGINTTEST */ + case(SOCFPGA_MEMCTRL(DERRADDRA)): /* DERRADDRA */ + + case(SOCFPGA_SYSMGR(EMAC_0)): /* EMAC0 */ + case(SOCFPGA_SYSMGR(EMAC_1)): /* EMAC1 */ + case(SOCFPGA_SYSMGR(EMAC_2)): /* EMAC2 */ + case(SOCFPGA_SYSMGR(ECC_INTMASK_VALUE)): /* ECC_INT_MASK_VALUE */ + case(SOCFPGA_SYSMGR(ECC_INTMASK_SET)): /* ECC_INT_MASK_SET */ + case(SOCFPGA_SYSMGR(ECC_INTMASK_CLR)): /* ECC_INT_MASK_CLEAR */ + case(SOCFPGA_SYSMGR(ECC_INTMASK_SERR)): /* ECC_INTSTATUS_SERR */ + case(SOCFPGA_SYSMGR(ECC_INTMASK_DERR)): /* ECC_INTSTATUS_DERR */ + case(SOCFPGA_SYSMGR(NOC_TIMEOUT)): /* NOC_TIMEOUT */ + case(SOCFPGA_SYSMGR(NOC_IDLESTATUS)): /* NOC_IDLESTATUS */ + case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_0)): /* BOOT_SCRATCH_COLD0 */ + case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_1)): /* BOOT_SCRATCH_COLD1 */ + case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_8)): /* BOOT_SCRATCH_COLD8 */ + case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_9)): /* BOOT_SCRATCH_COLD9 */ + return 0; +#endif default: break; }