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Merge changes from topic "el3spmc-fix-v2.12-rc0" into integration

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* changes:
  feat(qemu): increase size of bl31
  fix(qemu): fix EL3-SPMC data store alignment
  fix(qemu): fix build error with spmd
This commit is contained in:
Olivier Deprez 2024-11-19 14:57:37 +01:00 committed by TrustedFirmware Code Review
commit 847d6f4ab9
2 changed files with 8 additions and 7 deletions
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13
plat/qemu/common/qemu_common.c
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@ -178,7 +178,7 @@ int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size)
*/
#define PLAT_SPMC_SHMEM_DATASTORE_SIZE 64 * 1024
uint8_t plat_spmc_shmem_datastore[PLAT_SPMC_SHMEM_DATASTORE_SIZE];
uint8_t plat_spmc_shmem_datastore[PLAT_SPMC_SHMEM_DATASTORE_SIZE] __aligned(2 * sizeof(long));
int plat_spmc_shmem_datastore_get(uint8_t **datastore, size_t *size)
{
@ -198,16 +198,17 @@ int plat_spmc_shmem_reclaim(struct ffa_mtd *desc)
}
#endif
#if defined(SPD_spmd) && (SPMC_AT_EL3 == 0)
/*
* A dummy implementation of the platform handler for Group0 secure interrupt.
*/
#if defined(SPD_spmd)
int plat_spmd_handle_group0_interrupt(uint32_t intid)
{
/*
* Currently, there are no sources of Group0 secure interrupt
* enabled for QEMU.
*/
(void)intid;
return -1;
}
#endif /*defined(SPD_spmd) && (SPMC_AT_EL3 == 0)*/
#endif /*defined(SPD_spmd)*/
#if ENABLE_RME
/*

2
plat/qemu/qemu/include/platform_def.h
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@ -150,7 +150,7 @@
* Put BL3-1 at the top of the Trusted SRAM. BL31_BASE is calculated using the
* current BL3-1 debug size plus a little space for growth.
*/
#define BL31_BASE (BL31_LIMIT - 0x60000)
#define BL31_BASE (BL31_LIMIT - 0x70000)
#define BL31_LIMIT (BL_RAM_BASE + BL_RAM_SIZE - FW_HANDOFF_SIZE)
#define BL31_PROGBITS_LIMIT BL1_RW_BASE