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feat(nxp-clk): set rate for clock fixed divider
Add set rate support for fixed divider clock modules of whose role is to reduce the source frequency by a factor. Change-Id: I8a29a2c5b1a829db0c396407c3517c9e66caaa93 Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
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@ -316,6 +316,30 @@ static int set_pll_div_freq(const struct s32cc_clk_obj *module, unsigned long ra
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return 0;
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}
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static int set_fixed_div_freq(const struct s32cc_clk_obj *module, unsigned long rate,
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unsigned long *orate, unsigned int *depth)
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{
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const struct s32cc_fixed_div *fdiv = s32cc_obj2fixeddiv(module);
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int ret;
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ret = update_stack_depth(depth);
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if (ret != 0) {
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return ret;
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}
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if (fdiv->parent == NULL) {
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ERROR("The divider doesn't have a valid parent\b");
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return -EINVAL;
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}
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ret = set_module_rate(fdiv->parent, rate * fdiv->rate_div, orate, depth);
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/* Update the output rate based on the parent's rate */
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*orate /= fdiv->rate_div;
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return ret;
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}
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static int set_module_rate(const struct s32cc_clk_obj *module,
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unsigned long rate, unsigned long *orate,
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unsigned int *depth)
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@ -340,9 +364,11 @@ static int set_module_rate(const struct s32cc_clk_obj *module,
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case s32cc_pll_out_div_t:
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ret = set_pll_div_freq(module, rate, orate, depth);
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break;
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case s32cc_fixed_div_t:
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ret = set_fixed_div_freq(module, rate, orate, depth);
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break;
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case s32cc_clkmux_t:
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case s32cc_shared_clkmux_t:
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case s32cc_fixed_div_t:
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ret = -ENOTSUP;
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break;
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default:
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@ -229,4 +229,12 @@ static inline struct s32cc_pll_out_div *s32cc_obj2plldiv(const struct s32cc_clk_
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return (struct s32cc_pll_out_div *)plldiv_addr;
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}
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static inline struct s32cc_fixed_div *s32cc_obj2fixeddiv(const struct s32cc_clk_obj *mod)
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{
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uintptr_t fdiv_addr;
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fdiv_addr = ((uintptr_t)mod) - offsetof(struct s32cc_fixed_div, desc);
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return (struct s32cc_fixed_div *)fdiv_addr;
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}
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#endif /* S32CC_CLK_MODULES_H */
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