mirror of
https://git.kernel.org/pub/scm/utils/mmc/mmc-utils.git
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c62dd8e415
Implements the alternative boot operation for eMMCs. Note the limitations of the help. This is mostly useful for testing purposes if you set up the boot partition configuration correctly. Usage: $ sudo dd if=/dev/mmcblk2boot0 of=bootdatammcblk count=2 2+0 records in 2+0 records out 1024 bytes (1.0 kB, 1.0 KiB) copied, 0.00482308 s, 212 kB/s $ sudo ./mmc boot_operation bootdata /dev/mmcblk2 $ diff -s bootdata bootdatammcblk Files bootdata and bootdatammcblk are identical Signed-off-by: Christian Loehle <cloehle@hyperstone.com> Reviewed-by: Avri Altman <avri.altman@wdc.com> Link: https://lore.kernel.org/r/f999a7ed7bb645948ac74d5d5341e913@hyperstone.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
253 lines
9.8 KiB
C
253 lines
9.8 KiB
C
/*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public
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* License v2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public
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* License along with this program; if not, write to the
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* Free Software Foundation, Inc., 59 Temple Place - Suite 330,
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* Boston, MA 021110-1307, USA.
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*
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* Modified to add field firmware update support,
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* those modifications are Copyright (c) 2016 SanDisk Corp.
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*/
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#include <linux/major.h>
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#include <linux/mmc/ioctl.h>
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/* From kernel linux/mmc/mmc.h */
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#define MMC_GO_IDLE_STATE 0 /* bc */
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#define MMC_GO_IDLE_STATE_ARG 0x0
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#define MMC_GO_PRE_IDLE_STATE_ARG 0xF0F0F0F0
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#define MMC_BOOT_INITIATION_ARG 0xFFFFFFFA
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#define MMC_SWITCH 6 /* ac [31:0] See below R1b */
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#define MMC_SEND_EXT_CSD 8 /* adtc R1 */
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#define MMC_SEND_STATUS 13 /* ac [31:16] RCA R1 */
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#define R1_SWITCH_ERROR (1 << 7) /* sx, c */
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#define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target to value */
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#define MMC_READ_MULTIPLE_BLOCK 18 /* adtc [31:0] data addr R1 */
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#define MMC_SET_BLOCK_COUNT 23 /* adtc [31:0] data addr R1 */
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#define MMC_WRITE_BLOCK 24 /* adtc [31:0] data addr R1 */
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#define MMC_WRITE_MULTIPLE_BLOCK 25 /* adtc R1 */
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#define MMC_SET_WRITE_PROT 28 /* ac [31:0] data addr R1b */
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#define MMC_CLEAR_WRITE_PROT 29 /* ac [31:0] data addr R1b */
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#define MMC_SEND_WRITE_PROT_TYPE 31 /* ac [31:0] data addr R1 */
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#define MMC_ERASE_GROUP_START 35 /* ac [31:0] data addr R1 */
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#define MMC_ERASE_GROUP_END 36 /* ac [31:0] data addr R1 */
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#define MMC_ERASE 38 /* ac [31] Secure request
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[30:16] set to 0
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[15] Force Garbage Collect request
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[14:2] set to 0
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[1] Discard Enable
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[0] Identify Write Blocks for
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Erase (or TRIM Enable) R1b */
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#define MMC_GEN_CMD 56 /* adtc [31:1] stuff bits.
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[0]: RD/WR1 R1 */
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#define R1_OUT_OF_RANGE (1 << 31) /* er, c */
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#define R1_ADDRESS_ERROR (1 << 30) /* erx, c */
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#define R1_BLOCK_LEN_ERROR (1 << 29) /* er, c */
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#define R1_ERASE_SEQ_ERROR (1 << 28) /* er, c */
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#define R1_ERASE_PARAM (1 << 27) /* ex, c */
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#define R1_WP_VIOLATION (1 << 26) /* erx, c */
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#define R1_CARD_IS_LOCKED (1 << 25) /* sx, a */
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#define R1_LOCK_UNLOCK_FAILED (1 << 24) /* erx, c */
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#define R1_COM_CRC_ERROR (1 << 23) /* er, b */
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#define R1_ILLEGAL_COMMAND (1 << 22) /* er, b */
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#define R1_CARD_ECC_FAILED (1 << 21) /* ex, c */
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#define R1_CC_ERROR (1 << 20) /* erx, c */
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#define R1_ERROR (1 << 19) /* erx, c */
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#define R1_CID_CSD_OVERWRITE (1 << 16) /* erx, c, CID/CSD overwrite */
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#define R1_WP_ERASE_SKIP (1 << 15) /* sx, c */
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#define R1_CARD_ECC_DISABLED (1 << 14) /* sx, a */
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#define R1_ERASE_RESET (1 << 13) /* sr, c */
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#define R1_READY_FOR_DATA (1 << 8) /* sx, a */
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#define R1_EXCEPTION_EVENT (1 << 6) /* sr, a */
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#define R1_APP_CMD (1 << 5) /* sr, c */
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/*
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* EXT_CSD fields
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*/
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#define EXT_CSD_S_CMD_SET 504
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#define EXT_CSD_HPI_FEATURE 503
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#define EXT_CSD_BKOPS_SUPPORT 502 /* RO */
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#define EXT_CSD_SUPPORTED_MODES 493 /* RO */
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#define EXT_CSD_FFU_FEATURES 492 /* RO */
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#define EXT_CSD_FFU_ARG_3 490 /* RO */
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#define EXT_CSD_FFU_ARG_2 489 /* RO */
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#define EXT_CSD_FFU_ARG_1 488 /* RO */
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#define EXT_CSD_FFU_ARG_0 487 /* RO */
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#define EXT_CSD_CMDQ_DEPTH 307 /* RO */
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#define EXT_CSD_CMDQ_SUPPORT 308 /* RO */
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#define EXT_CSD_NUM_OF_FW_SEC_PROG_3 305 /* RO */
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#define EXT_CSD_NUM_OF_FW_SEC_PROG_2 304 /* RO */
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#define EXT_CSD_NUM_OF_FW_SEC_PROG_1 303 /* RO */
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#define EXT_CSD_NUM_OF_FW_SEC_PROG_0 302 /* RO */
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#define EXT_CSD_DEVICE_LIFE_TIME_EST_TYP_B 269 /* RO */
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#define EXT_CSD_DEVICE_LIFE_TIME_EST_TYP_A 268 /* RO */
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#define EXT_CSD_PRE_EOL_INFO 267 /* RO */
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#define EXT_CSD_FIRMWARE_VERSION 254 /* RO */
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#define EXT_CSD_CACHE_SIZE_3 252
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#define EXT_CSD_CACHE_SIZE_2 251
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#define EXT_CSD_CACHE_SIZE_1 250
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#define EXT_CSD_CACHE_SIZE_0 249
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#define EXT_CSD_SEC_FEATURE_SUPPORT 231
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#define EXT_CSD_BOOT_INFO 228 /* R/W */
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#define EXT_CSD_BOOT_MULT 226 /* RO */
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#define EXT_CSD_HC_ERASE_GRP_SIZE 224
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#define EXT_CSD_HC_WP_GRP_SIZE 221
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#define EXT_CSD_SEC_COUNT_3 215
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#define EXT_CSD_SEC_COUNT_2 214
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#define EXT_CSD_SEC_COUNT_1 213
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#define EXT_CSD_SEC_COUNT_0 212
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#define EXT_CSD_PART_SWITCH_TIME 199
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#define EXT_CSD_REV 192
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#define EXT_CSD_BOOT_CFG 179
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#define EXT_CSD_PART_CONFIG 179
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#define EXT_CSD_BOOT_BUS_CONDITIONS 177
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#define EXT_CSD_ERASE_GROUP_DEF 175
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#define EXT_CSD_BOOT_WP_STATUS 174
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#define EXT_CSD_BOOT_WP 173
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#define EXT_CSD_USER_WP 171
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#define EXT_CSD_FW_CONFIG 169 /* R/W */
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#define EXT_CSD_WR_REL_SET 167
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#define EXT_CSD_WR_REL_PARAM 166
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#define EXT_CSD_SANITIZE_START 165
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#define EXT_CSD_BKOPS_EN 163 /* R/W */
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#define EXT_CSD_RST_N_FUNCTION 162 /* R/W */
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#define EXT_CSD_PARTITIONING_SUPPORT 160 /* RO */
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#define EXT_CSD_MAX_ENH_SIZE_MULT_2 159
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#define EXT_CSD_MAX_ENH_SIZE_MULT_1 158
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#define EXT_CSD_MAX_ENH_SIZE_MULT_0 157
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#define EXT_CSD_PARTITIONS_ATTRIBUTE 156 /* R/W */
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#define EXT_CSD_PARTITION_SETTING_COMPLETED 155 /* R/W */
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#define EXT_CSD_GP_SIZE_MULT_4_2 154
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#define EXT_CSD_GP_SIZE_MULT_4_1 153
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#define EXT_CSD_GP_SIZE_MULT_4_0 152
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#define EXT_CSD_GP_SIZE_MULT_3_2 151
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#define EXT_CSD_GP_SIZE_MULT_3_1 150
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#define EXT_CSD_GP_SIZE_MULT_3_0 149
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#define EXT_CSD_GP_SIZE_MULT_2_2 148
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#define EXT_CSD_GP_SIZE_MULT_2_1 147
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#define EXT_CSD_GP_SIZE_MULT_2_0 146
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#define EXT_CSD_GP_SIZE_MULT_1_2 145
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#define EXT_CSD_GP_SIZE_MULT_1_1 144
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#define EXT_CSD_GP_SIZE_MULT_1_0 143
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#define EXT_CSD_ENH_SIZE_MULT_2 142
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#define EXT_CSD_ENH_SIZE_MULT_1 141
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#define EXT_CSD_ENH_SIZE_MULT_0 140
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#define EXT_CSD_ENH_START_ADDR_3 139
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#define EXT_CSD_ENH_START_ADDR_2 138
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#define EXT_CSD_ENH_START_ADDR_1 137
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#define EXT_CSD_ENH_START_ADDR_0 136
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#define EXT_CSD_NATIVE_SECTOR_SIZE 63 /* R */
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#define EXT_CSD_USE_NATIVE_SECTOR 62 /* R/W */
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#define EXT_CSD_DATA_SECTOR_SIZE 61 /* R */
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#define EXT_CSD_EXT_PARTITIONS_ATTRIBUTE_1 53
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#define EXT_CSD_EXT_PARTITIONS_ATTRIBUTE_0 52
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#define EXT_CSD_CACHE_CTRL 33
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#define EXT_CSD_MODE_CONFIG 30
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#define EXT_CSD_MODE_OPERATION_CODES 29 /* W */
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#define EXT_CSD_FFU_STATUS 26 /* R */
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#define EXT_CSD_SECURE_REMOVAL_TYPE 16 /* R/W */
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#define EXT_CSD_CMDQ_MODE_EN 15 /* R/W */
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/*
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* WR_REL_PARAM field definitions
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*/
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#define HS_CTRL_REL (1<<0)
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#define EN_REL_WR (1<<2)
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/*
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* BKOPS_EN field definitions
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*/
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#define BKOPS_MAN_ENABLE (1<<0)
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#define BKOPS_AUTO_ENABLE (1<<1)
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/*
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* EXT_CSD field definitions
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*/
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#define EXT_CSD_CONFIG_SECRM_TYPE (0x30)
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#define EXT_CSD_SUPPORTED_SECRM_TYPE (0x0f)
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#define EXT_CSD_FFU_INSTALL (0x01)
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#define EXT_CSD_FFU_MODE (0x01)
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#define EXT_CSD_NORMAL_MODE (0x00)
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#define EXT_CSD_FFU (1<<0)
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#define EXT_CSD_UPDATE_DISABLE (1<<0)
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#define EXT_CSD_HPI_SUPP (1<<0)
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#define EXT_CSD_HPI_IMPL (1<<1)
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#define EXT_CSD_CMD_SET_NORMAL (1<<0)
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/* NOTE: The eMMC spec calls the partitions "Area 1" and "Area 2", but Linux
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* calls them mmcblk0boot0 and mmcblk0boot1. To avoid confustion between the two
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* numbering schemes, this tool uses 0 and 1 throughout. */
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#define EXT_CSD_BOOT_WP_S_AREA_1_PERM (0x08)
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#define EXT_CSD_BOOT_WP_S_AREA_1_PWR (0x04)
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#define EXT_CSD_BOOT_WP_S_AREA_0_PERM (0x02)
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#define EXT_CSD_BOOT_WP_S_AREA_0_PWR (0x01)
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#define EXT_CSD_BOOT_WP_B_SEC_WP_SEL (0x80)
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#define EXT_CSD_BOOT_WP_B_PWR_WP_DIS (0x40)
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#define EXT_CSD_BOOT_WP_B_PERM_WP_DIS (0x10)
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#define EXT_CSD_BOOT_WP_B_PERM_WP_SEC_SEL (0x08)
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#define EXT_CSD_BOOT_WP_B_PERM_WP_EN (0x04)
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#define EXT_CSD_BOOT_WP_B_PWR_WP_SEC_SEL (0x02)
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#define EXT_CSD_BOOT_WP_B_PWR_WP_EN (0x01)
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#define EXT_CSD_BOOT_INFO_HS_MODE (1<<2)
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#define EXT_CSD_BOOT_INFO_DDR_DDR (1<<1)
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#define EXT_CSD_BOOT_INFO_ALT (1<<0)
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#define EXT_CSD_BOOT_CFG_ACK (1<<6)
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#define EXT_CSD_BOOT_CFG_EN (0x38)
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#define EXT_CSD_BOOT_CFG_ACC (0x07)
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#define EXT_CSD_RST_N_EN_MASK (0x03)
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#define EXT_CSD_HW_RESET_EN (0x01)
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#define EXT_CSD_HW_RESET_DIS (0x02)
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#define EXT_CSD_PART_CONFIG_ACC_MASK (0x7)
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#define EXT_CSD_PART_CONFIG_ACC_NONE (0x0)
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#define EXT_CSD_PART_CONFIG_ACC_BOOT0 (0x1)
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#define EXT_CSD_PART_CONFIG_ACC_BOOT1 (0x2)
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#define EXT_CSD_PART_CONFIG_ACC_USER_AREA (0x7)
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#define EXT_CSD_PART_CONFIG_ACC_ACK (0x40)
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#define EXT_CSD_PARTITIONING_EN (1<<0)
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#define EXT_CSD_ENH_ATTRIBUTE_EN (1<<1)
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#define EXT_CSD_ENH_4 (1<<4)
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#define EXT_CSD_ENH_3 (1<<3)
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#define EXT_CSD_ENH_2 (1<<2)
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#define EXT_CSD_ENH_1 (1<<1)
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#define EXT_CSD_ENH_USR (1<<0)
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#define EXT_CSD_REV_V5_1 8
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#define EXT_CSD_REV_V5_0 7
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#define EXT_CSD_REV_V4_5 6
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#define EXT_CSD_REV_V4_4_1 5
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#define EXT_CSD_REV_V4_3 3
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#define EXT_CSD_REV_V4_2 2
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#define EXT_CSD_REV_V4_1 1
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#define EXT_CSD_REV_V4_0 0
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#define EXT_CSD_SEC_GB_CL_EN (1<<4)
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#define EXT_CSD_SEC_ER_EN (1<<0)
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/* From kernel linux/mmc/core.h */
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#define MMC_RSP_NONE 0 /* no response */
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#define MMC_RSP_PRESENT (1 << 0)
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#define MMC_RSP_136 (1 << 1) /* 136 bit response */
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#define MMC_RSP_CRC (1 << 2) /* expect valid crc */
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#define MMC_RSP_BUSY (1 << 3) /* card may send busy */
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#define MMC_RSP_OPCODE (1 << 4) /* response contains opcode */
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#define MMC_CMD_AC (0 << 5)
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#define MMC_CMD_ADTC (1 << 5)
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#define MMC_CMD_BC (2 << 5)
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#define MMC_RSP_SPI_S1 (1 << 7) /* one status byte */
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#define MMC_RSP_SPI_BUSY (1 << 10) /* card may send busy */
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#define MMC_RSP_SPI_R1 (MMC_RSP_SPI_S1)
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#define MMC_RSP_SPI_R1B (MMC_RSP_SPI_S1|MMC_RSP_SPI_BUSY)
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#define MMC_RSP_R1 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
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#define MMC_RSP_R1B (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE|MMC_RSP_BUSY)
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