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289 lines
7.0 KiB
C
289 lines
7.0 KiB
C
/*
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* 3c359.h (c) 2000 Mike Phillips (mikep@linuxtr.net) All Rights Reserved
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*
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* Linux driver for 3Com 3C359 Token Link PCI XL cards.
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*
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* This software may be used and distributed according to the terms
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* of the GNU General Public License Version 2 or (at your option)
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* any later verion, incorporated herein by reference.
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*/
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/* Memory Access Commands */
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#define IO_BYTE_READ 0x28 << 24
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#define IO_BYTE_WRITE 0x18 << 24
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#define IO_WORD_READ 0x20 << 24
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#define IO_WORD_WRITE 0x10 << 24
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#define MMIO_BYTE_READ 0x88 << 24
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#define MMIO_BYTE_WRITE 0x48 << 24
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#define MMIO_WORD_READ 0x80 << 24
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#define MMIO_WORD_WRITE 0x40 << 24
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#define MEM_BYTE_READ 0x8C << 24
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#define MEM_BYTE_WRITE 0x4C << 24
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#define MEM_WORD_READ 0x84 << 24
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#define MEM_WORD_WRITE 0x44 << 24
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#define PMBAR 0x1C80
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#define PMB_CPHOLD (1<<10)
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#define CPATTENTION 0x180D
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#define CPA_PMBARVIS (1<<7)
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#define CPA_MEMWREN (1<<6)
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#define SWITCHSETTINGS 0x1C88
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#define EECONTROL 0x1C8A
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#define EEDATA 0x1C8C
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#define EEREAD 0x0080
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#define EEWRITE 0x0040
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#define EEERASE 0x0060
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#define EE_ENABLE_WRITE 0x0030
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#define EEBUSY (1<<15)
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#define WRBR 0xCDE02
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#define WWOR 0xCDE04
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#define WWCR 0xCDE06
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#define MACSTATUS 0xCDE08
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#define MISR_RW 0xCDE0B
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#define MISR_AND 0xCDE2B
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#define MISR_SET 0xCDE4B
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#define RXBUFAREA 0xCDE10
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#define RXEARLYTHRESH 0xCDE12
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#define TXSTARTTHRESH 0x58
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#define DNPRIREQTHRESH 0x2C
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#define MISR_CSRB (1<<5)
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#define MISR_RASB (1<<4)
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#define MISR_SRBFR (1<<3)
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#define MISR_ASBFR (1<<2)
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#define MISR_ARBF (1<<1)
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/* MISR Flags memory locations */
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#define MF_SSBF 0xDFFE0
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#define MF_ARBF 0xDFFE1
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#define MF_ASBFR 0xDFFE2
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#define MF_SRBFR 0xDFFE3
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#define MF_RASB 0xDFFE4
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#define MF_CSRB 0xDFFE5
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#define MMIO_MACDATA 0x10
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#define MMIO_MAC_ACCESS_CMD 0x14
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#define MMIO_TIMER 0x1A
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#define MMIO_DMA_CTRL 0x20
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#define MMIO_DNLISTPTR 0x24
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#define MMIO_HASHFILTER 0x28
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#define MMIO_CONFIG 0x29
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#define MMIO_DNPRIREQTHRESH 0x2C
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#define MMIO_DNPOLL 0x2D
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#define MMIO_UPPKTSTATUS 0x30
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#define MMIO_FREETIMER 0x34
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#define MMIO_COUNTDOWN 0x36
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#define MMIO_UPLISTPTR 0x38
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#define MMIO_UPPOLL 0x3C
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#define MMIO_UPBURSTTHRESH 0x40
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#define MMIO_DNBURSTTHRESH 0x41
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#define MMIO_INTSTATUS_AUTO 0x56
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#define MMIO_TXSTARTTHRESH 0x58
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#define MMIO_INTERRUPTENABLE 0x5A
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#define MMIO_INDICATIONENABLE 0x5C
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#define MMIO_COMMAND 0x5E /* These two are meant to be the same */
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#define MMIO_INTSTATUS 0x5E /* Makes the code more readable this way */
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#define INTSTAT_CMD_IN_PROGRESS (1<<12)
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#define INTSTAT_SRB (1<<14)
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#define INTSTAT_INTLATCH (1<<0)
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/* Indication / Interrupt Mask
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* Annoyingly the bits to be set in the indication and interrupt enable
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* do not match with the actual bits received in the interrupt, although
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* they are in the same order.
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* The mapping for the indication / interrupt are:
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* Bit Indication / Interrupt
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* 0 HostError
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* 1 txcomplete
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* 2 updneeded
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* 3 rxcomplete
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* 4 intrequested
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* 5 macerror
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* 6 dncomplete
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* 7 upcomplete
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* 8 txunderrun
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* 9 asbf
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* 10 srbr
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* 11 arbc
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*
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* The only ones we don't want to receive are txcomplete and rxcomplete
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* we use dncomplete and upcomplete instead.
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*/
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#define INT_MASK 0xFF5
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/* Note the subtle difference here, IND and INT */
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#define SETINDENABLE (8<<12)
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#define SETINTENABLE (7<<12)
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#define SRBBIT (1<<10)
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#define ASBBIT (1<<9)
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#define ARBBIT (1<<11)
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#define SRB 0xDFE90
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#define ASB 0xDFED0
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#define ARB 0xD0000
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#define SCRATCH 0xDFEF0
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#define INT_REQUEST 0x6000 /* (6 << 12) */
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#define ACK_INTERRUPT 0x6800 /* (13 <<11) */
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#define GLOBAL_RESET 0x00
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#define DNDISABLE 0x5000
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#define DNENABLE 0x4800
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#define DNSTALL 0x3002
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#define DNRESET 0x5800
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#define DNUNSTALL 0x3003
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#define UPRESET 0x2800
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#define UPSTALL 0x3000
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#define UPUNSTALL 0x3001
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#define SETCONFIG 0x4000
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#define SETTXSTARTTHRESH 0x9800
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/* Received Interrupts */
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#define ASBFINT (1<<13)
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#define SRBRINT (1<<14)
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#define ARBCINT (1<<15)
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#define TXUNDERRUN (1<<11)
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#define UPCOMPINT (1<<10)
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#define DNCOMPINT (1<<9)
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#define HARDERRINT (1<<7)
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#define RXCOMPLETE (1<<4)
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#define TXCOMPINT (1<<2)
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#define HOSTERRINT (1<<1)
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/* Receive descriptor bits */
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#define RXOVERRUN cpu_to_le32(1<<19)
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#define RXFC cpu_to_le32(1<<21)
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#define RXAR cpu_to_le32(1<<22)
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#define RXUPDCOMPLETE cpu_to_le32(1<<23)
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#define RXUPDFULL cpu_to_le32(1<<24)
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#define RXUPLASTFRAG cpu_to_le32(1<<31)
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/* Transmit descriptor bits */
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#define TXDNCOMPLETE cpu_to_le32(1<<16)
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#define TXTXINDICATE cpu_to_le32(1<<27)
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#define TXDPDEMPTY cpu_to_le32(1<<29)
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#define TXDNINDICATE cpu_to_le32(1<<31)
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#define TXDNFRAGLAST cpu_to_le32(1<<31)
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/* Interrupts to Acknowledge */
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#define LATCH_ACK 1
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#define TXCOMPACK (1<<1)
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#define INTREQACK (1<<2)
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#define DNCOMPACK (1<<3)
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#define UPCOMPACK (1<<4)
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#define ASBFACK (1<<5)
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#define SRBRACK (1<<6)
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#define ARBCACK (1<<7)
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#define XL_IO_SPACE 128
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#define SRB_COMMAND_SIZE 50
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/* Adapter Commands */
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#define REQUEST_INT 0x00
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#define MODIFY_OPEN_PARMS 0x01
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#define RESTORE_OPEN_PARMS 0x02
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#define OPEN_NIC 0x03
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#define CLOSE_NIC 0x04
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#define SET_SLEEP_MODE 0x05
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#define SET_GROUP_ADDRESS 0x06
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#define SET_FUNC_ADDRESS 0x07
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#define READ_LOG 0x08
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#define SET_MULTICAST_MODE 0x0C
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#define CHANGE_WAKEUP_PATTERN 0x0D
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#define GET_STATISTICS 0x13
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#define SET_RECEIVE_MODE 0x1F
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/* ARB Commands */
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#define RECEIVE_DATA 0x81
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#define RING_STATUS_CHANGE 0x84
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/* ASB Commands */
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#define ASB_RECEIVE_DATE 0x81
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/* Defines for LAN STATUS CHANGE reports */
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#define LSC_SIG_LOSS 0x8000
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#define LSC_HARD_ERR 0x4000
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#define LSC_SOFT_ERR 0x2000
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#define LSC_TRAN_BCN 0x1000
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#define LSC_LWF 0x0800
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#define LSC_ARW 0x0400
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#define LSC_FPE 0x0200
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#define LSC_RR 0x0100
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#define LSC_CO 0x0080
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#define LSC_SS 0x0040
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#define LSC_RING_REC 0x0020
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#define LSC_SR_CO 0x0010
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#define LSC_FDX_MODE 0x0004
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#define XL_MAX_ADAPTERS 8 /* 0x08 __MODULE_STRING can't hand 0xnn */
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/* 3c359 defaults for buffers */
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#define XL_RX_RING_SIZE 16 /* must be a power of 2 */
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#define XL_TX_RING_SIZE 16 /* must be a power of 2 */
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#define PKT_BUF_SZ 4096 /* Default packet size */
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/* 3c359 data structures */
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struct xl_tx_desc {
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__le32 dnnextptr;
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__le32 framestartheader;
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__le32 buffer;
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__le32 buffer_length;
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};
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struct xl_rx_desc {
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__le32 upnextptr;
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__le32 framestatus;
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__le32 upfragaddr;
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__le32 upfraglen;
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};
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struct xl_private {
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/* These two structures must be aligned on 8 byte boundaries */
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/* struct xl_rx_desc xl_rx_ring[XL_RX_RING_SIZE]; */
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/* struct xl_tx_desc xl_tx_ring[XL_TX_RING_SIZE]; */
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struct xl_rx_desc *xl_rx_ring ;
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struct xl_tx_desc *xl_tx_ring ;
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struct sk_buff *tx_ring_skb[XL_TX_RING_SIZE], *rx_ring_skb[XL_RX_RING_SIZE];
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int tx_ring_head, tx_ring_tail ;
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int rx_ring_tail, rx_ring_no ;
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int free_ring_entries ;
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u16 srb;
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u16 arb;
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u16 asb;
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u8 __iomem *xl_mmio;
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const char *xl_card_name;
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struct pci_dev *pdev ;
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spinlock_t xl_lock ;
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volatile int srb_queued;
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struct wait_queue *srb_wait;
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volatile int asb_queued;
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u16 mac_buffer ;
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u16 xl_lan_status ;
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u8 xl_ring_speed ;
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u16 pkt_buf_sz ;
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u8 xl_message_level;
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u16 xl_copy_all_options ;
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unsigned char xl_functional_addr[4] ;
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u16 xl_addr_table_addr, xl_parms_addr ;
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u8 xl_laa[6] ;
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u32 rx_ring_dma_addr ;
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u32 tx_ring_dma_addr ;
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};
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