linux/drivers/clk
Martin Blumenstingl ff54938dd1 clk: meson: gxbb: Fix the SDM_EN bit for MPLL0 on GXBB
There are reports that 48kHz audio does not work on the WeTek Play 2
(which uses a GXBB SoC), while 44.1kHz audio works fine on the same
board. There are also reports of 48kHz audio working fine on GXL and
GXM SoCs, which are using an (almost) identical AIU (audio controller).

Experimenting has shown that MPLL0 is causing this problem. In the .dts
we have by default:
	assigned-clocks = <&clkc CLKID_MPLL0>,
			  <&clkc CLKID_MPLL1>,
			  <&clkc CLKID_MPLL2>;
	assigned-clock-rates = <294912000>,
			       <270950400>,
			       <393216000>;
The MPLL0 rate is divisible by 48kHz without remainder and the MPLL1
rate is divisible by 44.1kHz without remainder. Swapping these two clock
rates "fixes" 48kHz audio but breaks 44.1kHz audio.

Everything looks normal when looking at the info provided by the common
clock framework while playing 48kHz audio (via I2S with mclk-fs = 256):
        mpll_prediv                 1        1        0  2000000000
           mpll0_div                1        1        0   294909641
              mpll0                 1        1        0   294909641
                 cts_amclk_sel       1        1        0   294909641
                    cts_amclk_div       1        1        0    12287902
                       cts_amclk       1        1        0    12287902

meson-clk-msr however shows that the actual MPLL0 clock is off by more
than 38MHz:
        mp0_out               333322917    +/-10416Hz

The rate seen by meson-clk-msr is very close to what we would get when
SDM (the fractional part) was ignored:
  (2000000000Hz * 16384) / ((16384 * 6) = 333.33MHz
If SDM was considered the we should get close to:
  (2000000000Hz * 16384) / ((16384 * 6) + 12808) = 294.9MHz

Further experimenting shows that HHI_MPLL_CNTL7[15] does not have any
effect on the rate of MPLL0 as seen my meson-clk-msr (regardless of
whether that bit is zero or one the rate is always the same according to
meson-clk-msr). Using HHI_MPLL_CNTL[25] on the other hand as SDM_EN
results in SDM being considered for the rate output by the hardware. The
rate - as seen by meson-clk-msr - matches with what we expect when
SDM_EN is enabled (fractional part is being considered, resulting in a
294.9MHz output) or disable (fractional part being ignored, resulting in
a 333.33MHz output).

Reported-by: Christian Hewitt <christianshewitt@gmail.com>
Tested-by: Christian Hewitt <christianshewitt@gmail.com>
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://lore.kernel.org/r/20211031135006.1508796-1-martin.blumenstingl@googlemail.com
2021-11-30 10:28:52 +01:00
..
actions clk/actions/owl-factor.c: remove superfluous headers 2021-11-02 14:28:29 -07:00
analogbits Merge branch 'akpm' (patches from Andrew) 2021-07-02 12:08:10 -07:00
at91 clk: at91: sama7g5: set low limit for mck0 at 32KHz 2021-10-26 18:27:43 -07:00
axis
axs10x
baikal-t1 clk: baikal-t1: Mark Ethernet PLL as critical 2020-10-13 19:48:34 -07:00
bcm clk: bcm2835: Switch to clk_divider.determine_rate 2021-08-05 17:36:10 -07:00
berlin
davinci This pull request contains zero diff to the core framework. It is a collection 2020-10-22 12:53:28 -07:00
h8300
hisilicon clk: hisilicon: hi3559a: select RESET_HISI 2021-07-26 17:23:40 -07:00
imgtec treewide: replace '---help---' in Kconfig files with 'help' 2020-06-14 01:57:21 +09:00
imx clk: imx8m: Do not set IMX_COMPOSITE_CORE for non-regular composites 2021-11-05 15:26:16 -07:00
ingenic Devicetree fixes for v5.16, take 1: 2021-11-14 11:11:51 -08:00
keystone clk: keystone: syscon-clk: Add support for AM64 specific epwm-tbclk 2021-06-22 14:18:26 -07:00
loongson1
mediatek clk:mediatek: remove duplicate include in clk-mt8195-imp_iic_wrap.c 2021-11-02 15:27:21 -07:00
meson clk: meson: gxbb: Fix the SDM_EN bit for MPLL0 on GXBB 2021-11-30 10:28:52 +01:00
microchip
mmp clk: mmp2: fix build without CONFIG_PM 2021-01-12 12:10:55 -08:00
mstar clk: mstar: msc313-mpll: Fix format specifier 2021-02-16 12:52:28 -08:00
mvebu clk: mvebu: ap-cpu-clk: Fix a memory leak in error handling paths 2021-09-14 18:25:16 -07:00
mxs
nxp
pistachio clk: pistachio: Make it selectable for generic MIPS kernel 2021-08-12 16:01:49 +02:00
pxa clk: pxa: Constify static struct clk_ops 2020-10-13 19:49:11 -07:00
qcom This is the second batch of clk driver updates that needed 2021-11-13 13:07:29 -08:00
ralink clk: ralink: avoid to set 'CLK_IS_CRITICAL' flag for gates 2021-08-28 22:24:06 -07:00
renesas clk: renesas: r8a779[56]x: Add MLP clocks 2021-10-15 09:46:14 +02:00
rockchip clk: rockchip: drop module parts from rk3399 and rk3568 drivers 2021-11-02 17:59:00 -07:00
samsung clk: samsung: describe drivers in Kconfig 2021-10-18 10:12:48 +02:00
sifive clk: sifive: Fix kernel-doc 2021-06-01 23:39:15 -07:00
socfpga clk: socfpga: agilex: fix duplicate s2f_user0_clk 2021-09-24 16:03:08 -07:00
spear clk: spear: Move prototype to accessible header 2021-02-11 11:56:06 -08:00
sprd This time around we have 4 lines of diff in the core framework, removing a 2020-06-10 11:42:19 -07:00
st clk: st: clkgen-fsyn: embed soc clock outputs within compatible data 2021-06-27 19:53:40 -07:00
sunxi clk: sunxi: sun8i-apb0: Make use of the helper function devm_platform_ioremap_resource() 2021-09-13 09:03:24 +02:00
sunxi-ng clk: sunxi-ng: ccu-sun9i-a80-usb: Make use of the helper function devm_platform_ioremap_resource() 2021-09-13 09:03:23 +02:00
tegra Nothing changed in the clk framework core this time around. We did get 2021-09-02 14:17:24 -07:00
ti clk: ti: am43xx: Add clkctrl data for am43xx ADC1 2021-10-20 17:06:20 +01:00
uniphier clk: uniphier: Add SoC-glue clock source selector support for Pro4 2021-11-02 14:34:51 -07:00
ux500 clk: ux500: Add driver for the reset portions of PRCC 2021-10-26 18:06:05 -07:00
versatile clk: versatile: clk-icst: Ensure clock names are unique 2021-11-11 22:27:16 -06:00
x86 clk: x86: Rename clk-lpt to more specific clk-lpss-atom 2021-07-27 14:03:47 -07:00
xilinx clk: xilinx: move xlnx_vcu clock driver from soc 2021-02-08 18:31:25 -08:00
zynq clk: zynq: clkc: Remove various instances of an unused variable 'clk' 2021-02-11 11:56:07 -08:00
zynqmp Merge branches 'clk-kirkwood', 'clk-imx', 'clk-doc', 'clk-zynq' and 'clk-ralink' into clk-next 2021-09-01 15:27:07 -07:00
clk-asm9260.c clk: asm9260: fix __clk_hw_register_fixed_rate_with_accuracy typo 2020-04-13 12:20:06 -07:00
clk-aspeed.c
clk-aspeed.h
clk-ast2600.c clk/ast2600: Fix soc revision for AHB 2021-11-03 19:42:35 -07:00
clk-axi-clkgen.c clk: axi-clkgen: use devm_platform_ioremap_resource() short-hand 2021-02-08 18:13:13 -08:00
clk-axm5516.c
clk-bd718x7.c clk: bd718xx: Drop BD70528 support 2021-06-27 18:42:45 -07:00
clk-bm1880.c
clk-bulk.c
clk-cdce706.c Replace HTTP links with HTTPS ones: Common CLK framework 2020-07-10 17:15:34 -07:00
clk-cdce925.c
clk-clps711x.c
clk-composite.c clk: composite: Fix 'switching' to same clock 2021-11-03 17:49:54 -07:00
clk-conf.c
clk-cs2000-cp.c
clk-devres.c clk: fix leak on devm_clk_bulk_get_all() unwind 2021-07-31 00:53:38 -07:00
clk-divider.c clk: divider: Implement and wire up .determine_rate by default 2021-08-05 17:35:58 -07:00
clk-fixed-factor.c clk: fixed: fix double free in resource managed fixed-factor clock 2021-04-07 16:01:25 -07:00
clk-fixed-mmio.c clk: clk-fixed-mmio: Demote obvious kernel-doc abuse 2021-02-11 11:56:05 -08:00
clk-fixed-rate.c clk: fixed: add missing kerneldoc 2020-09-22 12:44:14 -07:00
clk-fractional-divider.c clk: fractional-divider: Document the arithmetics used behind the code 2021-08-12 12:42:00 -07:00
clk-fractional-divider.h clk: fractional-divider: Hide clk_fractional_divider_ops from wide audience 2021-08-12 12:42:00 -07:00
clk-fsl-flexspi.c clk: fsl-flexspi: new driver 2020-12-07 16:56:41 -08:00
clk-fsl-sai.c clk: fsl-sai: use devm_clk_hw_register_composite_pdata() 2020-12-07 14:06:16 -08:00
clk-gate.c treewide: Remove uninitialized_var() usage 2020-07-16 12:35:15 -07:00
clk-gemini.c
clk-gpio.c Replace HTTP links with HTTPS ones: Common CLK framework 2020-07-10 17:15:34 -07:00
clk-hi655x.c
clk-highbank.c
clk-hsdk-pll.c CLK: HSDK: CGU: add support for 148.5MHz clock 2020-05-28 21:06:39 -07:00
clk-k210.c clk: k210: Fix k210_clk_set_parent() 2021-06-30 11:34:36 -07:00
clk-lmk04832.c clk: lmk04832: drop redundant fallthrough statements 2021-07-27 11:52:30 -07:00
clk-lochnagar.c
clk-max9485.c
clk-max77686.c
clk-milbeaut.c
clk-moxart.c
clk-multiplier.c
clk-mux.c clk: mux: provide devm_clk_hw_register_mux() 2021-04-07 11:05:44 -07:00
clk-nomadik.c
clk-npcm7xx.c clk: clk-npcm7xx: Remove unused static const tables 'npcm7xx_gates' and 'npcm7xx_divs_fx' 2021-02-11 11:56:05 -08:00
clk-nspire.c
clk-oxnas.c
clk-palmas.c clk: palmas: Add a missing SPDX license header 2021-08-05 17:34:30 -07:00
clk-plldig.c clk: ls1028a: fix a dereference of pointer 'parent' before a null check 2020-02-03 23:03:49 -08:00
clk-pwm.c clk: pwm: drop of_match_ptr from of_device_id table 2020-12-10 12:24:18 -08:00
clk-qoriq.c clk: qoriq: use macros to generate pll_mask 2021-02-14 13:02:01 -08:00
clk-rk808.c
clk-s2mps11.c clk: s2mps11: Fix a resource leak in error handling paths in the probe function 2020-12-19 15:53:31 -08:00
clk-scmi.c clk: scmi: Port driver to the new scmi_clk_proto_ops interface 2021-03-30 16:34:37 +01:00
clk-scpi.c clk: scpi: mark scpi_clk_match as maybe unused 2020-12-10 12:24:40 -08:00
clk-si514.c
clk-si544.c
clk-si570.c clk: si570: Skip NVM to RAM recall operation if an optional property is set 2021-02-11 12:13:50 -08:00
clk-si5341.c clk: si5341: Add sysfs properties to allow checking/resetting device faults 2021-06-27 19:58:15 -07:00
clk-si5351.c clk: si5351: Update datasheet references 2021-11-02 14:29:17 -07:00
clk-si5351.h clk: si5351: Update datasheet references 2021-11-02 14:29:17 -07:00
clk-sparx5.c clk: sparx5: Add Sparx5 SoC DPLL clock driver 2020-07-28 18:17:56 -07:00
clk-stm32f4.c Nothing changed in the clk framework core this time around. We did get 2021-09-02 14:17:24 -07:00
clk-stm32h7.c clk: stm32h7: Switch to clk_divider.determine_rate 2021-08-05 17:36:10 -07:00
clk-stm32mp1.c clk: stm32mp1: Switch to clk_divider.determine_rate 2021-08-05 17:36:10 -07:00
clk-twl6040.c
clk-versaclock5.c clk: vc5: Use i2c .probe_new 2021-11-02 14:28:51 -07:00
clk-vt8500.c
clk-wm831x.c
clk-xgene.c clk: clk-xgene: Add description for 'mask' and fix formatting for 'flags' 2021-02-11 11:56:06 -08:00
clk.c clk: use clk_core_get_rate_recalc() in clk_rate_get() 2021-10-26 18:31:23 -07:00
clk.h
clkdev.c clkdev: remove unused clkdev_alloc() interfaces 2021-06-08 17:00:09 +02:00
Kconfig clk: pistachio: Make it selectable for generic MIPS kernel 2021-08-12 16:01:49 +02:00
Makefile clk: pistachio: Make it selectable for generic MIPS kernel 2021-08-12 16:01:49 +02:00