Stephen Boyd ff060019f4 Merge branches 'clk-stm32f4', 'clk-tegra', 'clk-at91', 'clk-sifive-fu540' and 'clk-spdx' into clk-next ... - Support for STM32F769 - Rework AT91 sckc DT bindings - Fix slow RC oscillator issue on sama5d3 - AT91 sam9x60 PMC support - SiFive FU540 PRCI and PLL support * clk-stm32f4: clk: stm32mp1: Add ddrperfm clock clk: stm32: Introduce clocks of STM32F769 board * clk-tegra: clk: tegra: divider: Mark Memory Controller clock as read-only clk: tegra: emc: Replace BUG() with WARN_ONCE() clk: tegra: emc: Fix EMC max-rate clamping clk: tegra: emc: Support multiple RAM codes clk: tegra: emc: Don't enable EMC clock manually clk: tegra124: Remove lock-enable bit from PLLM clk: tegra: Fix PLLM programming on Tegra124+ when PMC overrides divider clk: tegra: Don't enable already enabled PLLs * clk-at91: clk: at91: Mark struct clk_range as const clk: at91: add sam9x60 pmc driver dt-bindings: clk: at91: add bindings for SAM9X60 pmc clk: at91: add sam9x60 PLL driver clk: at91: master: Add sam9x60 support clk: at91: usb: Add sam9x60 support clk: at91: allow configuring generated PCR layout clk: at91: allow configuring peripheral PCR layout clk: at91: sckc: handle different RC startup time clk: at91: modernize sckc binding dt-bindings: clock: at91: new sckc bindings * clk-sifive-fu540: clk: sifive: add a driver for the SiFive FU540 PRCI IP block clk: analogbits: add Wide-Range PLL library dt-bindings: clk: add documentation for the SiFive PRCI driver * clk-spdx: clk: sunxi-ng: Use the correct style for SPDX License Identifier clk: sprd: Use the correct style for SPDX License Identifier clk: renesas: Use the correct style for SPDX License Identifier clk: qcom: Use the correct style for SPDX License Identifier clk: davinci: Use the correct style for SPDX License Identifier clk: actions: Use the correct style for SPDX License Identifier		2019-05-07 11:45:29 -07:00
..
da8xx-cfgchip.c	clk: davinci: cfgchip: use PTR_ERR_OR_ZERO in da8xx_cfgchip_register_div4p5	2019-04-11 11:45:02 -07:00
Makefile	clk: davinci: New driver for TI DA8XX CFGCHIP clocks	2018-03-20 10:16:26 -07:00
pll-da830.c	clk: davinci: pll: allow dev == NULL	2018-05-30 12:48:35 -07:00
pll-da850.c	clk: davinci: da850-pll: change PLL0 to CLK_OF_DECLARE	2018-05-30 12:48:39 -07:00
pll-dm355.c	clk: davinci: pll: allow dev == NULL	2018-05-30 12:48:35 -07:00
pll-dm365.c	clk: davinci: pll: allow dev == NULL	2018-05-30 12:48:35 -07:00
pll-dm644x.c	clk: davinci: pll: allow dev == NULL	2018-05-30 12:48:35 -07:00
pll-dm646x.c	clk: davinci: pll: allow dev == NULL	2018-05-30 12:48:35 -07:00
pll.c	Merge branches 'clk-davinci-psc-da830', 'clk-renesas', 'clk-at91-recalc', 'clk-davinci' and 'clk-meson' into clk-next	2018-06-04 12:37:41 -07:00
pll.h	clk: davinci: Use the correct style for SPDX License Identifier	2019-05-01 13:01:11 -07:00
psc-da830.c	clk: davinci: psc-da830: add a lookup entry for aemif clock	2018-07-06 12:34:54 -05:00
psc-da850.c	clk: davinci: psc-da850: remove the 'davinci_nand.0" lookup	2018-07-06 12:33:57 -05:00
psc-dm355.c	clk: davinci: psc: allow for dev == NULL	2018-05-30 12:48:44 -07:00
psc-dm365.c	clk: davinci: psc-dm365: use two lookup entries for the aemif clock	2018-07-06 12:34:54 -05:00
psc-dm644x.c	clk: davinci: psc-dm644x: use two lookup entries for the aemif clock	2018-07-06 12:34:54 -05:00
psc-dm646x.c	clk: davinci: psc-dm646x: use two lookup entries for the aemif clock	2018-07-06 12:34:54 -05:00
psc.c	clk: davinci: kill davinci_clk_reset_assert/deassert()	2018-10-02 08:54:14 -07:00
psc.h	clk: davinci: Use the correct style for SPDX License Identifier	2019-05-01 13:01:11 -07:00