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The Allwinner D1 family of SoCs contain a PPU power domain controller separate from the PRCM. It can power down the video engine and DSP, and it contains special logic for hardware-assisted CPU idle. Other recent Allwinner SoCs (e.g. TV303) have a PPU with a different set of domains. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Samuel Holland <samuel@sholland.org> Link: https://lore.kernel.org/r/20230126063419.15971-2-samuel@sholland.org Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
55 lines
1.1 KiB
YAML
55 lines
1.1 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/power/allwinner,sun20i-d1-ppu.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Allwinner SoCs PPU power domain controller
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maintainers:
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- Samuel Holland <samuel@sholland.org>
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description:
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D1 and related SoCs contain a power domain controller for the CPUs, GPU, and
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video-related hardware.
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properties:
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compatible:
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enum:
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- allwinner,sun20i-d1-ppu
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reg:
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maxItems: 1
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clocks:
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description: Bus Clock
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maxItems: 1
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resets:
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maxItems: 1
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'#power-domain-cells':
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const: 1
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required:
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- compatible
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- reg
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- clocks
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- resets
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- '#power-domain-cells'
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/sun20i-d1-r-ccu.h>
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#include <dt-bindings/reset/sun20i-d1-r-ccu.h>
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ppu: power-controller@7001000 {
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compatible = "allwinner,sun20i-d1-ppu";
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reg = <0x7001000 0x1000>;
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clocks = <&r_ccu CLK_BUS_R_PPU>;
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resets = <&r_ccu RST_BUS_R_PPU>;
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#power-domain-cells = <1>;
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};
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