Max Filippov fec3259c9f xtensa: increase ranges in ___invalidate_{i,d}cache_all ... Cache invalidation macros use cache line size to iterate over invalidated cache lines, assuming that all cache ways are invalidated by single instruction, but xtensa ISA recommends to not assume that for future compatibility: In some implementations all ways at index Addry-1..z are invalidated regardless of the specified way, but for future compatibility this behavior should not be assumed. Iterate over all cache ways in ___invalidate_icache_all and ___invalidate_dcache_all. Cc: stable@vger.kernel.org Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>		2018-08-13 20:08:01 -07:00
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boot	Xtensa improvements for v4.16:	2018-01-29 16:40:28 -08:00
configs	irqdomain: Kill CONFIG_IRQ_DOMAIN_DEBUG	2018-01-24 12:32:58 +01:00
include	xtensa: increase ranges in ___invalidate_{i,d}cache_all	2018-08-13 20:08:01 -07:00
kernel	Kbuild: rename CC_STACKPROTECTOR[_STRONG] config variables	2018-06-14 12:21:18 +09:00
lib	xtensa: add support for KASAN	2017-12-16 22:37:12 -08:00
mm	signal/xtensa: Use force_sig_fault where appropriate	2018-04-25 10:44:12 -05:00
oprofile	License cleanup: add SPDX GPL-2.0 license identifier to files with no license	2017-11-02 11:10:55 +01:00
platforms	tty: replace ->proc_fops with ->proc_show	2018-05-16 07:24:30 +02:00
variants	xtensa: Added Cadence CSP kernel configuration for Xtensa	2016-09-09 18:39:09 -07:00
Kconfig	Kbuild: rename HAVE_CC_STACKPROTECTOR config variable	2018-06-15 07:15:28 +09:00
Kconfig.debug	License cleanup: add SPDX GPL-2.0 license identifier to files with no license	2017-11-02 11:10:55 +01:00
Makefile	xtensa: build kernel with text-section-literals	2017-12-10 14:48:51 -08:00