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388637d972
Use pci_is_root_bus() rather than tracking the root bus number to determine if the bus is the root bus or not. This removes storing duplicated data as well as the need for the host bridge driver to have to care about the bus numbers in most cases. Link: https://lore.kernel.org/r/20200722022514.1283916-7-robh@kernel.org Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Karthikeyan Mitran <m.karthikeyan@mobiveil.co.in> Cc: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Bjorn Helgaas <bhelgaas@google.com>
226 lines
6.5 KiB
C
226 lines
6.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* PCIe host controller driver for Mobiveil PCIe Host controller
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*
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* Copyright (c) 2018 Mobiveil Inc.
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* Copyright 2019 NXP
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*
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* Author: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
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* Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
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*/
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#ifndef _PCIE_MOBIVEIL_H
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#define _PCIE_MOBIVEIL_H
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#include <linux/pci.h>
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#include <linux/irq.h>
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#include <linux/msi.h>
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#include "../../pci.h"
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/* register offsets and bit positions */
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/*
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* translation tables are grouped into windows, each window registers are
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* grouped into blocks of 4 or 16 registers each
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*/
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#define PAB_REG_BLOCK_SIZE 16
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#define PAB_EXT_REG_BLOCK_SIZE 4
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#define PAB_REG_ADDR(offset, win) \
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(offset + (win * PAB_REG_BLOCK_SIZE))
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#define PAB_EXT_REG_ADDR(offset, win) \
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(offset + (win * PAB_EXT_REG_BLOCK_SIZE))
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#define LTSSM_STATUS 0x0404
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#define LTSSM_STATUS_L0_MASK 0x3f
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#define LTSSM_STATUS_L0 0x2d
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#define PAB_CTRL 0x0808
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#define AMBA_PIO_ENABLE_SHIFT 0
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#define PEX_PIO_ENABLE_SHIFT 1
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#define PAGE_SEL_SHIFT 13
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#define PAGE_SEL_MASK 0x3f
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#define PAGE_LO_MASK 0x3ff
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#define PAGE_SEL_OFFSET_SHIFT 10
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#define PAB_ACTIVITY_STAT 0x81c
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#define PAB_AXI_PIO_CTRL 0x0840
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#define APIO_EN_MASK 0xf
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#define PAB_PEX_PIO_CTRL 0x08c0
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#define PIO_ENABLE_SHIFT 0
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#define PAB_INTP_AMBA_MISC_ENB 0x0b0c
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#define PAB_INTP_AMBA_MISC_STAT 0x0b1c
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#define PAB_INTP_RESET BIT(1)
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#define PAB_INTP_MSI BIT(3)
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#define PAB_INTP_INTA BIT(5)
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#define PAB_INTP_INTB BIT(6)
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#define PAB_INTP_INTC BIT(7)
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#define PAB_INTP_INTD BIT(8)
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#define PAB_INTP_PCIE_UE BIT(9)
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#define PAB_INTP_IE_PMREDI BIT(29)
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#define PAB_INTP_IE_EC BIT(30)
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#define PAB_INTP_MSI_MASK PAB_INTP_MSI
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#define PAB_INTP_INTX_MASK (PAB_INTP_INTA | PAB_INTP_INTB |\
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PAB_INTP_INTC | PAB_INTP_INTD)
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#define PAB_AXI_AMAP_CTRL(win) PAB_REG_ADDR(0x0ba0, win)
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#define WIN_ENABLE_SHIFT 0
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#define WIN_TYPE_SHIFT 1
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#define WIN_TYPE_MASK 0x3
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#define WIN_SIZE_MASK 0xfffffc00
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#define PAB_EXT_AXI_AMAP_SIZE(win) PAB_EXT_REG_ADDR(0xbaf0, win)
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#define PAB_EXT_AXI_AMAP_AXI_WIN(win) PAB_EXT_REG_ADDR(0x80a0, win)
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#define PAB_AXI_AMAP_AXI_WIN(win) PAB_REG_ADDR(0x0ba4, win)
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#define AXI_WINDOW_ALIGN_MASK 3
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#define PAB_AXI_AMAP_PEX_WIN_L(win) PAB_REG_ADDR(0x0ba8, win)
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#define PAB_BUS_SHIFT 24
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#define PAB_DEVICE_SHIFT 19
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#define PAB_FUNCTION_SHIFT 16
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#define PAB_AXI_AMAP_PEX_WIN_H(win) PAB_REG_ADDR(0x0bac, win)
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#define PAB_INTP_AXI_PIO_CLASS 0x474
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#define PAB_PEX_AMAP_CTRL(win) PAB_REG_ADDR(0x4ba0, win)
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#define AMAP_CTRL_EN_SHIFT 0
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#define AMAP_CTRL_TYPE_SHIFT 1
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#define AMAP_CTRL_TYPE_MASK 3
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#define PAB_EXT_PEX_AMAP_SIZEN(win) PAB_EXT_REG_ADDR(0xbef0, win)
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#define PAB_EXT_PEX_AMAP_AXI_WIN(win) PAB_EXT_REG_ADDR(0xb4a0, win)
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#define PAB_PEX_AMAP_AXI_WIN(win) PAB_REG_ADDR(0x4ba4, win)
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#define PAB_PEX_AMAP_PEX_WIN_L(win) PAB_REG_ADDR(0x4ba8, win)
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#define PAB_PEX_AMAP_PEX_WIN_H(win) PAB_REG_ADDR(0x4bac, win)
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/* starting offset of INTX bits in status register */
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#define PAB_INTX_START 5
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/* supported number of MSI interrupts */
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#define PCI_NUM_MSI 16
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/* MSI registers */
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#define MSI_BASE_LO_OFFSET 0x04
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#define MSI_BASE_HI_OFFSET 0x08
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#define MSI_SIZE_OFFSET 0x0c
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#define MSI_ENABLE_OFFSET 0x14
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#define MSI_STATUS_OFFSET 0x18
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#define MSI_DATA_OFFSET 0x20
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#define MSI_ADDR_L_OFFSET 0x24
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#define MSI_ADDR_H_OFFSET 0x28
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/* outbound and inbound window definitions */
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#define WIN_NUM_0 0
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#define WIN_NUM_1 1
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#define CFG_WINDOW_TYPE 0
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#define IO_WINDOW_TYPE 1
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#define MEM_WINDOW_TYPE 2
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#define IB_WIN_SIZE ((u64)256 * 1024 * 1024 * 1024)
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#define MAX_PIO_WINDOWS 8
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/* Parameters for the waiting for link up routine */
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#define LINK_WAIT_MAX_RETRIES 10
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#define LINK_WAIT_MIN 90000
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#define LINK_WAIT_MAX 100000
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#define PAGED_ADDR_BNDRY 0xc00
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#define OFFSET_TO_PAGE_ADDR(off) \
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((off & PAGE_LO_MASK) | PAGED_ADDR_BNDRY)
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#define OFFSET_TO_PAGE_IDX(off) \
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((off >> PAGE_SEL_OFFSET_SHIFT) & PAGE_SEL_MASK)
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struct mobiveil_msi { /* MSI information */
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struct mutex lock; /* protect bitmap variable */
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struct irq_domain *msi_domain;
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struct irq_domain *dev_domain;
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phys_addr_t msi_pages_phys;
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int num_of_vectors;
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DECLARE_BITMAP(msi_irq_in_use, PCI_NUM_MSI);
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};
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struct mobiveil_pcie;
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struct mobiveil_rp_ops {
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int (*interrupt_init)(struct mobiveil_pcie *pcie);
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};
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struct mobiveil_root_port {
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void __iomem *config_axi_slave_base; /* endpoint config base */
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struct resource *ob_io_res;
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struct mobiveil_rp_ops *ops;
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int irq;
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raw_spinlock_t intx_mask_lock;
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struct irq_domain *intx_domain;
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struct mobiveil_msi msi;
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struct pci_host_bridge *bridge;
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};
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struct mobiveil_pab_ops {
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int (*link_up)(struct mobiveil_pcie *pcie);
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};
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struct mobiveil_pcie {
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struct platform_device *pdev;
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void __iomem *csr_axi_slave_base; /* root port config base */
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void __iomem *apb_csr_base; /* MSI register base */
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phys_addr_t pcie_reg_base; /* Physical PCIe Controller Base */
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int apio_wins;
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int ppio_wins;
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int ob_wins_configured; /* configured outbound windows */
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int ib_wins_configured; /* configured inbound windows */
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const struct mobiveil_pab_ops *ops;
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struct mobiveil_root_port rp;
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};
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int mobiveil_pcie_host_probe(struct mobiveil_pcie *pcie);
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int mobiveil_host_init(struct mobiveil_pcie *pcie, bool reinit);
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bool mobiveil_pcie_link_up(struct mobiveil_pcie *pcie);
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int mobiveil_bringup_link(struct mobiveil_pcie *pcie);
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void program_ob_windows(struct mobiveil_pcie *pcie, int win_num, u64 cpu_addr,
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u64 pci_addr, u32 type, u64 size);
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void program_ib_windows(struct mobiveil_pcie *pcie, int win_num, u64 cpu_addr,
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u64 pci_addr, u32 type, u64 size);
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u32 mobiveil_csr_read(struct mobiveil_pcie *pcie, u32 off, size_t size);
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void mobiveil_csr_write(struct mobiveil_pcie *pcie, u32 val, u32 off,
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size_t size);
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static inline u32 mobiveil_csr_readl(struct mobiveil_pcie *pcie, u32 off)
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{
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return mobiveil_csr_read(pcie, off, 0x4);
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}
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static inline u16 mobiveil_csr_readw(struct mobiveil_pcie *pcie, u32 off)
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{
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return mobiveil_csr_read(pcie, off, 0x2);
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}
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static inline u8 mobiveil_csr_readb(struct mobiveil_pcie *pcie, u32 off)
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{
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return mobiveil_csr_read(pcie, off, 0x1);
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}
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static inline void mobiveil_csr_writel(struct mobiveil_pcie *pcie, u32 val,
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u32 off)
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{
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mobiveil_csr_write(pcie, val, off, 0x4);
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}
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static inline void mobiveil_csr_writew(struct mobiveil_pcie *pcie, u16 val,
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u32 off)
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{
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mobiveil_csr_write(pcie, val, off, 0x2);
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}
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static inline void mobiveil_csr_writeb(struct mobiveil_pcie *pcie, u8 val,
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u32 off)
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{
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mobiveil_csr_write(pcie, val, off, 0x1);
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}
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#endif /* _PCIE_MOBIVEIL_H */
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