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fe9b842f72
linux/arch/riscv/kernel
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Christoph Hellwig fe9b842f72
riscv: disable SUM in the exception handler 
The SUM bit is enabled at the beginning of the copy_{to,from}_user and
{get,put}_user routines, and cleared before they return.  But these user
copy helper can be interrupted by exceptions, in which case the SUM bit
will remain set, which leads to elevated privileges for the code running
in exception context, as that can now access userspace address space
unconditionally.  This frequently happens when the user copy routines
access freshly allocated user memory that hasn't been faulted in, and a
pagefault needs to be taken before the user copy routines can continue.

Fix this by unconditionally clearing SUM when the exception handler is
called - the restore code will automatically restore it based on the
saved value.

Signed-off-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2018-01-30 19:12:38 -08:00
..
vdso RISC-V: Make __NR_riscv_flush_icache visible to userspace 2018-01-07 15:14:37 -08:00
.gitignore RISC-V: Build Infrastructure 2017-09-26 15:26:49 -07:00
asm-offsets.c RISC-V: Task implementation 2017-09-26 15:26:46 -07:00
cacheinfo.c RISC-V: Init and Halt Code 2017-09-26 15:26:44 -07:00
cpu.c RISC-V: Init and Halt Code 2017-09-26 15:26:44 -07:00
cpufeature.c RISC-V: User-facing API 2017-09-26 15:26:48 -07:00
entry.S riscv: disable SUM in the exception handler 2018-01-30 19:12:38 -08:00
ftrace.c riscv/ftrace: Add basic support 2018-01-30 19:10:54 -08:00
head.S RISC-V: move empty_zero_page definition to C and export it 2017-11-30 10:01:10 -08:00
irq.c RISC-V: Init and Halt Code 2017-09-26 15:26:44 -07:00
Makefile riscv/ftrace: Add basic support 2018-01-30 19:10:54 -08:00
mcount.S riscv/ftrace: Add basic support 2018-01-30 19:10:54 -08:00
module.c RISC-V: User-facing API 2017-09-26 15:26:48 -07:00
process.c riscv: rename SR_* constants to match the spec 2018-01-07 15:14:39 -08:00
ptrace.c RISC-V: User-facing API 2017-09-26 15:26:48 -07:00
reset.c RISC-V: Init and Halt Code 2017-09-26 15:26:44 -07:00
riscv_ksyms.c RISC-V: Export some expected symbols for modules 2017-11-30 10:01:10 -08:00
setup.c RISC-V: Remove mem_end command line processing 2018-01-30 19:09:53 -08:00
signal.c RISC-V: User-facing API 2017-09-26 15:26:48 -07:00
smp.c RISC-V: Fixes for clean allmodconfig build 2017-12-01 13:31:31 -08:00
smpboot.c RISC-V: Init and Halt Code 2017-09-26 15:26:44 -07:00
stacktrace.c RISC-V: Generic library routines and assembly 2017-09-26 15:26:45 -07:00
sys_riscv.c RISC-V: Logical vs Bitwise typo 2017-12-11 07:51:06 -08:00
syscall_table.c RISC-V: Make __NR_riscv_flush_icache visible to userspace 2018-01-07 15:14:37 -08:00
time.c RISC-V: Init and Halt Code 2017-09-26 15:26:44 -07:00
traps.c RISC-V: Init and Halt Code 2017-09-26 15:26:44 -07:00
vdso.c riscv: remove redundant unlikely() 2018-01-30 19:12:06 -08:00
vmlinux.lds.S RISC-V: Build Infrastructure 2017-09-26 15:26:49 -07:00