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14f8c55d48
In case of error, the function devm_regmap_init_i2c() returns
ERR_PTR() and never returns NULL. The NULL test in the return
value check should be replaced with IS_ERR().
Fixes: 6b149f3310 ("mfd: pm8008: Add driver for QCOM PM8008 PMIC")
Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Acked-by: Guru Das Srinagesh <gurus@codeaurora.org>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221125073626.1868229-1-yangyingliang@huawei.com
248 lines
6.8 KiB
C
248 lines
6.8 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2021, The Linux Foundation. All rights reserved.
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*/
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#include <linux/bitops.h>
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#include <linux/i2c.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/irqdomain.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/of_platform.h>
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#include <linux/pinctrl/consumer.h>
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#include <linux/regmap.h>
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#include <linux/slab.h>
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#include <dt-bindings/mfd/qcom-pm8008.h>
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#define I2C_INTR_STATUS_BASE 0x0550
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#define INT_RT_STS_OFFSET 0x10
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#define INT_SET_TYPE_OFFSET 0x11
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#define INT_POL_HIGH_OFFSET 0x12
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#define INT_POL_LOW_OFFSET 0x13
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#define INT_LATCHED_CLR_OFFSET 0x14
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#define INT_EN_SET_OFFSET 0x15
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#define INT_EN_CLR_OFFSET 0x16
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#define INT_LATCHED_STS_OFFSET 0x18
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enum {
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PM8008_MISC,
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PM8008_TEMP_ALARM,
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PM8008_GPIO1,
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PM8008_GPIO2,
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PM8008_NUM_PERIPHS,
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};
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#define PM8008_PERIPH_0_BASE 0x900
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#define PM8008_PERIPH_1_BASE 0x2400
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#define PM8008_PERIPH_2_BASE 0xC000
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#define PM8008_PERIPH_3_BASE 0xC100
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#define PM8008_TEMP_ALARM_ADDR PM8008_PERIPH_1_BASE
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#define PM8008_GPIO1_ADDR PM8008_PERIPH_2_BASE
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#define PM8008_GPIO2_ADDR PM8008_PERIPH_3_BASE
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#define PM8008_STATUS_BASE (PM8008_PERIPH_0_BASE | INT_LATCHED_STS_OFFSET)
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#define PM8008_MASK_BASE (PM8008_PERIPH_0_BASE | INT_EN_SET_OFFSET)
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#define PM8008_UNMASK_BASE (PM8008_PERIPH_0_BASE | INT_EN_CLR_OFFSET)
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#define PM8008_TYPE_BASE (PM8008_PERIPH_0_BASE | INT_SET_TYPE_OFFSET)
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#define PM8008_ACK_BASE (PM8008_PERIPH_0_BASE | INT_LATCHED_CLR_OFFSET)
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#define PM8008_POLARITY_HI_BASE (PM8008_PERIPH_0_BASE | INT_POL_HIGH_OFFSET)
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#define PM8008_POLARITY_LO_BASE (PM8008_PERIPH_0_BASE | INT_POL_LOW_OFFSET)
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#define PM8008_PERIPH_OFFSET(paddr) (paddr - PM8008_PERIPH_0_BASE)
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static unsigned int p0_offs[] = {PM8008_PERIPH_OFFSET(PM8008_PERIPH_0_BASE)};
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static unsigned int p1_offs[] = {PM8008_PERIPH_OFFSET(PM8008_PERIPH_1_BASE)};
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static unsigned int p2_offs[] = {PM8008_PERIPH_OFFSET(PM8008_PERIPH_2_BASE)};
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static unsigned int p3_offs[] = {PM8008_PERIPH_OFFSET(PM8008_PERIPH_3_BASE)};
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static struct regmap_irq_sub_irq_map pm8008_sub_reg_offsets[] = {
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REGMAP_IRQ_MAIN_REG_OFFSET(p0_offs),
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REGMAP_IRQ_MAIN_REG_OFFSET(p1_offs),
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REGMAP_IRQ_MAIN_REG_OFFSET(p2_offs),
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REGMAP_IRQ_MAIN_REG_OFFSET(p3_offs),
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};
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static unsigned int pm8008_virt_regs[] = {
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PM8008_POLARITY_HI_BASE,
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PM8008_POLARITY_LO_BASE,
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};
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enum {
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POLARITY_HI_INDEX,
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POLARITY_LO_INDEX,
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PM8008_NUM_VIRT_REGS,
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};
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static struct regmap_irq pm8008_irqs[] = {
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REGMAP_IRQ_REG(PM8008_IRQ_MISC_UVLO, PM8008_MISC, BIT(0)),
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REGMAP_IRQ_REG(PM8008_IRQ_MISC_OVLO, PM8008_MISC, BIT(1)),
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REGMAP_IRQ_REG(PM8008_IRQ_MISC_OTST2, PM8008_MISC, BIT(2)),
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REGMAP_IRQ_REG(PM8008_IRQ_MISC_OTST3, PM8008_MISC, BIT(3)),
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REGMAP_IRQ_REG(PM8008_IRQ_MISC_LDO_OCP, PM8008_MISC, BIT(4)),
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REGMAP_IRQ_REG(PM8008_IRQ_TEMP_ALARM, PM8008_TEMP_ALARM, BIT(0)),
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REGMAP_IRQ_REG(PM8008_IRQ_GPIO1, PM8008_GPIO1, BIT(0)),
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REGMAP_IRQ_REG(PM8008_IRQ_GPIO2, PM8008_GPIO2, BIT(0)),
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};
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static int pm8008_set_type_virt(unsigned int **virt_buf,
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unsigned int type, unsigned long hwirq,
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int reg)
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{
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switch (type) {
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case IRQ_TYPE_EDGE_FALLING:
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case IRQ_TYPE_LEVEL_LOW:
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virt_buf[POLARITY_HI_INDEX][reg] &= ~pm8008_irqs[hwirq].mask;
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virt_buf[POLARITY_LO_INDEX][reg] |= pm8008_irqs[hwirq].mask;
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break;
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case IRQ_TYPE_EDGE_RISING:
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case IRQ_TYPE_LEVEL_HIGH:
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virt_buf[POLARITY_HI_INDEX][reg] |= pm8008_irqs[hwirq].mask;
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virt_buf[POLARITY_LO_INDEX][reg] &= ~pm8008_irqs[hwirq].mask;
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break;
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case IRQ_TYPE_EDGE_BOTH:
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virt_buf[POLARITY_HI_INDEX][reg] |= pm8008_irqs[hwirq].mask;
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virt_buf[POLARITY_LO_INDEX][reg] |= pm8008_irqs[hwirq].mask;
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static struct regmap_irq_chip pm8008_irq_chip = {
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.name = "pm8008_irq",
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.main_status = I2C_INTR_STATUS_BASE,
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.num_main_regs = 1,
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.num_virt_regs = PM8008_NUM_VIRT_REGS,
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.irqs = pm8008_irqs,
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.num_irqs = ARRAY_SIZE(pm8008_irqs),
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.num_regs = PM8008_NUM_PERIPHS,
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.not_fixed_stride = true,
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.sub_reg_offsets = pm8008_sub_reg_offsets,
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.set_type_virt = pm8008_set_type_virt,
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.status_base = PM8008_STATUS_BASE,
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.mask_base = PM8008_MASK_BASE,
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.unmask_base = PM8008_UNMASK_BASE,
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.type_base = PM8008_TYPE_BASE,
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.ack_base = PM8008_ACK_BASE,
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.virt_reg_base = pm8008_virt_regs,
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.num_type_reg = PM8008_NUM_PERIPHS,
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};
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static struct regmap_config qcom_mfd_regmap_cfg = {
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.reg_bits = 16,
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.val_bits = 8,
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.max_register = 0xFFFF,
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};
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static int pm8008_init(struct regmap *regmap)
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{
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int rc;
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/*
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* Set TEMP_ALARM peripheral's TYPE so that the regmap-irq framework
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* reads this as the default value instead of zero, the HW default.
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* This is required to enable the writing of TYPE registers in
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* regmap_irq_sync_unlock().
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*/
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rc = regmap_write(regmap, (PM8008_TEMP_ALARM_ADDR | INT_SET_TYPE_OFFSET), BIT(0));
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if (rc)
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return rc;
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/* Do the same for GPIO1 and GPIO2 peripherals */
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rc = regmap_write(regmap, (PM8008_GPIO1_ADDR | INT_SET_TYPE_OFFSET), BIT(0));
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if (rc)
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return rc;
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rc = regmap_write(regmap, (PM8008_GPIO2_ADDR | INT_SET_TYPE_OFFSET), BIT(0));
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return rc;
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}
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static int pm8008_probe_irq_peripherals(struct device *dev,
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struct regmap *regmap,
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int client_irq)
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{
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int rc, i;
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struct regmap_irq_type *type;
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struct regmap_irq_chip_data *irq_data;
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rc = pm8008_init(regmap);
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if (rc) {
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dev_err(dev, "Init failed: %d\n", rc);
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return rc;
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}
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for (i = 0; i < ARRAY_SIZE(pm8008_irqs); i++) {
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type = &pm8008_irqs[i].type;
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type->type_reg_offset = pm8008_irqs[i].reg_offset;
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type->type_rising_val = pm8008_irqs[i].mask;
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type->type_falling_val = pm8008_irqs[i].mask;
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type->type_level_high_val = 0;
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type->type_level_low_val = 0;
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if (type->type_reg_offset == PM8008_MISC)
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type->types_supported = IRQ_TYPE_EDGE_RISING;
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else
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type->types_supported = (IRQ_TYPE_EDGE_BOTH |
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IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW);
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}
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rc = devm_regmap_add_irq_chip(dev, regmap, client_irq,
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IRQF_SHARED, 0, &pm8008_irq_chip, &irq_data);
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if (rc) {
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dev_err(dev, "Failed to add IRQ chip: %d\n", rc);
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return rc;
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}
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return 0;
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}
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static int pm8008_probe(struct i2c_client *client)
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{
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int rc;
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struct device *dev;
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struct regmap *regmap;
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dev = &client->dev;
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regmap = devm_regmap_init_i2c(client, &qcom_mfd_regmap_cfg);
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if (IS_ERR(regmap))
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return PTR_ERR(regmap);
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i2c_set_clientdata(client, regmap);
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if (of_property_read_bool(dev->of_node, "interrupt-controller")) {
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rc = pm8008_probe_irq_peripherals(dev, regmap, client->irq);
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if (rc)
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dev_err(dev, "Failed to probe irq periphs: %d\n", rc);
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}
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return devm_of_platform_populate(dev);
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}
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static const struct of_device_id pm8008_match[] = {
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{ .compatible = "qcom,pm8008", },
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{ },
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};
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static struct i2c_driver pm8008_mfd_driver = {
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.driver = {
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.name = "pm8008",
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.of_match_table = pm8008_match,
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},
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.probe_new = pm8008_probe,
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};
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module_i2c_driver(pm8008_mfd_driver);
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MODULE_LICENSE("GPL v2");
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MODULE_ALIAS("i2c:qcom-pm8008");
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