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9ef986a697
All the machines using the MMCI are passing GPIOs for the card detect and write protect using the device tree or descriptor table (one single case, Integrator/AP IM-PD1). Drop support for passing global GPIO numbers through platform data, noone is using it. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
358 lines
9.8 KiB
C
358 lines
9.8 KiB
C
/*
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* Versatile board support using the device tree
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*
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* Copyright (C) 2010 Secret Lab Technologies Ltd.
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* Copyright (C) 2009 Jeremy Kerr <jeremy.kerr@canonical.com>
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* Copyright (C) 2004 ARM Limited
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* Copyright (C) 2000 Deep Blue Solutions Ltd
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/of_platform.h>
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#include <linux/slab.h>
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#include <linux/amba/bus.h>
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#include <linux/amba/clcd.h>
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#include <linux/platform_data/video-clcd-versatile.h>
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#include <linux/amba/mmci.h>
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#include <asm/mach-types.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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/* macro to get at MMIO space when running virtually */
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#define IO_ADDRESS(x) (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + 0xf0000000)
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#define __io_address(n) ((void __iomem __force *)IO_ADDRESS(n))
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/*
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* ------------------------------------------------------------------------
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* Versatile Registers
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* ------------------------------------------------------------------------
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*/
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#define VERSATILE_SYS_PCICTL_OFFSET 0x44
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#define VERSATILE_SYS_MCI_OFFSET 0x48
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#define VERSATILE_SYS_CLCD_OFFSET 0x50
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/*
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* VERSATILE peripheral addresses
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*/
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#define VERSATILE_MMCI0_BASE 0x10005000 /* MMC interface */
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#define VERSATILE_MMCI1_BASE 0x1000B000 /* MMC Interface */
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#define VERSATILE_CLCD_BASE 0x10120000 /* CLCD */
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#define VERSATILE_SCTL_BASE 0x101E0000 /* System controller */
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#define VERSATILE_IB2_BASE 0x24000000 /* IB2 module */
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#define VERSATILE_IB2_CTL_BASE (VERSATILE_IB2_BASE + 0x03000000)
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/*
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* System controller bit assignment
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*/
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#define VERSATILE_REFCLK 0
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#define VERSATILE_TIMCLK 1
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#define VERSATILE_TIMER1_EnSel 15
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#define VERSATILE_TIMER2_EnSel 17
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#define VERSATILE_TIMER3_EnSel 19
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#define VERSATILE_TIMER4_EnSel 21
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static void __iomem *versatile_sys_base;
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static void __iomem *versatile_ib2_ctrl;
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unsigned int mmc_status(struct device *dev)
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{
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struct amba_device *adev = container_of(dev, struct amba_device, dev);
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u32 mask;
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if (adev->res.start == VERSATILE_MMCI0_BASE)
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mask = 1;
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else
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mask = 2;
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return readl(versatile_sys_base + VERSATILE_SYS_MCI_OFFSET) & mask;
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}
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static struct mmci_platform_data mmc0_plat_data = {
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.ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
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.status = mmc_status,
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};
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static struct mmci_platform_data mmc1_plat_data = {
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.ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
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.status = mmc_status,
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};
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/*
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* CLCD support.
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*/
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#define SYS_CLCD_MODE_MASK (3 << 0)
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#define SYS_CLCD_MODE_888 (0 << 0)
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#define SYS_CLCD_MODE_5551 (1 << 0)
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#define SYS_CLCD_MODE_565_RLSB (2 << 0)
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#define SYS_CLCD_MODE_565_BLSB (3 << 0)
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#define SYS_CLCD_NLCDIOON (1 << 2)
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#define SYS_CLCD_VDDPOSSWITCH (1 << 3)
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#define SYS_CLCD_PWR3V5SWITCH (1 << 4)
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#define SYS_CLCD_ID_MASK (0x1f << 8)
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#define SYS_CLCD_ID_SANYO_3_8 (0x00 << 8)
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#define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
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#define SYS_CLCD_ID_EPSON_2_2 (0x02 << 8)
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#define SYS_CLCD_ID_SANYO_2_5 (0x07 << 8)
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#define SYS_CLCD_ID_VGA (0x1f << 8)
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static bool is_sanyo_2_5_lcd;
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/*
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* Disable all display connectors on the interface module.
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*/
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static void versatile_clcd_disable(struct clcd_fb *fb)
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{
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void __iomem *sys_clcd = versatile_sys_base + VERSATILE_SYS_CLCD_OFFSET;
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u32 val;
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val = readl(sys_clcd);
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val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
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writel(val, sys_clcd);
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/*
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* If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light off
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*/
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if (of_machine_is_compatible("arm,versatile-ab") && is_sanyo_2_5_lcd) {
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unsigned long ctrl;
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ctrl = readl(versatile_ib2_ctrl);
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ctrl &= ~0x01;
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writel(ctrl, versatile_ib2_ctrl);
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}
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}
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/*
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* Enable the relevant connector on the interface module.
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*/
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static void versatile_clcd_enable(struct clcd_fb *fb)
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{
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struct fb_var_screeninfo *var = &fb->fb.var;
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void __iomem *sys_clcd = versatile_sys_base + VERSATILE_SYS_CLCD_OFFSET;
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u32 val;
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val = readl(sys_clcd);
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val &= ~SYS_CLCD_MODE_MASK;
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switch (var->green.length) {
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case 5:
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val |= SYS_CLCD_MODE_5551;
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break;
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case 6:
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if (var->red.offset == 0)
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val |= SYS_CLCD_MODE_565_RLSB;
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else
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val |= SYS_CLCD_MODE_565_BLSB;
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break;
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case 8:
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val |= SYS_CLCD_MODE_888;
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break;
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}
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/*
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* Set the MUX
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*/
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writel(val, sys_clcd);
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/*
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* And now enable the PSUs
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*/
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val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
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writel(val, sys_clcd);
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/*
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* If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light on
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*/
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if (of_machine_is_compatible("arm,versatile-ab") && is_sanyo_2_5_lcd) {
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unsigned long ctrl;
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ctrl = readl(versatile_ib2_ctrl);
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ctrl |= 0x01;
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writel(ctrl, versatile_ib2_ctrl);
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}
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}
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/*
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* Detect which LCD panel is connected, and return the appropriate
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* clcd_panel structure. Note: we do not have any information on
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* the required timings for the 8.4in panel, so we presently assume
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* VGA timings.
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*/
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static int versatile_clcd_setup(struct clcd_fb *fb)
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{
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void __iomem *sys_clcd = versatile_sys_base + VERSATILE_SYS_CLCD_OFFSET;
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const char *panel_name;
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u32 val;
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is_sanyo_2_5_lcd = false;
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val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
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if (val == SYS_CLCD_ID_SANYO_3_8)
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panel_name = "Sanyo TM38QV67A02A";
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else if (val == SYS_CLCD_ID_SANYO_2_5) {
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panel_name = "Sanyo QVGA Portrait";
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is_sanyo_2_5_lcd = true;
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} else if (val == SYS_CLCD_ID_EPSON_2_2)
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panel_name = "Epson L2F50113T00";
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else if (val == SYS_CLCD_ID_VGA)
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panel_name = "VGA";
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else {
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printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
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val);
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panel_name = "VGA";
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}
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fb->panel = versatile_clcd_get_panel(panel_name);
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if (!fb->panel)
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return -EINVAL;
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return versatile_clcd_setup_dma(fb, SZ_1M);
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}
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static void versatile_clcd_decode(struct clcd_fb *fb, struct clcd_regs *regs)
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{
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clcdfb_decode(fb, regs);
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/* Always clear BGR for RGB565: we do the routing externally */
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if (fb->fb.var.green.length == 6)
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regs->cntl &= ~CNTL_BGR;
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}
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static struct clcd_board clcd_plat_data = {
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.name = "Versatile",
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.caps = CLCD_CAP_5551 | CLCD_CAP_565 | CLCD_CAP_888,
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.check = clcdfb_check,
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.decode = versatile_clcd_decode,
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.disable = versatile_clcd_disable,
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.enable = versatile_clcd_enable,
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.setup = versatile_clcd_setup,
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.mmap = versatile_clcd_mmap_dma,
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.remove = versatile_clcd_remove_dma,
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};
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/*
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* Lookup table for attaching a specific name and platform_data pointer to
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* devices as they get created by of_platform_populate(). Ideally this table
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* would not exist, but the current clock implementation depends on some devices
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* having a specific name.
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*/
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struct of_dev_auxdata versatile_auxdata_lookup[] __initdata = {
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OF_DEV_AUXDATA("arm,primecell", VERSATILE_MMCI0_BASE, "fpga:05", &mmc0_plat_data),
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OF_DEV_AUXDATA("arm,primecell", VERSATILE_MMCI1_BASE, "fpga:0b", &mmc1_plat_data),
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OF_DEV_AUXDATA("arm,primecell", VERSATILE_CLCD_BASE, "dev:20", &clcd_plat_data),
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{}
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};
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static struct map_desc versatile_io_desc[] __initdata __maybe_unused = {
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{
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.virtual = IO_ADDRESS(VERSATILE_SCTL_BASE),
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.pfn = __phys_to_pfn(VERSATILE_SCTL_BASE),
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.length = SZ_4K * 9,
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.type = MT_DEVICE
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}
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};
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static void __init versatile_map_io(void)
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{
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debug_ll_io_init();
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iotable_init(versatile_io_desc, ARRAY_SIZE(versatile_io_desc));
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}
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static void __init versatile_init_early(void)
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{
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u32 val;
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/*
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* set clock frequency:
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* VERSATILE_REFCLK is 32KHz
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* VERSATILE_TIMCLK is 1MHz
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*/
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val = readl(__io_address(VERSATILE_SCTL_BASE));
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writel((VERSATILE_TIMCLK << VERSATILE_TIMER1_EnSel) |
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(VERSATILE_TIMCLK << VERSATILE_TIMER2_EnSel) |
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(VERSATILE_TIMCLK << VERSATILE_TIMER3_EnSel) |
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(VERSATILE_TIMCLK << VERSATILE_TIMER4_EnSel) | val,
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__io_address(VERSATILE_SCTL_BASE));
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}
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static void __init versatile_dt_pci_init(void)
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{
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u32 val;
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struct device_node *np;
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struct property *newprop;
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np = of_find_compatible_node(NULL, NULL, "arm,versatile-pci");
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if (!np)
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return;
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/* Check if PCI backplane is detected */
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val = readl(versatile_sys_base + VERSATILE_SYS_PCICTL_OFFSET);
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if (val & 1) {
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/*
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* Enable PCI accesses. Note that the documentaton is
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* inconsistent whether or not this is needed, but the old
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* driver had it so we will keep it.
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*/
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writel(1, versatile_sys_base + VERSATILE_SYS_PCICTL_OFFSET);
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return;
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}
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newprop = kzalloc(sizeof(*newprop), GFP_KERNEL);
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if (!newprop)
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return;
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newprop->name = kstrdup("status", GFP_KERNEL);
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newprop->value = kstrdup("disabled", GFP_KERNEL);
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newprop->length = sizeof("disabled");
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of_update_property(np, newprop);
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pr_info("Not plugged into PCI backplane!\n");
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}
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static void __init versatile_dt_init(void)
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{
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struct device_node *np;
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np = of_find_compatible_node(NULL, NULL, "arm,core-module-versatile");
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if (np)
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versatile_sys_base = of_iomap(np, 0);
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WARN_ON(!versatile_sys_base);
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versatile_ib2_ctrl = ioremap(VERSATILE_IB2_CTL_BASE, SZ_4K);
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versatile_dt_pci_init();
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of_platform_default_populate(NULL, versatile_auxdata_lookup, NULL);
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}
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static const char *const versatile_dt_match[] __initconst = {
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"arm,versatile-ab",
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"arm,versatile-pb",
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NULL,
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};
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DT_MACHINE_START(VERSATILE_PB, "ARM-Versatile (Device Tree Support)")
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.map_io = versatile_map_io,
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.init_early = versatile_init_early,
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.init_machine = versatile_dt_init,
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.dt_compat = versatile_dt_match,
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MACHINE_END
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