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bdc753c7fc
late breaking reports that a patch series to rework clk rate range support broke boot on some devices, so I've left that branch out of this PR. Hopefully we can get to that next week, or punt on it and let it bake another cycle. That means we don't really have any changes to the core framework this time around besides a few typo fixes. Instead this is all clk driver updates and fixes. The usual suspects are here (again), with Qualcomm dominating the diffstat. We look to have gained support for quite a few new Qualcomm SoCs and Dmitry worked on updating many of the existing Qualcomm drivers to use clk_parent_data. After that we have MediaTek drivers getting some much needed updates, in particular to support GPU DVFS. There are also quite a few Samsung clk driver patches, but that's mostly because there was a maintainer change and so last release we missed some of those patches. Overall things look normal, but I'm slowly reviewing core framework code nowadays and that shows given the rate range patches had to be yanked last minute. Let's hope this situation changes soon. New Drivers: - Support for Renesas VersaClock7 clock generator family - Add Spreadtrum UMS512 SoC clk support - New clock drivers for MediaTek Helio X10 MT6795 - Display clks for Qualcomm SM6115, SM8450 - GPU clks for Qualcomm SC8280XP - Qualcomm MSM8909 and SM6375 global and SMD RPM clk drivers Deleted Drivers: - Remove DaVinci DM644x and DM646x clk driver support Updates: - Convert Baikal-T1 CCU driver to platform driver - Split reset support out of primary Baikal-T1 CCU driver - Add some missing clks required for RPiVid Video Decoder on RaspberryPi - Mark PLLC critical on bcm2835 - More devm helpers for fixed rate registration - Various PXA168 clk driver fixes - Add resets for MediaTek MT8195 PCIe and USB - Miscellaneous of_node_put() fixes - Nuke dt-bindings/clk path (again) by moving headers to dt-bindings/clock - Convert gpio-clk-gate binding to YAML - Various fixes to AMD/Xilinx Zynqmp clk driver - Graduate AMD/Xilinx "clocking wizard" driver from staging - Add missing DPI1_HDMI clock in MT8195 VDOSYS1 - Clock driver changes to support GPU DVFS on MT8183, MT8192, MT8195 - Fix GPU clock topology on MT8195 - Propogate rate changes from GPU clock gate up the tree - Clock mux notifiers for GPU-related PLLs - Conversion of more "simple" drivers to mtk_clk_simple_probe() - Hook up mtk_clk_simple_remove() for "simple" MT8192 clock drivers - Fixes to previous |struct clk| to |struct clk_hw| conversion on MediaTek - Shrink MT8192 clock driver by deduplicating clock parent lists - Change order between 'sim_enet_root_clk' and 'enet_qos_root_clk' clocks for i.MX8MP - Drop unnecessary newline in i.MX8MM dt-bindings - Add more MU1 and SAI clocks dt-bindings Ids - Introduce slice busy bit check for i.MX93 composite clock - Introduce white list bit check for i.MX93 composite clock - Add new i.MX93 clock gate - Add MU1 and MU2 clocks to i.MX93 clock provider - Add SAI IPG clocks to i.MX93 clock provider - add generic clocks for U(S)ART available on SAMA5D2 SoCs - reset controller support for Polarfire clocks - .round_rate and .set rate support for clk-mpfs - code cleanup for clk-mpfs - PLL support for PolarFire SoC's Clock Conditioning Circuitry - Add watchdog, I2C, pin control/GPIO, and Ethernet clocks on R-Car V4H - Add SDHI, Timer (CMT/TMU), and SPI (MSIOF) clocks on R-Car S4-8 - Add I2C clocks and resets on RZ/V2M - Document clock support for the RZ/Five SoC - mux-variant clock using the table variant to select parents - clock controller for the rv1126 soc - conversion of rk3128 to yaml and relicensing of the yaml bindings to gpl2+MIT (following dt-binding guildelines) - Exynos7885: add FSYS, TREX and MFC clock controllers - Exynos850: add IS and AUD (audio) clock controllers with bindings - ExynosAutov9: add FSYS clock controllers with bindings - ExynosAutov9: correct clock IDs in bindings of Peric 0 and 1 clock controllers, due to duplicated entries. This is an acceptable ABI break: recently developed/added platform so without legacies, acked by known users/developers - ExynosAutov9: add few missing Peric 0/1 gates - ExynosAutov9: correct register offsets of few Peric 0/1 clocks - Minor code improvements (use of_device_get_match_data() helper, code style) - Add Krzysztof Kozlowski as co-maintainer of Samsung SoC clocks, as he already maintainers that architecture/platform - Keep Qualcomm GDSCs enabled when PWRSTS_RET flag is there, solving retention issues during suspend of USB on Qualcomm sc7180/sc7280 and SC8280XP - Qualcomm SM6115 and QCM2260 are moved to reuse PLL configuration - Qualcomm SDM660 SDCC1 moved to floor clk ops - Support for the APCS PLLs for Qualcomm IPQ8064, IPQ8074 and IPQ6018 was added/fixed - The Qualcomm MSM8996 CPU clocks are updated with support for ACD - Support for Qualcomm SDM670 GCC and RPMh clks was added - Transition to parent_data, parent_hws and use of ARRAY_SIZE() for num_parents was done for many Qualcomm SoCs - Support for per-reset defined delay on Qualcomm was introduced -----BEGIN PGP SIGNATURE----- iQJFBAABCAAvFiEE9L57QeeUxqYDyoaDrQKIl8bklSUFAmM/trwRHHNib3lkQGtl cm5lbC5vcmcACgkQrQKIl8bklSUEoA/+LiftbrF8Xtu7lGdxRjqLzRftUmHaUQWO d0cadtzMsgxzFJsxp99IiJBVJoaYCBOGlnZDx8p/JGv+mmdhl5+yHgKQbR8nEmTk 5A+bdA1okOdm8SPBPMcLvuMjsgmx+DHkuxvnC2hT8ZGfQDoa+6PnObpP30LJkHT0 oVY8g8ScEuHI5eJcNz3UgxAetKeJd+WRQPxKCrjsOeyhWuNAJ7wdTVQjjzH49X4C RS3fjeHvhr2VZm23IgildY++a6hPO72gtBjEpDRoFwnmWAVqUtxiwptoJJNkC5kB toD/ndQHOLh/XOJFKgksS20L4JHtSp5F3Ma8sIuOjAXmDCyqMdTQhydnl5Pyrow+ ct8BMUGkx0Sw8pXBJYINtHpwTtIxvLu/sBNqBb/lRCWd8byrPlUnKvF/COcoxp27 miZTwJI28fHU5a2K/46iWZCI5YUvVcnBSz8WbEWWvOltIT8S0JvZozA3KuRm5vys /k2HaQwO2I0QWQzPjfg6SRlTTWH6p+Hc47fSg7LSM6Scsb7ZraajTM2QOvgn7Mgp m/136q7jr9mvuLqqy1fBY3F2hDZYNSJX+UfmIFcpCyxvht0GVFN9YCc+Ibgyl2vQ P3b9LXV2OqhtDJg6ds7v8aPgAGUwUFO8GTPBG1cuom7z5u/kdIpjKaFAyr8wWSuJ wqPIFevggsA= =9jI+ -----END PGP SIGNATURE----- Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "We have some late breaking reports that a patch series to rework clk rate range support broke boot on some devices, so I've left that branch out of this. Hopefully we can get to that next week, or punt on it and let it bake another cycle. That means we don't really have any changes to the core framework this time around besides a few typo fixes. Instead this is all clk driver updates and fixes. The usual suspects are here (again), with Qualcomm dominating the diffstat. We look to have gained support for quite a few new Qualcomm SoCs and Dmitry worked on updating many of the existing Qualcomm drivers to use clk_parent_data. After that we have MediaTek drivers getting some much needed updates, in particular to support GPU DVFS. There are also quite a few Samsung clk driver patches, but that's mostly because there was a maintainer change and so last release we missed some of those patches. Overall things look normal, but I'm slowly reviewing core framework code nowadays and that shows given the rate range patches had to be yanked last minute. Let's hope this situation changes soon. New Drivers: - Support for Renesas VersaClock7 clock generator family - Add Spreadtrum UMS512 SoC clk support - New clock drivers for MediaTek Helio X10 MT6795 - Display clks for Qualcomm SM6115, SM8450 - GPU clks for Qualcomm SC8280XP - Qualcomm MSM8909 and SM6375 global and SMD RPM clk drivers Deleted Drivers: - Remove DaVinci DM644x and DM646x clk driver support Updates: - Convert Baikal-T1 CCU driver to platform driver - Split reset support out of primary Baikal-T1 CCU driver - Add some missing clks required for RPiVid Video Decoder on RaspberryPi - Mark PLLC critical on bcm2835 - More devm helpers for fixed rate registration - Various PXA168 clk driver fixes - Add resets for MediaTek MT8195 PCIe and USB - Miscellaneous of_node_put() fixes - Nuke dt-bindings/clk path (again) by moving headers to dt-bindings/clock - Convert gpio-clk-gate binding to YAML - Various fixes to AMD/Xilinx Zynqmp clk driver - Graduate AMD/Xilinx "clocking wizard" driver from staging - Add missing DPI1_HDMI clock in MT8195 VDOSYS1 - Clock driver changes to support GPU DVFS on MT8183, MT8192, MT8195 - Fix GPU clock topology on MT8195 - Propogate rate changes from GPU clock gate up the tree - Clock mux notifiers for GPU-related PLLs - Conversion of more "simple" drivers to mtk_clk_simple_probe() - Hook up mtk_clk_simple_remove() for "simple" MT8192 clock drivers - Fixes to previous |struct clk| to |struct clk_hw| conversion on MediaTek - Shrink MT8192 clock driver by deduplicating clock parent lists - Change order between 'sim_enet_root_clk' and 'enet_qos_root_clk' clocks for i.MX8MP - Drop unnecessary newline in i.MX8MM dt-bindings - Add more MU1 and SAI clocks dt-bindings Ids - Introduce slice busy bit check for i.MX93 composite clock - Introduce white list bit check for i.MX93 composite clock - Add new i.MX93 clock gate - Add MU1 and MU2 clocks to i.MX93 clock provider - Add SAI IPG clocks to i.MX93 clock provider - add generic clocks for U(S)ART available on SAMA5D2 SoCs - reset controller support for Polarfire clocks - .round_rate and .set rate support for clk-mpfs - code cleanup for clk-mpfs - PLL support for PolarFire SoC's Clock Conditioning Circuitry - Add watchdog, I2C, pin control/GPIO, and Ethernet clocks on R-Car V4H - Add SDHI, Timer (CMT/TMU), and SPI (MSIOF) clocks on R-Car S4-8 - Add I2C clocks and resets on RZ/V2M - Document clock support for the RZ/Five SoC - mux-variant clock using the table variant to select parents - clock controller for the rv1126 soc - conversion of rk3128 to yaml and relicensing of the yaml bindings to gpl2+MIT (following dt-binding guildelines) - Exynos7885: add FSYS, TREX and MFC clock controllers - Exynos850: add IS and AUD (audio) clock controllers with bindings - ExynosAutov9: add FSYS clock controllers with bindings - ExynosAutov9: correct clock IDs in bindings of Peric 0 and 1 clock controllers, due to duplicated entries. This is an acceptable ABI break: recently developed/added platform so without legacies, acked by known users/developers - ExynosAutov9: add few missing Peric 0/1 gates - ExynosAutov9: correct register offsets of few Peric 0/1 clocks - Minor code improvements (use of_device_get_match_data() helper, code style) - Add Krzysztof Kozlowski as co-maintainer of Samsung SoC clocks, as he already maintainers that architecture/platform - Keep Qualcomm GDSCs enabled when PWRSTS_RET flag is there, solving retention issues during suspend of USB on Qualcomm sc7180/sc7280 and SC8280XP - Qualcomm SM6115 and QCM2260 are moved to reuse PLL configuration - Qualcomm SDM660 SDCC1 moved to floor clk ops - Support for the APCS PLLs for Qualcomm IPQ8064, IPQ8074 and IPQ6018 was added/fixed - The Qualcomm MSM8996 CPU clocks are updated with support for ACD - Support for Qualcomm SDM670 GCC and RPMh clks was added - Transition to parent_data, parent_hws and use of ARRAY_SIZE() for num_parents was done for many Qualcomm SoCs - Support for per-reset defined delay on Qualcomm was introduced" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (283 commits) clk: qcom: gcc-sm6375: Ensure unsigned long type clk: qcom: gcc-sm6375: Remove unused variables clk: qcom: kpss-xcc: convert to parent data API clk: introduce (devm_)hw_register_mux_parent_data_table API clk: allow building lan966x as a module clk: clk-xgene: simplify if-if to if-else clk: ast2600: BCLK comes from EPLL clk: clocking-wizard: Depend on HAS_IOMEM clk: clocking-wizard: Use dev_err_probe() helper clk: nxp: fix typo in comment clk: pxa: add a check for the return value of kzalloc() clk: vc5: Add support for IDT/Renesas VersaClock 5P49V6975 dt-bindings: clock: vc5: Add 5P49V6975 clk: mvebu: armada-37xx-tbg: Remove the unneeded result variable clk: ti: dra7-atl: Fix reference leak in of_dra7_atl_clk_probe clk: Renesas versaclock7 ccf device driver dt-bindings: Renesas versaclock7 device tree bindings clk: ti: Balance of_node_get() calls for of_find_node_by_name() clk: imx: scu: fix memleak on platform_device_add() fails clk: vc5: Use regmap_{set,clear}_bits() where appropriate ...
662 lines
15 KiB
C
662 lines
15 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* TI clock support
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*
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* Copyright (C) 2013 Texas Instruments, Inc.
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*
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* Tero Kristo <t-kristo@ti.com>
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*/
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/clkdev.h>
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#include <linux/clk/ti.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/list.h>
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#include <linux/regmap.h>
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#include <linux/memblock.h>
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#include <linux/device.h>
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#include "clock.h"
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#undef pr_fmt
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#define pr_fmt(fmt) "%s: " fmt, __func__
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static LIST_HEAD(clk_hw_omap_clocks);
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struct ti_clk_ll_ops *ti_clk_ll_ops;
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static struct device_node *clocks_node_ptr[CLK_MAX_MEMMAPS];
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struct ti_clk_features ti_clk_features;
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struct clk_iomap {
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struct regmap *regmap;
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void __iomem *mem;
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};
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static struct clk_iomap *clk_memmaps[CLK_MAX_MEMMAPS];
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static void clk_memmap_writel(u32 val, const struct clk_omap_reg *reg)
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{
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struct clk_iomap *io = clk_memmaps[reg->index];
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if (reg->ptr)
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writel_relaxed(val, reg->ptr);
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else if (io->regmap)
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regmap_write(io->regmap, reg->offset, val);
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else
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writel_relaxed(val, io->mem + reg->offset);
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}
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static void _clk_rmw(u32 val, u32 mask, void __iomem *ptr)
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{
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u32 v;
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v = readl_relaxed(ptr);
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v &= ~mask;
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v |= val;
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writel_relaxed(v, ptr);
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}
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static void clk_memmap_rmw(u32 val, u32 mask, const struct clk_omap_reg *reg)
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{
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struct clk_iomap *io = clk_memmaps[reg->index];
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if (reg->ptr) {
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_clk_rmw(val, mask, reg->ptr);
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} else if (io->regmap) {
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regmap_update_bits(io->regmap, reg->offset, mask, val);
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} else {
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_clk_rmw(val, mask, io->mem + reg->offset);
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}
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}
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static u32 clk_memmap_readl(const struct clk_omap_reg *reg)
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{
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u32 val;
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struct clk_iomap *io = clk_memmaps[reg->index];
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if (reg->ptr)
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val = readl_relaxed(reg->ptr);
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else if (io->regmap)
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regmap_read(io->regmap, reg->offset, &val);
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else
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val = readl_relaxed(io->mem + reg->offset);
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return val;
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}
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/**
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* ti_clk_setup_ll_ops - setup low level clock operations
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* @ops: low level clock ops descriptor
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*
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* Sets up low level clock operations for TI clock driver. This is used
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* to provide various callbacks for the clock driver towards platform
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* specific code. Returns 0 on success, -EBUSY if ll_ops have been
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* registered already.
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*/
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int ti_clk_setup_ll_ops(struct ti_clk_ll_ops *ops)
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{
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if (ti_clk_ll_ops) {
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pr_err("Attempt to register ll_ops multiple times.\n");
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return -EBUSY;
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}
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ti_clk_ll_ops = ops;
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ops->clk_readl = clk_memmap_readl;
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ops->clk_writel = clk_memmap_writel;
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ops->clk_rmw = clk_memmap_rmw;
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return 0;
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}
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/*
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* Eventually we could standardize to using '_' for clk-*.c files to follow the
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* TRM naming and leave out the tmp name here.
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*/
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static struct device_node *ti_find_clock_provider(struct device_node *from,
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const char *name)
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{
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struct device_node *np;
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bool found = false;
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const char *n;
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char *tmp;
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tmp = kstrdup(name, GFP_KERNEL);
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if (!tmp)
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return NULL;
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strreplace(tmp, '-', '_');
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/* Node named "clock" with "clock-output-names" */
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for_each_of_allnodes_from(from, np) {
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if (of_property_read_string_index(np, "clock-output-names",
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0, &n))
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continue;
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if (!strncmp(n, tmp, strlen(tmp))) {
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of_node_get(np);
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found = true;
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break;
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}
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}
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kfree(tmp);
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if (found) {
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of_node_put(from);
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return np;
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}
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/* Fall back to using old node name base provider name */
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return of_find_node_by_name(from, name);
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}
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/**
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* ti_dt_clocks_register - register DT alias clocks during boot
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* @oclks: list of clocks to register
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*
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* Register alias or non-standard DT clock entries during boot. By
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* default, DT clocks are found based on their clock-output-names
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* property, or the clock node name for legacy cases. If any
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* additional con-id / dev-id -> clock mapping is required, use this
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* function to list these.
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*/
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void __init ti_dt_clocks_register(struct ti_dt_clk oclks[])
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{
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struct ti_dt_clk *c;
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struct device_node *node, *parent, *child;
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struct clk *clk;
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struct of_phandle_args clkspec;
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char buf[64];
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char *ptr;
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char *tags[2];
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int i;
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int num_args;
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int ret;
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static bool clkctrl_nodes_missing;
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static bool has_clkctrl_data;
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static bool compat_mode;
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compat_mode = ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT;
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for (c = oclks; c->node_name != NULL; c++) {
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strcpy(buf, c->node_name);
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ptr = buf;
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for (i = 0; i < 2; i++)
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tags[i] = NULL;
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num_args = 0;
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while (*ptr) {
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if (*ptr == ':') {
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if (num_args >= 2) {
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pr_warn("Bad number of tags on %s\n",
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c->node_name);
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return;
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}
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tags[num_args++] = ptr + 1;
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*ptr = 0;
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}
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ptr++;
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}
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if (num_args && clkctrl_nodes_missing)
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continue;
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node = ti_find_clock_provider(NULL, buf);
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if (num_args && compat_mode) {
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parent = node;
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child = of_get_child_by_name(parent, "clock");
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if (!child)
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child = of_get_child_by_name(parent, "clk");
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if (child) {
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of_node_put(parent);
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node = child;
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}
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}
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clkspec.np = node;
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clkspec.args_count = num_args;
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for (i = 0; i < num_args; i++) {
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ret = kstrtoint(tags[i], i ? 10 : 16, clkspec.args + i);
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if (ret) {
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pr_warn("Bad tag in %s at %d: %s\n",
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c->node_name, i, tags[i]);
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of_node_put(node);
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return;
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}
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}
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clk = of_clk_get_from_provider(&clkspec);
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of_node_put(node);
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if (!IS_ERR(clk)) {
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c->lk.clk = clk;
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clkdev_add(&c->lk);
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} else {
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if (num_args && !has_clkctrl_data) {
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struct device_node *np;
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np = of_find_compatible_node(NULL, NULL,
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"ti,clkctrl");
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if (np) {
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has_clkctrl_data = true;
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of_node_put(np);
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} else {
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clkctrl_nodes_missing = true;
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pr_warn("missing clkctrl nodes, please update your dts.\n");
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continue;
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}
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}
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pr_warn("failed to lookup clock node %s, ret=%ld\n",
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c->node_name, PTR_ERR(clk));
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}
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}
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}
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struct clk_init_item {
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struct device_node *node;
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void *user;
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ti_of_clk_init_cb_t func;
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struct list_head link;
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};
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static LIST_HEAD(retry_list);
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/**
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* ti_clk_retry_init - retries a failed clock init at later phase
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* @node: device not for the clock
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* @user: user data pointer
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* @func: init function to be called for the clock
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*
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* Adds a failed clock init to the retry list. The retry list is parsed
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* once all the other clocks have been initialized.
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*/
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int __init ti_clk_retry_init(struct device_node *node, void *user,
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ti_of_clk_init_cb_t func)
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{
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struct clk_init_item *retry;
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pr_debug("%pOFn: adding to retry list...\n", node);
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retry = kzalloc(sizeof(*retry), GFP_KERNEL);
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if (!retry)
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return -ENOMEM;
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retry->node = node;
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retry->func = func;
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retry->user = user;
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list_add(&retry->link, &retry_list);
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return 0;
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}
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/**
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|
* ti_clk_get_reg_addr - get register address for a clock register
|
|
* @node: device node for the clock
|
|
* @index: register index from the clock node
|
|
* @reg: pointer to target register struct
|
|
*
|
|
* Builds clock register address from device tree information, and returns
|
|
* the data via the provided output pointer @reg. Returns 0 on success,
|
|
* negative error value on failure.
|
|
*/
|
|
int ti_clk_get_reg_addr(struct device_node *node, int index,
|
|
struct clk_omap_reg *reg)
|
|
{
|
|
u32 val;
|
|
int i;
|
|
|
|
for (i = 0; i < CLK_MAX_MEMMAPS; i++) {
|
|
if (clocks_node_ptr[i] == node->parent)
|
|
break;
|
|
if (clocks_node_ptr[i] == node->parent->parent)
|
|
break;
|
|
}
|
|
|
|
if (i == CLK_MAX_MEMMAPS) {
|
|
pr_err("clk-provider not found for %pOFn!\n", node);
|
|
return -ENOENT;
|
|
}
|
|
|
|
reg->index = i;
|
|
|
|
if (of_property_read_u32_index(node, "reg", index, &val)) {
|
|
if (of_property_read_u32_index(node->parent, "reg",
|
|
index, &val)) {
|
|
pr_err("%pOFn or parent must have reg[%d]!\n",
|
|
node, index);
|
|
return -EINVAL;
|
|
}
|
|
}
|
|
|
|
reg->offset = val;
|
|
reg->ptr = NULL;
|
|
|
|
return 0;
|
|
}
|
|
|
|
void ti_clk_latch(struct clk_omap_reg *reg, s8 shift)
|
|
{
|
|
u32 latch;
|
|
|
|
if (shift < 0)
|
|
return;
|
|
|
|
latch = 1 << shift;
|
|
|
|
ti_clk_ll_ops->clk_rmw(latch, latch, reg);
|
|
ti_clk_ll_ops->clk_rmw(0, latch, reg);
|
|
ti_clk_ll_ops->clk_readl(reg); /* OCP barrier */
|
|
}
|
|
|
|
/**
|
|
* omap2_clk_provider_init - init master clock provider
|
|
* @parent: master node
|
|
* @index: internal index for clk_reg_ops
|
|
* @syscon: syscon regmap pointer for accessing clock registers
|
|
* @mem: iomem pointer for the clock provider memory area, only used if
|
|
* syscon is not provided
|
|
*
|
|
* Initializes a master clock IP block. This basically sets up the
|
|
* mapping from clocks node to the memory map index. All the clocks
|
|
* are then initialized through the common of_clk_init call, and the
|
|
* clocks will access their memory maps based on the node layout.
|
|
* Returns 0 in success.
|
|
*/
|
|
int __init omap2_clk_provider_init(struct device_node *parent, int index,
|
|
struct regmap *syscon, void __iomem *mem)
|
|
{
|
|
struct device_node *clocks;
|
|
struct clk_iomap *io;
|
|
|
|
/* get clocks for this parent */
|
|
clocks = of_get_child_by_name(parent, "clocks");
|
|
if (!clocks) {
|
|
pr_err("%pOFn missing 'clocks' child node.\n", parent);
|
|
return -EINVAL;
|
|
}
|
|
|
|
/* add clocks node info */
|
|
clocks_node_ptr[index] = clocks;
|
|
|
|
io = kzalloc(sizeof(*io), GFP_KERNEL);
|
|
if (!io)
|
|
return -ENOMEM;
|
|
|
|
io->regmap = syscon;
|
|
io->mem = mem;
|
|
|
|
clk_memmaps[index] = io;
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* omap2_clk_legacy_provider_init - initialize a legacy clock provider
|
|
* @index: index for the clock provider
|
|
* @mem: iomem pointer for the clock provider memory area
|
|
*
|
|
* Initializes a legacy clock provider memory mapping.
|
|
*/
|
|
void __init omap2_clk_legacy_provider_init(int index, void __iomem *mem)
|
|
{
|
|
struct clk_iomap *io;
|
|
|
|
io = memblock_alloc(sizeof(*io), SMP_CACHE_BYTES);
|
|
if (!io)
|
|
panic("%s: Failed to allocate %zu bytes\n", __func__,
|
|
sizeof(*io));
|
|
|
|
io->mem = mem;
|
|
|
|
clk_memmaps[index] = io;
|
|
}
|
|
|
|
/**
|
|
* ti_dt_clk_init_retry_clks - init clocks from the retry list
|
|
*
|
|
* Initializes any clocks that have failed to initialize before,
|
|
* reasons being missing parent node(s) during earlier init. This
|
|
* typically happens only for DPLLs which need to have both of their
|
|
* parent clocks ready during init.
|
|
*/
|
|
void ti_dt_clk_init_retry_clks(void)
|
|
{
|
|
struct clk_init_item *retry;
|
|
struct clk_init_item *tmp;
|
|
int retries = 5;
|
|
|
|
while (!list_empty(&retry_list) && retries) {
|
|
list_for_each_entry_safe(retry, tmp, &retry_list, link) {
|
|
pr_debug("retry-init: %pOFn\n", retry->node);
|
|
retry->func(retry->user, retry->node);
|
|
list_del(&retry->link);
|
|
kfree(retry);
|
|
}
|
|
retries--;
|
|
}
|
|
}
|
|
|
|
static const struct of_device_id simple_clk_match_table[] __initconst = {
|
|
{ .compatible = "fixed-clock" },
|
|
{ .compatible = "fixed-factor-clock" },
|
|
{ }
|
|
};
|
|
|
|
/**
|
|
* ti_dt_clk_name - init clock name from first output name or node name
|
|
* @np: device node
|
|
*
|
|
* Use the first clock-output-name for the clock name if found. Fall back
|
|
* to legacy naming based on node name.
|
|
*/
|
|
const char *ti_dt_clk_name(struct device_node *np)
|
|
{
|
|
const char *name;
|
|
|
|
if (!of_property_read_string_index(np, "clock-output-names", 0,
|
|
&name))
|
|
return name;
|
|
|
|
return np->name;
|
|
}
|
|
|
|
/**
|
|
* ti_clk_add_aliases - setup clock aliases
|
|
*
|
|
* Sets up any missing clock aliases. No return value.
|
|
*/
|
|
void __init ti_clk_add_aliases(void)
|
|
{
|
|
struct device_node *np;
|
|
struct clk *clk;
|
|
|
|
for_each_matching_node(np, simple_clk_match_table) {
|
|
struct of_phandle_args clkspec;
|
|
|
|
clkspec.np = np;
|
|
clk = of_clk_get_from_provider(&clkspec);
|
|
|
|
ti_clk_add_alias(NULL, clk, ti_dt_clk_name(np));
|
|
}
|
|
}
|
|
|
|
/**
|
|
* ti_clk_setup_features - setup clock features flags
|
|
* @features: features definition to use
|
|
*
|
|
* Initializes the clock driver features flags based on platform
|
|
* provided data. No return value.
|
|
*/
|
|
void __init ti_clk_setup_features(struct ti_clk_features *features)
|
|
{
|
|
memcpy(&ti_clk_features, features, sizeof(*features));
|
|
}
|
|
|
|
/**
|
|
* ti_clk_get_features - get clock driver features flags
|
|
*
|
|
* Get TI clock driver features description. Returns a pointer
|
|
* to the current feature setup.
|
|
*/
|
|
const struct ti_clk_features *ti_clk_get_features(void)
|
|
{
|
|
return &ti_clk_features;
|
|
}
|
|
|
|
/**
|
|
* omap2_clk_enable_init_clocks - prepare & enable a list of clocks
|
|
* @clk_names: ptr to an array of strings of clock names to enable
|
|
* @num_clocks: number of clock names in @clk_names
|
|
*
|
|
* Prepare and enable a list of clocks, named by @clk_names. No
|
|
* return value. XXX Deprecated; only needed until these clocks are
|
|
* properly claimed and enabled by the drivers or core code that uses
|
|
* them. XXX What code disables & calls clk_put on these clocks?
|
|
*/
|
|
void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks)
|
|
{
|
|
struct clk *init_clk;
|
|
int i;
|
|
|
|
for (i = 0; i < num_clocks; i++) {
|
|
init_clk = clk_get(NULL, clk_names[i]);
|
|
if (WARN(IS_ERR(init_clk), "could not find init clock %s\n",
|
|
clk_names[i]))
|
|
continue;
|
|
clk_prepare_enable(init_clk);
|
|
}
|
|
}
|
|
|
|
/**
|
|
* ti_clk_add_alias - add a clock alias for a TI clock
|
|
* @dev: device alias for this clock
|
|
* @clk: clock handle to create alias for
|
|
* @con: connection ID for this clock
|
|
*
|
|
* Creates a clock alias for a TI clock. Allocates the clock lookup entry
|
|
* and assigns the data to it. Returns 0 if successful, negative error
|
|
* value otherwise.
|
|
*/
|
|
int ti_clk_add_alias(struct device *dev, struct clk *clk, const char *con)
|
|
{
|
|
struct clk_lookup *cl;
|
|
|
|
if (!clk)
|
|
return 0;
|
|
|
|
if (IS_ERR(clk))
|
|
return PTR_ERR(clk);
|
|
|
|
cl = kzalloc(sizeof(*cl), GFP_KERNEL);
|
|
if (!cl)
|
|
return -ENOMEM;
|
|
|
|
if (dev)
|
|
cl->dev_id = dev_name(dev);
|
|
cl->con_id = con;
|
|
cl->clk = clk;
|
|
|
|
clkdev_add(cl);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* ti_clk_register - register a TI clock to the common clock framework
|
|
* @dev: device for this clock
|
|
* @hw: hardware clock handle
|
|
* @con: connection ID for this clock
|
|
*
|
|
* Registers a TI clock to the common clock framework, and adds a clock
|
|
* alias for it. Returns a handle to the registered clock if successful,
|
|
* ERR_PTR value in failure.
|
|
*/
|
|
struct clk *ti_clk_register(struct device *dev, struct clk_hw *hw,
|
|
const char *con)
|
|
{
|
|
struct clk *clk;
|
|
int ret;
|
|
|
|
clk = clk_register(dev, hw);
|
|
if (IS_ERR(clk))
|
|
return clk;
|
|
|
|
ret = ti_clk_add_alias(dev, clk, con);
|
|
if (ret) {
|
|
clk_unregister(clk);
|
|
return ERR_PTR(ret);
|
|
}
|
|
|
|
return clk;
|
|
}
|
|
|
|
/**
|
|
* ti_clk_register_omap_hw - register a clk_hw_omap to the clock framework
|
|
* @dev: device for this clock
|
|
* @hw: hardware clock handle
|
|
* @con: connection ID for this clock
|
|
*
|
|
* Registers a clk_hw_omap clock to the clock framewor, adds a clock alias
|
|
* for it, and adds the list to the available clk_hw_omap type clocks.
|
|
* Returns a handle to the registered clock if successful, ERR_PTR value
|
|
* in failure.
|
|
*/
|
|
struct clk *ti_clk_register_omap_hw(struct device *dev, struct clk_hw *hw,
|
|
const char *con)
|
|
{
|
|
struct clk *clk;
|
|
struct clk_hw_omap *oclk;
|
|
|
|
clk = ti_clk_register(dev, hw, con);
|
|
if (IS_ERR(clk))
|
|
return clk;
|
|
|
|
oclk = to_clk_hw_omap(hw);
|
|
|
|
list_add(&oclk->node, &clk_hw_omap_clocks);
|
|
|
|
return clk;
|
|
}
|
|
|
|
/**
|
|
* omap2_clk_for_each - call function for each registered clk_hw_omap
|
|
* @fn: pointer to a callback function
|
|
*
|
|
* Call @fn for each registered clk_hw_omap, passing @hw to each
|
|
* function. @fn must return 0 for success or any other value for
|
|
* failure. If @fn returns non-zero, the iteration across clocks
|
|
* will stop and the non-zero return value will be passed to the
|
|
* caller of omap2_clk_for_each().
|
|
*/
|
|
int omap2_clk_for_each(int (*fn)(struct clk_hw_omap *hw))
|
|
{
|
|
int ret;
|
|
struct clk_hw_omap *hw;
|
|
|
|
list_for_each_entry(hw, &clk_hw_omap_clocks, node) {
|
|
ret = (*fn)(hw);
|
|
if (ret)
|
|
break;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
/**
|
|
* omap2_clk_is_hw_omap - check if the provided clk_hw is OMAP clock
|
|
* @hw: clk_hw to check if it is an omap clock or not
|
|
*
|
|
* Checks if the provided clk_hw is OMAP clock or not. Returns true if
|
|
* it is, false otherwise.
|
|
*/
|
|
bool omap2_clk_is_hw_omap(struct clk_hw *hw)
|
|
{
|
|
struct clk_hw_omap *oclk;
|
|
|
|
list_for_each_entry(oclk, &clk_hw_omap_clocks, node) {
|
|
if (&oclk->hw == hw)
|
|
return true;
|
|
}
|
|
|
|
return false;
|
|
}
|