David Abdurachmanov 7ede12b01b riscv: dts: fu740: fix cache-controller interrupts ... The order of interrupt numbers is incorrect. The order for FU740 is: DirError, DataError, DataFail, DirFail From SiFive FU740-C000 Manual: 19 - L2 Cache DirError 20 - L2 Cache DirFail 21 - L2 Cache DataError 22 - L2 Cache DataFail Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>		2021-06-19 00:11:53 -07:00
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canaan	riscv: Add Kendryte KD233 board device tree	2021-02-22 17:51:18 -08:00
microchip	riscv: Fix BUILTIN_DTB for sifive and microchip soc	2021-06-11 21:07:09 -07:00
sifive	riscv: dts: fu740: fix cache-controller interrupts	2021-06-19 00:11:53 -07:00
Makefile	RISC-V: Initial DTS for Microchip ICICLE board	2021-04-26 08:31:31 -07:00