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c6f56e7d79
Every frontend now uses DVBv5 way. So, let's not use the DVBv3 macros internally anymore. Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
557 lines
16 KiB
C
557 lines
16 KiB
C
/*
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* dib3000mb_priv.h
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*
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* Copyright (C) 2004 Patrick Boettcher (patrick.boettcher@desy.de)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation, version 2.
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*
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* for more information see dib3000mb.c .
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*/
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#ifndef __DIB3000MB_PRIV_H_INCLUDED__
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#define __DIB3000MB_PRIV_H_INCLUDED__
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/* info and err, taken from usb.h, if there is anything available like by default. */
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#define err(format, arg...) printk(KERN_ERR "dib3000: " format "\n" , ## arg)
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#define info(format, arg...) printk(KERN_INFO "dib3000: " format "\n" , ## arg)
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#define warn(format, arg...) printk(KERN_WARNING "dib3000: " format "\n" , ## arg)
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/* handy shortcuts */
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#define rd(reg) dib3000_read_reg(state,reg)
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#define wr(reg,val) if (dib3000_write_reg(state,reg,val)) \
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{ err("while sending 0x%04x to 0x%04x.",val,reg); return -EREMOTEIO; }
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#define wr_foreach(a,v) { int i; \
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if (sizeof(a) != sizeof(v)) \
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err("sizeof: %zu %zu is different",sizeof(a),sizeof(v));\
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for (i=0; i < sizeof(a)/sizeof(u16); i++) \
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wr(a[i],v[i]); \
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}
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#define set_or(reg,val) wr(reg,rd(reg) | val)
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#define set_and(reg,val) wr(reg,rd(reg) & val)
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/* debug */
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#define dprintk(level,args...) \
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do { if ((debug & level)) { printk(args); } } while (0)
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/* mask for enabling a specific pid for the pid_filter */
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#define DIB3000_ACTIVATE_PID_FILTERING (0x2000)
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/* common values for tuning */
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#define DIB3000_ALPHA_0 ( 0)
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#define DIB3000_ALPHA_1 ( 1)
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#define DIB3000_ALPHA_2 ( 2)
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#define DIB3000_ALPHA_4 ( 4)
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#define DIB3000_CONSTELLATION_QPSK ( 0)
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#define DIB3000_CONSTELLATION_16QAM ( 1)
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#define DIB3000_CONSTELLATION_64QAM ( 2)
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#define DIB3000_GUARD_TIME_1_32 ( 0)
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#define DIB3000_GUARD_TIME_1_16 ( 1)
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#define DIB3000_GUARD_TIME_1_8 ( 2)
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#define DIB3000_GUARD_TIME_1_4 ( 3)
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#define DIB3000_TRANSMISSION_MODE_2K ( 0)
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#define DIB3000_TRANSMISSION_MODE_8K ( 1)
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#define DIB3000_SELECT_LP ( 0)
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#define DIB3000_SELECT_HP ( 1)
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#define DIB3000_FEC_1_2 ( 1)
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#define DIB3000_FEC_2_3 ( 2)
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#define DIB3000_FEC_3_4 ( 3)
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#define DIB3000_FEC_5_6 ( 5)
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#define DIB3000_FEC_7_8 ( 7)
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#define DIB3000_HRCH_OFF ( 0)
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#define DIB3000_HRCH_ON ( 1)
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#define DIB3000_DDS_INVERSION_OFF ( 0)
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#define DIB3000_DDS_INVERSION_ON ( 1)
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#define DIB3000_TUNER_WRITE_ENABLE(a) (0xffff & (a << 8))
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#define DIB3000_TUNER_WRITE_DISABLE(a) (0xffff & ((a << 8) | (1 << 7)))
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#define DIB3000_REG_MANUFACTOR_ID ( 1025)
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#define DIB3000_I2C_ID_DIBCOM (0x01b3)
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#define DIB3000_REG_DEVICE_ID ( 1026)
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#define DIB3000MB_DEVICE_ID (0x3000)
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#define DIB3000MC_DEVICE_ID (0x3001)
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#define DIB3000P_DEVICE_ID (0x3002)
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/* frontend state */
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struct dib3000_state {
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struct i2c_adapter* i2c;
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/* configuration settings */
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struct dib3000_config config;
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struct dvb_frontend frontend;
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int timing_offset;
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int timing_offset_comp_done;
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u32 last_tuned_bw;
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u32 last_tuned_freq;
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};
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/* register addresses and some of their default values */
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/* restart subsystems */
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#define DIB3000MB_REG_RESTART ( 0)
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#define DIB3000MB_RESTART_OFF ( 0)
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#define DIB3000MB_RESTART_AUTO_SEARCH (1 << 1)
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#define DIB3000MB_RESTART_CTRL (1 << 2)
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#define DIB3000MB_RESTART_AGC (1 << 3)
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/* FFT size */
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#define DIB3000MB_REG_FFT ( 1)
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/* Guard time */
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#define DIB3000MB_REG_GUARD_TIME ( 2)
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/* QAM */
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#define DIB3000MB_REG_QAM ( 3)
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/* Alpha coefficient high priority Viterbi algorithm */
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#define DIB3000MB_REG_VIT_ALPHA ( 4)
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/* spectrum inversion */
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#define DIB3000MB_REG_DDS_INV ( 5)
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/* DDS frequency value (IF position) ad ? values don't match reg_3000mb.txt */
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#define DIB3000MB_REG_DDS_FREQ_MSB ( 6)
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#define DIB3000MB_REG_DDS_FREQ_LSB ( 7)
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#define DIB3000MB_DDS_FREQ_MSB ( 178)
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#define DIB3000MB_DDS_FREQ_LSB ( 8990)
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/* timing frequency (carrier spacing) */
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static u16 dib3000mb_reg_timing_freq[] = { 8,9 };
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static u16 dib3000mb_timing_freq[][2] = {
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{ 126 , 48873 }, /* 6 MHz */
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{ 147 , 57019 }, /* 7 MHz */
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{ 168 , 65164 }, /* 8 MHz */
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};
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/* impulse noise parameter */
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/* 36 ??? */
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static u16 dib3000mb_reg_impulse_noise[] = { 10,11,12,15,36 };
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enum dib3000mb_impulse_noise_type {
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DIB3000MB_IMPNOISE_OFF,
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DIB3000MB_IMPNOISE_MOBILE,
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DIB3000MB_IMPNOISE_FIXED,
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DIB3000MB_IMPNOISE_DEFAULT
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};
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static u16 dib3000mb_impulse_noise_values[][5] = {
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{ 0x0000, 0x0004, 0x0014, 0x01ff, 0x0399 }, /* off */
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{ 0x0001, 0x0004, 0x0014, 0x01ff, 0x037b }, /* mobile */
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{ 0x0001, 0x0004, 0x0020, 0x01bd, 0x0399 }, /* fixed */
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{ 0x0000, 0x0002, 0x000a, 0x01ff, 0x0399 }, /* default */
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};
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/*
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* Dual Automatic-Gain-Control
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* - gains RF in tuner (AGC1)
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* - gains IF after filtering (AGC2)
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*/
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/* also from 16 to 18 */
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static u16 dib3000mb_reg_agc_gain[] = {
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19,20,21,22,23,24,25,26,27,28,29,30,31,32
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};
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static u16 dib3000mb_default_agc_gain[] =
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{ 0x0001, 52429, 623, 128, 166, 195, 61, /* RF ??? */
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0x0001, 53766, 38011, 0, 90, 33, 23 }; /* IF ??? */
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/* phase noise */
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/* 36 is set when setting the impulse noise */
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static u16 dib3000mb_reg_phase_noise[] = { 33,34,35,37,38 };
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static u16 dib3000mb_default_noise_phase[] = { 2, 544, 0, 5, 4 };
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/* lock duration */
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static u16 dib3000mb_reg_lock_duration[] = { 39,40 };
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static u16 dib3000mb_default_lock_duration[] = { 135, 135 };
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/* AGC loop bandwidth */
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static u16 dib3000mb_reg_agc_bandwidth[] = { 43,44,45,46,47,48,49,50 };
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static u16 dib3000mb_agc_bandwidth_low[] =
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{ 2088, 10, 2088, 10, 3448, 5, 3448, 5 };
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static u16 dib3000mb_agc_bandwidth_high[] =
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{ 2349, 5, 2349, 5, 2586, 2, 2586, 2 };
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/*
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* lock0 definition (coff_lock)
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*/
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#define DIB3000MB_REG_LOCK0_MASK ( 51)
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#define DIB3000MB_LOCK0_DEFAULT ( 4)
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/*
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* lock1 definition (cpil_lock)
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* for auto search
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* which values hide behind the lock masks
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*/
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#define DIB3000MB_REG_LOCK1_MASK ( 52)
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#define DIB3000MB_LOCK1_SEARCH_4 (0x0004)
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#define DIB3000MB_LOCK1_SEARCH_2048 (0x0800)
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#define DIB3000MB_LOCK1_DEFAULT (0x0001)
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/*
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* lock2 definition (fec_lock) */
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#define DIB3000MB_REG_LOCK2_MASK ( 53)
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#define DIB3000MB_LOCK2_DEFAULT (0x0080)
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/*
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* SEQ ? what was that again ... :)
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* changes when, inversion, guard time and fft is
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* either automatically detected or not
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*/
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#define DIB3000MB_REG_SEQ ( 54)
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/* bandwidth */
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static u16 dib3000mb_reg_bandwidth[] = { 55,56,57,58,59,60,61,62,63,64,65,66,67 };
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static u16 dib3000mb_bandwidth_6mhz[] =
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{ 0, 33, 53312, 112, 46635, 563, 36565, 0, 1000, 0, 1010, 1, 45264 };
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static u16 dib3000mb_bandwidth_7mhz[] =
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{ 0, 28, 64421, 96, 39973, 483, 3255, 0, 1000, 0, 1010, 1, 45264 };
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static u16 dib3000mb_bandwidth_8mhz[] =
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{ 0, 25, 23600, 84, 34976, 422, 43808, 0, 1000, 0, 1010, 1, 45264 };
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#define DIB3000MB_REG_UNK_68 ( 68)
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#define DIB3000MB_UNK_68 ( 0)
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#define DIB3000MB_REG_UNK_69 ( 69)
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#define DIB3000MB_UNK_69 ( 0)
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#define DIB3000MB_REG_UNK_71 ( 71)
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#define DIB3000MB_UNK_71 ( 0)
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#define DIB3000MB_REG_UNK_77 ( 77)
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#define DIB3000MB_UNK_77 ( 6)
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#define DIB3000MB_REG_UNK_78 ( 78)
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#define DIB3000MB_UNK_78 (0x0080)
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/* isi */
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#define DIB3000MB_REG_ISI ( 79)
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#define DIB3000MB_ISI_ACTIVATE ( 0)
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#define DIB3000MB_ISI_INHIBIT ( 1)
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/* sync impovement */
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#define DIB3000MB_REG_SYNC_IMPROVEMENT ( 84)
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#define DIB3000MB_SYNC_IMPROVE_2K_1_8 ( 3)
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#define DIB3000MB_SYNC_IMPROVE_DEFAULT ( 0)
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/* phase noise compensation inhibition */
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#define DIB3000MB_REG_PHASE_NOISE ( 87)
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#define DIB3000MB_PHASE_NOISE_DEFAULT ( 0)
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#define DIB3000MB_REG_UNK_92 ( 92)
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#define DIB3000MB_UNK_92 (0x0080)
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#define DIB3000MB_REG_UNK_96 ( 96)
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#define DIB3000MB_UNK_96 (0x0010)
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#define DIB3000MB_REG_UNK_97 ( 97)
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#define DIB3000MB_UNK_97 (0x0009)
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/* mobile mode ??? */
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#define DIB3000MB_REG_MOBILE_MODE ( 101)
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#define DIB3000MB_MOBILE_MODE_ON ( 1)
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#define DIB3000MB_MOBILE_MODE_OFF ( 0)
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#define DIB3000MB_REG_UNK_106 ( 106)
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#define DIB3000MB_UNK_106 (0x0080)
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#define DIB3000MB_REG_UNK_107 ( 107)
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#define DIB3000MB_UNK_107 (0x0080)
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#define DIB3000MB_REG_UNK_108 ( 108)
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#define DIB3000MB_UNK_108 (0x0080)
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/* fft */
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#define DIB3000MB_REG_UNK_121 ( 121)
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#define DIB3000MB_UNK_121_2K ( 7)
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#define DIB3000MB_UNK_121_DEFAULT ( 5)
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#define DIB3000MB_REG_UNK_122 ( 122)
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#define DIB3000MB_UNK_122 ( 2867)
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/* QAM for mobile mode */
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#define DIB3000MB_REG_MOBILE_MODE_QAM ( 126)
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#define DIB3000MB_MOBILE_MODE_QAM_64 ( 3)
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#define DIB3000MB_MOBILE_MODE_QAM_QPSK_16 ( 1)
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#define DIB3000MB_MOBILE_MODE_QAM_OFF ( 0)
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/*
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* data diversity when having more than one chip on-board
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* see also DIB3000MB_OUTPUT_MODE_DATA_DIVERSITY
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*/
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#define DIB3000MB_REG_DATA_IN_DIVERSITY ( 127)
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#define DIB3000MB_DATA_DIVERSITY_IN_OFF ( 0)
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#define DIB3000MB_DATA_DIVERSITY_IN_ON ( 2)
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/* vit hrch */
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#define DIB3000MB_REG_VIT_HRCH ( 128)
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/* vit code rate */
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#define DIB3000MB_REG_VIT_CODE_RATE ( 129)
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/* vit select hp */
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#define DIB3000MB_REG_VIT_HP ( 130)
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/* time frame for Bit-Error-Rate calculation */
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#define DIB3000MB_REG_BERLEN ( 135)
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#define DIB3000MB_BERLEN_LONG ( 0)
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#define DIB3000MB_BERLEN_DEFAULT ( 1)
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#define DIB3000MB_BERLEN_MEDIUM ( 2)
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#define DIB3000MB_BERLEN_SHORT ( 3)
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/* 142 - 152 FIFO parameters
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* which is what ?
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*/
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#define DIB3000MB_REG_FIFO_142 ( 142)
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#define DIB3000MB_FIFO_142 ( 0)
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/* MPEG2 TS output mode */
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#define DIB3000MB_REG_MPEG2_OUT_MODE ( 143)
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#define DIB3000MB_MPEG2_OUT_MODE_204 ( 0)
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#define DIB3000MB_MPEG2_OUT_MODE_188 ( 1)
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#define DIB3000MB_REG_PID_PARSE ( 144)
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#define DIB3000MB_PID_PARSE_INHIBIT ( 0)
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#define DIB3000MB_PID_PARSE_ACTIVATE ( 1)
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#define DIB3000MB_REG_FIFO ( 145)
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#define DIB3000MB_FIFO_INHIBIT ( 1)
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#define DIB3000MB_FIFO_ACTIVATE ( 0)
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#define DIB3000MB_REG_FIFO_146 ( 146)
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#define DIB3000MB_FIFO_146 ( 3)
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#define DIB3000MB_REG_FIFO_147 ( 147)
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#define DIB3000MB_FIFO_147 (0x0100)
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/*
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* pidfilter
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* it is not a hardware pidfilter but a filter which drops all pids
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* except the ones set. Necessary because of the limited USB1.1 bandwidth.
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* regs 153-168
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*/
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#define DIB3000MB_REG_FIRST_PID ( 153)
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#define DIB3000MB_NUM_PIDS ( 16)
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/*
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* output mode
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* USB devices have to use 'slave'-mode
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* see also DIB3000MB_REG_ELECT_OUT_MODE
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*/
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#define DIB3000MB_REG_OUTPUT_MODE ( 169)
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#define DIB3000MB_OUTPUT_MODE_GATED_CLK ( 0)
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#define DIB3000MB_OUTPUT_MODE_CONT_CLK ( 1)
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#define DIB3000MB_OUTPUT_MODE_SERIAL ( 2)
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#define DIB3000MB_OUTPUT_MODE_DATA_DIVERSITY ( 5)
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#define DIB3000MB_OUTPUT_MODE_SLAVE ( 6)
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/* irq event mask */
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#define DIB3000MB_REG_IRQ_EVENT_MASK ( 170)
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#define DIB3000MB_IRQ_EVENT_MASK ( 0)
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/* filter coefficients */
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static u16 dib3000mb_reg_filter_coeffs[] = {
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171, 172, 173, 174, 175, 176, 177, 178,
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179, 180, 181, 182, 183, 184, 185, 186,
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188, 189, 190, 191, 192, 194
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};
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static u16 dib3000mb_filter_coeffs[] = {
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226, 160, 29,
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979, 998, 19,
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22, 1019, 1006,
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1022, 12, 6,
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1017, 1017, 3,
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6, 1019,
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1021, 2, 3,
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1, 0,
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};
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/*
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* mobile algorithm (when you are moving with your device)
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* but not faster than 90 km/h
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*/
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#define DIB3000MB_REG_MOBILE_ALGO ( 195)
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#define DIB3000MB_MOBILE_ALGO_ON ( 0)
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#define DIB3000MB_MOBILE_ALGO_OFF ( 1)
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/* multiple demodulators algorithm */
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#define DIB3000MB_REG_MULTI_DEMOD_MSB ( 206)
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#define DIB3000MB_REG_MULTI_DEMOD_LSB ( 207)
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/* terminator, no more demods */
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#define DIB3000MB_MULTI_DEMOD_MSB ( 32767)
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#define DIB3000MB_MULTI_DEMOD_LSB ( 4095)
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/* bring the device into a known */
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#define DIB3000MB_REG_RESET_DEVICE ( 1024)
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#define DIB3000MB_RESET_DEVICE (0x812c)
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#define DIB3000MB_RESET_DEVICE_RST ( 0)
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/* hardware clock configuration */
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#define DIB3000MB_REG_CLOCK ( 1027)
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#define DIB3000MB_CLOCK_DEFAULT (0x9000)
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#define DIB3000MB_CLOCK_DIVERSITY (0x92b0)
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/* power down config */
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#define DIB3000MB_REG_POWER_CONTROL ( 1028)
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#define DIB3000MB_POWER_DOWN ( 1)
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#define DIB3000MB_POWER_UP ( 0)
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/* electrical output mode */
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#define DIB3000MB_REG_ELECT_OUT_MODE ( 1029)
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#define DIB3000MB_ELECT_OUT_MODE_OFF ( 0)
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#define DIB3000MB_ELECT_OUT_MODE_ON ( 1)
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/* set the tuner i2c address */
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#define DIB3000MB_REG_TUNER ( 1089)
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/* monitoring registers (read only) */
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/* agc loop locked (size: 1) */
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#define DIB3000MB_REG_AGC_LOCK ( 324)
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/* agc power (size: 16) */
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#define DIB3000MB_REG_AGC_POWER ( 325)
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/* agc1 value (16) */
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#define DIB3000MB_REG_AGC1_VALUE ( 326)
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/* agc2 value (16) */
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#define DIB3000MB_REG_AGC2_VALUE ( 327)
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/* total RF power (16), can be used for signal strength */
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#define DIB3000MB_REG_RF_POWER ( 328)
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/* dds_frequency with offset (24) */
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#define DIB3000MB_REG_DDS_VALUE_MSB ( 339)
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#define DIB3000MB_REG_DDS_VALUE_LSB ( 340)
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/* timing offset signed (24) */
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#define DIB3000MB_REG_TIMING_OFFSET_MSB ( 341)
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#define DIB3000MB_REG_TIMING_OFFSET_LSB ( 342)
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/* fft start position (13) */
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#define DIB3000MB_REG_FFT_WINDOW_POS ( 353)
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/* carriers locked (1) */
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#define DIB3000MB_REG_CARRIER_LOCK ( 355)
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/* noise power (24) */
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#define DIB3000MB_REG_NOISE_POWER_MSB ( 372)
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#define DIB3000MB_REG_NOISE_POWER_LSB ( 373)
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#define DIB3000MB_REG_MOBILE_NOISE_MSB ( 374)
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#define DIB3000MB_REG_MOBILE_NOISE_LSB ( 375)
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/*
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* signal power (16), this and the above can be
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* used to calculate the signal/noise - ratio
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*/
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#define DIB3000MB_REG_SIGNAL_POWER ( 380)
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/* mer (24) */
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#define DIB3000MB_REG_MER_MSB ( 381)
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#define DIB3000MB_REG_MER_LSB ( 382)
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/*
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* Transmission Parameter Signalling (TPS)
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* the following registers can be used to get TPS-information.
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* The values are according to the DVB-T standard.
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*/
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/* TPS locked (1) */
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#define DIB3000MB_REG_TPS_LOCK ( 394)
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/* QAM from TPS (2) (values according to DIB3000MB_REG_QAM) */
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#define DIB3000MB_REG_TPS_QAM ( 398)
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/* hierarchy from TPS (1) */
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#define DIB3000MB_REG_TPS_HRCH ( 399)
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/* alpha from TPS (3) (values according to DIB3000MB_REG_VIT_ALPHA) */
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#define DIB3000MB_REG_TPS_VIT_ALPHA ( 400)
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/* code rate high priority from TPS (3) (values according to DIB3000MB_FEC_*) */
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#define DIB3000MB_REG_TPS_CODE_RATE_HP ( 401)
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/* code rate low priority from TPS (3) if DIB3000MB_REG_TPS_VIT_ALPHA */
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#define DIB3000MB_REG_TPS_CODE_RATE_LP ( 402)
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/* guard time from TPS (2) (values according to DIB3000MB_REG_GUARD_TIME */
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#define DIB3000MB_REG_TPS_GUARD_TIME ( 403)
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/* fft size from TPS (2) (values according to DIB3000MB_REG_FFT) */
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#define DIB3000MB_REG_TPS_FFT ( 404)
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/* cell id from TPS (16) */
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#define DIB3000MB_REG_TPS_CELL_ID ( 406)
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/* TPS (68) */
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#define DIB3000MB_REG_TPS_1 ( 408)
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#define DIB3000MB_REG_TPS_2 ( 409)
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#define DIB3000MB_REG_TPS_3 ( 410)
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#define DIB3000MB_REG_TPS_4 ( 411)
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#define DIB3000MB_REG_TPS_5 ( 412)
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/* bit error rate (before RS correction) (21) */
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#define DIB3000MB_REG_BER_MSB ( 414)
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#define DIB3000MB_REG_BER_LSB ( 415)
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/* packet error rate (uncorrected TS packets) (16) */
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#define DIB3000MB_REG_PACKET_ERROR_RATE ( 417)
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/* uncorrected packet count (16) */
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#define DIB3000MB_REG_UNC ( 420)
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/* viterbi locked (1) */
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#define DIB3000MB_REG_VIT_LCK ( 421)
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/* viterbi inidcator (16) */
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#define DIB3000MB_REG_VIT_INDICATOR ( 422)
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/* transport stream sync lock (1) */
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#define DIB3000MB_REG_TS_SYNC_LOCK ( 423)
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/* transport stream RS lock (1) */
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#define DIB3000MB_REG_TS_RS_LOCK ( 424)
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/* lock mask 0 value (1) */
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#define DIB3000MB_REG_LOCK0_VALUE ( 425)
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/* lock mask 1 value (1) */
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#define DIB3000MB_REG_LOCK1_VALUE ( 426)
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/* lock mask 2 value (1) */
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#define DIB3000MB_REG_LOCK2_VALUE ( 427)
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/* interrupt pending for auto search */
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#define DIB3000MB_REG_AS_IRQ_PENDING ( 434)
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#endif
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