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Add TI WL18XX Wifi for BTicino i.MX6DL board. Signed-off-by: Simone CIANNI <simone.cianni@bticino.it> Signed-off-by: Raffaele RECALCATI <raffaele.recalcati@bticino.it> Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
463 lines
11 KiB
Plaintext
463 lines
11 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (C) 2018 BTicino
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* Copyright (C) 2018 Amarula Solutions B.V.
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*/
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/dts-v1/;
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#include <dt-bindings/gpio/gpio.h>
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#include "imx6dl.dtsi"
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/ {
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model = "BTicino i.MX6DL Mamoj board";
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compatible = "bticino,imx6dl-mamoj", "fsl,imx6dl";
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backlight_lcd: backlight-lcd {
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compatible = "pwm-backlight";
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pwms = <&pwm3 0 25000>; /* 25000ns -> 40kHz */
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brightness-levels = <0 4 8 16 32 64 128 160 192 224 255>;
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default-brightness-level = <7>;
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};
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display: disp0 {
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compatible = "fsl,imx-parallel-display";
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#address-cells = <1>;
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#size-cells = <0>;
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interface-pix-fmt = "rgb24";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ipu1_lcdif>;
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status = "okay";
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port@0 {
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reg = <0>;
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lcd_display_in: endpoint {
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remote-endpoint = <&ipu1_di0_disp0>;
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};
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};
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port@1 {
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reg = <1>;
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lcd_display_out: endpoint {
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remote-endpoint = <&lcd_panel_in>;
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};
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};
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};
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panel-lcd {
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compatible = "rocktech,rk070er9427";
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backlight = <&backlight_lcd>;
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power-supply = <®_lcd_lr>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ipu1_lcdif_pwr>;
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port {
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lcd_panel_in: endpoint {
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remote-endpoint = <&lcd_display_out>;
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};
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};
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};
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reg_lcd_3v3: regulator-lcd-dvdd {
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compatible = "regulator-fixed";
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regulator-name = "lcd-dvdd";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio3 1 0>;
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enable-active-high;
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startup-delay-us = <21000>;
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};
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reg_lcd_power: regulator-lcd-power {
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compatible = "regulator-fixed";
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regulator-name = "lcd-enable";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio3 6 0>;
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enable-active-high;
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vin-supply = <®_lcd_3v3>;
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};
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reg_lcd_vgl: regulator-lcd-vgl {
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compatible = "regulator-fixed";
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regulator-name = "lcd-vgl";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>;
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startup-delay-us = <6000>;
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enable-active-high;
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vin-supply = <®_lcd_power>;
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};
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reg_lcd_vgh: regulator-lcd-vgh {
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compatible = "regulator-fixed";
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regulator-name = "lcd-vgh";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>;
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startup-delay-us = <6000>;
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enable-active-high;
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vin-supply = <®_lcd_avdd>;
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};
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reg_lcd_vcom: regulator-lcd-vcom {
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compatible = "regulator-fixed";
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regulator-name = "lcd-vcom";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio4 14 GPIO_ACTIVE_HIGH>;
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startup-delay-us = <11000>;
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enable-active-high;
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vin-supply = <®_lcd_vgh>;
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};
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reg_lcd_lr: regulator-lcd-lr {
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compatible = "regulator-fixed";
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regulator-name = "lcd-lr";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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vin-supply = <®_lcd_vcom>;
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};
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reg_lcd_avdd: regulator-lcd-avdd {
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compatible = "regulator-fixed";
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regulator-name = "lcd-avdd";
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regulator-min-microvolt = <10280000>;
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regulator-max-microvolt = <10280000>;
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gpio = <&gpio2 13 GPIO_ACTIVE_HIGH>;
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startup-delay-us = <6000>;
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enable-active-high;
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vin-supply = <®_lcd_vgl>;
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};
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reg_wl18xx_vmmc: regulator-wl18xx-vmcc {
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compatible = "regulator-fixed";
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regulator-name = "vwl1807";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_wlan>;
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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gpio = <&gpio6 21 GPIO_ACTIVE_HIGH>;
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startup-delay-us = <70000>;
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enable-active-high;
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};
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};
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&fec {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_enet>;
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phy-mode = "mii";
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status = "okay";
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};
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&i2c3 {
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clock-frequency = <400000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c3>;
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status = "okay";
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};
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&i2c4 {
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c4>;
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status = "okay";
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pfuze100: pmic@8 {
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compatible = "fsl,pfuze100";
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reg = <0x08>;
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regulators {
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/* CPU vdd_arm core */
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sw1a_reg: sw1ab {
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regulator-min-microvolt = <300000>;
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regulator-max-microvolt = <1875000>;
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regulator-boot-on;
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regulator-always-on;
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regulator-ramp-delay = <6250>;
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};
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/* SOC vdd_soc */
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sw1c_reg: sw1c {
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regulator-min-microvolt = <300000>;
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regulator-max-microvolt = <1875000>;
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regulator-boot-on;
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regulator-always-on;
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regulator-ramp-delay = <6250>;
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};
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/* I/O power GEN_3V3 */
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sw2_reg: sw2 {
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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/* DDR memory */
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sw3a_reg: sw3a {
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regulator-min-microvolt = <400000>;
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regulator-max-microvolt = <1975000>;
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regulator-boot-on;
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regulator-always-on;
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};
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/* DDR memory */
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sw3b_reg: sw3b {
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regulator-min-microvolt = <400000>;
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regulator-max-microvolt = <1975000>;
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regulator-boot-on;
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regulator-always-on;
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};
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/* not used */
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sw4_reg: sw4 {
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <3300000>;
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};
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/* not used */
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swbst_reg: swbst {
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5150000>;
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};
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/* PMIC vsnvs. EX boot mode */
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snvs_reg: vsnvs {
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regulator-min-microvolt = <1000000>;
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regulator-max-microvolt = <3000000>;
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regulator-boot-on;
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regulator-always-on;
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};
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vref_reg: vrefddr {
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regulator-boot-on;
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regulator-always-on;
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};
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/* not used */
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vgen1_reg: vgen1 {
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <1550000>;
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};
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/* not used */
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vgen2_reg: vgen2 {
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <1550000>;
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};
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/* not used */
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vgen3_reg: vgen3 {
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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};
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/* 1v8 general power */
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vgen4_reg: vgen4 {
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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/* 2v8 general power IMX6 */
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vgen5_reg: vgen5 {
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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/* 3v3 Ethernet */
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vgen6_reg: vgen6 {
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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};
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};
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};
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&ipu1_di0_disp0 {
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remote-endpoint = <&lcd_display_in>;
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};
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&pwm3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pwm3>;
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status = "okay";
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};
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&uart3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart3>;
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status = "okay";
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};
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&usdhc1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc1>;
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bus-width = <4>;
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vmmc-supply = <®_wl18xx_vmmc>;
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no-1-8-v;
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non-removable;
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wakeup-source;
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keep-power-in-suspend;
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cap-power-off-card;
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max-frequency = <25000000>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "okay";
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wlcore: wlcore@2 {
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compatible = "ti,wl1837";
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reg = <2>;
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interrupt-parent = <&gpio6>;
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interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
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tcxo-clock-frequency = <26000000>;
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};
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};
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&usdhc3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc3>;
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bus-width = <8>;
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non-removable;
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keep-power-in-suspend;
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status = "okay";
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};
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&iomuxc {
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pinctrl_enet: enetgrp {
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fsl,pins = <
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MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
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MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
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MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b1
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MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0
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MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0
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MX6QDL_PAD_KEY_ROW2__ENET_TX_DATA2 0x1b0b0
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MX6QDL_PAD_KEY_ROW0__ENET_TX_DATA3 0x1b0b0
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MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
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MX6QDL_PAD_GPIO_19__ENET_TX_ER 0x1b0b0
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MX6QDL_PAD_GPIO_18__ENET_RX_CLK 0x1b0b1
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MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0
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MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0
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MX6QDL_PAD_KEY_COL2__ENET_RX_DATA2 0x1b0b0
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MX6QDL_PAD_KEY_COL0__ENET_RX_DATA3 0x1b0b0
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MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
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MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0
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MX6QDL_PAD_KEY_COL3__ENET_CRS 0x1b0b0
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MX6QDL_PAD_KEY_ROW1__ENET_COL 0x1b0b0
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>;
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};
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pinctrl_i2c3: i2c3grp {
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fsl,pins = <
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MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
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MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
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>;
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};
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pinctrl_i2c4: i2c4grp {
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fsl,pins = <
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MX6QDL_PAD_GPIO_7__I2C4_SCL 0x4001b8b1
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MX6QDL_PAD_GPIO_8__I2C4_SDA 0x4001b8b1
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>;
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};
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pinctrl_ipu1_lcdif: pinctrlipu1lcdif { /* parallel port 24-bit */
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fsl,pins = <
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MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 /* VDOUT_PCLK */
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MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
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MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 /* VDOUT_HSYNC */
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MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 /* VDOUT_VSYNC */
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MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x10 /* VDOUT_RESET */
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MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
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MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
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MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
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MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
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MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
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MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
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MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
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MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
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MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
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MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
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MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
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MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
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MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
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MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
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MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
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MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
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MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
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MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
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MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
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MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
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MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
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MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
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MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
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MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
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>;
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};
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pinctrl_ipu1_lcdif_pwr: ipu1lcdifpwrgrp {
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fsl,pins = <
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MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x40013058 /* EN_LCD33V */
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MX6QDL_PAD_SD4_DAT5__GPIO2_IO13 0x4001b0b0 /* EN_AVDD */
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MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x40013058 /* ENVGH */
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MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x40013058 /* ENVGL */
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MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x40013058 /* LCD_POWER */
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MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x40013058 /* EN_VCOM_LCD */
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MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x40013058 /* LCD_L_R */
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MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x40013058 /* LCD_U_D */
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>;
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};
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pinctrl_pwm3: pwm3grp {
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fsl,pins = <
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MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
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>;
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};
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pinctrl_uart3: uart3grp {
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fsl,pins = <
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MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
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MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
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>;
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};
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pinctrl_usdhc1: usdhc1grp {
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fsl,pins = <
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MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17069
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MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10079
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MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17069
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MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17069
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MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17069
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MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17069
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>;
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};
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|
|
pinctrl_usdhc3: usdhc3grp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
|
|
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
|
|
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
|
|
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
|
|
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
|
|
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
|
|
MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
|
|
MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
|
|
MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
|
|
MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
|
|
>;
|
|
};
|
|
|
|
pinctrl_wlan: wlangrp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_RGMII_TD1__GPIO6_IO21 0x4001b0b0
|
|
>;
|
|
};
|
|
};
|