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75ab939394
The OPPs for the A83T CPU cores were added in v4.17 in commit 2db639d8c1
("ARM: dts: sun8i: a83t: add stable OPP tables and CPUfreq"), but board
level regulator supplies for the CPU clusters were only added for the
TBS-A711 tablet. This means the other A83T boards do not benefit from
voltage scaling, or worse, if the implementation does not scale the
frequency when the voltage is fixed, no benefit at all.
Add board level CPU cluster power supplies to all the A83T development
boards, so they can have proper dynamic CPU voltage and frequency scaling.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
365 lines
8.2 KiB
Plaintext
365 lines
8.2 KiB
Plaintext
/*
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* Copyright 2017 Chen-Yu Tsai
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*
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* Chen-Yu Tsai <wens@csie.org>
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This file is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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/dts-v1/;
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#include "sun8i-a83t.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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/ {
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model = "Banana Pi BPI-M3";
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compatible = "sinovoip,bpi-m3", "allwinner,sun8i-a83t";
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aliases {
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ethernet0 = &emac;
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serial0 = &uart0;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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connector {
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compatible = "hdmi-connector";
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type = "a";
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port {
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hdmi_con_in: endpoint {
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remote-endpoint = <&hdmi_out_con>;
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};
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};
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};
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leds {
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compatible = "gpio-leds";
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blue {
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label = "bananapi-m3:blue:usr";
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gpios = <&axp_gpio 1 GPIO_ACTIVE_HIGH>;
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};
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green {
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label = "bananapi-m3:green:usr";
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gpios = <&axp_gpio 0 GPIO_ACTIVE_HIGH>;
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};
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};
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reg_usb1_vbus: reg-usb1-vbus {
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compatible = "regulator-fixed";
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regulator-name = "usb1-vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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regulator-boot-on;
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enable-active-high;
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gpio = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* PD24 */
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};
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wifi_pwrseq: wifi_pwrseq {
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compatible = "mmc-pwrseq-simple";
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clocks = <&ac100_rtc 1>;
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clock-names = "ext_clock";
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/* The WiFi low power clock must be 32768 Hz */
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assigned-clocks = <&ac100_rtc 1>;
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assigned-clock-rates = <32768>;
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/* enables internal regulator and de-asserts reset */
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reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 WL-PMU-EN */
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};
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};
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&cpu0 {
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cpu-supply = <®_dcdc2>;
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};
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&cpu100 {
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cpu-supply = <®_dcdc3>;
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};
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&de {
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status = "okay";
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};
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&ehci0 {
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/* Terminus Tech FE 1.1s 4-port USB 2.0 hub here */
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status = "okay";
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/* TODO GL830 USB-to-SATA bridge downstream w/ GPIO power controls */
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};
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&emac {
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pinctrl-names = "default";
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pinctrl-0 = <&emac_rgmii_pins>;
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phy-supply = <®_sw>;
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phy-handle = <&rgmii_phy>;
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phy-mode = "rgmii";
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allwinner,rx-delay-ps = <700>;
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allwinner,tx-delay-ps = <700>;
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status = "okay";
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};
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&hdmi {
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status = "okay";
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};
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&hdmi_out {
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hdmi_out_con: endpoint {
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remote-endpoint = <&hdmi_con_in>;
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};
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};
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&mdio {
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rgmii_phy: ethernet-phy@1 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <1>;
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};
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};
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&mmc0 {
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pinctrl-names = "default";
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pinctrl-0 = <&mmc0_pins>;
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vmmc-supply = <®_dcdc1>;
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bus-width = <4>;
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cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
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status = "okay";
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};
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&mmc1 {
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vmmc-supply = <®_dldo1>;
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vqmmc-supply = <®_dldo1>;
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mmc-pwrseq = <&wifi_pwrseq>;
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bus-width = <4>;
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non-removable;
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status = "okay";
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brcmf: wifi@1 {
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reg = <1>;
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compatible = "brcm,bcm4329-fmac";
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interrupt-parent = <&r_pio>;
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interrupts = <0 3 IRQ_TYPE_LEVEL_LOW>;
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interrupt-names = "host-wake";
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};
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};
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&mmc2 {
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pinctrl-names = "default";
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pinctrl-0 = <&mmc2_8bit_emmc_pins>;
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vmmc-supply = <®_dcdc1>;
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vqmmc-supply = <®_dcdc1>;
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bus-width = <8>;
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non-removable;
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cap-mmc-hw-reset;
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status = "okay";
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};
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&r_rsb {
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status = "okay";
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axp81x: pmic@3a3 {
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compatible = "x-powers,axp813";
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reg = <0x3a3>;
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interrupt-parent = <&r_intc>;
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interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
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eldoin-supply = <®_dcdc1>;
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fldoin-supply = <®_dcdc5>;
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swin-supply = <®_dcdc1>;
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x-powers,drive-vbus-en;
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};
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ac100: codec@e89 {
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compatible = "x-powers,ac100";
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reg = <0xe89>;
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ac100_codec: codec {
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compatible = "x-powers,ac100-codec";
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interrupt-parent = <&r_pio>;
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interrupts = <0 11 IRQ_TYPE_LEVEL_LOW>; /* PL11 */
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#clock-cells = <0>;
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clock-output-names = "4M_adda";
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};
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ac100_rtc: rtc {
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compatible = "x-powers,ac100-rtc";
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interrupt-parent = <&r_intc>;
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interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&ac100_codec>;
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#clock-cells = <1>;
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clock-output-names = "cko1_rtc",
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"cko2_rtc",
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"cko3_rtc";
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};
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};
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};
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#include "axp81x.dtsi"
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®_aldo1 {
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regulator-always-on;
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-name = "vcc-1v8";
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};
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®_aldo2 {
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regulator-always-on;
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-name = "dram-pll";
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};
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®_aldo3 {
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regulator-always-on;
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regulator-min-microvolt = <3000000>;
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regulator-max-microvolt = <3000000>;
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regulator-name = "avcc";
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};
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®_dcdc1 {
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/* schematics says 3.1V but FEX file says 3.3V */
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regulator-always-on;
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-name = "vcc-3v3";
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};
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®_dcdc2 {
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regulator-always-on;
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regulator-min-microvolt = <700000>;
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regulator-max-microvolt = <1100000>;
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regulator-name = "vdd-cpua";
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};
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®_dcdc3 {
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regulator-always-on;
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regulator-min-microvolt = <700000>;
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regulator-max-microvolt = <1100000>;
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regulator-name = "vdd-cpub";
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};
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®_dcdc4 {
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regulator-min-microvolt = <700000>;
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regulator-max-microvolt = <1100000>;
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regulator-name = "vdd-gpu";
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};
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®_dcdc5 {
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regulator-always-on;
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regulator-min-microvolt = <1200000>;
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regulator-max-microvolt = <1200000>;
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regulator-name = "vcc-dram";
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};
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®_dcdc6 {
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regulator-always-on;
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regulator-min-microvolt = <900000>;
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regulator-max-microvolt = <900000>;
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regulator-name = "vdd-sys";
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};
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®_dldo1 {
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/*
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* This powers both the WiFi/BT module's main power, I/O supply,
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* and external pull-ups on all the data lines. It should be set
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* to the same voltage as the I/O supply (DCDC1 in this case) to
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* avoid any leakage or mismatch.
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*/
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-name = "vcc-wifi";
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};
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®_dldo3 {
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regulator-always-on;
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regulator-min-microvolt = <2500000>;
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regulator-max-microvolt = <2500000>;
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regulator-name = "vcc-pd";
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};
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®_drivevbus {
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regulator-name = "usb0-vbus";
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status = "okay";
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};
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®_fldo1 {
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regulator-min-microvolt = <1080000>;
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regulator-max-microvolt = <1320000>;
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regulator-name = "vdd12-hsic";
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};
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®_fldo2 {
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/*
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* Despite the embedded CPUs core not being used in any way,
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* this must remain on or the system will hang.
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*/
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regulator-always-on;
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regulator-min-microvolt = <700000>;
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regulator-max-microvolt = <1100000>;
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regulator-name = "vdd-cpus";
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};
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®_rtc_ldo {
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regulator-name = "vcc-rtc";
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};
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®_sw {
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/*
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* The PHY requires 20ms after all voltages
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* are applied until core logic is ready and
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* 30ms after the reset pin is de-asserted.
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* Set a 100ms delay to account for PMIC
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* ramp time and board traces.
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*/
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regulator-enable-ramp-delay = <100000>;
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regulator-name = "vcc-ephy";
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};
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&uart0 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart0_pb_pins>;
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status = "okay";
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};
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&usbphy {
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usb1_vbus-supply = <®_usb1_vbus>;
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status = "okay";
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};
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