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261625e0ba
Add the support for mem ops implementation to handle the sequence of enable/disable of the memories in ethernet PHY, prior to enable/disable of the respective clocks, which helps retain the respecive block's register contents. Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231123064735.2979802-3-quic_imrashai@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
194 lines
4.6 KiB
C
194 lines
4.6 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2013, The Linux Foundation. All rights reserved.
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* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include <linux/kernel.h>
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#include <linux/bitops.h>
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#include <linux/err.h>
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#include <linux/delay.h>
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#include <linux/export.h>
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#include <linux/clk-provider.h>
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#include <linux/regmap.h>
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#include "clk-branch.h"
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static bool clk_branch_in_hwcg_mode(const struct clk_branch *br)
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{
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u32 val;
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if (!br->hwcg_reg)
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return false;
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regmap_read(br->clkr.regmap, br->hwcg_reg, &val);
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return !!(val & BIT(br->hwcg_bit));
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}
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static bool clk_branch_check_halt(const struct clk_branch *br, bool enabling)
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{
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bool invert = (br->halt_check == BRANCH_HALT_ENABLE);
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u32 val;
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regmap_read(br->clkr.regmap, br->halt_reg, &val);
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val &= BIT(br->halt_bit);
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if (invert)
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val = !val;
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return !!val == !enabling;
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}
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static bool clk_branch2_check_halt(const struct clk_branch *br, bool enabling)
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{
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u32 val;
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u32 mask;
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bool invert = (br->halt_check == BRANCH_HALT_ENABLE);
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mask = CBCR_NOC_FSM_STATUS;
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mask |= CBCR_CLK_OFF;
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regmap_read(br->clkr.regmap, br->halt_reg, &val);
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if (enabling) {
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val &= mask;
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return (val & CBCR_CLK_OFF) == (invert ? CBCR_CLK_OFF : 0) ||
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FIELD_GET(CBCR_NOC_FSM_STATUS, val) == FSM_STATUS_ON;
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}
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return (val & CBCR_CLK_OFF) == (invert ? 0 : CBCR_CLK_OFF);
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}
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static int clk_branch_wait(const struct clk_branch *br, bool enabling,
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bool (check_halt)(const struct clk_branch *, bool))
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{
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bool voted = br->halt_check & BRANCH_VOTED;
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const char *name = clk_hw_get_name(&br->clkr.hw);
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/*
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* Skip checking halt bit if we're explicitly ignoring the bit or the
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* clock is in hardware gated mode
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*/
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if (br->halt_check == BRANCH_HALT_SKIP || clk_branch_in_hwcg_mode(br))
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return 0;
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if (br->halt_check == BRANCH_HALT_DELAY || (!enabling && voted)) {
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udelay(10);
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} else if (br->halt_check == BRANCH_HALT_ENABLE ||
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br->halt_check == BRANCH_HALT ||
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(enabling && voted)) {
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int count = 200;
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while (count-- > 0) {
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if (check_halt(br, enabling))
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return 0;
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udelay(1);
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}
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WARN(1, "%s status stuck at 'o%s'", name,
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enabling ? "ff" : "n");
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return -EBUSY;
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}
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return 0;
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}
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static int clk_branch_toggle(struct clk_hw *hw, bool en,
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bool (check_halt)(const struct clk_branch *, bool))
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{
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struct clk_branch *br = to_clk_branch(hw);
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int ret;
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if (en) {
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ret = clk_enable_regmap(hw);
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if (ret)
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return ret;
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} else {
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clk_disable_regmap(hw);
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}
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return clk_branch_wait(br, en, check_halt);
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}
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static int clk_branch_enable(struct clk_hw *hw)
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{
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return clk_branch_toggle(hw, true, clk_branch_check_halt);
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}
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static void clk_branch_disable(struct clk_hw *hw)
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{
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clk_branch_toggle(hw, false, clk_branch_check_halt);
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}
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const struct clk_ops clk_branch_ops = {
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.enable = clk_branch_enable,
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.disable = clk_branch_disable,
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.is_enabled = clk_is_enabled_regmap,
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};
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EXPORT_SYMBOL_GPL(clk_branch_ops);
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static int clk_branch2_enable(struct clk_hw *hw)
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{
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return clk_branch_toggle(hw, true, clk_branch2_check_halt);
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}
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static void clk_branch2_disable(struct clk_hw *hw)
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{
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clk_branch_toggle(hw, false, clk_branch2_check_halt);
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}
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static int clk_branch2_mem_enable(struct clk_hw *hw)
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{
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struct clk_mem_branch *mem_br = to_clk_mem_branch(hw);
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struct clk_branch branch = mem_br->branch;
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u32 val;
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int ret;
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regmap_update_bits(branch.clkr.regmap, mem_br->mem_enable_reg,
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mem_br->mem_enable_ack_mask, mem_br->mem_enable_ack_mask);
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ret = regmap_read_poll_timeout(branch.clkr.regmap, mem_br->mem_ack_reg,
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val, val & mem_br->mem_enable_ack_mask, 0, 200);
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if (ret) {
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WARN(1, "%s mem enable failed\n", clk_hw_get_name(&branch.clkr.hw));
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return ret;
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}
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return clk_branch2_enable(hw);
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}
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static void clk_branch2_mem_disable(struct clk_hw *hw)
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{
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struct clk_mem_branch *mem_br = to_clk_mem_branch(hw);
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regmap_update_bits(mem_br->branch.clkr.regmap, mem_br->mem_enable_reg,
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mem_br->mem_enable_ack_mask, 0);
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return clk_branch2_disable(hw);
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}
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const struct clk_ops clk_branch2_mem_ops = {
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.enable = clk_branch2_mem_enable,
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.disable = clk_branch2_mem_disable,
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.is_enabled = clk_is_enabled_regmap,
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};
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EXPORT_SYMBOL_GPL(clk_branch2_mem_ops);
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const struct clk_ops clk_branch2_ops = {
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.enable = clk_branch2_enable,
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.disable = clk_branch2_disable,
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.is_enabled = clk_is_enabled_regmap,
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};
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EXPORT_SYMBOL_GPL(clk_branch2_ops);
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const struct clk_ops clk_branch2_aon_ops = {
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.enable = clk_branch2_enable,
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.is_enabled = clk_is_enabled_regmap,
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};
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EXPORT_SYMBOL_GPL(clk_branch2_aon_ops);
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const struct clk_ops clk_branch_simple_ops = {
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.enable = clk_enable_regmap,
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.disable = clk_disable_regmap,
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.is_enabled = clk_is_enabled_regmap,
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};
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EXPORT_SYMBOL_GPL(clk_branch_simple_ops);
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