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c1d676cec5
The current parent, plld_out0, does not exist. The proper name is
pll_d_out0. While at it, rename the plld_dsi clock to pll_d_dsi_out to
be more consistent with other clock names.
Fixes: b270491eb9 ("clk: tegra: Define PLLD_DSI and remove dsia(b)_mux")
Signed-off-by: Thierry Reding <treding@nvidia.com>
346 lines
8.4 KiB
C
346 lines
8.4 KiB
C
/*
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* This header provides constants for binding nvidia,tegra124-car or
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* nvidia,tegra132-car.
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*
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* The first 192 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
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* registers. These IDs often match those in the CAR's RST_DEVICES registers,
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* but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
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* this case, those clocks are assigned IDs above 185 in order to highlight
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* this issue. Implementations that interpret these clock IDs as bit values
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* within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
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* explicitly handle these special cases.
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*
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* The balance of the clocks controlled by the CAR are assigned IDs of 185 and
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* above.
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*/
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#ifndef _DT_BINDINGS_CLOCK_TEGRA124_CAR_COMMON_H
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#define _DT_BINDINGS_CLOCK_TEGRA124_CAR_COMMON_H
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/* 0 */
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/* 1 */
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/* 2 */
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#define TEGRA124_CLK_ISPB 3
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#define TEGRA124_CLK_RTC 4
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#define TEGRA124_CLK_TIMER 5
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#define TEGRA124_CLK_UARTA 6
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/* 7 (register bit affects uartb and vfir) */
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/* 8 */
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#define TEGRA124_CLK_SDMMC2 9
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/* 10 (register bit affects spdif_in and spdif_out) */
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#define TEGRA124_CLK_I2S1 11
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#define TEGRA124_CLK_I2C1 12
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/* 13 */
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#define TEGRA124_CLK_SDMMC1 14
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#define TEGRA124_CLK_SDMMC4 15
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/* 16 */
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#define TEGRA124_CLK_PWM 17
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#define TEGRA124_CLK_I2S2 18
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/* 20 (register bit affects vi and vi_sensor) */
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/* 21 */
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#define TEGRA124_CLK_USBD 22
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#define TEGRA124_CLK_ISP 23
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/* 26 */
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/* 25 */
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#define TEGRA124_CLK_DISP2 26
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#define TEGRA124_CLK_DISP1 27
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#define TEGRA124_CLK_HOST1X 28
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#define TEGRA124_CLK_VCP 29
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#define TEGRA124_CLK_I2S0 30
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/* 31 */
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#define TEGRA124_CLK_MC 32
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/* 33 */
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#define TEGRA124_CLK_APBDMA 34
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/* 35 */
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#define TEGRA124_CLK_KBC 36
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/* 37 */
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/* 38 */
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/* 39 (register bit affects fuse and fuse_burn) */
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#define TEGRA124_CLK_KFUSE 40
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#define TEGRA124_CLK_SBC1 41
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#define TEGRA124_CLK_NOR 42
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/* 43 */
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#define TEGRA124_CLK_SBC2 44
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/* 45 */
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#define TEGRA124_CLK_SBC3 46
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#define TEGRA124_CLK_I2C5 47
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#define TEGRA124_CLK_DSIA 48
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/* 49 */
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#define TEGRA124_CLK_MIPI 50
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#define TEGRA124_CLK_HDMI 51
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#define TEGRA124_CLK_CSI 52
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/* 53 */
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#define TEGRA124_CLK_I2C2 54
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#define TEGRA124_CLK_UARTC 55
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#define TEGRA124_CLK_MIPI_CAL 56
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#define TEGRA124_CLK_EMC 57
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#define TEGRA124_CLK_USB2 58
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#define TEGRA124_CLK_USB3 59
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/* 60 */
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#define TEGRA124_CLK_VDE 61
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#define TEGRA124_CLK_BSEA 62
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#define TEGRA124_CLK_BSEV 63
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/* 64 */
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#define TEGRA124_CLK_UARTD 65
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/* 66 */
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#define TEGRA124_CLK_I2C3 67
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#define TEGRA124_CLK_SBC4 68
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#define TEGRA124_CLK_SDMMC3 69
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#define TEGRA124_CLK_PCIE 70
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#define TEGRA124_CLK_OWR 71
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#define TEGRA124_CLK_AFI 72
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#define TEGRA124_CLK_CSITE 73
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/* 74 */
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/* 75 */
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#define TEGRA124_CLK_LA 76
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#define TEGRA124_CLK_TRACE 77
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#define TEGRA124_CLK_SOC_THERM 78
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#define TEGRA124_CLK_DTV 79
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/* 80 */
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#define TEGRA124_CLK_I2CSLOW 81
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#define TEGRA124_CLK_DSIB 82
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#define TEGRA124_CLK_TSEC 83
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/* 84 */
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/* 85 */
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/* 86 */
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/* 87 */
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/* 88 */
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#define TEGRA124_CLK_XUSB_HOST 89
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/* 90 */
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#define TEGRA124_CLK_MSENC 91
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#define TEGRA124_CLK_CSUS 92
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/* 93 */
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/* 94 */
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/* 95 (bit affects xusb_dev and xusb_dev_src) */
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/* 96 */
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/* 97 */
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/* 98 */
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#define TEGRA124_CLK_MSELECT 99
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#define TEGRA124_CLK_TSENSOR 100
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#define TEGRA124_CLK_I2S3 101
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#define TEGRA124_CLK_I2S4 102
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#define TEGRA124_CLK_I2C4 103
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#define TEGRA124_CLK_SBC5 104
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#define TEGRA124_CLK_SBC6 105
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#define TEGRA124_CLK_D_AUDIO 106
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#define TEGRA124_CLK_APBIF 107
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#define TEGRA124_CLK_DAM0 108
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#define TEGRA124_CLK_DAM1 109
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#define TEGRA124_CLK_DAM2 110
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#define TEGRA124_CLK_HDA2CODEC_2X 111
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/* 112 */
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#define TEGRA124_CLK_AUDIO0_2X 113
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#define TEGRA124_CLK_AUDIO1_2X 114
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#define TEGRA124_CLK_AUDIO2_2X 115
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#define TEGRA124_CLK_AUDIO3_2X 116
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#define TEGRA124_CLK_AUDIO4_2X 117
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#define TEGRA124_CLK_SPDIF_2X 118
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#define TEGRA124_CLK_ACTMON 119
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#define TEGRA124_CLK_EXTERN1 120
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#define TEGRA124_CLK_EXTERN2 121
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#define TEGRA124_CLK_EXTERN3 122
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#define TEGRA124_CLK_SATA_OOB 123
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#define TEGRA124_CLK_SATA 124
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#define TEGRA124_CLK_HDA 125
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/* 126 */
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#define TEGRA124_CLK_SE 127
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#define TEGRA124_CLK_HDA2HDMI 128
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#define TEGRA124_CLK_SATA_COLD 129
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/* 130 */
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/* 131 */
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/* 132 */
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/* 133 */
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/* 134 */
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/* 135 */
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/* 136 */
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/* 137 */
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/* 138 */
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/* 139 */
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/* 140 */
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/* 141 */
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/* 142 */
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/* 143 (bit affects xusb_falcon_src, xusb_fs_src, */
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/* xusb_host_src and xusb_ss_src) */
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#define TEGRA124_CLK_CILAB 144
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#define TEGRA124_CLK_CILCD 145
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#define TEGRA124_CLK_CILE 146
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#define TEGRA124_CLK_DSIALP 147
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#define TEGRA124_CLK_DSIBLP 148
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#define TEGRA124_CLK_ENTROPY 149
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#define TEGRA124_CLK_DDS 150
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/* 151 */
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#define TEGRA124_CLK_DP2 152
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#define TEGRA124_CLK_AMX 153
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#define TEGRA124_CLK_ADX 154
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/* 155 (bit affects dfll_ref and dfll_soc) */
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#define TEGRA124_CLK_XUSB_SS 156
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/* 157 */
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/* 158 */
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/* 159 */
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/* 160 */
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/* 161 */
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/* 162 */
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/* 163 */
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/* 164 */
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/* 165 */
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#define TEGRA124_CLK_I2C6 166
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/* 167 */
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/* 168 */
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/* 169 */
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/* 170 */
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#define TEGRA124_CLK_VIM2_CLK 171
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/* 172 */
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/* 173 */
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/* 174 */
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/* 175 */
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#define TEGRA124_CLK_HDMI_AUDIO 176
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#define TEGRA124_CLK_CLK72MHZ 177
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#define TEGRA124_CLK_VIC03 178
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/* 179 */
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#define TEGRA124_CLK_ADX1 180
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#define TEGRA124_CLK_DPAUX 181
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#define TEGRA124_CLK_SOR0 182
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/* 183 */
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#define TEGRA124_CLK_GPU 184
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#define TEGRA124_CLK_AMX1 185
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/* 186 */
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/* 187 */
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/* 188 */
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/* 189 */
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/* 190 */
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/* 191 */
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#define TEGRA124_CLK_UARTB 192
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#define TEGRA124_CLK_VFIR 193
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#define TEGRA124_CLK_SPDIF_IN 194
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#define TEGRA124_CLK_SPDIF_OUT 195
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#define TEGRA124_CLK_VI 196
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#define TEGRA124_CLK_VI_SENSOR 197
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#define TEGRA124_CLK_FUSE 198
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#define TEGRA124_CLK_FUSE_BURN 199
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#define TEGRA124_CLK_CLK_32K 200
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#define TEGRA124_CLK_CLK_M 201
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#define TEGRA124_CLK_CLK_M_DIV2 202
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#define TEGRA124_CLK_CLK_M_DIV4 203
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#define TEGRA124_CLK_PLL_REF 204
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#define TEGRA124_CLK_PLL_C 205
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#define TEGRA124_CLK_PLL_C_OUT1 206
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#define TEGRA124_CLK_PLL_C2 207
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#define TEGRA124_CLK_PLL_C3 208
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#define TEGRA124_CLK_PLL_M 209
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#define TEGRA124_CLK_PLL_M_OUT1 210
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#define TEGRA124_CLK_PLL_P 211
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#define TEGRA124_CLK_PLL_P_OUT1 212
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#define TEGRA124_CLK_PLL_P_OUT2 213
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#define TEGRA124_CLK_PLL_P_OUT3 214
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#define TEGRA124_CLK_PLL_P_OUT4 215
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#define TEGRA124_CLK_PLL_A 216
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#define TEGRA124_CLK_PLL_A_OUT0 217
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#define TEGRA124_CLK_PLL_D 218
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#define TEGRA124_CLK_PLL_D_OUT0 219
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#define TEGRA124_CLK_PLL_D2 220
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#define TEGRA124_CLK_PLL_D2_OUT0 221
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#define TEGRA124_CLK_PLL_U 222
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#define TEGRA124_CLK_PLL_U_480M 223
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#define TEGRA124_CLK_PLL_U_60M 224
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#define TEGRA124_CLK_PLL_U_48M 225
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#define TEGRA124_CLK_PLL_U_12M 226
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/* 227 */
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/* 228 */
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#define TEGRA124_CLK_PLL_RE_VCO 229
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#define TEGRA124_CLK_PLL_RE_OUT 230
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#define TEGRA124_CLK_PLL_E 231
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#define TEGRA124_CLK_SPDIF_IN_SYNC 232
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#define TEGRA124_CLK_I2S0_SYNC 233
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#define TEGRA124_CLK_I2S1_SYNC 234
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#define TEGRA124_CLK_I2S2_SYNC 235
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#define TEGRA124_CLK_I2S3_SYNC 236
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#define TEGRA124_CLK_I2S4_SYNC 237
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#define TEGRA124_CLK_VIMCLK_SYNC 238
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#define TEGRA124_CLK_AUDIO0 239
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#define TEGRA124_CLK_AUDIO1 240
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#define TEGRA124_CLK_AUDIO2 241
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#define TEGRA124_CLK_AUDIO3 242
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#define TEGRA124_CLK_AUDIO4 243
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#define TEGRA124_CLK_SPDIF 244
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#define TEGRA124_CLK_CLK_OUT_1 245
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#define TEGRA124_CLK_CLK_OUT_2 246
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#define TEGRA124_CLK_CLK_OUT_3 247
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#define TEGRA124_CLK_BLINK 248
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/* 249 */
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/* 250 */
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/* 251 */
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#define TEGRA124_CLK_XUSB_HOST_SRC 252
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#define TEGRA124_CLK_XUSB_FALCON_SRC 253
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#define TEGRA124_CLK_XUSB_FS_SRC 254
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#define TEGRA124_CLK_XUSB_SS_SRC 255
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#define TEGRA124_CLK_XUSB_DEV_SRC 256
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#define TEGRA124_CLK_XUSB_DEV 257
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#define TEGRA124_CLK_XUSB_HS_SRC 258
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#define TEGRA124_CLK_SCLK 259
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#define TEGRA124_CLK_HCLK 260
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#define TEGRA124_CLK_PCLK 261
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/* 262 */
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/* 263 */
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#define TEGRA124_CLK_DFLL_REF 264
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#define TEGRA124_CLK_DFLL_SOC 265
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#define TEGRA124_CLK_VI_SENSOR2 266
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#define TEGRA124_CLK_PLL_P_OUT5 267
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#define TEGRA124_CLK_CML0 268
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#define TEGRA124_CLK_CML1 269
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#define TEGRA124_CLK_PLL_C4 270
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#define TEGRA124_CLK_PLL_DP 271
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#define TEGRA124_CLK_PLL_E_MUX 272
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#define TEGRA124_CLK_PLL_D_DSI_OUT 273
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/* 274 */
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/* 275 */
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/* 276 */
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/* 277 */
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/* 278 */
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/* 279 */
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/* 280 */
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/* 281 */
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/* 282 */
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/* 283 */
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/* 284 */
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/* 285 */
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/* 286 */
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/* 287 */
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/* 288 */
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/* 289 */
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/* 290 */
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/* 291 */
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/* 292 */
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/* 293 */
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/* 294 */
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/* 295 */
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/* 296 */
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/* 297 */
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/* 298 */
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/* 299 */
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#define TEGRA124_CLK_AUDIO0_MUX 300
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#define TEGRA124_CLK_AUDIO1_MUX 301
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#define TEGRA124_CLK_AUDIO2_MUX 302
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#define TEGRA124_CLK_AUDIO3_MUX 303
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#define TEGRA124_CLK_AUDIO4_MUX 304
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#define TEGRA124_CLK_SPDIF_MUX 305
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#define TEGRA124_CLK_CLK_OUT_1_MUX 306
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#define TEGRA124_CLK_CLK_OUT_2_MUX 307
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#define TEGRA124_CLK_CLK_OUT_3_MUX 308
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/* 309 */
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/* 310 */
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#define TEGRA124_CLK_SOR0_LVDS 311
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#define TEGRA124_CLK_XUSB_SS_DIV2 312
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#define TEGRA124_CLK_PLL_M_UD 313
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#define TEGRA124_CLK_PLL_C_UD 314
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#endif /* _DT_BINDINGS_CLOCK_TEGRA124_CAR_COMMON_H */
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