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pinctrl subsystem needs gpio chip base to prepare set of gpio pin ranges, which a given pinctrl driver can handle. This is important to handle pinctrl gpio request calls in order to program a given pin properly for gpio operation. As gpio base is allocated dynamically during gpiochip registration, presently there exists no clean way to pass this information to the pinctrl subsystem. After few discussions from [1], it was concluded that may be gpio controller reporting the pin range it supports, is a better way than pinctrl subsystem directly registering it. [1] http://comments.gmane.org/gmane.linux.ports.arm.kernel/184816 Cc: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com> [Edited documentation a bit] Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
115 lines
3.6 KiB
Plaintext
115 lines
3.6 KiB
Plaintext
Specifying GPIO information for devices
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============================================
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1) gpios property
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-----------------
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Nodes that makes use of GPIOs should specify them using one or more
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properties, each containing a 'gpio-list':
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gpio-list ::= <single-gpio> [gpio-list]
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single-gpio ::= <gpio-phandle> <gpio-specifier>
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gpio-phandle : phandle to gpio controller node
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gpio-specifier : Array of #gpio-cells specifying specific gpio
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(controller specific)
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GPIO properties should be named "[<name>-]gpios". Exact
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meaning of each gpios property must be documented in the device tree
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binding for each device.
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For example, the following could be used to describe gpios pins to use
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as chip select lines; with chip selects 0, 1 and 3 populated, and chip
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select 2 left empty:
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gpio1: gpio1 {
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gpio-controller
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#gpio-cells = <2>;
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};
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gpio2: gpio2 {
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gpio-controller
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#gpio-cells = <1>;
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};
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[...]
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chipsel-gpios = <&gpio1 12 0>,
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<&gpio1 13 0>,
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<0>, /* holes are permitted, means no GPIO 2 */
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<&gpio2 2>;
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Note that gpio-specifier length is controller dependent. In the
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above example, &gpio1 uses 2 cells to specify a gpio, while &gpio2
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only uses one.
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gpio-specifier may encode: bank, pin position inside the bank,
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whether pin is open-drain and whether pin is logically inverted.
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Exact meaning of each specifier cell is controller specific, and must
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be documented in the device tree binding for the device.
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Example of the node using GPIOs:
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node {
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gpios = <&qe_pio_e 18 0>;
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};
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In this example gpio-specifier is "18 0" and encodes GPIO pin number,
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and empty GPIO flags as accepted by the "qe_pio_e" gpio-controller.
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2) gpio-controller nodes
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------------------------
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Every GPIO controller node must both an empty "gpio-controller"
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property, and have #gpio-cells contain the size of the gpio-specifier.
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Example of two SOC GPIO banks defined as gpio-controller nodes:
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qe_pio_a: gpio-controller@1400 {
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#gpio-cells = <2>;
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compatible = "fsl,qe-pario-bank-a", "fsl,qe-pario-bank";
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reg = <0x1400 0x18>;
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gpio-controller;
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};
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qe_pio_e: gpio-controller@1460 {
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#gpio-cells = <2>;
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compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank";
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reg = <0x1460 0x18>;
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gpio-controller;
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};
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2.1) gpio-controller and pinctrl subsystem
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------------------------------------------
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gpio-controller on a SOC might be tightly coupled with the pinctrl
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subsystem, in the sense that the pins can be used by other functions
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together with optional gpio feature.
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While the pin allocation is totally managed by the pin ctrl subsystem,
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gpio (under gpiolib) is still maintained by gpio drivers. It may happen
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that different pin ranges in a SoC is managed by different gpio drivers.
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This makes it logical to let gpio drivers announce their pin ranges to
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the pin ctrl subsystem and call 'pinctrl_request_gpio' in order to
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request the corresponding pin before any gpio usage.
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For this, the gpio controller can use a pinctrl phandle and pins to
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announce the pinrange to the pin ctrl subsystem. For example,
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qe_pio_e: gpio-controller@1460 {
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#gpio-cells = <2>;
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compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank";
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reg = <0x1460 0x18>;
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gpio-controller;
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gpio-ranges = <&pinctrl1 20 10>, <&pinctrl2 50 20>;
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}
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where,
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&pinctrl1 and &pinctrl2 is the phandle to the pinctrl DT node.
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Next values specify the base pin and number of pins for the range
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handled by 'qe_pio_e' gpio. In the given example from base pin 20 to
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pin 29 under pinctrl1 and pin 50 to pin 69 under pinctrl2 is handled
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by this gpio controller.
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The pinctrl node must have "#gpio-range-cells" property to show number of
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arguments to pass with phandle from gpio controllers node.
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