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109bd48ea2
The driver currently works based on platform data. Remove this
and add support for DT. A single master can have multiple ports
connected to more than one iommu.
master
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------------------------
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IOMMU0 IOMMU1
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ctx0 ctx1 ctx0 ctx1
This association of master and iommus/contexts were previously
represented by platform data parent/child device details. The client
drivers were responsible for programming all of the iommus/contexts
for the device. Now while adapting to generic DT bindings we maintain the
list of iommus, contexts that each master domain is connected to and
program all of them on attach/detach.
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
Tested-by: Archit Taneja <architt@codeaurora.org>
Tested-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Joerg Roedel <jroedel@suse.de>
100 lines
3.2 KiB
C
100 lines
3.2 KiB
C
/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
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* 02110-1301, USA.
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*/
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#ifndef MSM_IOMMU_H
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#define MSM_IOMMU_H
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#include <linux/interrupt.h>
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#include <linux/clk.h>
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/* Sharability attributes of MSM IOMMU mappings */
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#define MSM_IOMMU_ATTR_NON_SH 0x0
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#define MSM_IOMMU_ATTR_SH 0x4
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/* Cacheability attributes of MSM IOMMU mappings */
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#define MSM_IOMMU_ATTR_NONCACHED 0x0
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#define MSM_IOMMU_ATTR_CACHED_WB_WA 0x1
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#define MSM_IOMMU_ATTR_CACHED_WB_NWA 0x2
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#define MSM_IOMMU_ATTR_CACHED_WT 0x3
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/* Mask for the cache policy attribute */
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#define MSM_IOMMU_CP_MASK 0x03
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/* Maximum number of Machine IDs that we are allowing to be mapped to the same
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* context bank. The number of MIDs mapped to the same CB does not affect
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* performance, but there is a practical limit on how many distinct MIDs may
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* be present. These mappings are typically determined at design time and are
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* not expected to change at run time.
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*/
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#define MAX_NUM_MIDS 32
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/* Maximum number of context banks that can be present in IOMMU */
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#define IOMMU_MAX_CBS 128
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/**
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* struct msm_iommu_dev - a single IOMMU hardware instance
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* ncb Number of context banks present on this IOMMU HW instance
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* dev: IOMMU device
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* irq: Interrupt number
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* clk: The bus clock for this IOMMU hardware instance
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* pclk: The clock for the IOMMU bus interconnect
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* dev_node: list head in qcom_iommu_device_list
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* dom_node: list head for domain
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* ctx_list: list of 'struct msm_iommu_ctx_dev'
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* context_map: Bitmap to track allocated context banks
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*/
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struct msm_iommu_dev {
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void __iomem *base;
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int ncb;
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struct device *dev;
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int irq;
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struct clk *clk;
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struct clk *pclk;
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struct list_head dev_node;
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struct list_head dom_node;
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struct list_head ctx_list;
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DECLARE_BITMAP(context_map, IOMMU_MAX_CBS);
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};
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/**
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* struct msm_iommu_ctx_dev - an IOMMU context bank instance
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* of_node node ptr of client device
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* num Index of this context bank within the hardware
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* mids List of Machine IDs that are to be mapped into this context
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* bank, terminated by -1. The MID is a set of signals on the
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* AXI bus that identifies the function associated with a specific
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* memory request. (See ARM spec).
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* num_mids Total number of mids
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* node list head in ctx_list
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*/
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struct msm_iommu_ctx_dev {
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struct device_node *of_node;
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int num;
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int mids[MAX_NUM_MIDS];
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int num_mids;
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struct list_head list;
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};
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/*
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* Interrupt handler for the IOMMU context fault interrupt. Hooking the
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* interrupt is not supported in the API yet, but this will print an error
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* message and dump useful IOMMU registers.
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*/
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irqreturn_t msm_iommu_fault_handler(int irq, void *dev_id);
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#endif
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