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Based on the normalized pattern:
this software file (the file ) is distributed by marvell international
ltd under the terms of the gnu general public license version 2 june
1991 (the license ) you may use redistribute and/or modify this file
in accordance with the terms and conditions of the license a copy of
which is available by writing to the free software foundation inc 51
franklin street fifth floor boston ma 02110-1301 usa or on the
worldwide web at http://www gnu org/licenses/old-licenses/gpl-2 0 txt
the file is distributed as-is without warranty of any kind and the
implied warranties of merchantability or fitness for a particular
purpose are expressly disclaimed the license provides additional
details about this warranty disclaimer
extracted by the scancode license scanner the SPDX license identifier
GPL-2.0-only
has been chosen to replace the boilerplate/reference.
Reviewed-by: Allison Randal <allison@lohutok.net>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
115 lines
2.6 KiB
C
115 lines
2.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/**
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* Marvell BT-over-SDIO driver: SDIO interface related definitions
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*
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* Copyright (C) 2009, Marvell International Ltd.
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**/
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#define SDIO_HEADER_LEN 4
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/* SD block size can not bigger than 64 due to buf size limit in firmware */
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/* define SD block size for data Tx/Rx */
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#define SDIO_BLOCK_SIZE 64
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/* Number of blocks for firmware transfer */
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#define FIRMWARE_TRANSFER_NBLOCK 2
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/* This is for firmware specific length */
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#define FW_EXTRA_LEN 36
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#define MRVDRV_SIZE_OF_CMD_BUFFER (2 * 1024)
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#define MRVDRV_BT_RX_PACKET_BUFFER_SIZE \
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(HCI_MAX_FRAME_SIZE + FW_EXTRA_LEN)
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#define ALLOC_BUF_SIZE (((max_t (int, MRVDRV_BT_RX_PACKET_BUFFER_SIZE, \
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MRVDRV_SIZE_OF_CMD_BUFFER) + SDIO_HEADER_LEN \
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+ SDIO_BLOCK_SIZE - 1) / SDIO_BLOCK_SIZE) \
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* SDIO_BLOCK_SIZE)
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/* The number of times to try when polling for status */
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#define MAX_POLL_TRIES 100
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/* Max retry number of CMD53 write */
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#define MAX_WRITE_IOMEM_RETRY 2
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/* register bitmasks */
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#define HOST_POWER_UP BIT(1)
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#define HOST_CMD53_FIN BIT(2)
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#define HIM_DISABLE 0xff
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#define HIM_ENABLE (BIT(0) | BIT(1))
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#define UP_LD_HOST_INT_STATUS BIT(0)
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#define DN_LD_HOST_INT_STATUS BIT(1)
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#define DN_LD_CARD_RDY BIT(0)
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#define CARD_IO_READY BIT(3)
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#define FIRMWARE_READY 0xfedc
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struct btmrvl_plt_wake_cfg {
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int irq_bt;
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bool wake_by_bt;
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};
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struct btmrvl_sdio_card_reg {
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u8 cfg;
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u8 host_int_mask;
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u8 host_intstatus;
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u8 card_status;
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u8 sq_read_base_addr_a0;
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u8 sq_read_base_addr_a1;
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u8 card_revision;
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u8 card_fw_status0;
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u8 card_fw_status1;
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u8 card_rx_len;
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u8 card_rx_unit;
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u8 io_port_0;
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u8 io_port_1;
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u8 io_port_2;
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bool int_read_to_clear;
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u8 host_int_rsr;
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u8 card_misc_cfg;
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u8 fw_dump_ctrl;
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u8 fw_dump_start;
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u8 fw_dump_end;
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};
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struct btmrvl_sdio_card {
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struct sdio_func *func;
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u32 ioport;
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const char *helper;
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const char *firmware;
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const struct btmrvl_sdio_card_reg *reg;
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bool support_pscan_win_report;
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bool supports_fw_dump;
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u16 sd_blksz_fw_dl;
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u8 rx_unit;
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struct btmrvl_private *priv;
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struct device_node *plt_of_node;
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struct btmrvl_plt_wake_cfg *plt_wake_cfg;
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};
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struct btmrvl_sdio_device {
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const char *helper;
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const char *firmware;
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const struct btmrvl_sdio_card_reg *reg;
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const bool support_pscan_win_report;
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u16 sd_blksz_fw_dl;
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bool supports_fw_dump;
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};
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/* Platform specific DMA alignment */
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#define BTSDIO_DMA_ALIGN 8
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/* Macros for Data Alignment : size */
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#define ALIGN_SZ(p, a) \
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(((p) + ((a) - 1)) & ~((a) - 1))
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/* Macros for Data Alignment : address */
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#define ALIGN_ADDR(p, a) \
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((((unsigned long)(p)) + (((unsigned long)(a)) - 1)) & \
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~(((unsigned long)(a)) - 1))
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