Robin Murphy f6cabb721c arm64: dts: juno: Remove GICv2m dma-range ... [ Upstream commit 31eeb6b09f ] Although it is painstakingly honest to describe all 3 PCI windows in "dma-ranges", it misses the the subtle distinction that the window for the GICv2m range is normally programmed for Device memory attributes rather than Normal Cacheable like the DRAM windows. Since MMU-401 only offers stage 2 translation, this means that when the PCI SMMU is enabled, accesses through that IPA range unexpectedly lose coherency if mapped as cacheable at the SMMU, due to the attribute combining rules. Since an extra 256KB is neither here nor there when we still have 10GB worth of usable address space, rather than attempting to describe and cope with this detail let's just remove the offending range. If the SMMU is not used then it makes no difference anyway. Link: https://lore.kernel.org/r/856c3f7192c6c3ce545ba67462f2ce9c86ed6b0c.1643046936.git.robin.murphy@arm.com Fixes: 4ac4d146cb ("arm64: dts: juno: Describe PCI dma-ranges") Reported-by: Anders Roxell <anders.roxell@linaro.org> Acked-by: Liviu Dudau <liviu.dudau@arm.com> Signed-off-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com> Signed-off-by: Sasha Levin <sashal@kernel.org>		2022-03-08 19:12:49 +01:00
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dts	arm64: dts: juno: Remove GICv2m dma-range	2022-03-08 19:12:49 +01:00
.gitignore	.gitignore: add SPDX License Identifier	2020-03-25 11:50:48 +01:00
install.sh
Makefile	arm64: move the (z)install rules to arch/arm64/Makefile	2021-08-03 16:19:03 +01:00