mirror of
https://mirrors.bfsu.edu.cn/git/linux.git
synced 2024-11-20 18:54:09 +08:00
682c1e5221
Provide a default implementation of mips_cpc_default_phys_base() which simply returns 0, and adjust mips_cpc_phys_base() to allow for mips_cpc_default_phys_base() returning 0. This allows kernels which include CPC support to be built without platform code & simply ignore the CPC if it wasn't already enabled by the bootloader. This fixes link failures such as the following from generic defconfigs: arch/mips/built-in.o: In function `mips_cpc_phys_base': arch/mips/kernel/mips-cpc.c:47: undefined reference to `mips_cpc_default_phys_base' [ralf@linux-mips.org: changed prototype for coding style compliance.] Signed-off-by: Paul Burton <paul.burton@imgtec.com> Reported-by: kbuild test robot <fengguang.wu@intel.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14401/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
114 lines
2.7 KiB
C
114 lines
2.7 KiB
C
/*
|
|
* Copyright (C) 2013 Imagination Technologies
|
|
* Author: Paul Burton <paul.burton@imgtec.com>
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify it
|
|
* under the terms of the GNU General Public License as published by the
|
|
* Free Software Foundation; either version 2 of the License, or (at your
|
|
* option) any later version.
|
|
*/
|
|
|
|
#include <linux/errno.h>
|
|
#include <linux/percpu.h>
|
|
#include <linux/spinlock.h>
|
|
|
|
#include <asm/mips-cm.h>
|
|
#include <asm/mips-cpc.h>
|
|
|
|
void __iomem *mips_cpc_base;
|
|
|
|
static DEFINE_PER_CPU_ALIGNED(spinlock_t, cpc_core_lock);
|
|
|
|
static DEFINE_PER_CPU_ALIGNED(unsigned long, cpc_core_lock_flags);
|
|
|
|
phys_addr_t __weak mips_cpc_default_phys_base(void)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* mips_cpc_phys_base - retrieve the physical base address of the CPC
|
|
*
|
|
* This function returns the physical base address of the Cluster Power
|
|
* Controller memory mapped registers, or 0 if no Cluster Power Controller
|
|
* is present.
|
|
*/
|
|
static phys_addr_t mips_cpc_phys_base(void)
|
|
{
|
|
unsigned long cpc_base;
|
|
|
|
if (!mips_cm_present())
|
|
return 0;
|
|
|
|
if (!(read_gcr_cpc_status() & CM_GCR_CPC_STATUS_EX_MSK))
|
|
return 0;
|
|
|
|
/* If the CPC is already enabled, leave it so */
|
|
cpc_base = read_gcr_cpc_base();
|
|
if (cpc_base & CM_GCR_CPC_BASE_CPCEN_MSK)
|
|
return cpc_base & CM_GCR_CPC_BASE_CPCBASE_MSK;
|
|
|
|
/* Otherwise, use the default address */
|
|
cpc_base = mips_cpc_default_phys_base();
|
|
if (!cpc_base)
|
|
return cpc_base;
|
|
|
|
/* Enable the CPC, mapped at the default address */
|
|
write_gcr_cpc_base(cpc_base | CM_GCR_CPC_BASE_CPCEN_MSK);
|
|
return cpc_base;
|
|
}
|
|
|
|
int mips_cpc_probe(void)
|
|
{
|
|
phys_addr_t addr;
|
|
unsigned int cpu;
|
|
|
|
for_each_possible_cpu(cpu)
|
|
spin_lock_init(&per_cpu(cpc_core_lock, cpu));
|
|
|
|
addr = mips_cpc_phys_base();
|
|
if (!addr)
|
|
return -ENODEV;
|
|
|
|
mips_cpc_base = ioremap_nocache(addr, 0x8000);
|
|
if (!mips_cpc_base)
|
|
return -ENXIO;
|
|
|
|
return 0;
|
|
}
|
|
|
|
void mips_cpc_lock_other(unsigned int core)
|
|
{
|
|
unsigned int curr_core;
|
|
|
|
if (mips_cm_revision() >= CM_REV_CM3)
|
|
/* Systems with CM >= 3 lock the CPC via mips_cm_lock_other */
|
|
return;
|
|
|
|
preempt_disable();
|
|
curr_core = current_cpu_data.core;
|
|
spin_lock_irqsave(&per_cpu(cpc_core_lock, curr_core),
|
|
per_cpu(cpc_core_lock_flags, curr_core));
|
|
write_cpc_cl_other(core << CPC_Cx_OTHER_CORENUM_SHF);
|
|
|
|
/*
|
|
* Ensure the core-other region reflects the appropriate core &
|
|
* VP before any accesses to it occur.
|
|
*/
|
|
mb();
|
|
}
|
|
|
|
void mips_cpc_unlock_other(void)
|
|
{
|
|
unsigned int curr_core;
|
|
|
|
if (mips_cm_revision() >= CM_REV_CM3)
|
|
/* Systems with CM >= 3 lock the CPC via mips_cm_lock_other */
|
|
return;
|
|
|
|
curr_core = current_cpu_data.core;
|
|
spin_unlock_irqrestore(&per_cpu(cpc_core_lock, curr_core),
|
|
per_cpu(cpc_core_lock_flags, curr_core));
|
|
preempt_enable();
|
|
}
|