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be884c15de
W=1 builds now warn if module is built without a MODULE_DESCRIPTION(). Add descriptions to the Lynx, XPCS and LynxI PCS drivers. Signed-off-by: Breno Leitao <leitao@debian.org> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
308 lines
8.7 KiB
C
308 lines
8.7 KiB
C
// SPDX-License-Identifier: GPL-2.0
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// Copyright (c) 2018-2019 MediaTek Inc.
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/* A library for MediaTek SGMII circuit
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*
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* Author: Sean Wang <sean.wang@mediatek.com>
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* Author: Alexander Couzens <lynxis@fe80.eu>
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* Author: Daniel Golle <daniel@makrotopia.org>
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*
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*/
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#include <linux/mdio.h>
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#include <linux/of.h>
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#include <linux/pcs/pcs-mtk-lynxi.h>
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#include <linux/phylink.h>
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#include <linux/regmap.h>
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/* SGMII subsystem config registers */
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/* BMCR (low 16) BMSR (high 16) */
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#define SGMSYS_PCS_CONTROL_1 0x0
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#define SGMII_BMCR GENMASK(15, 0)
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#define SGMII_BMSR GENMASK(31, 16)
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#define SGMSYS_PCS_DEVICE_ID 0x4
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#define SGMII_LYNXI_DEV_ID 0x4d544950
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#define SGMSYS_PCS_ADVERTISE 0x8
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#define SGMII_ADVERTISE GENMASK(15, 0)
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#define SGMII_LPA GENMASK(31, 16)
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#define SGMSYS_PCS_SCRATCH 0x14
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#define SGMII_DEV_VERSION GENMASK(31, 16)
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/* Register to programmable link timer, the unit in 2 * 8ns */
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#define SGMSYS_PCS_LINK_TIMER 0x18
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#define SGMII_LINK_TIMER_MASK GENMASK(19, 0)
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#define SGMII_LINK_TIMER_VAL(ns) FIELD_PREP(SGMII_LINK_TIMER_MASK, \
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((ns) / 2 / 8))
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/* Register to control remote fault */
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#define SGMSYS_SGMII_MODE 0x20
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#define SGMII_IF_MODE_SGMII BIT(0)
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#define SGMII_SPEED_DUPLEX_AN BIT(1)
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#define SGMII_SPEED_MASK GENMASK(3, 2)
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#define SGMII_SPEED_10 FIELD_PREP(SGMII_SPEED_MASK, 0)
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#define SGMII_SPEED_100 FIELD_PREP(SGMII_SPEED_MASK, 1)
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#define SGMII_SPEED_1000 FIELD_PREP(SGMII_SPEED_MASK, 2)
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#define SGMII_DUPLEX_HALF BIT(4)
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#define SGMII_REMOTE_FAULT_DIS BIT(8)
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/* Register to reset SGMII design */
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#define SGMSYS_RESERVED_0 0x34
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#define SGMII_SW_RESET BIT(0)
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/* Register to set SGMII speed, ANA RG_ Control Signals III */
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#define SGMII_PHY_SPEED_MASK GENMASK(3, 2)
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#define SGMII_PHY_SPEED_1_25G FIELD_PREP(SGMII_PHY_SPEED_MASK, 0)
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#define SGMII_PHY_SPEED_3_125G FIELD_PREP(SGMII_PHY_SPEED_MASK, 1)
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/* Register to power up QPHY */
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#define SGMSYS_QPHY_PWR_STATE_CTRL 0xe8
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#define SGMII_PHYA_PWD BIT(4)
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/* Register to QPHY wrapper control */
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#define SGMSYS_QPHY_WRAP_CTRL 0xec
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#define SGMII_PN_SWAP_MASK GENMASK(1, 0)
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#define SGMII_PN_SWAP_TX_RX (BIT(0) | BIT(1))
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/* struct mtk_pcs_lynxi - This structure holds each sgmii regmap andassociated
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* data
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* @regmap: The register map pointing at the range used to setup
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* SGMII modes
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* @dev: Pointer to device owning the PCS
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* @ana_rgc3: The offset of register ANA_RGC3 relative to regmap
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* @interface: Currently configured interface mode
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* @pcs: Phylink PCS structure
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* @flags: Flags indicating hardware properties
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*/
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struct mtk_pcs_lynxi {
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struct regmap *regmap;
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u32 ana_rgc3;
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phy_interface_t interface;
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struct phylink_pcs pcs;
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u32 flags;
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};
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static struct mtk_pcs_lynxi *pcs_to_mtk_pcs_lynxi(struct phylink_pcs *pcs)
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{
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return container_of(pcs, struct mtk_pcs_lynxi, pcs);
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}
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static void mtk_pcs_lynxi_get_state(struct phylink_pcs *pcs,
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struct phylink_link_state *state)
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{
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struct mtk_pcs_lynxi *mpcs = pcs_to_mtk_pcs_lynxi(pcs);
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unsigned int bm, adv;
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/* Read the BMSR and LPA */
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regmap_read(mpcs->regmap, SGMSYS_PCS_CONTROL_1, &bm);
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regmap_read(mpcs->regmap, SGMSYS_PCS_ADVERTISE, &adv);
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phylink_mii_c22_pcs_decode_state(state, FIELD_GET(SGMII_BMSR, bm),
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FIELD_GET(SGMII_LPA, adv));
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}
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static int mtk_pcs_lynxi_config(struct phylink_pcs *pcs, unsigned int neg_mode,
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phy_interface_t interface,
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const unsigned long *advertising,
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bool permit_pause_to_mac)
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{
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struct mtk_pcs_lynxi *mpcs = pcs_to_mtk_pcs_lynxi(pcs);
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bool mode_changed = false, changed;
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unsigned int rgc3, sgm_mode, bmcr;
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int advertise, link_timer;
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advertise = phylink_mii_c22_pcs_encode_advertisement(interface,
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advertising);
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if (advertise < 0)
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return advertise;
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/* Clearing IF_MODE_BIT0 switches the PCS to BASE-X mode, and
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* we assume that fixes it's speed at bitrate = line rate (in
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* other words, 1000Mbps or 2500Mbps).
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*/
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if (interface == PHY_INTERFACE_MODE_SGMII)
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sgm_mode = SGMII_IF_MODE_SGMII;
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else
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sgm_mode = 0;
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if (neg_mode & PHYLINK_PCS_NEG_INBAND)
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sgm_mode |= SGMII_REMOTE_FAULT_DIS;
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if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) {
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if (interface == PHY_INTERFACE_MODE_SGMII)
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sgm_mode |= SGMII_SPEED_DUPLEX_AN;
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bmcr = BMCR_ANENABLE;
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} else {
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bmcr = 0;
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}
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if (mpcs->interface != interface) {
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link_timer = phylink_get_link_timer_ns(interface);
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if (link_timer < 0)
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return link_timer;
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/* PHYA power down */
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regmap_set_bits(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL,
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SGMII_PHYA_PWD);
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/* Reset SGMII PCS state */
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regmap_set_bits(mpcs->regmap, SGMSYS_RESERVED_0,
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SGMII_SW_RESET);
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if (mpcs->flags & MTK_SGMII_FLAG_PN_SWAP)
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regmap_update_bits(mpcs->regmap, SGMSYS_QPHY_WRAP_CTRL,
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SGMII_PN_SWAP_MASK,
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SGMII_PN_SWAP_TX_RX);
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if (interface == PHY_INTERFACE_MODE_2500BASEX)
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rgc3 = SGMII_PHY_SPEED_3_125G;
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else
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rgc3 = SGMII_PHY_SPEED_1_25G;
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/* Configure the underlying interface speed */
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regmap_update_bits(mpcs->regmap, mpcs->ana_rgc3,
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SGMII_PHY_SPEED_MASK, rgc3);
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/* Setup the link timer */
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regmap_write(mpcs->regmap, SGMSYS_PCS_LINK_TIMER,
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SGMII_LINK_TIMER_VAL(link_timer));
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mpcs->interface = interface;
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mode_changed = true;
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}
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/* Update the advertisement, noting whether it has changed */
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regmap_update_bits_check(mpcs->regmap, SGMSYS_PCS_ADVERTISE,
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SGMII_ADVERTISE, advertise, &changed);
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/* Update the sgmsys mode register */
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regmap_update_bits(mpcs->regmap, SGMSYS_SGMII_MODE,
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SGMII_REMOTE_FAULT_DIS | SGMII_SPEED_DUPLEX_AN |
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SGMII_IF_MODE_SGMII, sgm_mode);
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/* Update the BMCR */
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regmap_update_bits(mpcs->regmap, SGMSYS_PCS_CONTROL_1,
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BMCR_ANENABLE, bmcr);
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/* Release PHYA power down state
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* Only removing bit SGMII_PHYA_PWD isn't enough.
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* There are cases when the SGMII_PHYA_PWD register contains 0x9 which
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* prevents SGMII from working. The SGMII still shows link but no traffic
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* can flow. Writing 0x0 to the PHYA_PWD register fix the issue. 0x0 was
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* taken from a good working state of the SGMII interface.
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* Unknown how much the QPHY needs but it is racy without a sleep.
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* Tested on mt7622 & mt7986.
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*/
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usleep_range(50, 100);
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regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, 0);
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return changed || mode_changed;
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}
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static void mtk_pcs_lynxi_restart_an(struct phylink_pcs *pcs)
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{
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struct mtk_pcs_lynxi *mpcs = pcs_to_mtk_pcs_lynxi(pcs);
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regmap_set_bits(mpcs->regmap, SGMSYS_PCS_CONTROL_1, BMCR_ANRESTART);
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}
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static void mtk_pcs_lynxi_link_up(struct phylink_pcs *pcs,
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unsigned int neg_mode,
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phy_interface_t interface, int speed,
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int duplex)
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{
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struct mtk_pcs_lynxi *mpcs = pcs_to_mtk_pcs_lynxi(pcs);
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unsigned int sgm_mode;
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if (neg_mode != PHYLINK_PCS_NEG_INBAND_ENABLED) {
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/* Force the speed and duplex setting */
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if (speed == SPEED_10)
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sgm_mode = SGMII_SPEED_10;
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else if (speed == SPEED_100)
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sgm_mode = SGMII_SPEED_100;
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else
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sgm_mode = SGMII_SPEED_1000;
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if (duplex != DUPLEX_FULL)
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sgm_mode |= SGMII_DUPLEX_HALF;
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regmap_update_bits(mpcs->regmap, SGMSYS_SGMII_MODE,
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SGMII_DUPLEX_HALF | SGMII_SPEED_MASK,
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sgm_mode);
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}
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}
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static void mtk_pcs_lynxi_disable(struct phylink_pcs *pcs)
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{
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struct mtk_pcs_lynxi *mpcs = pcs_to_mtk_pcs_lynxi(pcs);
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mpcs->interface = PHY_INTERFACE_MODE_NA;
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}
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static const struct phylink_pcs_ops mtk_pcs_lynxi_ops = {
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.pcs_get_state = mtk_pcs_lynxi_get_state,
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.pcs_config = mtk_pcs_lynxi_config,
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.pcs_an_restart = mtk_pcs_lynxi_restart_an,
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.pcs_link_up = mtk_pcs_lynxi_link_up,
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.pcs_disable = mtk_pcs_lynxi_disable,
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};
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struct phylink_pcs *mtk_pcs_lynxi_create(struct device *dev,
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struct regmap *regmap, u32 ana_rgc3,
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u32 flags)
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{
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struct mtk_pcs_lynxi *mpcs;
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u32 id, ver;
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int ret;
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ret = regmap_read(regmap, SGMSYS_PCS_DEVICE_ID, &id);
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if (ret < 0)
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return NULL;
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if (id != SGMII_LYNXI_DEV_ID) {
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dev_err(dev, "unknown PCS device id %08x\n", id);
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return NULL;
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}
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ret = regmap_read(regmap, SGMSYS_PCS_SCRATCH, &ver);
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if (ret < 0)
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return NULL;
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ver = FIELD_GET(SGMII_DEV_VERSION, ver);
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if (ver != 0x1) {
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dev_err(dev, "unknown PCS device version %04x\n", ver);
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return NULL;
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}
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dev_dbg(dev, "MediaTek LynxI SGMII PCS (id 0x%08x, ver 0x%04x)\n", id,
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ver);
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mpcs = kzalloc(sizeof(*mpcs), GFP_KERNEL);
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if (!mpcs)
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return NULL;
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mpcs->ana_rgc3 = ana_rgc3;
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mpcs->regmap = regmap;
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mpcs->flags = flags;
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mpcs->pcs.ops = &mtk_pcs_lynxi_ops;
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mpcs->pcs.neg_mode = true;
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mpcs->pcs.poll = true;
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mpcs->interface = PHY_INTERFACE_MODE_NA;
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return &mpcs->pcs;
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}
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EXPORT_SYMBOL(mtk_pcs_lynxi_create);
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void mtk_pcs_lynxi_destroy(struct phylink_pcs *pcs)
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{
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if (!pcs)
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return;
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kfree(pcs_to_mtk_pcs_lynxi(pcs));
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}
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EXPORT_SYMBOL(mtk_pcs_lynxi_destroy);
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MODULE_DESCRIPTION("MediaTek SGMII library for LynxI");
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MODULE_LICENSE("GPL");
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