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a853450bf4
When calling crypto_finalize_request, BH should be disabled to avoid
triggering the following calltrace:
------------[ cut here ]------------
WARNING: CPU: 2 PID: 74 at crypto/crypto_engine.c:58 crypto_finalize_request+0xa0/0x118
Modules linked in: cryptodev(O)
CPU: 2 PID: 74 Comm: firmware:zynqmp Tainted: G O 6.8.0-rc1-yocto-standard #323
Hardware name: ZynqMP ZCU102 Rev1.0 (DT)
pstate: 40000005 (nZcv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--)
pc : crypto_finalize_request+0xa0/0x118
lr : crypto_finalize_request+0x104/0x118
sp : ffffffc085353ce0
x29: ffffffc085353ce0 x28: 0000000000000000 x27: ffffff8808ea8688
x26: ffffffc081715038 x25: 0000000000000000 x24: ffffff880100db00
x23: ffffff880100da80 x22: 0000000000000000 x21: 0000000000000000
x20: ffffff8805b14000 x19: ffffff880100da80 x18: 0000000000010450
x17: 0000000000000000 x16: 0000000000000000 x15: 0000000000000000
x14: 0000000000000003 x13: 0000000000000000 x12: ffffff880100dad0
x11: 0000000000000000 x10: ffffffc0832dcd08 x9 : ffffffc0812416d8
x8 : 00000000000001f4 x7 : ffffffc0830d2830 x6 : 0000000000000001
x5 : ffffffc082091000 x4 : ffffffc082091658 x3 : 0000000000000000
x2 : ffffffc7f9653000 x1 : 0000000000000000 x0 : ffffff8802d20000
Call trace:
crypto_finalize_request+0xa0/0x118
crypto_finalize_aead_request+0x18/0x30
zynqmp_handle_aes_req+0xcc/0x388
crypto_pump_work+0x168/0x2d8
kthread_worker_fn+0xfc/0x3a0
kthread+0x118/0x138
ret_from_fork+0x10/0x20
irq event stamp: 40
hardirqs last enabled at (39): [<ffffffc0812416f8>] _raw_spin_unlock_irqrestore+0x70/0xb0
hardirqs last disabled at (40): [<ffffffc08122d208>] el1_dbg+0x28/0x90
softirqs last enabled at (36): [<ffffffc080017dec>] kernel_neon_begin+0x8c/0xf0
softirqs last disabled at (34): [<ffffffc080017dc0>] kernel_neon_begin+0x60/0xf0
---[ end trace 0000000000000000 ]---
Fixes: 4d96f7d481
("crypto: xilinx - Add Xilinx AES driver")
Signed-off-by: Quanyang Wang <quanyang.wang@windriver.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
450 lines
12 KiB
C
450 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Xilinx ZynqMP AES Driver.
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* Copyright (c) 2020 Xilinx Inc.
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*/
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#include <crypto/aes.h>
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#include <crypto/engine.h>
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#include <crypto/gcm.h>
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#include <crypto/internal/aead.h>
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#include <crypto/scatterwalk.h>
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#include <linux/dma-mapping.h>
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#include <linux/err.h>
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#include <linux/firmware/xlnx-zynqmp.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/mod_devicetable.h>
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#include <linux/platform_device.h>
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#include <linux/string.h>
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#define ZYNQMP_DMA_BIT_MASK 32U
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#define ZYNQMP_AES_KEY_SIZE AES_KEYSIZE_256
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#define ZYNQMP_AES_AUTH_SIZE 16U
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#define ZYNQMP_KEY_SRC_SEL_KEY_LEN 1U
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#define ZYNQMP_AES_BLK_SIZE 1U
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#define ZYNQMP_AES_MIN_INPUT_BLK_SIZE 4U
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#define ZYNQMP_AES_WORD_LEN 4U
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#define ZYNQMP_AES_GCM_TAG_MISMATCH_ERR 0x01
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#define ZYNQMP_AES_WRONG_KEY_SRC_ERR 0x13
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#define ZYNQMP_AES_PUF_NOT_PROGRAMMED 0xE300
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enum zynqmp_aead_op {
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ZYNQMP_AES_DECRYPT = 0,
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ZYNQMP_AES_ENCRYPT
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};
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enum zynqmp_aead_keysrc {
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ZYNQMP_AES_KUP_KEY = 0,
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ZYNQMP_AES_DEV_KEY,
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ZYNQMP_AES_PUF_KEY
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};
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struct zynqmp_aead_drv_ctx {
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union {
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struct aead_engine_alg aead;
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} alg;
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struct device *dev;
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struct crypto_engine *engine;
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};
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struct zynqmp_aead_hw_req {
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u64 src;
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u64 iv;
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u64 key;
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u64 dst;
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u64 size;
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u64 op;
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u64 keysrc;
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};
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struct zynqmp_aead_tfm_ctx {
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struct device *dev;
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u8 key[ZYNQMP_AES_KEY_SIZE];
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u8 *iv;
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u32 keylen;
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u32 authsize;
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enum zynqmp_aead_keysrc keysrc;
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struct crypto_aead *fbk_cipher;
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};
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struct zynqmp_aead_req_ctx {
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enum zynqmp_aead_op op;
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};
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static int zynqmp_aes_aead_cipher(struct aead_request *req)
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{
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struct crypto_aead *aead = crypto_aead_reqtfm(req);
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struct zynqmp_aead_tfm_ctx *tfm_ctx = crypto_aead_ctx(aead);
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struct zynqmp_aead_req_ctx *rq_ctx = aead_request_ctx(req);
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struct device *dev = tfm_ctx->dev;
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struct zynqmp_aead_hw_req *hwreq;
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dma_addr_t dma_addr_data, dma_addr_hw_req;
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unsigned int data_size;
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unsigned int status;
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int ret;
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size_t dma_size;
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char *kbuf;
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int err;
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if (tfm_ctx->keysrc == ZYNQMP_AES_KUP_KEY)
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dma_size = req->cryptlen + ZYNQMP_AES_KEY_SIZE
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+ GCM_AES_IV_SIZE;
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else
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dma_size = req->cryptlen + GCM_AES_IV_SIZE;
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kbuf = dma_alloc_coherent(dev, dma_size, &dma_addr_data, GFP_KERNEL);
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if (!kbuf)
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return -ENOMEM;
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hwreq = dma_alloc_coherent(dev, sizeof(struct zynqmp_aead_hw_req),
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&dma_addr_hw_req, GFP_KERNEL);
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if (!hwreq) {
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dma_free_coherent(dev, dma_size, kbuf, dma_addr_data);
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return -ENOMEM;
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}
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data_size = req->cryptlen;
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scatterwalk_map_and_copy(kbuf, req->src, 0, req->cryptlen, 0);
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memcpy(kbuf + data_size, req->iv, GCM_AES_IV_SIZE);
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hwreq->src = dma_addr_data;
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hwreq->dst = dma_addr_data;
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hwreq->iv = hwreq->src + data_size;
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hwreq->keysrc = tfm_ctx->keysrc;
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hwreq->op = rq_ctx->op;
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if (hwreq->op == ZYNQMP_AES_ENCRYPT)
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hwreq->size = data_size;
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else
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hwreq->size = data_size - ZYNQMP_AES_AUTH_SIZE;
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if (hwreq->keysrc == ZYNQMP_AES_KUP_KEY) {
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memcpy(kbuf + data_size + GCM_AES_IV_SIZE,
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tfm_ctx->key, ZYNQMP_AES_KEY_SIZE);
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hwreq->key = hwreq->src + data_size + GCM_AES_IV_SIZE;
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} else {
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hwreq->key = 0;
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}
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ret = zynqmp_pm_aes_engine(dma_addr_hw_req, &status);
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if (ret) {
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dev_err(dev, "ERROR: AES PM API failed\n");
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err = ret;
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} else if (status) {
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switch (status) {
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case ZYNQMP_AES_GCM_TAG_MISMATCH_ERR:
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dev_err(dev, "ERROR: Gcm Tag mismatch\n");
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break;
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case ZYNQMP_AES_WRONG_KEY_SRC_ERR:
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dev_err(dev, "ERROR: Wrong KeySrc, enable secure mode\n");
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break;
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case ZYNQMP_AES_PUF_NOT_PROGRAMMED:
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dev_err(dev, "ERROR: PUF is not registered\n");
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break;
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default:
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dev_err(dev, "ERROR: Unknown error\n");
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break;
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}
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err = -status;
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} else {
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if (hwreq->op == ZYNQMP_AES_ENCRYPT)
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data_size = data_size + ZYNQMP_AES_AUTH_SIZE;
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else
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data_size = data_size - ZYNQMP_AES_AUTH_SIZE;
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sg_copy_from_buffer(req->dst, sg_nents(req->dst),
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kbuf, data_size);
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err = 0;
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}
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if (kbuf) {
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memzero_explicit(kbuf, dma_size);
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dma_free_coherent(dev, dma_size, kbuf, dma_addr_data);
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}
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if (hwreq) {
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memzero_explicit(hwreq, sizeof(struct zynqmp_aead_hw_req));
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dma_free_coherent(dev, sizeof(struct zynqmp_aead_hw_req),
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hwreq, dma_addr_hw_req);
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}
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return err;
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}
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static int zynqmp_fallback_check(struct zynqmp_aead_tfm_ctx *tfm_ctx,
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struct aead_request *req)
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{
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int need_fallback = 0;
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struct zynqmp_aead_req_ctx *rq_ctx = aead_request_ctx(req);
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if (tfm_ctx->authsize != ZYNQMP_AES_AUTH_SIZE)
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need_fallback = 1;
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if (tfm_ctx->keysrc == ZYNQMP_AES_KUP_KEY &&
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tfm_ctx->keylen != ZYNQMP_AES_KEY_SIZE) {
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need_fallback = 1;
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}
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if (req->assoclen != 0 ||
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req->cryptlen < ZYNQMP_AES_MIN_INPUT_BLK_SIZE) {
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need_fallback = 1;
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}
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if ((req->cryptlen % ZYNQMP_AES_WORD_LEN) != 0)
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need_fallback = 1;
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if (rq_ctx->op == ZYNQMP_AES_DECRYPT &&
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req->cryptlen <= ZYNQMP_AES_AUTH_SIZE) {
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need_fallback = 1;
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}
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return need_fallback;
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}
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static int zynqmp_handle_aes_req(struct crypto_engine *engine,
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void *req)
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{
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struct aead_request *areq =
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container_of(req, struct aead_request, base);
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struct crypto_aead *aead = crypto_aead_reqtfm(req);
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struct zynqmp_aead_tfm_ctx *tfm_ctx = crypto_aead_ctx(aead);
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struct zynqmp_aead_req_ctx *rq_ctx = aead_request_ctx(areq);
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struct aead_request *subreq = aead_request_ctx(req);
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int need_fallback;
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int err;
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need_fallback = zynqmp_fallback_check(tfm_ctx, areq);
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if (need_fallback) {
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aead_request_set_tfm(subreq, tfm_ctx->fbk_cipher);
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aead_request_set_callback(subreq, areq->base.flags,
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NULL, NULL);
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aead_request_set_crypt(subreq, areq->src, areq->dst,
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areq->cryptlen, areq->iv);
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aead_request_set_ad(subreq, areq->assoclen);
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if (rq_ctx->op == ZYNQMP_AES_ENCRYPT)
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err = crypto_aead_encrypt(subreq);
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else
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err = crypto_aead_decrypt(subreq);
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} else {
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err = zynqmp_aes_aead_cipher(areq);
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}
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local_bh_disable();
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crypto_finalize_aead_request(engine, areq, err);
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local_bh_enable();
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return 0;
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}
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static int zynqmp_aes_aead_setkey(struct crypto_aead *aead, const u8 *key,
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unsigned int keylen)
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{
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struct crypto_tfm *tfm = crypto_aead_tfm(aead);
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struct zynqmp_aead_tfm_ctx *tfm_ctx =
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(struct zynqmp_aead_tfm_ctx *)crypto_tfm_ctx(tfm);
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unsigned char keysrc;
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if (keylen == ZYNQMP_KEY_SRC_SEL_KEY_LEN) {
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keysrc = *key;
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if (keysrc == ZYNQMP_AES_KUP_KEY ||
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keysrc == ZYNQMP_AES_DEV_KEY ||
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keysrc == ZYNQMP_AES_PUF_KEY) {
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tfm_ctx->keysrc = (enum zynqmp_aead_keysrc)keysrc;
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} else {
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tfm_ctx->keylen = keylen;
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}
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} else {
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tfm_ctx->keylen = keylen;
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if (keylen == ZYNQMP_AES_KEY_SIZE) {
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tfm_ctx->keysrc = ZYNQMP_AES_KUP_KEY;
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memcpy(tfm_ctx->key, key, keylen);
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}
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}
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tfm_ctx->fbk_cipher->base.crt_flags &= ~CRYPTO_TFM_REQ_MASK;
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tfm_ctx->fbk_cipher->base.crt_flags |= (aead->base.crt_flags &
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CRYPTO_TFM_REQ_MASK);
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return crypto_aead_setkey(tfm_ctx->fbk_cipher, key, keylen);
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}
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static int zynqmp_aes_aead_setauthsize(struct crypto_aead *aead,
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unsigned int authsize)
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{
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struct crypto_tfm *tfm = crypto_aead_tfm(aead);
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struct zynqmp_aead_tfm_ctx *tfm_ctx =
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(struct zynqmp_aead_tfm_ctx *)crypto_tfm_ctx(tfm);
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tfm_ctx->authsize = authsize;
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return crypto_aead_setauthsize(tfm_ctx->fbk_cipher, authsize);
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}
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static int zynqmp_aes_aead_encrypt(struct aead_request *req)
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{
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struct zynqmp_aead_drv_ctx *drv_ctx;
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struct crypto_aead *aead = crypto_aead_reqtfm(req);
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struct aead_alg *alg = crypto_aead_alg(aead);
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struct zynqmp_aead_req_ctx *rq_ctx = aead_request_ctx(req);
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rq_ctx->op = ZYNQMP_AES_ENCRYPT;
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drv_ctx = container_of(alg, struct zynqmp_aead_drv_ctx, alg.aead.base);
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return crypto_transfer_aead_request_to_engine(drv_ctx->engine, req);
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}
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static int zynqmp_aes_aead_decrypt(struct aead_request *req)
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{
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struct zynqmp_aead_drv_ctx *drv_ctx;
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struct crypto_aead *aead = crypto_aead_reqtfm(req);
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struct aead_alg *alg = crypto_aead_alg(aead);
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struct zynqmp_aead_req_ctx *rq_ctx = aead_request_ctx(req);
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rq_ctx->op = ZYNQMP_AES_DECRYPT;
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drv_ctx = container_of(alg, struct zynqmp_aead_drv_ctx, alg.aead.base);
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return crypto_transfer_aead_request_to_engine(drv_ctx->engine, req);
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}
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static int zynqmp_aes_aead_init(struct crypto_aead *aead)
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{
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struct crypto_tfm *tfm = crypto_aead_tfm(aead);
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struct zynqmp_aead_tfm_ctx *tfm_ctx =
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(struct zynqmp_aead_tfm_ctx *)crypto_tfm_ctx(tfm);
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struct zynqmp_aead_drv_ctx *drv_ctx;
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struct aead_alg *alg = crypto_aead_alg(aead);
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drv_ctx = container_of(alg, struct zynqmp_aead_drv_ctx, alg.aead.base);
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tfm_ctx->dev = drv_ctx->dev;
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tfm_ctx->fbk_cipher = crypto_alloc_aead(drv_ctx->alg.aead.base.base.cra_name,
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0,
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CRYPTO_ALG_NEED_FALLBACK);
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if (IS_ERR(tfm_ctx->fbk_cipher)) {
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pr_err("%s() Error: failed to allocate fallback for %s\n",
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__func__, drv_ctx->alg.aead.base.base.cra_name);
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return PTR_ERR(tfm_ctx->fbk_cipher);
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}
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crypto_aead_set_reqsize(aead,
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max(sizeof(struct zynqmp_aead_req_ctx),
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sizeof(struct aead_request) +
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crypto_aead_reqsize(tfm_ctx->fbk_cipher)));
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return 0;
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}
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static void zynqmp_aes_aead_exit(struct crypto_aead *aead)
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{
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struct crypto_tfm *tfm = crypto_aead_tfm(aead);
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struct zynqmp_aead_tfm_ctx *tfm_ctx =
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(struct zynqmp_aead_tfm_ctx *)crypto_tfm_ctx(tfm);
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if (tfm_ctx->fbk_cipher) {
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crypto_free_aead(tfm_ctx->fbk_cipher);
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tfm_ctx->fbk_cipher = NULL;
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}
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memzero_explicit(tfm_ctx, sizeof(struct zynqmp_aead_tfm_ctx));
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}
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static struct zynqmp_aead_drv_ctx aes_drv_ctx = {
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.alg.aead.base = {
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.setkey = zynqmp_aes_aead_setkey,
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.setauthsize = zynqmp_aes_aead_setauthsize,
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.encrypt = zynqmp_aes_aead_encrypt,
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.decrypt = zynqmp_aes_aead_decrypt,
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.init = zynqmp_aes_aead_init,
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.exit = zynqmp_aes_aead_exit,
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.ivsize = GCM_AES_IV_SIZE,
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.maxauthsize = ZYNQMP_AES_AUTH_SIZE,
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.base = {
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.cra_name = "gcm(aes)",
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.cra_driver_name = "xilinx-zynqmp-aes-gcm",
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.cra_priority = 200,
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.cra_flags = CRYPTO_ALG_TYPE_AEAD |
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CRYPTO_ALG_ASYNC |
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CRYPTO_ALG_ALLOCATES_MEMORY |
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CRYPTO_ALG_KERN_DRIVER_ONLY |
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CRYPTO_ALG_NEED_FALLBACK,
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.cra_blocksize = ZYNQMP_AES_BLK_SIZE,
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.cra_ctxsize = sizeof(struct zynqmp_aead_tfm_ctx),
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.cra_module = THIS_MODULE,
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}
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},
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.alg.aead.op = {
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.do_one_request = zynqmp_handle_aes_req,
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},
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};
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static int zynqmp_aes_aead_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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int err;
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/* ZynqMP AES driver supports only one instance */
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if (!aes_drv_ctx.dev)
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aes_drv_ctx.dev = dev;
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else
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return -ENODEV;
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err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(ZYNQMP_DMA_BIT_MASK));
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if (err < 0) {
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dev_err(dev, "No usable DMA configuration\n");
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return err;
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}
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aes_drv_ctx.engine = crypto_engine_alloc_init(dev, 1);
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if (!aes_drv_ctx.engine) {
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dev_err(dev, "Cannot alloc AES engine\n");
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err = -ENOMEM;
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goto err_engine;
|
|
}
|
|
|
|
err = crypto_engine_start(aes_drv_ctx.engine);
|
|
if (err) {
|
|
dev_err(dev, "Cannot start AES engine\n");
|
|
goto err_engine;
|
|
}
|
|
|
|
err = crypto_engine_register_aead(&aes_drv_ctx.alg.aead);
|
|
if (err < 0) {
|
|
dev_err(dev, "Failed to register AEAD alg.\n");
|
|
goto err_aead;
|
|
}
|
|
return 0;
|
|
|
|
err_aead:
|
|
crypto_engine_unregister_aead(&aes_drv_ctx.alg.aead);
|
|
|
|
err_engine:
|
|
if (aes_drv_ctx.engine)
|
|
crypto_engine_exit(aes_drv_ctx.engine);
|
|
|
|
return err;
|
|
}
|
|
|
|
static void zynqmp_aes_aead_remove(struct platform_device *pdev)
|
|
{
|
|
crypto_engine_exit(aes_drv_ctx.engine);
|
|
crypto_engine_unregister_aead(&aes_drv_ctx.alg.aead);
|
|
}
|
|
|
|
static const struct of_device_id zynqmp_aes_dt_ids[] = {
|
|
{ .compatible = "xlnx,zynqmp-aes" },
|
|
{ /* sentinel */ }
|
|
};
|
|
MODULE_DEVICE_TABLE(of, zynqmp_aes_dt_ids);
|
|
|
|
static struct platform_driver zynqmp_aes_driver = {
|
|
.probe = zynqmp_aes_aead_probe,
|
|
.remove_new = zynqmp_aes_aead_remove,
|
|
.driver = {
|
|
.name = "zynqmp-aes",
|
|
.of_match_table = zynqmp_aes_dt_ids,
|
|
},
|
|
};
|
|
|
|
module_platform_driver(zynqmp_aes_driver);
|
|
MODULE_LICENSE("GPL");
|