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edfaf05c2f
All OMAP IP blocks expect LE data, but CPU may operate in BE mode. Need to use endian neutral functions to read/write h/w registers. I.e instead of __raw_read[lw] and __raw_write[lw] functions code need to use read[lw]_relaxed and write[lw]_relaxed functions. If the first simply reads/writes register, the second will byteswap it if host operates in BE mode. Changes are trivial sed like replacement of __raw_xxx functions with xxx_relaxed variant. Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org> Signed-off-by: Taras Kondratiuk <taras.kondratiuk@linaro.org> Signed-off-by: Tony Lindgren <tony@atomide.com>
121 lines
3.1 KiB
C
121 lines
3.1 KiB
C
/*
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* OMAP2/3 Clock Management (CM) register definitions
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*
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* Copyright (C) 2007-2009 Texas Instruments, Inc.
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* Copyright (C) 2007-2010 Nokia Corporation
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* Paul Walmsley
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* The CM hardware modules on the OMAP2/3 are quite similar to each
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* other. The CM modules/instances on OMAP4 are quite different, so
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* they are handled in a separate file.
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*/
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#ifndef __ARCH_ASM_MACH_OMAP2_CM2XXX_3XXX_H
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#define __ARCH_ASM_MACH_OMAP2_CM2XXX_3XXX_H
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#include "cm.h"
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/*
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* Module specific CM register offsets from CM_BASE + domain offset
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* Use cm_{read,write}_mod_reg() with these registers.
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* These register offsets generally appear in more than one PRCM submodule.
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*/
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/* Common between OMAP2 and OMAP3 */
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#define CM_FCLKEN 0x0000
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#define CM_FCLKEN1 CM_FCLKEN
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#define CM_CLKEN CM_FCLKEN
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#define CM_ICLKEN 0x0010
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#define CM_ICLKEN1 CM_ICLKEN
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#define CM_ICLKEN2 0x0014
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#define CM_ICLKEN3 0x0018
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#define CM_IDLEST 0x0020
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#define CM_IDLEST1 CM_IDLEST
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#define CM_IDLEST2 0x0024
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#define OMAP2430_CM_IDLEST3 0x0028
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#define CM_AUTOIDLE 0x0030
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#define CM_AUTOIDLE1 CM_AUTOIDLE
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#define CM_AUTOIDLE2 0x0034
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#define CM_AUTOIDLE3 0x0038
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#define CM_CLKSEL 0x0040
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#define CM_CLKSEL1 CM_CLKSEL
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#define CM_CLKSEL2 0x0044
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#define OMAP2_CM_CLKSTCTRL 0x0048
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#ifndef __ASSEMBLER__
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#include <linux/io.h>
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static inline u32 omap2_cm_read_mod_reg(s16 module, u16 idx)
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{
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return readl_relaxed(cm_base + module + idx);
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}
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static inline void omap2_cm_write_mod_reg(u32 val, s16 module, u16 idx)
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{
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writel_relaxed(val, cm_base + module + idx);
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}
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/* Read-modify-write a register in a CM module. Caller must lock */
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static inline u32 omap2_cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module,
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s16 idx)
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{
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u32 v;
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v = omap2_cm_read_mod_reg(module, idx);
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v &= ~mask;
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v |= bits;
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omap2_cm_write_mod_reg(v, module, idx);
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return v;
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}
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/* Read a CM register, AND it, and shift the result down to bit 0 */
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static inline u32 omap2_cm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask)
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{
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u32 v;
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v = omap2_cm_read_mod_reg(domain, idx);
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v &= mask;
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v >>= __ffs(mask);
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return v;
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}
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static inline u32 omap2_cm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
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{
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return omap2_cm_rmw_mod_reg_bits(bits, bits, module, idx);
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}
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static inline u32 omap2_cm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
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{
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return omap2_cm_rmw_mod_reg_bits(bits, 0x0, module, idx);
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}
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extern int omap2xxx_cm_apll54_enable(void);
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extern void omap2xxx_cm_apll54_disable(void);
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extern int omap2xxx_cm_apll96_enable(void);
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extern void omap2xxx_cm_apll96_disable(void);
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#endif
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/* CM register bits shared between 24XX and 3430 */
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/* CM_CLKSEL_GFX */
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#define OMAP_CLKSEL_GFX_SHIFT 0
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#define OMAP_CLKSEL_GFX_MASK (0x7 << 0)
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#define OMAP_CLKSEL_GFX_WIDTH 3
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/* CM_ICLKEN_GFX */
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#define OMAP_EN_GFX_SHIFT 0
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#define OMAP_EN_GFX_MASK (1 << 0)
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/* CM_IDLEST_GFX */
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#define OMAP_ST_GFX_MASK (1 << 0)
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#endif
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