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f5337346cd
Add missing L2 cache events: read/write accesses and misses, as well as the DTLB refills. Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> |
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.. | ||
boot | ||
configs | ||
crypto | ||
include | ||
kernel | ||
kvm | ||
lib | ||
mm | ||
net | ||
xen | ||
Kconfig | ||
Kconfig.debug | ||
Kconfig.platforms | ||
Makefile |