korg/linux
0
0
Fork 0
mirror of https://mirrors.bfsu.edu.cn/git/linux.git synced 2024-11-17 01:04:19 +08:00
Code Issues Packages Projects Releases Wiki Activity
f5079a9a2a
linux/arch/x86/events
History
Kan Liang 2dc0572f2c perf/x86/intel: Fix unchecked MSR access error caused by VLBR_EVENT 
On a Haswell machine, the perf_fuzzer managed to trigger this message:

[117248.075892] unchecked MSR access error: WRMSR to 0x3f1 (tried to
write 0x0400000000000000) at rIP: 0xffffffff8106e4f4
(native_write_msr+0x4/0x20)
[117248.089957] Call Trace:
[117248.092685]  intel_pmu_pebs_enable_all+0x31/0x40
[117248.097737]  intel_pmu_enable_all+0xa/0x10
[117248.102210]  __perf_event_task_sched_in+0x2df/0x2f0
[117248.107511]  finish_task_switch.isra.0+0x15f/0x280
[117248.112765]  schedule_tail+0xc/0x40
[117248.116562]  ret_from_fork+0x8/0x30

A fake event called VLBR_EVENT may use the bit 58 of the PEBS_ENABLE, if
the precise_ip is set. The bit 58 is reserved by the HW. Accessing the
bit causes the unchecked MSR access error.

The fake event doesn't support PEBS. The case should be rejected.

Fixes: 097e4311cd ("perf/x86: Add constraint to create guest LBR event without hw counter")
Reported-by: Vince Weaver <vincent.weaver@maine.edu>
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: stable@vger.kernel.org
Link: https://lkml.kernel.org/r/1615555298-140216-2-git-send-email-kan.liang@linux.intel.com
2021-03-16 21:44:39 +01:00
..
amd x86/CPU/AMD: Remove amd_get_nb_id() 2020-11-19 11:43:17 +01:00
intel perf/x86/intel: Fix unchecked MSR access error caused by VLBR_EVENT 2021-03-16 21:44:39 +01:00
zhaoxin x86/perf: Fix a typo 2020-07-22 10:22:08 +02:00
core.c x86/perf: Use RET0 as default for guest_get_msrs to handle "no PMU" case 2021-03-10 16:45:09 +01:00
Kconfig treewide: replace '---help---' in Kconfig files with 'help' 2020-06-14 01:57:21 +09:00
Makefile perf/x86/rapl: Fix RAPL config variable bug 2020-06-02 11:52:56 +02:00
msr.c perf/x86/msr: Add Rocket Lake CPU support 2020-10-29 11:00:40 +01:00
perf_event.h perf/x86/intel: Support CPUID 10.ECX to disable fixed counters 2021-02-01 15:31:37 +01:00
probe.c perf/x86/rapl: Add msr mask support 2021-02-10 14:44:54 +01:00
probe.h perf/x86/rapl: Add msr mask support 2021-02-10 14:44:54 +01:00
rapl.c perf/x86/rapl: Fix psys-energy event on Intel SPR platform 2021-02-10 14:44:55 +01:00