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196adf2f30
Since this macro is identical to pgprot_writecombine() and is only used in a single place, remove it completely to avoid confusion. On ARMv7+ processors, the coherent DMA mapping must be Normal NonCacheable (a.k.a. writecombine) to avoid mismatched hardware attribute aliases (with the kernel linear mapping as Normal Cacheable). Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
328 lines
9.3 KiB
C
328 lines
9.3 KiB
C
/*
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* SWIOTLB-based DMA API implementation
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*
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* Copyright (C) 2012 ARM Ltd.
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* Author: Catalin Marinas <catalin.marinas@arm.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/gfp.h>
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#include <linux/export.h>
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#include <linux/slab.h>
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#include <linux/dma-mapping.h>
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#include <linux/dma-contiguous.h>
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#include <linux/vmalloc.h>
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#include <linux/swiotlb.h>
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#include <asm/cacheflush.h>
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struct dma_map_ops *dma_ops;
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EXPORT_SYMBOL(dma_ops);
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static pgprot_t __get_dma_pgprot(struct dma_attrs *attrs, pgprot_t prot,
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bool coherent)
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{
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if (!coherent || dma_get_attr(DMA_ATTR_WRITE_COMBINE, attrs))
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return pgprot_writecombine(prot);
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return prot;
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}
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static void *__dma_alloc_coherent(struct device *dev, size_t size,
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dma_addr_t *dma_handle, gfp_t flags,
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struct dma_attrs *attrs)
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{
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if (dev == NULL) {
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WARN_ONCE(1, "Use an actual device structure for DMA allocation\n");
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return NULL;
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}
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if (IS_ENABLED(CONFIG_ZONE_DMA) &&
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dev->coherent_dma_mask <= DMA_BIT_MASK(32))
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flags |= GFP_DMA;
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if (IS_ENABLED(CONFIG_DMA_CMA)) {
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struct page *page;
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size = PAGE_ALIGN(size);
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page = dma_alloc_from_contiguous(dev, size >> PAGE_SHIFT,
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get_order(size));
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if (!page)
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return NULL;
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*dma_handle = phys_to_dma(dev, page_to_phys(page));
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return page_address(page);
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} else {
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return swiotlb_alloc_coherent(dev, size, dma_handle, flags);
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}
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}
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static void __dma_free_coherent(struct device *dev, size_t size,
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void *vaddr, dma_addr_t dma_handle,
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struct dma_attrs *attrs)
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{
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if (dev == NULL) {
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WARN_ONCE(1, "Use an actual device structure for DMA allocation\n");
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return;
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}
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if (IS_ENABLED(CONFIG_DMA_CMA)) {
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phys_addr_t paddr = dma_to_phys(dev, dma_handle);
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dma_release_from_contiguous(dev,
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phys_to_page(paddr),
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size >> PAGE_SHIFT);
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} else {
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swiotlb_free_coherent(dev, size, vaddr, dma_handle);
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}
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}
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static void *__dma_alloc_noncoherent(struct device *dev, size_t size,
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dma_addr_t *dma_handle, gfp_t flags,
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struct dma_attrs *attrs)
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{
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struct page *page, **map;
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void *ptr, *coherent_ptr;
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int order, i;
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size = PAGE_ALIGN(size);
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order = get_order(size);
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ptr = __dma_alloc_coherent(dev, size, dma_handle, flags, attrs);
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if (!ptr)
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goto no_mem;
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map = kmalloc(sizeof(struct page *) << order, flags & ~GFP_DMA);
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if (!map)
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goto no_map;
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/* remove any dirty cache lines on the kernel alias */
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__dma_flush_range(ptr, ptr + size);
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/* create a coherent mapping */
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page = virt_to_page(ptr);
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for (i = 0; i < (size >> PAGE_SHIFT); i++)
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map[i] = page + i;
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coherent_ptr = vmap(map, size >> PAGE_SHIFT, VM_MAP,
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__get_dma_pgprot(attrs, pgprot_default, false));
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kfree(map);
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if (!coherent_ptr)
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goto no_map;
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return coherent_ptr;
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no_map:
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__dma_free_coherent(dev, size, ptr, *dma_handle, attrs);
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no_mem:
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*dma_handle = ~0;
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return NULL;
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}
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static void __dma_free_noncoherent(struct device *dev, size_t size,
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void *vaddr, dma_addr_t dma_handle,
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struct dma_attrs *attrs)
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{
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void *swiotlb_addr = phys_to_virt(dma_to_phys(dev, dma_handle));
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vunmap(vaddr);
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__dma_free_coherent(dev, size, swiotlb_addr, dma_handle, attrs);
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}
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static dma_addr_t __swiotlb_map_page(struct device *dev, struct page *page,
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unsigned long offset, size_t size,
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enum dma_data_direction dir,
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struct dma_attrs *attrs)
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{
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dma_addr_t dev_addr;
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dev_addr = swiotlb_map_page(dev, page, offset, size, dir, attrs);
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__dma_map_area(phys_to_virt(dma_to_phys(dev, dev_addr)), size, dir);
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return dev_addr;
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}
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static void __swiotlb_unmap_page(struct device *dev, dma_addr_t dev_addr,
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size_t size, enum dma_data_direction dir,
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struct dma_attrs *attrs)
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{
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__dma_unmap_area(phys_to_virt(dma_to_phys(dev, dev_addr)), size, dir);
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swiotlb_unmap_page(dev, dev_addr, size, dir, attrs);
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}
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static int __swiotlb_map_sg_attrs(struct device *dev, struct scatterlist *sgl,
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int nelems, enum dma_data_direction dir,
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struct dma_attrs *attrs)
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{
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struct scatterlist *sg;
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int i, ret;
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ret = swiotlb_map_sg_attrs(dev, sgl, nelems, dir, attrs);
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for_each_sg(sgl, sg, ret, i)
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__dma_map_area(phys_to_virt(dma_to_phys(dev, sg->dma_address)),
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sg->length, dir);
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return ret;
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}
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static void __swiotlb_unmap_sg_attrs(struct device *dev,
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struct scatterlist *sgl, int nelems,
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enum dma_data_direction dir,
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struct dma_attrs *attrs)
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{
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struct scatterlist *sg;
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int i;
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for_each_sg(sgl, sg, nelems, i)
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__dma_unmap_area(phys_to_virt(dma_to_phys(dev, sg->dma_address)),
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sg->length, dir);
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swiotlb_unmap_sg_attrs(dev, sgl, nelems, dir, attrs);
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}
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static void __swiotlb_sync_single_for_cpu(struct device *dev,
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dma_addr_t dev_addr, size_t size,
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enum dma_data_direction dir)
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{
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__dma_unmap_area(phys_to_virt(dma_to_phys(dev, dev_addr)), size, dir);
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swiotlb_sync_single_for_cpu(dev, dev_addr, size, dir);
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}
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static void __swiotlb_sync_single_for_device(struct device *dev,
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dma_addr_t dev_addr, size_t size,
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enum dma_data_direction dir)
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{
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swiotlb_sync_single_for_device(dev, dev_addr, size, dir);
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__dma_map_area(phys_to_virt(dma_to_phys(dev, dev_addr)), size, dir);
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}
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static void __swiotlb_sync_sg_for_cpu(struct device *dev,
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struct scatterlist *sgl, int nelems,
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enum dma_data_direction dir)
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{
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struct scatterlist *sg;
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int i;
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for_each_sg(sgl, sg, nelems, i)
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__dma_unmap_area(phys_to_virt(dma_to_phys(dev, sg->dma_address)),
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sg->length, dir);
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swiotlb_sync_sg_for_cpu(dev, sgl, nelems, dir);
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}
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static void __swiotlb_sync_sg_for_device(struct device *dev,
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struct scatterlist *sgl, int nelems,
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enum dma_data_direction dir)
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{
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struct scatterlist *sg;
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int i;
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swiotlb_sync_sg_for_device(dev, sgl, nelems, dir);
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for_each_sg(sgl, sg, nelems, i)
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__dma_map_area(phys_to_virt(dma_to_phys(dev, sg->dma_address)),
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sg->length, dir);
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}
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/* vma->vm_page_prot must be set appropriately before calling this function */
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static int __dma_common_mmap(struct device *dev, struct vm_area_struct *vma,
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void *cpu_addr, dma_addr_t dma_addr, size_t size)
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{
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int ret = -ENXIO;
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unsigned long nr_vma_pages = (vma->vm_end - vma->vm_start) >>
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PAGE_SHIFT;
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unsigned long nr_pages = PAGE_ALIGN(size) >> PAGE_SHIFT;
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unsigned long pfn = dma_to_phys(dev, dma_addr) >> PAGE_SHIFT;
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unsigned long off = vma->vm_pgoff;
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if (dma_mmap_from_coherent(dev, vma, cpu_addr, size, &ret))
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return ret;
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if (off < nr_pages && nr_vma_pages <= (nr_pages - off)) {
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ret = remap_pfn_range(vma, vma->vm_start,
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pfn + off,
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vma->vm_end - vma->vm_start,
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vma->vm_page_prot);
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}
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return ret;
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}
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static int __swiotlb_mmap_noncoherent(struct device *dev,
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struct vm_area_struct *vma,
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void *cpu_addr, dma_addr_t dma_addr, size_t size,
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struct dma_attrs *attrs)
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{
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vma->vm_page_prot = __get_dma_pgprot(attrs, vma->vm_page_prot, false);
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return __dma_common_mmap(dev, vma, cpu_addr, dma_addr, size);
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}
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static int __swiotlb_mmap_coherent(struct device *dev,
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struct vm_area_struct *vma,
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void *cpu_addr, dma_addr_t dma_addr, size_t size,
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struct dma_attrs *attrs)
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{
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/* Just use whatever page_prot attributes were specified */
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return __dma_common_mmap(dev, vma, cpu_addr, dma_addr, size);
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}
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struct dma_map_ops noncoherent_swiotlb_dma_ops = {
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.alloc = __dma_alloc_noncoherent,
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.free = __dma_free_noncoherent,
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.mmap = __swiotlb_mmap_noncoherent,
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.map_page = __swiotlb_map_page,
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.unmap_page = __swiotlb_unmap_page,
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.map_sg = __swiotlb_map_sg_attrs,
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.unmap_sg = __swiotlb_unmap_sg_attrs,
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.sync_single_for_cpu = __swiotlb_sync_single_for_cpu,
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.sync_single_for_device = __swiotlb_sync_single_for_device,
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.sync_sg_for_cpu = __swiotlb_sync_sg_for_cpu,
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.sync_sg_for_device = __swiotlb_sync_sg_for_device,
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.dma_supported = swiotlb_dma_supported,
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.mapping_error = swiotlb_dma_mapping_error,
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};
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EXPORT_SYMBOL(noncoherent_swiotlb_dma_ops);
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struct dma_map_ops coherent_swiotlb_dma_ops = {
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.alloc = __dma_alloc_coherent,
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.free = __dma_free_coherent,
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.mmap = __swiotlb_mmap_coherent,
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.map_page = swiotlb_map_page,
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.unmap_page = swiotlb_unmap_page,
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.map_sg = swiotlb_map_sg_attrs,
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.unmap_sg = swiotlb_unmap_sg_attrs,
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.sync_single_for_cpu = swiotlb_sync_single_for_cpu,
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.sync_single_for_device = swiotlb_sync_single_for_device,
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.sync_sg_for_cpu = swiotlb_sync_sg_for_cpu,
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.sync_sg_for_device = swiotlb_sync_sg_for_device,
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.dma_supported = swiotlb_dma_supported,
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.mapping_error = swiotlb_dma_mapping_error,
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};
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EXPORT_SYMBOL(coherent_swiotlb_dma_ops);
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extern int swiotlb_late_init_with_default_size(size_t default_size);
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static int __init swiotlb_late_init(void)
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{
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size_t swiotlb_size = min(SZ_64M, MAX_ORDER_NR_PAGES << PAGE_SHIFT);
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dma_ops = &coherent_swiotlb_dma_ops;
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return swiotlb_late_init_with_default_size(swiotlb_size);
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}
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subsys_initcall(swiotlb_late_init);
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#define PREALLOC_DMA_DEBUG_ENTRIES 4096
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static int __init dma_debug_do_init(void)
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{
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dma_debug_init(PREALLOC_DMA_DEBUG_ENTRIES);
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return 0;
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}
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fs_initcall(dma_debug_do_init);
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