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f4a458fd83
Add SCFG MSI dts node and add msi-parent property to PCIe dts node that points to the corresponding MSI node. Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com> Tested-by: Alexander Stein <alexander.stein@systec-electronic.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
637 lines
18 KiB
Plaintext
637 lines
18 KiB
Plaintext
/*
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* Copyright 2013-2014 Freescale Semiconductor, Inc.
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This file is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public
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* License along with this file; if not, write to the Free
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* Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
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* MA 02110-1301 USA
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "skeleton64.dtsi"
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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compatible = "fsl,ls1021a";
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interrupt-parent = <&gic>;
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aliases {
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crypto = &crypto;
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ethernet0 = &enet0;
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ethernet1 = &enet1;
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ethernet2 = &enet2;
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serial0 = &lpuart0;
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serial1 = &lpuart1;
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serial2 = &lpuart2;
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serial3 = &lpuart3;
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serial4 = &lpuart4;
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serial5 = &lpuart5;
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sysclk = &sysclk;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@f00 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <0xf00>;
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clocks = <&cluster1_clk>;
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};
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cpu@f01 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <0xf01>;
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clocks = <&cluster1_clk>;
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};
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
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};
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pmu {
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compatible = "arm,cortex-a7-pmu";
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interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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device_type = "soc";
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interrupt-parent = <&gic>;
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ranges;
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gic: interrupt-controller@1400000 {
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compatible = "arm,cortex-a7-gic";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x0 0x1401000 0x0 0x1000>,
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<0x0 0x1402000 0x0 0x1000>,
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<0x0 0x1404000 0x0 0x2000>,
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<0x0 0x1406000 0x0 0x2000>;
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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msi1: msi-controller@1570e00 {
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compatible = "fsl,1s1021a-msi";
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reg = <0x0 0x1570e00 0x0 0x8>;
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msi-controller;
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interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
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};
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msi2: msi-controller@1570e08 {
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compatible = "fsl,1s1021a-msi";
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reg = <0x0 0x1570e08 0x0 0x8>;
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msi-controller;
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interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
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};
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ifc: ifc@1530000 {
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compatible = "fsl,ifc", "simple-bus";
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reg = <0x0 0x1530000 0x0 0x10000>;
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interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
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};
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dcfg: dcfg@1ee0000 {
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compatible = "fsl,ls1021a-dcfg", "syscon";
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reg = <0x0 0x1ee0000 0x0 0x10000>;
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big-endian;
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};
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esdhc: esdhc@1560000 {
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compatible = "fsl,esdhc";
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reg = <0x0 0x1560000 0x0 0x10000>;
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interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <0>;
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voltage-ranges = <1800 1800 3300 3300>;
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sdhci,auto-cmd12;
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big-endian;
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bus-width = <4>;
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status = "disabled";
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};
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sata: sata@3200000 {
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compatible = "fsl,ls1021a-ahci";
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reg = <0x0 0x3200000 0x0 0x10000>,
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<0x0 0x20220520 0x0 0x4>;
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reg-names = "ahci", "sata-ecc";
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interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&platform_clk 1>;
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dma-coherent;
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status = "disabled";
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};
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scfg: scfg@1570000 {
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compatible = "fsl,ls1021a-scfg", "syscon";
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reg = <0x0 0x1570000 0x0 0x10000>;
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big-endian;
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};
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crypto: crypto@1700000 {
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compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
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fsl,sec-era = <7>;
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x0 0x1700000 0x0 0x100000>;
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ranges = <0x0 0x0 0x1700000 0x100000>;
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interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
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sec_jr0: jr@10000 {
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compatible = "fsl,sec-v5.0-job-ring",
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"fsl,sec-v4.0-job-ring";
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reg = <0x10000 0x10000>;
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interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
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};
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sec_jr1: jr@20000 {
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compatible = "fsl,sec-v5.0-job-ring",
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"fsl,sec-v4.0-job-ring";
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reg = <0x20000 0x10000>;
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interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
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};
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sec_jr2: jr@30000 {
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compatible = "fsl,sec-v5.0-job-ring",
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"fsl,sec-v4.0-job-ring";
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reg = <0x30000 0x10000>;
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interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
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};
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sec_jr3: jr@40000 {
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compatible = "fsl,sec-v5.0-job-ring",
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"fsl,sec-v4.0-job-ring";
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reg = <0x40000 0x10000>;
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interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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clockgen: clocking@1ee1000 {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x0 0x1ee1000 0x10000>;
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sysclk: sysclk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-output-names = "sysclk";
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};
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cga_pll1: pll@800 {
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compatible = "fsl,qoriq-core-pll-2.0";
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#clock-cells = <1>;
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reg = <0x800 0x10>;
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clocks = <&sysclk>;
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clock-output-names = "cga-pll1", "cga-pll1-div2",
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"cga-pll1-div4";
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};
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platform_clk: pll@c00 {
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compatible = "fsl,qoriq-core-pll-2.0";
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#clock-cells = <1>;
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reg = <0xc00 0x10>;
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clocks = <&sysclk>;
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clock-output-names = "platform-clk", "platform-clk-div2";
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};
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cluster1_clk: clk0c0@0 {
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compatible = "fsl,qoriq-core-mux-2.0";
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#clock-cells = <0>;
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reg = <0x0 0x10>;
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clock-names = "pll1cga", "pll1cga-div2", "pll1cga-div4";
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clocks = <&cga_pll1 0>, <&cga_pll1 1>, <&cga_pll1 2>;
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clock-output-names = "cluster1-clk";
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};
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};
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dspi0: dspi@2100000 {
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compatible = "fsl,ls1021a-v1.0-dspi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x2100000 0x0 0x10000>;
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interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "dspi";
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clocks = <&platform_clk 1>;
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spi-num-chipselects = <5>;
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big-endian;
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status = "disabled";
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};
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dspi1: dspi@2110000 {
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compatible = "fsl,ls1021a-v1.0-dspi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x2110000 0x0 0x10000>;
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interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "dspi";
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clocks = <&platform_clk 1>;
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spi-num-chipselects = <5>;
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big-endian;
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status = "disabled";
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};
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i2c0: i2c@2180000 {
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compatible = "fsl,vf610-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x2180000 0x0 0x10000>;
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interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "i2c";
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clocks = <&platform_clk 1>;
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status = "disabled";
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};
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i2c1: i2c@2190000 {
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compatible = "fsl,vf610-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x2190000 0x0 0x10000>;
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interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "i2c";
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clocks = <&platform_clk 1>;
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status = "disabled";
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};
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i2c2: i2c@21a0000 {
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compatible = "fsl,vf610-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x21a0000 0x0 0x10000>;
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interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "i2c";
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clocks = <&platform_clk 1>;
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status = "disabled";
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};
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uart0: serial@21c0500 {
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compatible = "fsl,16550-FIFO64", "ns16550a";
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reg = <0x0 0x21c0500 0x0 0x100>;
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interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <0>;
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fifo-size = <15>;
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status = "disabled";
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};
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uart1: serial@21c0600 {
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compatible = "fsl,16550-FIFO64", "ns16550a";
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reg = <0x0 0x21c0600 0x0 0x100>;
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interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <0>;
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fifo-size = <15>;
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status = "disabled";
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};
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uart2: serial@21d0500 {
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compatible = "fsl,16550-FIFO64", "ns16550a";
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reg = <0x0 0x21d0500 0x0 0x100>;
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interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <0>;
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fifo-size = <15>;
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status = "disabled";
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};
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uart3: serial@21d0600 {
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compatible = "fsl,16550-FIFO64", "ns16550a";
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reg = <0x0 0x21d0600 0x0 0x100>;
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interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <0>;
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fifo-size = <15>;
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status = "disabled";
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};
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lpuart0: serial@2950000 {
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compatible = "fsl,ls1021a-lpuart";
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reg = <0x0 0x2950000 0x0 0x1000>;
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interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&sysclk>;
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clock-names = "ipg";
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status = "disabled";
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};
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lpuart1: serial@2960000 {
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compatible = "fsl,ls1021a-lpuart";
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reg = <0x0 0x2960000 0x0 0x1000>;
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interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&platform_clk 1>;
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clock-names = "ipg";
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status = "disabled";
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};
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lpuart2: serial@2970000 {
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compatible = "fsl,ls1021a-lpuart";
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reg = <0x0 0x2970000 0x0 0x1000>;
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interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&platform_clk 1>;
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clock-names = "ipg";
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status = "disabled";
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};
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lpuart3: serial@2980000 {
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compatible = "fsl,ls1021a-lpuart";
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reg = <0x0 0x2980000 0x0 0x1000>;
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interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&platform_clk 1>;
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clock-names = "ipg";
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status = "disabled";
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};
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lpuart4: serial@2990000 {
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compatible = "fsl,ls1021a-lpuart";
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reg = <0x0 0x2990000 0x0 0x1000>;
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interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&platform_clk 1>;
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clock-names = "ipg";
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status = "disabled";
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};
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lpuart5: serial@29a0000 {
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compatible = "fsl,ls1021a-lpuart";
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reg = <0x0 0x29a0000 0x0 0x1000>;
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interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&platform_clk 1>;
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clock-names = "ipg";
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status = "disabled";
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};
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wdog0: watchdog@2ad0000 {
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compatible = "fsl,imx21-wdt";
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reg = <0x0 0x2ad0000 0x0 0x10000>;
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interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&platform_clk 1>;
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clock-names = "wdog-en";
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big-endian;
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};
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sai1: sai@2b50000 {
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#sound-dai-cells = <0>;
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compatible = "fsl,vf610-sai";
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reg = <0x0 0x2b50000 0x0 0x10000>;
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interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&platform_clk 1>, <&platform_clk 1>,
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<&platform_clk 1>, <&platform_clk 1>;
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clock-names = "bus", "mclk1", "mclk2", "mclk3";
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dma-names = "tx", "rx";
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dmas = <&edma0 1 47>,
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<&edma0 1 46>;
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status = "disabled";
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};
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sai2: sai@2b60000 {
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#sound-dai-cells = <0>;
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compatible = "fsl,vf610-sai";
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reg = <0x0 0x2b60000 0x0 0x10000>;
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interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&platform_clk 1>, <&platform_clk 1>,
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<&platform_clk 1>, <&platform_clk 1>;
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clock-names = "bus", "mclk1", "mclk2", "mclk3";
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dma-names = "tx", "rx";
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dmas = <&edma0 1 45>,
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<&edma0 1 44>;
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status = "disabled";
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};
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edma0: edma@2c00000 {
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#dma-cells = <2>;
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compatible = "fsl,vf610-edma";
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reg = <0x0 0x2c00000 0x0 0x10000>,
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<0x0 0x2c10000 0x0 0x10000>,
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<0x0 0x2c20000 0x0 0x10000>;
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interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "edma-tx", "edma-err";
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dma-channels = <32>;
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big-endian;
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clock-names = "dmamux0", "dmamux1";
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clocks = <&platform_clk 1>,
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<&platform_clk 1>;
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};
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dcu: dcu@2ce0000 {
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compatible = "fsl,ls1021a-dcu";
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reg = <0x0 0x2ce0000 0x0 0x10000>;
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interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&platform_clk 0>;
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clock-names = "dcu";
|
|
big-endian;
|
|
status = "disabled";
|
|
};
|
|
|
|
mdio0: mdio@2d24000 {
|
|
compatible = "gianfar";
|
|
device_type = "mdio";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0x0 0x2d24000 0x0 0x4000>;
|
|
};
|
|
|
|
ptp_clock@2d10e00 {
|
|
compatible = "fsl,etsec-ptp";
|
|
reg = <0x0 0x2d10e00 0x0 0xb0>;
|
|
interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
|
|
fsl,tclk-period = <5>;
|
|
fsl,tmr-prsc = <2>;
|
|
fsl,tmr-add = <0xaaaaaaab>;
|
|
fsl,tmr-fiper1 = <999999990>;
|
|
fsl,tmr-fiper2 = <99990>;
|
|
fsl,max-adj = <499999999>;
|
|
};
|
|
|
|
enet0: ethernet@2d10000 {
|
|
compatible = "fsl,etsec2";
|
|
device_type = "network";
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
interrupt-parent = <&gic>;
|
|
model = "eTSEC";
|
|
fsl,magic-packet;
|
|
ranges;
|
|
dma-coherent;
|
|
|
|
queue-group@2d10000 {
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
reg = <0x0 0x2d10000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
queue-group@2d14000 {
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
reg = <0x0 0x2d14000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
};
|
|
|
|
enet1: ethernet@2d50000 {
|
|
compatible = "fsl,etsec2";
|
|
device_type = "network";
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
interrupt-parent = <&gic>;
|
|
model = "eTSEC";
|
|
ranges;
|
|
dma-coherent;
|
|
|
|
queue-group@2d50000 {
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
reg = <0x0 0x2d50000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
queue-group@2d54000 {
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
reg = <0x0 0x2d54000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
};
|
|
|
|
enet2: ethernet@2d90000 {
|
|
compatible = "fsl,etsec2";
|
|
device_type = "network";
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
interrupt-parent = <&gic>;
|
|
model = "eTSEC";
|
|
ranges;
|
|
dma-coherent;
|
|
|
|
queue-group@2d90000 {
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
reg = <0x0 0x2d90000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
queue-group@2d94000 {
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
reg = <0x0 0x2d94000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
};
|
|
|
|
usb@8600000 {
|
|
compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
|
|
reg = <0x0 0x8600000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
|
|
dr_mode = "host";
|
|
phy_type = "ulpi";
|
|
};
|
|
|
|
usb3@3100000 {
|
|
compatible = "snps,dwc3";
|
|
reg = <0x0 0x3100000 0x0 0x10000>;
|
|
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
|
|
dr_mode = "host";
|
|
snps,quirk-frame-length-adjustment = <0x20>;
|
|
};
|
|
|
|
pcie@3400000 {
|
|
compatible = "fsl,ls1021a-pcie", "snps,dw-pcie";
|
|
reg = <0x00 0x03400000 0x0 0x00010000 /* controller registers */
|
|
0x40 0x00000000 0x0 0x00002000>; /* configuration space */
|
|
reg-names = "regs", "config";
|
|
interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
|
|
fsl,pcie-scfg = <&scfg 0>;
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
device_type = "pci";
|
|
num-lanes = <4>;
|
|
bus-range = <0x0 0xff>;
|
|
ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
|
|
0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
|
msi-parent = <&msi1>;
|
|
#interrupt-cells = <1>;
|
|
interrupt-map-mask = <0 0 0 7>;
|
|
interrupt-map = <0000 0 0 1 &gic GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0000 0 0 2 &gic GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0000 0 0 3 &gic GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0000 0 0 4 &gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
pcie@3500000 {
|
|
compatible = "fsl,ls1021a-pcie", "snps,dw-pcie";
|
|
reg = <0x00 0x03500000 0x0 0x00010000 /* controller registers */
|
|
0x48 0x00000000 0x0 0x00002000>; /* configuration space */
|
|
reg-names = "regs", "config";
|
|
interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
|
|
fsl,pcie-scfg = <&scfg 1>;
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
device_type = "pci";
|
|
num-lanes = <4>;
|
|
bus-range = <0x0 0xff>;
|
|
ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
|
|
0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
|
msi-parent = <&msi2>;
|
|
#interrupt-cells = <1>;
|
|
interrupt-map-mask = <0 0 0 7>;
|
|
interrupt-map = <0000 0 0 1 &gic GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0000 0 0 2 &gic GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0000 0 0 3 &gic GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0000 0 0 4 &gic GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
};
|
|
};
|