Will Deacon f38d999c4d ARM: atomics: prefetch the destination word for write prior to strex ... The cost of changing a cacheline from shared to exclusive state can be significant, especially when this is triggered by an exclusive store, since it may result in having to retry the transaction. This patch prefixes our atomic access implementations with pldw instructions (on CPUs which support them) to try and grab the line in exclusive state from the start. Only the barrier-less functions are updated, since memory barriers can limit the usefulness of prefetching data. Acked-by: Nicolas Pitre <nico@linaro.org> Signed-off-by: Will Deacon <will.deacon@arm.com>		2013-09-30 16:42:56 +01:00
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asm	ARM: atomics: prefetch the destination word for write prior to strex	2013-09-30 16:42:56 +01:00
debug	ARM: SoC cleanups for 3.12	2013-09-06 13:21:16 -07:00
uapi/asm	ARM: 7791/1: a.out: remove partial a.out support	2013-07-26 12:02:10 +01:00