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https://mirrors.bfsu.edu.cn/git/linux.git
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f3867f439f
Rename to match the Linux subsystem responsible for the same kind of things. Will be investigating how feasible it will be to expose the GPU clock trees with it at some point. The namespace of NVKM is being changed to nvkm_ instead of nouveau_, which will be used for the DRM part of the driver. This is being done in order to make it very clear as to what part of the driver a given symbol belongs to, and as a minor step towards splitting the DRM driver out to be able to stand on its own (for virt). Because there's already a large amount of churn here anyway, this is as good a time as any to also switch to NVIDIA's device and chipset naming to ease collaboration with them. A comparison of objdump disassemblies proves no code changes. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
501 lines
12 KiB
C
501 lines
12 KiB
C
/*
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* Copyright 2013 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#include <subdev/clk.h>
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#include <subdev/timer.h>
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#include <subdev/bios.h>
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#include <subdev/bios/pll.h>
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#include "pll.h"
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struct nve0_clk_info {
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u32 freq;
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u32 ssel;
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u32 mdiv;
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u32 dsrc;
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u32 ddiv;
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u32 coef;
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};
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struct nve0_clk_priv {
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struct nouveau_clk base;
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struct nve0_clk_info eng[16];
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};
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static u32 read_div(struct nve0_clk_priv *, int, u32, u32);
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static u32 read_pll(struct nve0_clk_priv *, u32);
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static u32
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read_vco(struct nve0_clk_priv *priv, u32 dsrc)
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{
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u32 ssrc = nv_rd32(priv, dsrc);
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if (!(ssrc & 0x00000100))
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return read_pll(priv, 0x00e800);
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return read_pll(priv, 0x00e820);
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}
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static u32
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read_pll(struct nve0_clk_priv *priv, u32 pll)
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{
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u32 ctrl = nv_rd32(priv, pll + 0x00);
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u32 coef = nv_rd32(priv, pll + 0x04);
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u32 P = (coef & 0x003f0000) >> 16;
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u32 N = (coef & 0x0000ff00) >> 8;
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u32 M = (coef & 0x000000ff) >> 0;
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u32 sclk;
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u16 fN = 0xf000;
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if (!(ctrl & 0x00000001))
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return 0;
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switch (pll) {
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case 0x00e800:
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case 0x00e820:
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sclk = nv_device(priv)->crystal;
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P = 1;
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break;
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case 0x132000:
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sclk = read_pll(priv, 0x132020);
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P = (coef & 0x10000000) ? 2 : 1;
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break;
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case 0x132020:
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sclk = read_div(priv, 0, 0x137320, 0x137330);
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fN = nv_rd32(priv, pll + 0x10) >> 16;
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break;
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case 0x137000:
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case 0x137020:
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case 0x137040:
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case 0x1370e0:
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sclk = read_div(priv, (pll & 0xff) / 0x20, 0x137120, 0x137140);
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break;
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default:
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return 0;
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}
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if (P == 0)
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P = 1;
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sclk = (sclk * N) + (((u16)(fN + 4096) * sclk) >> 13);
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return sclk / (M * P);
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}
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static u32
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read_div(struct nve0_clk_priv *priv, int doff, u32 dsrc, u32 dctl)
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{
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u32 ssrc = nv_rd32(priv, dsrc + (doff * 4));
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u32 sctl = nv_rd32(priv, dctl + (doff * 4));
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switch (ssrc & 0x00000003) {
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case 0:
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if ((ssrc & 0x00030000) != 0x00030000)
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return nv_device(priv)->crystal;
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return 108000;
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case 2:
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return 100000;
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case 3:
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if (sctl & 0x80000000) {
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u32 sclk = read_vco(priv, dsrc + (doff * 4));
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u32 sdiv = (sctl & 0x0000003f) + 2;
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return (sclk * 2) / sdiv;
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}
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return read_vco(priv, dsrc + (doff * 4));
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default:
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return 0;
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}
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}
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static u32
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read_mem(struct nve0_clk_priv *priv)
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{
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switch (nv_rd32(priv, 0x1373f4) & 0x0000000f) {
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case 1: return read_pll(priv, 0x132020);
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case 2: return read_pll(priv, 0x132000);
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default:
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return 0;
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}
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}
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static u32
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read_clk(struct nve0_clk_priv *priv, int clk)
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{
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u32 sctl = nv_rd32(priv, 0x137250 + (clk * 4));
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u32 sclk, sdiv;
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if (clk < 7) {
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u32 ssel = nv_rd32(priv, 0x137100);
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if (ssel & (1 << clk)) {
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sclk = read_pll(priv, 0x137000 + (clk * 0x20));
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sdiv = 1;
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} else {
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sclk = read_div(priv, clk, 0x137160, 0x1371d0);
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sdiv = 0;
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}
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} else {
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u32 ssrc = nv_rd32(priv, 0x137160 + (clk * 0x04));
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if ((ssrc & 0x00000003) == 0x00000003) {
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sclk = read_div(priv, clk, 0x137160, 0x1371d0);
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if (ssrc & 0x00000100) {
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if (ssrc & 0x40000000)
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sclk = read_pll(priv, 0x1370e0);
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sdiv = 1;
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} else {
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sdiv = 0;
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}
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} else {
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sclk = read_div(priv, clk, 0x137160, 0x1371d0);
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sdiv = 0;
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}
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}
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if (sctl & 0x80000000) {
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if (sdiv)
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sdiv = ((sctl & 0x00003f00) >> 8) + 2;
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else
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sdiv = ((sctl & 0x0000003f) >> 0) + 2;
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return (sclk * 2) / sdiv;
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}
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return sclk;
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}
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static int
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nve0_clk_read(struct nouveau_clk *clk, enum nv_clk_src src)
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{
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struct nouveau_device *device = nv_device(clk);
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struct nve0_clk_priv *priv = (void *)clk;
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switch (src) {
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case nv_clk_src_crystal:
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return device->crystal;
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case nv_clk_src_href:
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return 100000;
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case nv_clk_src_mem:
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return read_mem(priv);
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case nv_clk_src_gpc:
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return read_clk(priv, 0x00);
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case nv_clk_src_rop:
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return read_clk(priv, 0x01);
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case nv_clk_src_hubk07:
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return read_clk(priv, 0x02);
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case nv_clk_src_hubk06:
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return read_clk(priv, 0x07);
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case nv_clk_src_hubk01:
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return read_clk(priv, 0x08);
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case nv_clk_src_daemon:
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return read_clk(priv, 0x0c);
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case nv_clk_src_vdec:
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return read_clk(priv, 0x0e);
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default:
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nv_error(clk, "invalid clock source %d\n", src);
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return -EINVAL;
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}
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}
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static u32
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calc_div(struct nve0_clk_priv *priv, int clk, u32 ref, u32 freq, u32 *ddiv)
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{
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u32 div = min((ref * 2) / freq, (u32)65);
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if (div < 2)
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div = 2;
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*ddiv = div - 2;
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return (ref * 2) / div;
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}
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static u32
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calc_src(struct nve0_clk_priv *priv, int clk, u32 freq, u32 *dsrc, u32 *ddiv)
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{
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u32 sclk;
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/* use one of the fixed frequencies if possible */
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*ddiv = 0x00000000;
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switch (freq) {
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case 27000:
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case 108000:
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*dsrc = 0x00000000;
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if (freq == 108000)
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*dsrc |= 0x00030000;
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return freq;
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case 100000:
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*dsrc = 0x00000002;
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return freq;
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default:
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*dsrc = 0x00000003;
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break;
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}
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/* otherwise, calculate the closest divider */
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sclk = read_vco(priv, 0x137160 + (clk * 4));
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if (clk < 7)
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sclk = calc_div(priv, clk, sclk, freq, ddiv);
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return sclk;
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}
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static u32
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calc_pll(struct nve0_clk_priv *priv, int clk, u32 freq, u32 *coef)
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{
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struct nouveau_bios *bios = nouveau_bios(priv);
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struct nvbios_pll limits;
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int N, M, P, ret;
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ret = nvbios_pll_parse(bios, 0x137000 + (clk * 0x20), &limits);
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if (ret)
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return 0;
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limits.refclk = read_div(priv, clk, 0x137120, 0x137140);
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if (!limits.refclk)
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return 0;
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ret = nva3_pll_calc(nv_subdev(priv), &limits, freq, &N, NULL, &M, &P);
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if (ret <= 0)
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return 0;
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*coef = (P << 16) | (N << 8) | M;
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return ret;
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}
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static int
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calc_clk(struct nve0_clk_priv *priv,
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struct nouveau_cstate *cstate, int clk, int dom)
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{
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struct nve0_clk_info *info = &priv->eng[clk];
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u32 freq = cstate->domain[dom];
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u32 src0, div0, div1D, div1P = 0;
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u32 clk0, clk1 = 0;
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/* invalid clock domain */
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if (!freq)
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return 0;
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/* first possible path, using only dividers */
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clk0 = calc_src(priv, clk, freq, &src0, &div0);
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clk0 = calc_div(priv, clk, clk0, freq, &div1D);
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/* see if we can get any closer using PLLs */
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if (clk0 != freq && (0x0000ff87 & (1 << clk))) {
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if (clk <= 7)
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clk1 = calc_pll(priv, clk, freq, &info->coef);
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else
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clk1 = cstate->domain[nv_clk_src_hubk06];
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clk1 = calc_div(priv, clk, clk1, freq, &div1P);
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}
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/* select the method which gets closest to target freq */
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if (abs((int)freq - clk0) <= abs((int)freq - clk1)) {
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info->dsrc = src0;
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if (div0) {
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info->ddiv |= 0x80000000;
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info->ddiv |= div0;
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}
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if (div1D) {
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info->mdiv |= 0x80000000;
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info->mdiv |= div1D;
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}
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info->ssel = 0;
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info->freq = clk0;
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} else {
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if (div1P) {
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info->mdiv |= 0x80000000;
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info->mdiv |= div1P << 8;
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}
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info->ssel = (1 << clk);
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info->dsrc = 0x40000100;
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info->freq = clk1;
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}
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return 0;
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}
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static int
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nve0_clk_calc(struct nouveau_clk *clk, struct nouveau_cstate *cstate)
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{
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struct nve0_clk_priv *priv = (void *)clk;
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int ret;
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if ((ret = calc_clk(priv, cstate, 0x00, nv_clk_src_gpc)) ||
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(ret = calc_clk(priv, cstate, 0x01, nv_clk_src_rop)) ||
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(ret = calc_clk(priv, cstate, 0x02, nv_clk_src_hubk07)) ||
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(ret = calc_clk(priv, cstate, 0x07, nv_clk_src_hubk06)) ||
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(ret = calc_clk(priv, cstate, 0x08, nv_clk_src_hubk01)) ||
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(ret = calc_clk(priv, cstate, 0x0c, nv_clk_src_daemon)) ||
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(ret = calc_clk(priv, cstate, 0x0e, nv_clk_src_vdec)))
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return ret;
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return 0;
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}
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static void
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nve0_clk_prog_0(struct nve0_clk_priv *priv, int clk)
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{
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struct nve0_clk_info *info = &priv->eng[clk];
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if (!info->ssel) {
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nv_mask(priv, 0x1371d0 + (clk * 0x04), 0x8000003f, info->ddiv);
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nv_wr32(priv, 0x137160 + (clk * 0x04), info->dsrc);
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}
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}
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static void
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nve0_clk_prog_1_0(struct nve0_clk_priv *priv, int clk)
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{
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nv_mask(priv, 0x137100, (1 << clk), 0x00000000);
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nv_wait(priv, 0x137100, (1 << clk), 0x00000000);
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}
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static void
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nve0_clk_prog_1_1(struct nve0_clk_priv *priv, int clk)
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{
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nv_mask(priv, 0x137160 + (clk * 0x04), 0x00000100, 0x00000000);
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}
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static void
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nve0_clk_prog_2(struct nve0_clk_priv *priv, int clk)
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{
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struct nve0_clk_info *info = &priv->eng[clk];
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const u32 addr = 0x137000 + (clk * 0x20);
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nv_mask(priv, addr + 0x00, 0x00000004, 0x00000000);
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nv_mask(priv, addr + 0x00, 0x00000001, 0x00000000);
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if (info->coef) {
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nv_wr32(priv, addr + 0x04, info->coef);
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nv_mask(priv, addr + 0x00, 0x00000001, 0x00000001);
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nv_wait(priv, addr + 0x00, 0x00020000, 0x00020000);
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nv_mask(priv, addr + 0x00, 0x00020004, 0x00000004);
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}
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}
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static void
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nve0_clk_prog_3(struct nve0_clk_priv *priv, int clk)
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{
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struct nve0_clk_info *info = &priv->eng[clk];
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if (info->ssel)
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nv_mask(priv, 0x137250 + (clk * 0x04), 0x00003f00, info->mdiv);
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else
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nv_mask(priv, 0x137250 + (clk * 0x04), 0x0000003f, info->mdiv);
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}
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static void
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nve0_clk_prog_4_0(struct nve0_clk_priv *priv, int clk)
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{
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struct nve0_clk_info *info = &priv->eng[clk];
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if (info->ssel) {
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nv_mask(priv, 0x137100, (1 << clk), info->ssel);
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nv_wait(priv, 0x137100, (1 << clk), info->ssel);
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}
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}
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static void
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nve0_clk_prog_4_1(struct nve0_clk_priv *priv, int clk)
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{
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struct nve0_clk_info *info = &priv->eng[clk];
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if (info->ssel) {
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nv_mask(priv, 0x137160 + (clk * 0x04), 0x40000000, 0x40000000);
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nv_mask(priv, 0x137160 + (clk * 0x04), 0x00000100, 0x00000100);
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}
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}
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static int
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nve0_clk_prog(struct nouveau_clk *clk)
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{
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struct nve0_clk_priv *priv = (void *)clk;
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struct {
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u32 mask;
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void (*exec)(struct nve0_clk_priv *, int);
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} stage[] = {
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{ 0x007f, nve0_clk_prog_0 }, /* div programming */
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{ 0x007f, nve0_clk_prog_1_0 }, /* select div mode */
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{ 0xff80, nve0_clk_prog_1_1 },
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{ 0x00ff, nve0_clk_prog_2 }, /* (maybe) program pll */
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{ 0xff80, nve0_clk_prog_3 }, /* final divider */
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{ 0x007f, nve0_clk_prog_4_0 }, /* (maybe) select pll mode */
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{ 0xff80, nve0_clk_prog_4_1 },
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};
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int i, j;
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for (i = 0; i < ARRAY_SIZE(stage); i++) {
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for (j = 0; j < ARRAY_SIZE(priv->eng); j++) {
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if (!(stage[i].mask & (1 << j)))
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continue;
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if (!priv->eng[j].freq)
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continue;
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stage[i].exec(priv, j);
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}
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}
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return 0;
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}
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static void
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nve0_clk_tidy(struct nouveau_clk *clk)
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{
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struct nve0_clk_priv *priv = (void *)clk;
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memset(priv->eng, 0x00, sizeof(priv->eng));
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}
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static struct nouveau_domain
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nve0_domain[] = {
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{ nv_clk_src_crystal, 0xff },
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{ nv_clk_src_href , 0xff },
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{ nv_clk_src_gpc , 0x00, NVKM_CLK_DOM_FLAG_CORE, "core", 2000 },
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{ nv_clk_src_hubk07 , 0x01, NVKM_CLK_DOM_FLAG_CORE },
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{ nv_clk_src_rop , 0x02, NVKM_CLK_DOM_FLAG_CORE },
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{ nv_clk_src_mem , 0x03, 0, "memory", 500 },
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{ nv_clk_src_hubk06 , 0x04, NVKM_CLK_DOM_FLAG_CORE },
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{ nv_clk_src_hubk01 , 0x05 },
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{ nv_clk_src_vdec , 0x06 },
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{ nv_clk_src_daemon , 0x07 },
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{ nv_clk_src_max }
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};
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static int
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nve0_clk_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
|
|
struct nouveau_oclass *oclass, void *data, u32 size,
|
|
struct nouveau_object **pobject)
|
|
{
|
|
struct nve0_clk_priv *priv;
|
|
int ret;
|
|
|
|
ret = nouveau_clk_create(parent, engine, oclass, nve0_domain, NULL, 0,
|
|
true, &priv);
|
|
*pobject = nv_object(priv);
|
|
if (ret)
|
|
return ret;
|
|
|
|
priv->base.read = nve0_clk_read;
|
|
priv->base.calc = nve0_clk_calc;
|
|
priv->base.prog = nve0_clk_prog;
|
|
priv->base.tidy = nve0_clk_tidy;
|
|
return 0;
|
|
}
|
|
|
|
struct nouveau_oclass
|
|
nve0_clk_oclass = {
|
|
.handle = NV_SUBDEV(CLK, 0xe0),
|
|
.ofuncs = &(struct nouveau_ofuncs) {
|
|
.ctor = nve0_clk_ctor,
|
|
.dtor = _nouveau_clk_dtor,
|
|
.init = _nouveau_clk_init,
|
|
.fini = _nouveau_clk_fini,
|
|
},
|
|
};
|