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According to the official website [1], the R-Car V3U SoC is based on the R-Car Gen4 architecture. So, introduce R-Car Gen4 SYSC driver. [1] https://www.renesas.com/us/en/products/automotive-products/automotive-system-chips-socs/r-car-v3u-best-class-r-car-v3u-asil-d-system-chip-automated-driving Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20211201073308.1003945-6-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
77 lines
3.2 KiB
C
77 lines
3.2 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Renesas R-Car V3U System Controller
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*
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* Copyright (C) 2020 Renesas Electronics Corp.
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*/
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#include <linux/bits.h>
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#include <linux/clk/renesas.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <linux/of_address.h>
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#include <linux/pm_domain.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include <linux/types.h>
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#include <dt-bindings/power/r8a779a0-sysc.h>
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#include "rcar-gen4-sysc.h"
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static struct rcar_gen4_sysc_area r8a779a0_areas[] __initdata = {
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{ "always-on", R8A779A0_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
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{ "a3e0", R8A779A0_PD_A3E0, R8A779A0_PD_ALWAYS_ON, PD_SCU },
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{ "a3e1", R8A779A0_PD_A3E1, R8A779A0_PD_ALWAYS_ON, PD_SCU },
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{ "a2e0d0", R8A779A0_PD_A2E0D0, R8A779A0_PD_A3E0, PD_SCU },
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{ "a2e0d1", R8A779A0_PD_A2E0D1, R8A779A0_PD_A3E0, PD_SCU },
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{ "a2e1d0", R8A779A0_PD_A2E1D0, R8A779A0_PD_A3E1, PD_SCU },
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{ "a2e1d1", R8A779A0_PD_A2E1D1, R8A779A0_PD_A3E1, PD_SCU },
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{ "a1e0d0c0", R8A779A0_PD_A1E0D0C0, R8A779A0_PD_A2E0D0, PD_CPU_NOCR },
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{ "a1e0d0c1", R8A779A0_PD_A1E0D0C1, R8A779A0_PD_A2E0D0, PD_CPU_NOCR },
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{ "a1e0d1c0", R8A779A0_PD_A1E0D1C0, R8A779A0_PD_A2E0D1, PD_CPU_NOCR },
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{ "a1e0d1c1", R8A779A0_PD_A1E0D1C1, R8A779A0_PD_A2E0D1, PD_CPU_NOCR },
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{ "a1e1d0c0", R8A779A0_PD_A1E1D0C0, R8A779A0_PD_A2E1D0, PD_CPU_NOCR },
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{ "a1e1d0c1", R8A779A0_PD_A1E1D0C1, R8A779A0_PD_A2E1D0, PD_CPU_NOCR },
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{ "a1e1d1c0", R8A779A0_PD_A1E1D1C0, R8A779A0_PD_A2E1D1, PD_CPU_NOCR },
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{ "a1e1d1c1", R8A779A0_PD_A1E1D1C1, R8A779A0_PD_A2E1D1, PD_CPU_NOCR },
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{ "3dg-a", R8A779A0_PD_3DG_A, R8A779A0_PD_ALWAYS_ON },
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{ "3dg-b", R8A779A0_PD_3DG_B, R8A779A0_PD_3DG_A },
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{ "a3vip0", R8A779A0_PD_A3VIP0, R8A779A0_PD_ALWAYS_ON },
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{ "a3vip1", R8A779A0_PD_A3VIP1, R8A779A0_PD_ALWAYS_ON },
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{ "a3vip3", R8A779A0_PD_A3VIP3, R8A779A0_PD_ALWAYS_ON },
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{ "a3vip2", R8A779A0_PD_A3VIP2, R8A779A0_PD_ALWAYS_ON },
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{ "a3isp01", R8A779A0_PD_A3ISP01, R8A779A0_PD_ALWAYS_ON },
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{ "a3isp23", R8A779A0_PD_A3ISP23, R8A779A0_PD_ALWAYS_ON },
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{ "a3ir", R8A779A0_PD_A3IR, R8A779A0_PD_ALWAYS_ON },
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{ "a2cn0", R8A779A0_PD_A2CN0, R8A779A0_PD_A3IR },
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{ "a2imp01", R8A779A0_PD_A2IMP01, R8A779A0_PD_A3IR },
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{ "a2dp0", R8A779A0_PD_A2DP0, R8A779A0_PD_A3IR },
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{ "a2cv0", R8A779A0_PD_A2CV0, R8A779A0_PD_A3IR },
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{ "a2cv1", R8A779A0_PD_A2CV1, R8A779A0_PD_A3IR },
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{ "a2cv4", R8A779A0_PD_A2CV4, R8A779A0_PD_A3IR },
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{ "a2cv6", R8A779A0_PD_A2CV6, R8A779A0_PD_A3IR },
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{ "a2cn2", R8A779A0_PD_A2CN2, R8A779A0_PD_A3IR },
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{ "a2imp23", R8A779A0_PD_A2IMP23, R8A779A0_PD_A3IR },
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{ "a2dp1", R8A779A0_PD_A2DP0, R8A779A0_PD_A3IR },
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{ "a2cv2", R8A779A0_PD_A2CV0, R8A779A0_PD_A3IR },
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{ "a2cv3", R8A779A0_PD_A2CV1, R8A779A0_PD_A3IR },
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{ "a2cv5", R8A779A0_PD_A2CV4, R8A779A0_PD_A3IR },
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{ "a2cv7", R8A779A0_PD_A2CV6, R8A779A0_PD_A3IR },
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{ "a2cn1", R8A779A0_PD_A2CN1, R8A779A0_PD_A3IR },
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{ "a1cnn0", R8A779A0_PD_A1CNN0, R8A779A0_PD_A2CN0 },
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{ "a1cnn2", R8A779A0_PD_A1CNN2, R8A779A0_PD_A2CN2 },
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{ "a1dsp0", R8A779A0_PD_A1DSP0, R8A779A0_PD_A2CN2 },
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{ "a1cnn1", R8A779A0_PD_A1CNN1, R8A779A0_PD_A2CN1 },
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{ "a1dsp1", R8A779A0_PD_A1DSP1, R8A779A0_PD_A2CN1 },
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};
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const struct rcar_gen4_sysc_info r8a779a0_sysc_info __initconst = {
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.areas = r8a779a0_areas,
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.num_areas = ARRAY_SIZE(r8a779a0_areas),
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};
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