linux/drivers/gpu
Alistair Popple f2fcb0692d drm/nouveau/fifo/tu102: Turing channel preemption fix
Previous hardware allowed a MMU fault to be generated by software to
trigger a context switch for engine recovery. Turing has the capability
to preempt all work from a specific runlist processor and removed the
registers currently used for triggering MMU faults. Attempting to access
these non-existent registers results in further errors, so use the
runlist preemption register instead.

Signed-off-by: Alistair Popple <apopple@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2021-01-29 16:49:13 +10:00
..
drm drm/nouveau/fifo/tu102: Turing channel preemption fix 2021-01-29 16:49:13 +10:00
host1x gpu/host1x: bus: Add missing description for 'driver' 2020-11-05 22:12:55 +01:00
ipu-v3 gpu/ipu-v3/ipu-di: Strip out 2 unused 'di_sync_config' entries 2021-01-04 12:54:18 +01:00
trace
vga pci-v5.11-changes 2020-12-15 16:49:59 -08:00
Makefile