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d721a15c30
The r8a7790.dtsi file has four sdhi nodes which the first two have the wrong
resource size for their register block. This causes the sh_modbile_sdhi driver
to fail to communicate with card at-all.
Change sdhi{0,1} node size from 0x100 to 0x200 to correct these nodes
as per Kuninori Morimoto's response to the original patch where all four
nodes where changed. sdhi{2,3} are the correct size.
This bug has been present since sdhi resources were added to the r8a7790 by
8c9b1aa418 ("ARM: shmobile: r8a7790: add MMCIF and SDHI DT
templates") in v3.11-rc2.
Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
Tested-by: William Towle <william.towle@codethink.co.uk>
Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
278 lines
6.0 KiB
Plaintext
278 lines
6.0 KiB
Plaintext
/*
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* Device Tree Source for the r8a7790 SoC
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*
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* Copyright (C) 2013 Renesas Solutions Corp.
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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/ {
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compatible = "renesas,r8a7790";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0>;
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clock-frequency = <1300000000>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <1>;
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clock-frequency = <1300000000>;
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};
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cpu2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <2>;
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clock-frequency = <1300000000>;
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};
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cpu3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <3>;
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clock-frequency = <1300000000>;
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};
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cpu4: cpu@4 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x100>;
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clock-frequency = <780000000>;
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};
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cpu5: cpu@5 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x101>;
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clock-frequency = <780000000>;
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};
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cpu6: cpu@6 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x102>;
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clock-frequency = <780000000>;
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};
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cpu7: cpu@7 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x103>;
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clock-frequency = <780000000>;
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};
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};
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gic: interrupt-controller@f1001000 {
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compatible = "arm,cortex-a15-gic";
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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reg = <0 0xf1001000 0 0x1000>,
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<0 0xf1002000 0 0x1000>,
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<0 0xf1004000 0 0x2000>,
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<0 0xf1006000 0 0x2000>;
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interrupts = <1 9 0xf04>;
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};
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gpio0: gpio@e6050000 {
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compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
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reg = <0 0xe6050000 0 0x50>;
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interrupt-parent = <&gic>;
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interrupts = <0 4 0x4>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 0 32>;
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#interrupt-cells = <2>;
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interrupt-controller;
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};
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gpio1: gpio@e6051000 {
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compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
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reg = <0 0xe6051000 0 0x50>;
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interrupt-parent = <&gic>;
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interrupts = <0 5 0x4>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 32 32>;
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#interrupt-cells = <2>;
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interrupt-controller;
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};
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gpio2: gpio@e6052000 {
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compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
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reg = <0 0xe6052000 0 0x50>;
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interrupt-parent = <&gic>;
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interrupts = <0 6 0x4>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 64 32>;
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#interrupt-cells = <2>;
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interrupt-controller;
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};
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gpio3: gpio@e6053000 {
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compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
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reg = <0 0xe6053000 0 0x50>;
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interrupt-parent = <&gic>;
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interrupts = <0 7 0x4>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 96 32>;
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#interrupt-cells = <2>;
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interrupt-controller;
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};
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gpio4: gpio@e6054000 {
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compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
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reg = <0 0xe6054000 0 0x50>;
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interrupt-parent = <&gic>;
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interrupts = <0 8 0x4>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 128 32>;
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#interrupt-cells = <2>;
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interrupt-controller;
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};
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gpio5: gpio@e6055000 {
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compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
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reg = <0 0xe6055000 0 0x50>;
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interrupt-parent = <&gic>;
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interrupts = <0 9 0x4>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 160 32>;
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#interrupt-cells = <2>;
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interrupt-controller;
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupts = <1 13 0xf08>,
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<1 14 0xf08>,
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<1 11 0xf08>,
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<1 10 0xf08>;
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};
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irqc0: interrupt-controller@e61c0000 {
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compatible = "renesas,irqc";
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#interrupt-cells = <2>;
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interrupt-controller;
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reg = <0 0xe61c0000 0 0x200>;
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interrupt-parent = <&gic>;
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interrupts = <0 0 4>, <0 1 4>, <0 2 4>, <0 3 4>;
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};
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i2c0: i2c@e6508000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "renesas,i2c-r8a7790";
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reg = <0 0xe6508000 0 0x40>;
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interrupt-parent = <&gic>;
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interrupts = <0 287 0x4>;
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status = "disabled";
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};
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i2c1: i2c@e6518000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "renesas,i2c-r8a7790";
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reg = <0 0xe6518000 0 0x40>;
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interrupt-parent = <&gic>;
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interrupts = <0 288 0x4>;
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status = "disabled";
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};
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i2c2: i2c@e6530000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "renesas,i2c-r8a7790";
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reg = <0 0xe6530000 0 0x40>;
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interrupt-parent = <&gic>;
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interrupts = <0 286 0x4>;
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status = "disabled";
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};
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i2c3: i2c@e6540000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "renesas,i2c-r8a7790";
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reg = <0 0xe6540000 0 0x40>;
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interrupt-parent = <&gic>;
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interrupts = <0 290 0x4>;
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status = "disabled";
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};
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mmcif0: mmcif@ee200000 {
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compatible = "renesas,sh-mmcif";
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reg = <0 0xee200000 0 0x80>;
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interrupt-parent = <&gic>;
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interrupts = <0 169 0x4>;
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reg-io-width = <4>;
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status = "disabled";
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};
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mmcif1: mmcif@ee220000 {
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compatible = "renesas,sh-mmcif";
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reg = <0 0xee220000 0 0x80>;
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interrupt-parent = <&gic>;
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interrupts = <0 170 0x4>;
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reg-io-width = <4>;
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status = "disabled";
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};
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pfc: pfc@e6060000 {
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compatible = "renesas,pfc-r8a7790";
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reg = <0 0xe6060000 0 0x250>;
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};
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sdhi0: sdhi@ee100000 {
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compatible = "renesas,sdhi-r8a7790";
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reg = <0 0xee100000 0 0x200>;
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interrupt-parent = <&gic>;
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interrupts = <0 165 4>;
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cap-sd-highspeed;
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status = "disabled";
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};
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sdhi1: sdhi@ee120000 {
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compatible = "renesas,sdhi-r8a7790";
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reg = <0 0xee120000 0 0x200>;
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interrupt-parent = <&gic>;
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interrupts = <0 166 4>;
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cap-sd-highspeed;
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status = "disabled";
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};
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sdhi2: sdhi@ee140000 {
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compatible = "renesas,sdhi-r8a7790";
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reg = <0 0xee140000 0 0x100>;
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interrupt-parent = <&gic>;
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interrupts = <0 167 4>;
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cap-sd-highspeed;
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status = "disabled";
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};
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sdhi3: sdhi@ee160000 {
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compatible = "renesas,sdhi-r8a7790";
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reg = <0 0xee160000 0 0x100>;
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interrupt-parent = <&gic>;
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interrupts = <0 168 4>;
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cap-sd-highspeed;
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status = "disabled";
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};
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};
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