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21083f5152
While a memX device on /sys/bus/cxl represents a CXL memory expander
control interface, a pmemX device represents the persistent memory
sub-functionality. It bridges the CXL subystem to the libnvdimm nmemX
control interface.
With this skeleton ndctl can now see persistent memory devices on a
"CXL" bus. Later patches add support for translating libnvdimm native
commands to CXL commands.
# ndctl list -BDiu -b CXL
{
"provider":"CXL",
"dev":"ndbus1",
"dimms":[
{
"dev":"nmem1",
"state":"disabled"
},
{
"dev":"nmem0",
"state":"disabled"
}
]
}
Given nvdimm_bus_unregister() removes all devices on an ndbus0 the
cxl_pmem infrastructure needs to arrange ->remove() to be triggered on
cxl_nvdimm devices to keep their enabled state synchronized with the
registration state of their corresponding device on the nvdimm_bus. In
other words, always arrange for cxl_nvdimm_driver.remove() to unregister
nvdimms from an nvdimm_bus ahead of the bus being unregistered.
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://lore.kernel.org/r/162380012696.3039556.4293801691038740850.stgit@dwillia2-desk3.amr.corp.intel.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
82 lines
2.6 KiB
C
82 lines
2.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/* Copyright(c) 2020-2021 Intel Corporation. */
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#ifndef __CXL_MEM_H__
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#define __CXL_MEM_H__
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#include <linux/cdev.h>
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#include "cxl.h"
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/* CXL 2.0 8.2.8.5.1.1 Memory Device Status Register */
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#define CXLMDEV_STATUS_OFFSET 0x0
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#define CXLMDEV_DEV_FATAL BIT(0)
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#define CXLMDEV_FW_HALT BIT(1)
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#define CXLMDEV_STATUS_MEDIA_STATUS_MASK GENMASK(3, 2)
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#define CXLMDEV_MS_NOT_READY 0
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#define CXLMDEV_MS_READY 1
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#define CXLMDEV_MS_ERROR 2
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#define CXLMDEV_MS_DISABLED 3
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#define CXLMDEV_READY(status) \
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(FIELD_GET(CXLMDEV_STATUS_MEDIA_STATUS_MASK, status) == \
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CXLMDEV_MS_READY)
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#define CXLMDEV_MBOX_IF_READY BIT(4)
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#define CXLMDEV_RESET_NEEDED_MASK GENMASK(7, 5)
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#define CXLMDEV_RESET_NEEDED_NOT 0
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#define CXLMDEV_RESET_NEEDED_COLD 1
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#define CXLMDEV_RESET_NEEDED_WARM 2
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#define CXLMDEV_RESET_NEEDED_HOT 3
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#define CXLMDEV_RESET_NEEDED_CXL 4
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#define CXLMDEV_RESET_NEEDED(status) \
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(FIELD_GET(CXLMDEV_RESET_NEEDED_MASK, status) != \
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CXLMDEV_RESET_NEEDED_NOT)
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/*
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* An entire PCI topology full of devices should be enough for any
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* config
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*/
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#define CXL_MEM_MAX_DEVS 65536
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/**
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* struct cxl_memdev - CXL bus object representing a Type-3 Memory Device
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* @dev: driver core device object
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* @cdev: char dev core object for ioctl operations
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* @cxlm: pointer to the parent device driver data
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* @id: id number of this memdev instance.
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*/
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struct cxl_memdev {
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struct device dev;
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struct cdev cdev;
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struct cxl_mem *cxlm;
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int id;
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};
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/**
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* struct cxl_mem - A CXL memory device
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* @pdev: The PCI device associated with this CXL device.
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* @cxlmd: Logical memory device chardev / interface
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* @regs: Parsed register blocks
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* @payload_size: Size of space for payload
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* (CXL 2.0 8.2.8.4.3 Mailbox Capabilities Register)
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* @lsa_size: Size of Label Storage Area
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* (CXL 2.0 8.2.9.5.1.1 Identify Memory Device)
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* @mbox_mutex: Mutex to synchronize mailbox access.
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* @firmware_version: Firmware version for the memory device.
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* @enabled_cmds: Hardware commands found enabled in CEL.
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* @pmem_range: Persistent memory capacity information.
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* @ram_range: Volatile memory capacity information.
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*/
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struct cxl_mem {
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struct pci_dev *pdev;
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struct cxl_memdev *cxlmd;
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struct cxl_regs regs;
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size_t payload_size;
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size_t lsa_size;
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struct mutex mbox_mutex; /* Protects device mailbox and firmware */
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char firmware_version[0x10];
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unsigned long *enabled_cmds;
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struct range pmem_range;
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struct range ram_range;
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};
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#endif /* __CXL_MEM_H__ */
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